1NXP i.MX System Controller Firmware (SCFW) 2-------------------------------------------------------------------- 3 4The System Controller Firmware (SCFW) is a low-level system function 5which runs on a dedicated Cortex-M core to provide power, clock, and 6resource management. It exists on some i.MX8 processors. e.g. i.MX8QM 7(QM, QP), and i.MX8QX (QXP, DX). 8 9The AP communicates with the SC using a multi-ported MU module found 10in the LSIO subsystem. The current definition of this MU module provides 115 remote AP connections to the SC to support up to 5 execution environments 12(TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces 13with the LSIO DSC IP bus. The SC firmware will communicate with this MU 14using the MSI bus. 15 16System Controller Device Node: 17============================================================ 18 19The scu node with the following properties shall be under the /firmware/ node. 20 21Required properties: 22------------------- 23- compatible: should be "fsl,imx-scu". 24- mbox-names: should include "tx0", "tx1", "tx2", "tx3", 25 "rx0", "rx1", "rx2", "rx3"; 26 include "gip3" if want to support general MU interrupt. 27- mboxes: List of phandle of 4 MU channels for tx, 4 MU channels for 28 rx, and 1 optional MU channel for general interrupt. 29 All MU channels must be in the same MU instance. 30 Cross instances are not allowed. The MU instance can only 31 be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need 32 to make sure use the one which is not conflict with other 33 execution environments. e.g. ATF. 34 Note: 35 Channel 0 must be "tx0" or "rx0". 36 Channel 1 must be "tx1" or "rx1". 37 Channel 2 must be "tx2" or "rx2". 38 Channel 3 must be "tx3" or "rx3". 39 General interrupt rx channel must be "gip3". 40 e.g. 41 mboxes = <&lsio_mu1 0 0 42 &lsio_mu1 0 1 43 &lsio_mu1 0 2 44 &lsio_mu1 0 3 45 &lsio_mu1 1 0 46 &lsio_mu1 1 1 47 &lsio_mu1 1 2 48 &lsio_mu1 1 3 49 &lsio_mu1 3 3>; 50 See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml 51 for detailed mailbox binding. 52 53Note: Each mu which supports general interrupt should have an alias correctly 54numbered in "aliases" node. 55e.g. 56aliases { 57 mu1 = &lsio_mu1; 58}; 59 60i.MX SCU Client Device Node: 61============================================================ 62 63Client nodes are maintained as children of the relevant IMX-SCU device node. 64 65Power domain bindings based on SCU Message Protocol 66------------------------------------------------------------ 67 68This binding for the SCU power domain providers uses the generic power 69domain binding[2]. 70 71Required properties: 72- compatible: Should be one of: 73 "fsl,imx8qm-scu-pd", 74 "fsl,imx8qxp-scu-pd" 75 followed by "fsl,scu-pd" 76 77- #power-domain-cells: Must be 1. Contains the Resource ID used by 78 SCU commands. 79 See detailed Resource ID list from: 80 include/dt-bindings/firmware/imx/rsrc.h 81 82Clock bindings based on SCU Message Protocol 83------------------------------------------------------------ 84 85This binding uses the common clock binding[1]. 86 87Required properties: 88- compatible: Should be one of: 89 "fsl,imx8qm-clock" 90 "fsl,imx8qxp-clock" 91 followed by "fsl,scu-clk" 92- #clock-cells: Should be either 93 2: Contains the Resource and Clock ID value. 94 or 95 1: Contains the Clock ID value. (DEPRECATED) 96- clocks: List of clock specifiers, must contain an entry for 97 each required entry in clock-names 98- clock-names: Should include entries "xtal_32KHz", "xtal_24MHz" 99 100The clock consumer should specify the desired clock by having the clock 101ID in its "clocks" phandle cell. 102 103See the full list of clock IDs from: 104include/dt-bindings/clock/imx8qxp-clock.h 105 106Pinctrl bindings based on SCU Message Protocol 107------------------------------------------------------------ 108 109This binding uses the i.MX common pinctrl binding[3]. 110 111Required properties: 112- compatible: Should be one of: 113 "fsl,imx8qm-iomuxc", 114 "fsl,imx8qxp-iomuxc", 115 "fsl,imx8dxl-iomuxc". 116 117Required properties for Pinctrl sub nodes: 118- fsl,pins: Each entry consists of 3 integers which represents 119 the mux and config setting for one pin. The first 2 120 integers <pin_id mux_mode> are specified using a 121 PIN_FUNC_ID macro, which can be found in 122 <dt-bindings/pinctrl/pads-imx8qm.h>, 123 <dt-bindings/pinctrl/pads-imx8qxp.h>, 124 <dt-bindings/pinctrl/pads-imx8dxl.h>. 125 The last integer CONFIG is the pad setting value like 126 pull-up on this pin. 127 128 Please refer to i.MX8QXP Reference Manual for detailed 129 CONFIG settings. 130 131[1] Documentation/devicetree/bindings/clock/clock-bindings.txt 132[2] Documentation/devicetree/bindings/power/power-domain.yaml 133[3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt 134 135RTC bindings based on SCU Message Protocol 136------------------------------------------------------------ 137 138Required properties: 139- compatible: should be "fsl,imx8qxp-sc-rtc"; 140 141OCOTP bindings based on SCU Message Protocol 142------------------------------------------------------------ 143Required properties: 144- compatible: Should be one of: 145 "fsl,imx8qm-scu-ocotp", 146 "fsl,imx8qxp-scu-ocotp". 147- #address-cells: Must be 1. Contains byte index 148- #size-cells: Must be 1. Contains byte length 149 150Optional Child nodes: 151 152- Data cells of ocotp: 153 Detailed bindings are described in bindings/nvmem/nvmem.txt 154 155Watchdog bindings based on SCU Message Protocol 156------------------------------------------------------------ 157 158Required properties: 159- compatible: should be: 160 "fsl,imx8qxp-sc-wdt" 161 followed by "fsl,imx-sc-wdt"; 162Optional properties: 163- timeout-sec: contains the watchdog timeout in seconds. 164 165SCU key bindings based on SCU Message Protocol 166------------------------------------------------------------ 167 168Required properties: 169- compatible: should be: 170 "fsl,imx8qxp-sc-key" 171 followed by "fsl,imx-sc-key"; 172- linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml 173 174Thermal bindings based on SCU Message Protocol 175------------------------------------------------------------ 176 177Required properties: 178- compatible: Should be : 179 "fsl,imx8qxp-sc-thermal" 180 followed by "fsl,imx-sc-thermal"; 181 182- #thermal-sensor-cells: See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml 183 for a description. 184 185Example (imx8qxp): 186------------- 187aliases { 188 mu1 = &lsio_mu1; 189}; 190 191lsio_mu1: mailbox@5d1c0000 { 192 ... 193 #mbox-cells = <2>; 194}; 195 196firmware { 197 scu { 198 compatible = "fsl,imx-scu"; 199 mbox-names = "tx0", "tx1", "tx2", "tx3", 200 "rx0", "rx1", "rx2", "rx3", 201 "gip3"; 202 mboxes = <&lsio_mu1 0 0 203 &lsio_mu1 0 1 204 &lsio_mu1 0 2 205 &lsio_mu1 0 3 206 &lsio_mu1 1 0 207 &lsio_mu1 1 1 208 &lsio_mu1 1 2 209 &lsio_mu1 1 3 210 &lsio_mu1 3 3>; 211 212 clk: clk { 213 compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; 214 #clock-cells = <2>; 215 }; 216 217 iomuxc { 218 compatible = "fsl,imx8qxp-iomuxc"; 219 220 pinctrl_lpuart0: lpuart0grp { 221 fsl,pins = < 222 SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 223 SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 224 >; 225 }; 226 ... 227 }; 228 229 ocotp: imx8qx-ocotp { 230 compatible = "fsl,imx8qxp-scu-ocotp"; 231 #address-cells = <1>; 232 #size-cells = <1>; 233 234 fec_mac0: mac@2c4 { 235 reg = <0x2c4 8>; 236 }; 237 }; 238 239 pd: imx8qx-pd { 240 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd"; 241 #power-domain-cells = <1>; 242 }; 243 244 rtc: rtc { 245 compatible = "fsl,imx8qxp-sc-rtc"; 246 }; 247 248 scu_key: scu-key { 249 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key"; 250 linux,keycodes = <KEY_POWER>; 251 }; 252 253 watchdog { 254 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt"; 255 timeout-sec = <60>; 256 }; 257 258 tsens: thermal-sensor { 259 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; 260 #thermal-sensor-cells = <1>; 261 }; 262 }; 263}; 264 265serial@5a060000 { 266 ... 267 pinctrl-names = "default"; 268 pinctrl-0 = <&pinctrl_lpuart0>; 269 clocks = <&uart0_clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; 270 clock-names = "ipg"; 271 power-domains = <&pd IMX_SC_R_UART_0>; 272}; 273