1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/arm/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM CPUs 8 9maintainers: 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 11 12description: |+ 13 The device tree allows to describe the layout of CPUs in a system through 14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu") 15 defining properties for every cpu. 16 17 Bindings for CPU nodes follow the Devicetree Specification, available from: 18 19 https://www.devicetree.org/specifications/ 20 21 with updates for 32-bit and 64-bit ARM systems provided in this document. 22 23 ================================ 24 Convention used in this document 25 ================================ 26 27 This document follows the conventions described in the Devicetree 28 Specification, with the addition: 29 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 31 the reg property contained in bits 7 down to 0 32 33 ===================================== 34 cpus and cpu node bindings definition 35 ===================================== 36 37 The ARM architecture, in accordance with the Devicetree Specification, 38 requires the cpus and cpu nodes to be present and contain the properties 39 described below. 40 41properties: 42 reg: 43 maxItems: 1 44 description: | 45 Usage and definition depend on ARM architecture version and 46 configuration: 47 48 On uniprocessor ARM architectures previous to v7 49 this property is required and must be set to 0. 50 51 On ARM 11 MPcore based systems this property is 52 required and matches the CPUID[11:0] register bits. 53 54 Bits [11:0] in the reg cell must be set to 55 bits [11:0] in CPU ID register. 56 57 All other bits in the reg cell must be set to 0. 58 59 On 32-bit ARM v7 or later systems this property is 60 required and matches the CPU MPIDR[23:0] register 61 bits. 62 63 Bits [23:0] in the reg cell must be set to 64 bits [23:0] in MPIDR. 65 66 All other bits in the reg cell must be set to 0. 67 68 On ARM v8 64-bit systems this property is required 69 and matches the MPIDR_EL1 register affinity bits. 70 71 * If cpus node's #address-cells property is set to 2 72 73 The first reg cell bits [7:0] must be set to 74 bits [39:32] of MPIDR_EL1. 75 76 The second reg cell bits [23:0] must be set to 77 bits [23:0] of MPIDR_EL1. 78 79 * If cpus node's #address-cells property is set to 1 80 81 The reg cell bits [23:0] must be set to bits [23:0] 82 of MPIDR_EL1. 83 84 All other bits in the reg cells must be set to 0. 85 86 compatible: 87 enum: 88 - apple,avalanche 89 - apple,blizzard 90 - apple,icestorm 91 - apple,firestorm 92 - arm,arm710t 93 - arm,arm720t 94 - arm,arm740t 95 - arm,arm7ej-s 96 - arm,arm7tdmi 97 - arm,arm7tdmi-s 98 - arm,arm9es 99 - arm,arm9ej-s 100 - arm,arm920t 101 - arm,arm922t 102 - arm,arm925 103 - arm,arm926e-s 104 - arm,arm926ej-s 105 - arm,arm940t 106 - arm,arm946e-s 107 - arm,arm966e-s 108 - arm,arm968e-s 109 - arm,arm9tdmi 110 - arm,arm1020e 111 - arm,arm1020t 112 - arm,arm1022e 113 - arm,arm1026ej-s 114 - arm,arm1136j-s 115 - arm,arm1136jf-s 116 - arm,arm1156t2-s 117 - arm,arm1156t2f-s 118 - arm,arm1176jzf 119 - arm,arm1176jz-s 120 - arm,arm1176jzf-s 121 - arm,arm11mpcore 122 - arm,armv8 # Only for s/w models 123 - arm,cortex-a5 124 - arm,cortex-a7 125 - arm,cortex-a8 126 - arm,cortex-a9 127 - arm,cortex-a12 128 - arm,cortex-a15 129 - arm,cortex-a17 130 - arm,cortex-a32 131 - arm,cortex-a34 132 - arm,cortex-a35 133 - arm,cortex-a53 134 - arm,cortex-a55 135 - arm,cortex-a57 136 - arm,cortex-a65 137 - arm,cortex-a72 138 - arm,cortex-a73 139 - arm,cortex-a75 140 - arm,cortex-a76 141 - arm,cortex-a77 142 - arm,cortex-a78 143 - arm,cortex-a78ae 144 - arm,cortex-a78c 145 - arm,cortex-a510 146 - arm,cortex-a520 147 - arm,cortex-a710 148 - arm,cortex-a715 149 - arm,cortex-a720 150 - arm,cortex-m0 151 - arm,cortex-m0+ 152 - arm,cortex-m1 153 - arm,cortex-m3 154 - arm,cortex-m4 155 - arm,cortex-r4 156 - arm,cortex-r5 157 - arm,cortex-r7 158 - arm,cortex-r52 159 - arm,cortex-x1 160 - arm,cortex-x1c 161 - arm,cortex-x2 162 - arm,cortex-x3 163 - arm,cortex-x4 164 - arm,neoverse-e1 165 - arm,neoverse-n1 166 - arm,neoverse-n2 167 - arm,neoverse-v1 168 - brcm,brahma-b15 169 - brcm,brahma-b53 170 - brcm,vulcan 171 - cavium,thunder 172 - cavium,thunder2 173 - faraday,fa526 174 - intel,sa110 175 - intel,sa1100 176 - marvell,feroceon 177 - marvell,mohawk 178 - marvell,pj4a 179 - marvell,pj4b 180 - marvell,sheeva-v5 181 - marvell,sheeva-v7 182 - nvidia,tegra132-denver 183 - nvidia,tegra186-denver 184 - nvidia,tegra194-carmel 185 - qcom,krait 186 - qcom,kryo 187 - qcom,kryo240 188 - qcom,kryo250 189 - qcom,kryo260 190 - qcom,kryo280 191 - qcom,kryo360 192 - qcom,kryo385 193 - qcom,kryo465 194 - qcom,kryo468 195 - qcom,kryo485 196 - qcom,kryo560 197 - qcom,kryo570 198 - qcom,kryo660 199 - qcom,kryo685 200 - qcom,kryo780 201 - qcom,oryon 202 - qcom,scorpion 203 204 enable-method: 205 $ref: /schemas/types.yaml#/definitions/string 206 oneOf: 207 # On ARM v8 64-bit this property is required 208 - enum: 209 - psci 210 - spin-table 211 # On ARM 32-bit systems this property is optional 212 - enum: 213 - actions,s500-smp 214 - allwinner,sun6i-a31 215 - allwinner,sun8i-a23 216 - allwinner,sun9i-a80-smp 217 - allwinner,sun8i-a83t-smp 218 - amlogic,meson8-smp 219 - amlogic,meson8b-smp 220 - arm,realview-smp 221 - aspeed,ast2600-smp 222 - brcm,bcm11351-cpu-method 223 - brcm,bcm23550 224 - brcm,bcm2836-smp 225 - brcm,bcm63138 226 - brcm,bcm-nsp-smp 227 - brcm,brahma-b15 228 - marvell,armada-375-smp 229 - marvell,armada-380-smp 230 - marvell,armada-390-smp 231 - marvell,armada-xp-smp 232 - marvell,98dx3236-smp 233 - marvell,mmp3-smp 234 - mediatek,mt6589-smp 235 - mediatek,mt81xx-tz-smp 236 - qcom,gcc-msm8660 237 - qcom,kpss-acc-v1 238 - qcom,kpss-acc-v2 239 - qcom,msm8226-smp 240 - qcom,msm8909-smp 241 # Only valid on ARM 32-bit, see above for ARM v8 64-bit 242 - qcom,msm8916-smp 243 - renesas,apmu 244 - renesas,r9a06g032-smp 245 - rockchip,rk3036-smp 246 - rockchip,rk3066-smp 247 - socionext,milbeaut-m10v-smp 248 - ste,dbx500-smp 249 - ti,am3352 250 - ti,am4372 251 252 cpu-release-addr: 253 oneOf: 254 - $ref: /schemas/types.yaml#/definitions/uint32 255 - $ref: /schemas/types.yaml#/definitions/uint64 256 description: 257 The DT specification defines this as 64-bit always, but some 32-bit Arm 258 systems have used a 32-bit value which must be supported. 259 Required for systems that have an "enable-method" 260 property value of "spin-table". 261 262 cpu-idle-states: 263 $ref: /schemas/types.yaml#/definitions/phandle-array 264 items: 265 maxItems: 1 266 description: | 267 List of phandles to idle state nodes supported 268 by this cpu (see ./idle-states.yaml). 269 270 capacity-dmips-mhz: 271 description: 272 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in 273 DMIPS/MHz, relative to highest capacity-dmips-mhz 274 in the system. 275 276 cci-control-port: true 277 278 dynamic-power-coefficient: 279 $ref: /schemas/types.yaml#/definitions/uint32 280 description: 281 A u32 value that represents the running time dynamic 282 power coefficient in units of uW/MHz/V^2. The 283 coefficient can either be calculated from power 284 measurements or derived by analysis. 285 286 The dynamic power consumption of the CPU is 287 proportional to the square of the Voltage (V) and 288 the clock frequency (f). The coefficient is used to 289 calculate the dynamic power as below - 290 291 Pdyn = dynamic-power-coefficient * V^2 * f 292 293 where voltage is in V, frequency is in MHz. 294 295 performance-domains: 296 maxItems: 1 297 description: 298 List of phandles and performance domain specifiers, as defined by 299 bindings of the performance domain provider. See also 300 dvfs/performance-domain.yaml. 301 302 power-domains: 303 description: 304 List of phandles and PM domain specifiers, as defined by bindings of the 305 PM domain provider (see also ../power_domain.txt). 306 307 power-domain-names: 308 description: 309 A list of power domain name strings sorted in the same order as the 310 power-domains property. 311 312 For PSCI based platforms, the name corresponding to the index of the PSCI 313 PM domain provider, must be "psci". For SCMI based platforms, the name 314 corresponding to the index of an SCMI performance domain provider, must be 315 "perf". 316 317 qcom,saw: 318 $ref: /schemas/types.yaml#/definitions/phandle 319 description: | 320 Specifies the SAW* node associated with this CPU. 321 322 Required for systems that have an "enable-method" property 323 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" 324 325 * arm/msm/qcom,saw2.txt 326 327 qcom,acc: 328 $ref: /schemas/types.yaml#/definitions/phandle 329 description: | 330 Specifies the ACC* node associated with this CPU. 331 332 Required for systems that have an "enable-method" property 333 value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or 334 "qcom,msm8916-smp". 335 336 * arm/msm/qcom,kpss-acc.txt 337 338 rockchip,pmu: 339 $ref: /schemas/types.yaml#/definitions/phandle 340 description: | 341 Specifies the syscon node controlling the cpu core power domains. 342 343 Optional for systems that have an "enable-method" 344 property value of "rockchip,rk3066-smp" 345 While optional, it is the preferred way to get access to 346 the cpu-core power-domains. 347 348 secondary-boot-reg: 349 $ref: /schemas/types.yaml#/definitions/uint32 350 description: | 351 Required for systems that have an "enable-method" property value of 352 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". 353 354 This includes the following SoCs: | 355 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550 356 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 357 358 The secondary-boot-reg property is a u32 value that specifies the 359 physical address of the register used to request the ROM holding pen 360 code release a secondary CPU. The value written to the register is 361 formed by encoding the target CPU id into the low bits of the 362 physical start address it should jump to. 363 364if: 365 # If the enable-method property contains one of those values 366 properties: 367 enable-method: 368 contains: 369 enum: 370 - brcm,bcm11351-cpu-method 371 - brcm,bcm23550 372 - brcm,bcm-nsp-smp 373 # and if enable-method is present 374 required: 375 - enable-method 376 377then: 378 required: 379 - secondary-boot-reg 380 381required: 382 - device_type 383 - reg 384 - compatible 385 386dependencies: 387 rockchip,pmu: [enable-method] 388 389additionalProperties: true 390 391examples: 392 - | 393 cpus { 394 #size-cells = <0>; 395 #address-cells = <1>; 396 397 cpu@0 { 398 device_type = "cpu"; 399 compatible = "arm,cortex-a15"; 400 reg = <0x0>; 401 }; 402 403 cpu@1 { 404 device_type = "cpu"; 405 compatible = "arm,cortex-a15"; 406 reg = <0x1>; 407 }; 408 409 cpu@100 { 410 device_type = "cpu"; 411 compatible = "arm,cortex-a7"; 412 reg = <0x100>; 413 }; 414 415 cpu@101 { 416 device_type = "cpu"; 417 compatible = "arm,cortex-a7"; 418 reg = <0x101>; 419 }; 420 }; 421 422 - | 423 // Example 2 (Cortex-A8 uniprocessor 32-bit system): 424 cpus { 425 #size-cells = <0>; 426 #address-cells = <1>; 427 428 cpu@0 { 429 device_type = "cpu"; 430 compatible = "arm,cortex-a8"; 431 reg = <0x0>; 432 }; 433 }; 434 435 - | 436 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system): 437 cpus { 438 #size-cells = <0>; 439 #address-cells = <1>; 440 441 cpu@0 { 442 device_type = "cpu"; 443 compatible = "arm,arm926ej-s"; 444 reg = <0x0>; 445 }; 446 }; 447 448 - | 449 // Example 4 (ARM Cortex-A57 64-bit system): 450 cpus { 451 #size-cells = <0>; 452 #address-cells = <2>; 453 454 cpu@0 { 455 device_type = "cpu"; 456 compatible = "arm,cortex-a57"; 457 reg = <0x0 0x0>; 458 enable-method = "spin-table"; 459 cpu-release-addr = <0 0x20000000>; 460 }; 461 462 cpu@1 { 463 device_type = "cpu"; 464 compatible = "arm,cortex-a57"; 465 reg = <0x0 0x1>; 466 enable-method = "spin-table"; 467 cpu-release-addr = <0 0x20000000>; 468 }; 469 470 cpu@100 { 471 device_type = "cpu"; 472 compatible = "arm,cortex-a57"; 473 reg = <0x0 0x100>; 474 enable-method = "spin-table"; 475 cpu-release-addr = <0 0x20000000>; 476 }; 477 478 cpu@101 { 479 device_type = "cpu"; 480 compatible = "arm,cortex-a57"; 481 reg = <0x0 0x101>; 482 enable-method = "spin-table"; 483 cpu-release-addr = <0 0x20000000>; 484 }; 485 486 cpu@10000 { 487 device_type = "cpu"; 488 compatible = "arm,cortex-a57"; 489 reg = <0x0 0x10000>; 490 enable-method = "spin-table"; 491 cpu-release-addr = <0 0x20000000>; 492 }; 493 494 cpu@10001 { 495 device_type = "cpu"; 496 compatible = "arm,cortex-a57"; 497 reg = <0x0 0x10001>; 498 enable-method = "spin-table"; 499 cpu-release-addr = <0 0x20000000>; 500 }; 501 502 cpu@10100 { 503 device_type = "cpu"; 504 compatible = "arm,cortex-a57"; 505 reg = <0x0 0x10100>; 506 enable-method = "spin-table"; 507 cpu-release-addr = <0 0x20000000>; 508 }; 509 510 cpu@10101 { 511 device_type = "cpu"; 512 compatible = "arm,cortex-a57"; 513 reg = <0x0 0x10101>; 514 enable-method = "spin-table"; 515 cpu-release-addr = <0 0x20000000>; 516 }; 517 518 cpu@100000000 { 519 device_type = "cpu"; 520 compatible = "arm,cortex-a57"; 521 reg = <0x1 0x0>; 522 enable-method = "spin-table"; 523 cpu-release-addr = <0 0x20000000>; 524 }; 525 526 cpu@100000001 { 527 device_type = "cpu"; 528 compatible = "arm,cortex-a57"; 529 reg = <0x1 0x1>; 530 enable-method = "spin-table"; 531 cpu-release-addr = <0 0x20000000>; 532 }; 533 534 cpu@100000100 { 535 device_type = "cpu"; 536 compatible = "arm,cortex-a57"; 537 reg = <0x1 0x100>; 538 enable-method = "spin-table"; 539 cpu-release-addr = <0 0x20000000>; 540 }; 541 542 cpu@100000101 { 543 device_type = "cpu"; 544 compatible = "arm,cortex-a57"; 545 reg = <0x1 0x101>; 546 enable-method = "spin-table"; 547 cpu-release-addr = <0 0x20000000>; 548 }; 549 550 cpu@100010000 { 551 device_type = "cpu"; 552 compatible = "arm,cortex-a57"; 553 reg = <0x1 0x10000>; 554 enable-method = "spin-table"; 555 cpu-release-addr = <0 0x20000000>; 556 }; 557 558 cpu@100010001 { 559 device_type = "cpu"; 560 compatible = "arm,cortex-a57"; 561 reg = <0x1 0x10001>; 562 enable-method = "spin-table"; 563 cpu-release-addr = <0 0x20000000>; 564 }; 565 566 cpu@100010100 { 567 device_type = "cpu"; 568 compatible = "arm,cortex-a57"; 569 reg = <0x1 0x10100>; 570 enable-method = "spin-table"; 571 cpu-release-addr = <0 0x20000000>; 572 }; 573 574 cpu@100010101 { 575 device_type = "cpu"; 576 compatible = "arm,cortex-a57"; 577 reg = <0x1 0x10101>; 578 enable-method = "spin-table"; 579 cpu-release-addr = <0 0x20000000>; 580 }; 581 }; 582... 583