1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/arm/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM CPUs 8 9maintainers: 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 11 12description: |+ 13 The device tree allows to describe the layout of CPUs in a system through 14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu") 15 defining properties for every cpu. 16 17 Bindings for CPU nodes follow the Devicetree Specification, available from: 18 19 https://www.devicetree.org/specifications/ 20 21 with updates for 32-bit and 64-bit ARM systems provided in this document. 22 23 ================================ 24 Convention used in this document 25 ================================ 26 27 This document follows the conventions described in the Devicetree 28 Specification, with the addition: 29 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 31 the reg property contained in bits 7 down to 0 32 33 ===================================== 34 cpus and cpu node bindings definition 35 ===================================== 36 37 The ARM architecture, in accordance with the Devicetree Specification, 38 requires the cpus and cpu nodes to be present and contain the properties 39 described below. 40 41properties: 42 reg: 43 maxItems: 1 44 description: | 45 Usage and definition depend on ARM architecture version and 46 configuration: 47 48 On uniprocessor ARM architectures previous to v7 49 this property is required and must be set to 0. 50 51 On ARM 11 MPcore based systems this property is 52 required and matches the CPUID[11:0] register bits. 53 54 Bits [11:0] in the reg cell must be set to 55 bits [11:0] in CPU ID register. 56 57 All other bits in the reg cell must be set to 0. 58 59 On 32-bit ARM v7 or later systems this property is 60 required and matches the CPU MPIDR[23:0] register 61 bits. 62 63 Bits [23:0] in the reg cell must be set to 64 bits [23:0] in MPIDR. 65 66 All other bits in the reg cell must be set to 0. 67 68 On ARM v8 64-bit systems this property is required 69 and matches the MPIDR_EL1 register affinity bits. 70 71 * If cpus node's #address-cells property is set to 2 72 73 The first reg cell bits [7:0] must be set to 74 bits [39:32] of MPIDR_EL1. 75 76 The second reg cell bits [23:0] must be set to 77 bits [23:0] of MPIDR_EL1. 78 79 * If cpus node's #address-cells property is set to 1 80 81 The reg cell bits [23:0] must be set to bits [23:0] 82 of MPIDR_EL1. 83 84 All other bits in the reg cells must be set to 0. 85 86 compatible: 87 enum: 88 - apple,avalanche 89 - apple,blizzard 90 - apple,icestorm 91 - apple,firestorm 92 - arm,arm710t 93 - arm,arm720t 94 - arm,arm740t 95 - arm,arm7ej-s 96 - arm,arm7tdmi 97 - arm,arm7tdmi-s 98 - arm,arm9es 99 - arm,arm9ej-s 100 - arm,arm920t 101 - arm,arm922t 102 - arm,arm925 103 - arm,arm926e-s 104 - arm,arm926ej-s 105 - arm,arm940t 106 - arm,arm946e-s 107 - arm,arm966e-s 108 - arm,arm968e-s 109 - arm,arm9tdmi 110 - arm,arm1020e 111 - arm,arm1020t 112 - arm,arm1022e 113 - arm,arm1026ej-s 114 - arm,arm1136j-s 115 - arm,arm1136jf-s 116 - arm,arm1156t2-s 117 - arm,arm1156t2f-s 118 - arm,arm1176jzf 119 - arm,arm1176jz-s 120 - arm,arm1176jzf-s 121 - arm,arm11mpcore 122 - arm,armv8 # Only for s/w models 123 - arm,cortex-a5 124 - arm,cortex-a7 125 - arm,cortex-a8 126 - arm,cortex-a9 127 - arm,cortex-a12 128 - arm,cortex-a15 129 - arm,cortex-a17 130 - arm,cortex-a32 131 - arm,cortex-a34 132 - arm,cortex-a35 133 - arm,cortex-a53 134 - arm,cortex-a55 135 - arm,cortex-a57 136 - arm,cortex-a65 137 - arm,cortex-a72 138 - arm,cortex-a73 139 - arm,cortex-a75 140 - arm,cortex-a76 141 - arm,cortex-a77 142 - arm,cortex-a78 143 - arm,cortex-a78ae 144 - arm,cortex-a78c 145 - arm,cortex-a510 146 - arm,cortex-a710 147 - arm,cortex-a715 148 - arm,cortex-m0 149 - arm,cortex-m0+ 150 - arm,cortex-m1 151 - arm,cortex-m3 152 - arm,cortex-m4 153 - arm,cortex-r4 154 - arm,cortex-r5 155 - arm,cortex-r7 156 - arm,cortex-x1 157 - arm,cortex-x1c 158 - arm,cortex-x2 159 - arm,cortex-x3 160 - arm,neoverse-e1 161 - arm,neoverse-n1 162 - arm,neoverse-n2 163 - arm,neoverse-v1 164 - brcm,brahma-b15 165 - brcm,brahma-b53 166 - brcm,vulcan 167 - cavium,thunder 168 - cavium,thunder2 169 - faraday,fa526 170 - intel,sa110 171 - intel,sa1100 172 - marvell,feroceon 173 - marvell,mohawk 174 - marvell,pj4a 175 - marvell,pj4b 176 - marvell,sheeva-v5 177 - marvell,sheeva-v7 178 - nvidia,tegra132-denver 179 - nvidia,tegra186-denver 180 - nvidia,tegra194-carmel 181 - qcom,krait 182 - qcom,kryo 183 - qcom,kryo240 184 - qcom,kryo250 185 - qcom,kryo260 186 - qcom,kryo280 187 - qcom,kryo360 188 - qcom,kryo385 189 - qcom,kryo468 190 - qcom,kryo485 191 - qcom,kryo560 192 - qcom,kryo570 193 - qcom,kryo660 194 - qcom,kryo685 195 - qcom,kryo780 196 - qcom,scorpion 197 198 enable-method: 199 $ref: '/schemas/types.yaml#/definitions/string' 200 oneOf: 201 # On ARM v8 64-bit this property is required 202 - enum: 203 - psci 204 - spin-table 205 # On ARM 32-bit systems this property is optional 206 - enum: 207 - actions,s500-smp 208 - allwinner,sun6i-a31 209 - allwinner,sun8i-a23 210 - allwinner,sun9i-a80-smp 211 - allwinner,sun8i-a83t-smp 212 - amlogic,meson8-smp 213 - amlogic,meson8b-smp 214 - arm,realview-smp 215 - aspeed,ast2600-smp 216 - brcm,bcm11351-cpu-method 217 - brcm,bcm23550 218 - brcm,bcm2836-smp 219 - brcm,bcm63138 220 - brcm,bcm-nsp-smp 221 - brcm,brahma-b15 222 - marvell,armada-375-smp 223 - marvell,armada-380-smp 224 - marvell,armada-390-smp 225 - marvell,armada-xp-smp 226 - marvell,98dx3236-smp 227 - marvell,mmp3-smp 228 - mediatek,mt6589-smp 229 - mediatek,mt81xx-tz-smp 230 - qcom,gcc-msm8660 231 - qcom,kpss-acc-v1 232 - qcom,kpss-acc-v2 233 - qcom,msm8226-smp 234 - qcom,msm8909-smp 235 # Only valid on ARM 32-bit, see above for ARM v8 64-bit 236 - qcom,msm8916-smp 237 - renesas,apmu 238 - renesas,r9a06g032-smp 239 - rockchip,rk3036-smp 240 - rockchip,rk3066-smp 241 - socionext,milbeaut-m10v-smp 242 - ste,dbx500-smp 243 - ti,am3352 244 - ti,am4372 245 246 cpu-release-addr: 247 oneOf: 248 - $ref: '/schemas/types.yaml#/definitions/uint32' 249 - $ref: '/schemas/types.yaml#/definitions/uint64' 250 description: 251 The DT specification defines this as 64-bit always, but some 32-bit Arm 252 systems have used a 32-bit value which must be supported. 253 Required for systems that have an "enable-method" 254 property value of "spin-table". 255 256 cpu-idle-states: 257 $ref: '/schemas/types.yaml#/definitions/phandle-array' 258 items: 259 maxItems: 1 260 description: | 261 List of phandles to idle state nodes supported 262 by this cpu (see ./idle-states.yaml). 263 264 capacity-dmips-mhz: 265 description: 266 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in 267 DMIPS/MHz, relative to highest capacity-dmips-mhz 268 in the system. 269 270 cci-control-port: true 271 272 dynamic-power-coefficient: 273 $ref: '/schemas/types.yaml#/definitions/uint32' 274 description: 275 A u32 value that represents the running time dynamic 276 power coefficient in units of uW/MHz/V^2. The 277 coefficient can either be calculated from power 278 measurements or derived by analysis. 279 280 The dynamic power consumption of the CPU is 281 proportional to the square of the Voltage (V) and 282 the clock frequency (f). The coefficient is used to 283 calculate the dynamic power as below - 284 285 Pdyn = dynamic-power-coefficient * V^2 * f 286 287 where voltage is in V, frequency is in MHz. 288 289 performance-domains: 290 maxItems: 1 291 description: 292 List of phandles and performance domain specifiers, as defined by 293 bindings of the performance domain provider. See also 294 dvfs/performance-domain.yaml. 295 296 power-domains: 297 description: 298 List of phandles and PM domain specifiers, as defined by bindings of the 299 PM domain provider (see also ../power_domain.txt). 300 301 power-domain-names: 302 description: 303 A list of power domain name strings sorted in the same order as the 304 power-domains property. 305 306 For PSCI based platforms, the name corresponding to the index of the PSCI 307 PM domain provider, must be "psci". 308 309 qcom,saw: 310 $ref: '/schemas/types.yaml#/definitions/phandle' 311 description: | 312 Specifies the SAW* node associated with this CPU. 313 314 Required for systems that have an "enable-method" property 315 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" 316 317 * arm/msm/qcom,saw2.txt 318 319 qcom,acc: 320 $ref: '/schemas/types.yaml#/definitions/phandle' 321 description: | 322 Specifies the ACC* node associated with this CPU. 323 324 Required for systems that have an "enable-method" property 325 value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or 326 "qcom,msm8916-smp". 327 328 * arm/msm/qcom,kpss-acc.txt 329 330 rockchip,pmu: 331 $ref: '/schemas/types.yaml#/definitions/phandle' 332 description: | 333 Specifies the syscon node controlling the cpu core power domains. 334 335 Optional for systems that have an "enable-method" 336 property value of "rockchip,rk3066-smp" 337 While optional, it is the preferred way to get access to 338 the cpu-core power-domains. 339 340 secondary-boot-reg: 341 $ref: '/schemas/types.yaml#/definitions/uint32' 342 description: | 343 Required for systems that have an "enable-method" property value of 344 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". 345 346 This includes the following SoCs: | 347 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550 348 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 349 350 The secondary-boot-reg property is a u32 value that specifies the 351 physical address of the register used to request the ROM holding pen 352 code release a secondary CPU. The value written to the register is 353 formed by encoding the target CPU id into the low bits of the 354 physical start address it should jump to. 355 356if: 357 # If the enable-method property contains one of those values 358 properties: 359 enable-method: 360 contains: 361 enum: 362 - brcm,bcm11351-cpu-method 363 - brcm,bcm23550 364 - brcm,bcm-nsp-smp 365 # and if enable-method is present 366 required: 367 - enable-method 368 369then: 370 required: 371 - secondary-boot-reg 372 373required: 374 - device_type 375 - reg 376 - compatible 377 378dependencies: 379 rockchip,pmu: [enable-method] 380 381additionalProperties: true 382 383examples: 384 - | 385 cpus { 386 #size-cells = <0>; 387 #address-cells = <1>; 388 389 cpu@0 { 390 device_type = "cpu"; 391 compatible = "arm,cortex-a15"; 392 reg = <0x0>; 393 }; 394 395 cpu@1 { 396 device_type = "cpu"; 397 compatible = "arm,cortex-a15"; 398 reg = <0x1>; 399 }; 400 401 cpu@100 { 402 device_type = "cpu"; 403 compatible = "arm,cortex-a7"; 404 reg = <0x100>; 405 }; 406 407 cpu@101 { 408 device_type = "cpu"; 409 compatible = "arm,cortex-a7"; 410 reg = <0x101>; 411 }; 412 }; 413 414 - | 415 // Example 2 (Cortex-A8 uniprocessor 32-bit system): 416 cpus { 417 #size-cells = <0>; 418 #address-cells = <1>; 419 420 cpu@0 { 421 device_type = "cpu"; 422 compatible = "arm,cortex-a8"; 423 reg = <0x0>; 424 }; 425 }; 426 427 - | 428 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system): 429 cpus { 430 #size-cells = <0>; 431 #address-cells = <1>; 432 433 cpu@0 { 434 device_type = "cpu"; 435 compatible = "arm,arm926ej-s"; 436 reg = <0x0>; 437 }; 438 }; 439 440 - | 441 // Example 4 (ARM Cortex-A57 64-bit system): 442 cpus { 443 #size-cells = <0>; 444 #address-cells = <2>; 445 446 cpu@0 { 447 device_type = "cpu"; 448 compatible = "arm,cortex-a57"; 449 reg = <0x0 0x0>; 450 enable-method = "spin-table"; 451 cpu-release-addr = <0 0x20000000>; 452 }; 453 454 cpu@1 { 455 device_type = "cpu"; 456 compatible = "arm,cortex-a57"; 457 reg = <0x0 0x1>; 458 enable-method = "spin-table"; 459 cpu-release-addr = <0 0x20000000>; 460 }; 461 462 cpu@100 { 463 device_type = "cpu"; 464 compatible = "arm,cortex-a57"; 465 reg = <0x0 0x100>; 466 enable-method = "spin-table"; 467 cpu-release-addr = <0 0x20000000>; 468 }; 469 470 cpu@101 { 471 device_type = "cpu"; 472 compatible = "arm,cortex-a57"; 473 reg = <0x0 0x101>; 474 enable-method = "spin-table"; 475 cpu-release-addr = <0 0x20000000>; 476 }; 477 478 cpu@10000 { 479 device_type = "cpu"; 480 compatible = "arm,cortex-a57"; 481 reg = <0x0 0x10000>; 482 enable-method = "spin-table"; 483 cpu-release-addr = <0 0x20000000>; 484 }; 485 486 cpu@10001 { 487 device_type = "cpu"; 488 compatible = "arm,cortex-a57"; 489 reg = <0x0 0x10001>; 490 enable-method = "spin-table"; 491 cpu-release-addr = <0 0x20000000>; 492 }; 493 494 cpu@10100 { 495 device_type = "cpu"; 496 compatible = "arm,cortex-a57"; 497 reg = <0x0 0x10100>; 498 enable-method = "spin-table"; 499 cpu-release-addr = <0 0x20000000>; 500 }; 501 502 cpu@10101 { 503 device_type = "cpu"; 504 compatible = "arm,cortex-a57"; 505 reg = <0x0 0x10101>; 506 enable-method = "spin-table"; 507 cpu-release-addr = <0 0x20000000>; 508 }; 509 510 cpu@100000000 { 511 device_type = "cpu"; 512 compatible = "arm,cortex-a57"; 513 reg = <0x1 0x0>; 514 enable-method = "spin-table"; 515 cpu-release-addr = <0 0x20000000>; 516 }; 517 518 cpu@100000001 { 519 device_type = "cpu"; 520 compatible = "arm,cortex-a57"; 521 reg = <0x1 0x1>; 522 enable-method = "spin-table"; 523 cpu-release-addr = <0 0x20000000>; 524 }; 525 526 cpu@100000100 { 527 device_type = "cpu"; 528 compatible = "arm,cortex-a57"; 529 reg = <0x1 0x100>; 530 enable-method = "spin-table"; 531 cpu-release-addr = <0 0x20000000>; 532 }; 533 534 cpu@100000101 { 535 device_type = "cpu"; 536 compatible = "arm,cortex-a57"; 537 reg = <0x1 0x101>; 538 enable-method = "spin-table"; 539 cpu-release-addr = <0 0x20000000>; 540 }; 541 542 cpu@100010000 { 543 device_type = "cpu"; 544 compatible = "arm,cortex-a57"; 545 reg = <0x1 0x10000>; 546 enable-method = "spin-table"; 547 cpu-release-addr = <0 0x20000000>; 548 }; 549 550 cpu@100010001 { 551 device_type = "cpu"; 552 compatible = "arm,cortex-a57"; 553 reg = <0x1 0x10001>; 554 enable-method = "spin-table"; 555 cpu-release-addr = <0 0x20000000>; 556 }; 557 558 cpu@100010100 { 559 device_type = "cpu"; 560 compatible = "arm,cortex-a57"; 561 reg = <0x1 0x10100>; 562 enable-method = "spin-table"; 563 cpu-release-addr = <0 0x20000000>; 564 }; 565 566 cpu@100010101 { 567 device_type = "cpu"; 568 compatible = "arm,cortex-a57"; 569 reg = <0x1 0x10101>; 570 enable-method = "spin-table"; 571 cpu-release-addr = <0 0x20000000>; 572 }; 573 }; 574... 575