1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/arm/cpus.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM CPUs bindings 8 9maintainers: 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 11 12description: |+ 13 The device tree allows to describe the layout of CPUs in a system through 14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu") 15 defining properties for every cpu. 16 17 Bindings for CPU nodes follow the Devicetree Specification, available from: 18 19 https://www.devicetree.org/specifications/ 20 21 with updates for 32-bit and 64-bit ARM systems provided in this document. 22 23 ================================ 24 Convention used in this document 25 ================================ 26 27 This document follows the conventions described in the Devicetree 28 Specification, with the addition: 29 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 31 the reg property contained in bits 7 down to 0 32 33 ===================================== 34 cpus and cpu node bindings definition 35 ===================================== 36 37 The ARM architecture, in accordance with the Devicetree Specification, 38 requires the cpus and cpu nodes to be present and contain the properties 39 described below. 40 41properties: 42 reg: 43 maxItems: 1 44 description: | 45 Usage and definition depend on ARM architecture version and 46 configuration: 47 48 On uniprocessor ARM architectures previous to v7 49 this property is required and must be set to 0. 50 51 On ARM 11 MPcore based systems this property is 52 required and matches the CPUID[11:0] register bits. 53 54 Bits [11:0] in the reg cell must be set to 55 bits [11:0] in CPU ID register. 56 57 All other bits in the reg cell must be set to 0. 58 59 On 32-bit ARM v7 or later systems this property is 60 required and matches the CPU MPIDR[23:0] register 61 bits. 62 63 Bits [23:0] in the reg cell must be set to 64 bits [23:0] in MPIDR. 65 66 All other bits in the reg cell must be set to 0. 67 68 On ARM v8 64-bit systems this property is required 69 and matches the MPIDR_EL1 register affinity bits. 70 71 * If cpus node's #address-cells property is set to 2 72 73 The first reg cell bits [7:0] must be set to 74 bits [39:32] of MPIDR_EL1. 75 76 The second reg cell bits [23:0] must be set to 77 bits [23:0] of MPIDR_EL1. 78 79 * If cpus node's #address-cells property is set to 1 80 81 The reg cell bits [23:0] must be set to bits [23:0] 82 of MPIDR_EL1. 83 84 All other bits in the reg cells must be set to 0. 85 86 compatible: 87 enum: 88 - apple,icestorm 89 - apple,firestorm 90 - arm,arm710t 91 - arm,arm720t 92 - arm,arm740t 93 - arm,arm7ej-s 94 - arm,arm7tdmi 95 - arm,arm7tdmi-s 96 - arm,arm9es 97 - arm,arm9ej-s 98 - arm,arm920t 99 - arm,arm922t 100 - arm,arm925 101 - arm,arm926e-s 102 - arm,arm926ej-s 103 - arm,arm940t 104 - arm,arm946e-s 105 - arm,arm966e-s 106 - arm,arm968e-s 107 - arm,arm9tdmi 108 - arm,arm1020e 109 - arm,arm1020t 110 - arm,arm1022e 111 - arm,arm1026ej-s 112 - arm,arm1136j-s 113 - arm,arm1136jf-s 114 - arm,arm1156t2-s 115 - arm,arm1156t2f-s 116 - arm,arm1176jzf 117 - arm,arm1176jz-s 118 - arm,arm1176jzf-s 119 - arm,arm11mpcore 120 - arm,armv8 # Only for s/w models 121 - arm,cortex-a5 122 - arm,cortex-a7 123 - arm,cortex-a8 124 - arm,cortex-a9 125 - arm,cortex-a12 126 - arm,cortex-a15 127 - arm,cortex-a17 128 - arm,cortex-a32 129 - arm,cortex-a34 130 - arm,cortex-a35 131 - arm,cortex-a53 132 - arm,cortex-a55 133 - arm,cortex-a57 134 - arm,cortex-a65 135 - arm,cortex-a72 136 - arm,cortex-a73 137 - arm,cortex-a75 138 - arm,cortex-a76 139 - arm,cortex-a77 140 - arm,cortex-m0 141 - arm,cortex-m0+ 142 - arm,cortex-m1 143 - arm,cortex-m3 144 - arm,cortex-m4 145 - arm,cortex-r4 146 - arm,cortex-r5 147 - arm,cortex-r7 148 - arm,neoverse-e1 149 - arm,neoverse-n1 150 - brcm,brahma-b15 151 - brcm,brahma-b53 152 - brcm,vulcan 153 - cavium,thunder 154 - cavium,thunder2 155 - faraday,fa526 156 - intel,sa110 157 - intel,sa1100 158 - marvell,feroceon 159 - marvell,mohawk 160 - marvell,pj4a 161 - marvell,pj4b 162 - marvell,sheeva-v5 163 - marvell,sheeva-v7 164 - nvidia,tegra132-denver 165 - nvidia,tegra186-denver 166 - nvidia,tegra194-carmel 167 - qcom,krait 168 - qcom,kryo 169 - qcom,kryo260 170 - qcom,kryo280 171 - qcom,kryo385 172 - qcom,kryo468 173 - qcom,kryo485 174 - qcom,kryo685 175 - qcom,scorpion 176 177 enable-method: 178 $ref: '/schemas/types.yaml#/definitions/string' 179 oneOf: 180 # On ARM v8 64-bit this property is required 181 - enum: 182 - psci 183 - spin-table 184 # On ARM 32-bit systems this property is optional 185 - enum: 186 - actions,s500-smp 187 - allwinner,sun6i-a31 188 - allwinner,sun8i-a23 189 - allwinner,sun9i-a80-smp 190 - allwinner,sun8i-a83t-smp 191 - amlogic,meson8-smp 192 - amlogic,meson8b-smp 193 - arm,realview-smp 194 - aspeed,ast2600-smp 195 - brcm,bcm11351-cpu-method 196 - brcm,bcm23550 197 - brcm,bcm2836-smp 198 - brcm,bcm63138 199 - brcm,bcm-nsp-smp 200 - brcm,brahma-b15 201 - marvell,armada-375-smp 202 - marvell,armada-380-smp 203 - marvell,armada-390-smp 204 - marvell,armada-xp-smp 205 - marvell,98dx3236-smp 206 - marvell,mmp3-smp 207 - mediatek,mt6589-smp 208 - mediatek,mt81xx-tz-smp 209 - qcom,gcc-msm8660 210 - qcom,kpss-acc-v1 211 - qcom,kpss-acc-v2 212 - renesas,apmu 213 - renesas,r9a06g032-smp 214 - rockchip,rk3036-smp 215 - rockchip,rk3066-smp 216 - socionext,milbeaut-m10v-smp 217 - ste,dbx500-smp 218 - ti,am3352 219 - ti,am4372 220 221 cpu-release-addr: 222 $ref: '/schemas/types.yaml#/definitions/uint64' 223 224 description: 225 Required for systems that have an "enable-method" 226 property value of "spin-table". 227 On ARM v8 64-bit systems must be a two cell 228 property identifying a 64-bit zero-initialised 229 memory location. 230 231 cpu-idle-states: 232 $ref: '/schemas/types.yaml#/definitions/phandle-array' 233 description: | 234 List of phandles to idle state nodes supported 235 by this cpu (see ./idle-states.yaml). 236 237 capacity-dmips-mhz: 238 description: 239 u32 value representing CPU capacity (see ./cpu-capacity.txt) in 240 DMIPS/MHz, relative to highest capacity-dmips-mhz 241 in the system. 242 243 dynamic-power-coefficient: 244 $ref: '/schemas/types.yaml#/definitions/uint32' 245 description: 246 A u32 value that represents the running time dynamic 247 power coefficient in units of uW/MHz/V^2. The 248 coefficient can either be calculated from power 249 measurements or derived by analysis. 250 251 The dynamic power consumption of the CPU is 252 proportional to the square of the Voltage (V) and 253 the clock frequency (f). The coefficient is used to 254 calculate the dynamic power as below - 255 256 Pdyn = dynamic-power-coefficient * V^2 * f 257 258 where voltage is in V, frequency is in MHz. 259 260 performance-domains: 261 maxItems: 1 262 description: 263 List of phandles and performance domain specifiers, as defined by 264 bindings of the performance domain provider. See also 265 dvfs/performance-domain.yaml. 266 267 power-domains: 268 description: 269 List of phandles and PM domain specifiers, as defined by bindings of the 270 PM domain provider (see also ../power_domain.txt). 271 272 power-domain-names: 273 description: 274 A list of power domain name strings sorted in the same order as the 275 power-domains property. 276 277 For PSCI based platforms, the name corresponding to the index of the PSCI 278 PM domain provider, must be "psci". 279 280 qcom,saw: 281 $ref: '/schemas/types.yaml#/definitions/phandle' 282 description: | 283 Specifies the SAW* node associated with this CPU. 284 285 Required for systems that have an "enable-method" property 286 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" 287 288 * arm/msm/qcom,saw2.txt 289 290 qcom,acc: 291 $ref: '/schemas/types.yaml#/definitions/phandle' 292 description: | 293 Specifies the ACC* node associated with this CPU. 294 295 Required for systems that have an "enable-method" property 296 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2" 297 298 * arm/msm/qcom,kpss-acc.txt 299 300 rockchip,pmu: 301 $ref: '/schemas/types.yaml#/definitions/phandle' 302 description: | 303 Specifies the syscon node controlling the cpu core power domains. 304 305 Optional for systems that have an "enable-method" 306 property value of "rockchip,rk3066-smp" 307 While optional, it is the preferred way to get access to 308 the cpu-core power-domains. 309 310 secondary-boot-reg: 311 $ref: '/schemas/types.yaml#/definitions/uint32' 312 description: | 313 Required for systems that have an "enable-method" property value of 314 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp". 315 316 This includes the following SoCs: | 317 BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550 318 BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312 319 320 The secondary-boot-reg property is a u32 value that specifies the 321 physical address of the register used to request the ROM holding pen 322 code release a secondary CPU. The value written to the register is 323 formed by encoding the target CPU id into the low bits of the 324 physical start address it should jump to. 325 326if: 327 # If the enable-method property contains one of those values 328 properties: 329 enable-method: 330 contains: 331 enum: 332 - brcm,bcm11351-cpu-method 333 - brcm,bcm23550 334 - brcm,bcm-nsp-smp 335 # and if enable-method is present 336 required: 337 - enable-method 338 339then: 340 required: 341 - secondary-boot-reg 342 343required: 344 - device_type 345 - reg 346 - compatible 347 348dependencies: 349 rockchip,pmu: [enable-method] 350 351additionalProperties: true 352 353examples: 354 - | 355 cpus { 356 #size-cells = <0>; 357 #address-cells = <1>; 358 359 cpu@0 { 360 device_type = "cpu"; 361 compatible = "arm,cortex-a15"; 362 reg = <0x0>; 363 }; 364 365 cpu@1 { 366 device_type = "cpu"; 367 compatible = "arm,cortex-a15"; 368 reg = <0x1>; 369 }; 370 371 cpu@100 { 372 device_type = "cpu"; 373 compatible = "arm,cortex-a7"; 374 reg = <0x100>; 375 }; 376 377 cpu@101 { 378 device_type = "cpu"; 379 compatible = "arm,cortex-a7"; 380 reg = <0x101>; 381 }; 382 }; 383 384 - | 385 // Example 2 (Cortex-A8 uniprocessor 32-bit system): 386 cpus { 387 #size-cells = <0>; 388 #address-cells = <1>; 389 390 cpu@0 { 391 device_type = "cpu"; 392 compatible = "arm,cortex-a8"; 393 reg = <0x0>; 394 }; 395 }; 396 397 - | 398 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system): 399 cpus { 400 #size-cells = <0>; 401 #address-cells = <1>; 402 403 cpu@0 { 404 device_type = "cpu"; 405 compatible = "arm,arm926ej-s"; 406 reg = <0x0>; 407 }; 408 }; 409 410 - | 411 // Example 4 (ARM Cortex-A57 64-bit system): 412 cpus { 413 #size-cells = <0>; 414 #address-cells = <2>; 415 416 cpu@0 { 417 device_type = "cpu"; 418 compatible = "arm,cortex-a57"; 419 reg = <0x0 0x0>; 420 enable-method = "spin-table"; 421 cpu-release-addr = <0 0x20000000>; 422 }; 423 424 cpu@1 { 425 device_type = "cpu"; 426 compatible = "arm,cortex-a57"; 427 reg = <0x0 0x1>; 428 enable-method = "spin-table"; 429 cpu-release-addr = <0 0x20000000>; 430 }; 431 432 cpu@100 { 433 device_type = "cpu"; 434 compatible = "arm,cortex-a57"; 435 reg = <0x0 0x100>; 436 enable-method = "spin-table"; 437 cpu-release-addr = <0 0x20000000>; 438 }; 439 440 cpu@101 { 441 device_type = "cpu"; 442 compatible = "arm,cortex-a57"; 443 reg = <0x0 0x101>; 444 enable-method = "spin-table"; 445 cpu-release-addr = <0 0x20000000>; 446 }; 447 448 cpu@10000 { 449 device_type = "cpu"; 450 compatible = "arm,cortex-a57"; 451 reg = <0x0 0x10000>; 452 enable-method = "spin-table"; 453 cpu-release-addr = <0 0x20000000>; 454 }; 455 456 cpu@10001 { 457 device_type = "cpu"; 458 compatible = "arm,cortex-a57"; 459 reg = <0x0 0x10001>; 460 enable-method = "spin-table"; 461 cpu-release-addr = <0 0x20000000>; 462 }; 463 464 cpu@10100 { 465 device_type = "cpu"; 466 compatible = "arm,cortex-a57"; 467 reg = <0x0 0x10100>; 468 enable-method = "spin-table"; 469 cpu-release-addr = <0 0x20000000>; 470 }; 471 472 cpu@10101 { 473 device_type = "cpu"; 474 compatible = "arm,cortex-a57"; 475 reg = <0x0 0x10101>; 476 enable-method = "spin-table"; 477 cpu-release-addr = <0 0x20000000>; 478 }; 479 480 cpu@100000000 { 481 device_type = "cpu"; 482 compatible = "arm,cortex-a57"; 483 reg = <0x1 0x0>; 484 enable-method = "spin-table"; 485 cpu-release-addr = <0 0x20000000>; 486 }; 487 488 cpu@100000001 { 489 device_type = "cpu"; 490 compatible = "arm,cortex-a57"; 491 reg = <0x1 0x1>; 492 enable-method = "spin-table"; 493 cpu-release-addr = <0 0x20000000>; 494 }; 495 496 cpu@100000100 { 497 device_type = "cpu"; 498 compatible = "arm,cortex-a57"; 499 reg = <0x1 0x100>; 500 enable-method = "spin-table"; 501 cpu-release-addr = <0 0x20000000>; 502 }; 503 504 cpu@100000101 { 505 device_type = "cpu"; 506 compatible = "arm,cortex-a57"; 507 reg = <0x1 0x101>; 508 enable-method = "spin-table"; 509 cpu-release-addr = <0 0x20000000>; 510 }; 511 512 cpu@100010000 { 513 device_type = "cpu"; 514 compatible = "arm,cortex-a57"; 515 reg = <0x1 0x10000>; 516 enable-method = "spin-table"; 517 cpu-release-addr = <0 0x20000000>; 518 }; 519 520 cpu@100010001 { 521 device_type = "cpu"; 522 compatible = "arm,cortex-a57"; 523 reg = <0x1 0x10001>; 524 enable-method = "spin-table"; 525 cpu-release-addr = <0 0x20000000>; 526 }; 527 528 cpu@100010100 { 529 device_type = "cpu"; 530 compatible = "arm,cortex-a57"; 531 reg = <0x1 0x10100>; 532 enable-method = "spin-table"; 533 cpu-release-addr = <0 0x20000000>; 534 }; 535 536 cpu@100010101 { 537 device_type = "cpu"; 538 compatible = "arm,cortex-a57"; 539 reg = <0x1 0x10101>; 540 enable-method = "spin-table"; 541 cpu-release-addr = <0 0x20000000>; 542 }; 543 }; 544... 545