1* CoreSight CPU Debug Component: 2 3CoreSight CPU debug component are compliant with the ARMv8 architecture 4reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The 5external debug module is mainly used for two modes: self-hosted debug and 6external debug, and it can be accessed from mmio region from Coresight 7and eventually the debug module connects with CPU for debugging. And the 8debug module provides sample-based profiling extension, which can be used 9to sample CPU program counter, secure state and exception level, etc; 10usually every CPU has one dedicated debug module to be connected. 11 12Required properties: 13 14- compatible : should be "arm,coresight-cpu-debug"; supplemented with 15 "arm,primecell" since this driver is using the AMBA bus 16 interface. 17 18- reg : physical base address and length of the register set. 19 20- clocks : the clock associated to this component. 21 22- clock-names : the name of the clock referenced by the code. Since we are 23 using the AMBA framework, the name of the clock providing 24 the interconnect should be "apb_pclk" and the clock is 25 mandatory. The interface between the debug logic and the 26 processor core is clocked by the internal CPU clock, so it 27 is enabled with CPU clock by default. 28 29- cpu : the CPU phandle the debug module is affined to. Do not assume it 30 to default to CPU0 if omitted. 31 32Optional properties: 33 34- power-domains: a phandle to the debug power domain. We use "power-domains" 35 binding to turn on the debug logic if it has own dedicated 36 power domain and if necessary to use "cpuidle.off=1" or 37 "nohlt" in the kernel command line or sysfs node to 38 constrain idle states to ensure registers in the CPU power 39 domain are accessible. 40 41Example: 42 43 debug@f6590000 { 44 compatible = "arm,coresight-cpu-debug","arm,primecell"; 45 reg = <0 0xf6590000 0 0x1000>; 46 clocks = <&sys_ctrl HI6220_DAPB_CLK>; 47 clock-names = "apb_pclk"; 48 cpu = <&cpu0>; 49 }; 50