1*c66ec88fSEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*c66ec88fSEmmanuel Vadot%YAML 1.2 3*c66ec88fSEmmanuel Vadot--- 4*c66ec88fSEmmanuel Vadot$id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml# 5*c66ec88fSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6*c66ec88fSEmmanuel Vadot 7*c66ec88fSEmmanuel Vadottitle: Calxeda Highbank L2 cache ECC 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel Vadotdescription: | 10*c66ec88fSEmmanuel Vadot Binding for the Calxeda Highbank L2 cache controller ECC device. 11*c66ec88fSEmmanuel Vadot This does not cover the actual L2 cache controller control registers, 12*c66ec88fSEmmanuel Vadot but just the error reporting functionality. 13*c66ec88fSEmmanuel Vadot 14*c66ec88fSEmmanuel Vadotmaintainers: 15*c66ec88fSEmmanuel Vadot - Andre Przywara <andre.przywara@arm.com> 16*c66ec88fSEmmanuel Vadot 17*c66ec88fSEmmanuel Vadotproperties: 18*c66ec88fSEmmanuel Vadot compatible: 19*c66ec88fSEmmanuel Vadot const: "calxeda,hb-sregs-l2-ecc" 20*c66ec88fSEmmanuel Vadot 21*c66ec88fSEmmanuel Vadot reg: 22*c66ec88fSEmmanuel Vadot maxItems: 1 23*c66ec88fSEmmanuel Vadot 24*c66ec88fSEmmanuel Vadot interrupts: 25*c66ec88fSEmmanuel Vadot items: 26*c66ec88fSEmmanuel Vadot - description: single bit error interrupt 27*c66ec88fSEmmanuel Vadot - description: double bit error interrupt 28*c66ec88fSEmmanuel Vadot 29*c66ec88fSEmmanuel Vadotrequired: 30*c66ec88fSEmmanuel Vadot - compatible 31*c66ec88fSEmmanuel Vadot - reg 32*c66ec88fSEmmanuel Vadot - interrupts 33*c66ec88fSEmmanuel Vadot 34*c66ec88fSEmmanuel VadotadditionalProperties: false 35*c66ec88fSEmmanuel Vadot 36*c66ec88fSEmmanuel Vadotexamples: 37*c66ec88fSEmmanuel Vadot - | 38*c66ec88fSEmmanuel Vadot sregs@fff3c200 { 39*c66ec88fSEmmanuel Vadot compatible = "calxeda,hb-sregs-l2-ecc"; 40*c66ec88fSEmmanuel Vadot reg = <0xfff3c200 0x100>; 41*c66ec88fSEmmanuel Vadot interrupts = <0 71 4>, <0 72 4>; 42*c66ec88fSEmmanuel Vadot }; 43