1Atmel system registers 2 3Chipid required properties: 4- compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid" 5- reg : Should contain registers location and length 6 7PIT Timer required properties: 8- compatible: Should be "atmel,at91sam9260-pit" 9- reg: Should contain registers location and length 10- interrupts: Should contain interrupt for the PIT which is the IRQ line 11 shared across all System Controller members. 12 13PIT64B Timer required properties: 14- compatible: Should be "microchip,sam9x60-pit64b" 15- reg: Should contain registers location and length 16- interrupts: Should contain interrupt for PIT64B timer 17- clocks: Should contain the available clock sources for PIT64B timer. 18 19System Timer (ST) required properties: 20- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" 21- reg: Should contain registers location and length 22- interrupts: Should contain interrupt for the ST which is the IRQ line 23 shared across all System Controller members. 24- clocks: phandle to input clock. 25Its subnodes can be: 26- watchdog: compatible should be "atmel,at91rm9200-wdt" 27 28RAMC SDRAM/DDR Controller required properties: 29- compatible: Should be "atmel,at91rm9200-sdramc", "syscon" 30 "atmel,at91sam9260-sdramc", 31 "atmel,at91sam9g45-ddramc", 32 "atmel,sama5d3-ddramc", 33 "microchip,sam9x60-ddramc", 34 "microchip,sama7g5-uddrc" 35- reg: Should contain registers location and length 36 37Examples: 38 39 ramc0: ramc@ffffe800 { 40 compatible = "atmel,at91sam9g45-ddramc"; 41 reg = <0xffffe800 0x200>; 42 }; 43 44RAMC PHY Controller required properties: 45- compatible: Should be "microchip,sama7g5-ddr3phy", "syscon" 46- reg: Should contain registers location and length 47 48Example: 49 50 ddr3phy: ddr3phy@e3804000 { 51 compatible = "microchip,sama7g5-ddr3phy", "syscon"; 52 reg = <0xe3804000 0x1000>; 53}; 54 55SHDWC Shutdown Controller 56 57required properties: 58- compatible: Should be "atmel,<chip>-shdwc". 59 <chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5". 60- reg: Should contain registers location and length 61- clocks: phandle to input clock. 62 63optional properties: 64- atmel,wakeup-mode: String, operation mode of the wakeup mode. 65 Supported values are: "none", "high", "low", "any". 66- atmel,wakeup-counter: Counter on Wake-up 0 (between 0x0 and 0xf). 67 68optional at91sam9260 properties: 69- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. 70 71optional at91sam9rl properties: 72- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. 73- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. 74 75optional at91sam9x5 properties: 76- atmel,wakeup-rtc-timer: boolean to enable Real-time Clock Wake-up. 77 78Example: 79 80 shdwc@fffffd10 { 81 compatible = "atmel,at91sam9260-shdwc"; 82 reg = <0xfffffd10 0x10>; 83 clocks = <&clk32k>; 84 }; 85 86SHDWC SAMA5D2-Compatible Shutdown Controller 87 881) shdwc node 89 90required properties: 91- compatible: should be "atmel,sama5d2-shdwc", "microchip,sam9x60-shdwc" or 92 "microchip,sama7g5-shdwc" 93- reg: should contain registers location and length 94- clocks: phandle to input clock. 95- #address-cells: should be one. The cell is the wake-up input index. 96- #size-cells: should be zero. 97 98optional properties: 99 100- debounce-delay-us: minimum wake-up inputs debouncer period in 101 microseconds. It's usually a board-related property. 102- atmel,wakeup-rtc-timer: boolean to enable Real-Time Clock wake-up. 103 104optional microchip,sam9x60-shdwc or microchip,sama7g5-shdwc properties: 105- atmel,wakeup-rtt-timer: boolean to enable Real-time Timer Wake-up. 106 107The node contains child nodes for each wake-up input that the platform uses. 108 1092) input nodes 110 111Wake-up input nodes are usually described in the "board" part of the Device 112Tree. Note also that input 0 is linked to the wake-up pin and is frequently 113used. 114 115Required properties: 116- reg: should contain the wake-up input index [0 - 15]. 117 118Optional properties: 119- atmel,wakeup-active-high: boolean, the corresponding wake-up input described 120 by the child, forces the wake-up of the core power supply on a high level. 121 The default is to be active low. 122 123Example: 124 125On the SoC side: 126 shdwc@f8048010 { 127 compatible = "atmel,sama5d2-shdwc"; 128 reg = <0xf8048010 0x10>; 129 clocks = <&clk32k>; 130 #address-cells = <1>; 131 #size-cells = <0>; 132 atmel,wakeup-rtc-timer; 133 }; 134 135On the board side: 136 shdwc@f8048010 { 137 debounce-delay-us = <976>; 138 139 input@0 { 140 reg = <0>; 141 }; 142 143 input@1 { 144 reg = <1>; 145 atmel,wakeup-active-high; 146 }; 147 }; 148 149Special Function Registers (SFR) 150 151Special Function Registers (SFR) manage specific aspects of the integrated 152memory, bridge implementations, processor and other functionality not controlled 153elsewhere. 154 155required properties: 156- compatible: Should be "atmel,<chip>-sfr", "syscon" or 157 "atmel,<chip>-sfrbu", "syscon" 158 <chip> can be "sama5d3", "sama5d4" or "sama5d2". 159 It also can be "microchip,sam9x60-sfr", "syscon". 160- reg: Should contain registers location and length 161 162 sfr@f0038000 { 163 compatible = "atmel,sama5d3-sfr", "syscon"; 164 reg = <0xf0038000 0x60>; 165 }; 166 167Security Module (SECUMOD) 168 169The Security Module macrocell provides all necessary secure functions to avoid 170voltage, temperature, frequency and mechanical attacks on the chip. It also 171embeds secure memories that can be scrambled. 172 173The Security Module also offers the PIOBU pins which can be used as GPIO pins. 174Note that they maintain their voltage during Backup/Self-refresh. 175 176required properties: 177- compatible: Should be "atmel,<chip>-secumod", "syscon". 178 <chip> can be "sama5d2". 179- reg: Should contain registers location and length 180- gpio-controller: Marks the port as GPIO controller. 181- #gpio-cells: There are 2. The pin number is the 182 first, the second represents additional 183 parameters such as GPIO_ACTIVE_HIGH/LOW. 184 185 186 secumod@fc040000 { 187 compatible = "atmel,sama5d2-secumod", "syscon"; 188 reg = <0xfc040000 0x100>; 189 gpio-controller; 190 #gpio-cells = <2>; 191 }; 192