1* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU) 2 3ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores 4with a shared L3 memory system, control logic and external interfaces to 5form a multicore cluster. The PMU enables to gather various statistics on 6the operations of the DSU. The PMU provides independent 32bit counters that 7can count any of the supported events, along with a 64bit cycle counter. 8The PMU is accessed via CPU system registers and has no MMIO component. 9 10** DSU PMU required properties: 11 12- compatible : should be one of : 13 14 "arm,dsu-pmu" 15 16- interrupts : Exactly 1 SPI must be listed. 17 18- cpus : List of phandles for the CPUs connected to this DSU instance. 19 20 21** Example: 22 23dsu-pmu-0 { 24 compatible = "arm,dsu-pmu"; 25 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>; 26 cpus = <&cpu_0>, <&cpu_1>; 27}; 28