xref: /freebsd/sys/contrib/device-tree/Bindings/arm/arm,coresight-tpiu.yaml (revision b97ee269eae3cbaf35c18f51a459aea581c2a7dc) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/arm,coresight-tpiu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Arm CoreSight Trace Port Interface Unit
8
9maintainers:
10  - Mathieu Poirier <mathieu.poirier@linaro.org>
11  - Mike Leach <mike.leach@linaro.org>
12  - Leo Yan <leo.yan@linaro.org>
13  - Suzuki K Poulose <suzuki.poulose@arm.com>
14
15description: |
16  CoreSight components are compliant with the ARM CoreSight architecture
17  specification and can be connected in various topologies to suit a particular
18  SoCs tracing needs. These trace components can generally be classified as
19  sinks, links and sources. Trace data produced by one or more sources flows
20  through the intermediate links connecting the source to the currently selected
21  sink.
22
23  The CoreSight Trace Port Interface Unit captures trace data from the trace bus
24  and outputs it to an external trace port.
25
26# Need a custom select here or 'arm,primecell' will match on lots of nodes
27select:
28  properties:
29    compatible:
30      contains:
31        const: arm,coresight-tpiu
32  required:
33    - compatible
34
35allOf:
36  - $ref: /schemas/arm/primecell.yaml#
37
38properties:
39  compatible:
40    items:
41      - const: arm,coresight-tpiu
42      - const: arm,primecell
43
44  reg:
45    maxItems: 1
46
47  clocks:
48    minItems: 1
49    maxItems: 2
50
51  clock-names:
52    minItems: 1
53    items:
54      - const: apb_pclk
55      - const: atclk
56
57  in-ports:
58    $ref: /schemas/graph.yaml#/properties/ports
59    additionalProperties: false
60
61    properties:
62      port:
63        description: Input connection from the CoreSight Trace bus.
64        $ref: /schemas/graph.yaml#/properties/port
65
66required:
67  - compatible
68  - reg
69  - clocks
70  - clock-names
71  - in-ports
72
73unevaluatedProperties: false
74
75examples:
76  - |
77    tpiu@e3c05000 {
78        compatible = "arm,coresight-tpiu", "arm,primecell";
79        reg = <0xe3c05000 0x1000>;
80
81        clocks = <&clk_375m>;
82        clock-names = "apb_pclk";
83        in-ports {
84            port {
85                tpiu_in_port: endpoint {
86                    remote-endpoint = <&funnel4_out_port0>;
87                };
88            };
89        };
90    };
91...
92