1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_TXRX_H__ 6 #define __RTW89_TXRX_H__ 7 8 #include "debug.h" 9 10 #define DATA_RATE_MODE_CTRL_MASK GENMASK(8, 7) 11 #define DATA_RATE_NOT_HT_IDX_MASK GENMASK(3, 0) 12 #define DATA_RATE_MODE_NON_HT 0x0 13 #define DATA_RATE_HT_IDX_MASK GENMASK(4, 0) 14 #define DATA_RATE_MODE_HT 0x1 15 #define DATA_RATE_VHT_HE_NSS_MASK GENMASK(6, 4) 16 #define DATA_RATE_VHT_HE_IDX_MASK GENMASK(3, 0) 17 #define DATA_RATE_MODE_VHT 0x2 18 #define DATA_RATE_MODE_HE 0x3 19 #define GET_DATA_RATE_MODE(r) FIELD_GET(DATA_RATE_MODE_CTRL_MASK, r) 20 #define GET_DATA_RATE_NOT_HT_IDX(r) FIELD_GET(DATA_RATE_NOT_HT_IDX_MASK, r) 21 #define GET_DATA_RATE_HT_IDX(r) FIELD_GET(DATA_RATE_HT_IDX_MASK, r) 22 #define GET_DATA_RATE_VHT_HE_IDX(r) FIELD_GET(DATA_RATE_VHT_HE_IDX_MASK, r) 23 #define GET_DATA_RATE_NSS(r) FIELD_GET(DATA_RATE_VHT_HE_NSS_MASK, r) 24 25 /* TX WD BODY DWORD 0 */ 26 #define RTW89_TXWD_BODY0_WP_OFFSET GENMASK(31, 24) 27 #define RTW89_TXWD_BODY0_WP_OFFSET_V1 GENMASK(28, 24) 28 #define RTW89_TXWD_BODY0_MORE_DATA BIT(23) 29 #define RTW89_TXWD_BODY0_WD_INFO_EN BIT(22) 30 #define RTW89_TXWD_BODY0_FW_DL BIT(20) 31 #define RTW89_TXWD_BODY0_CHANNEL_DMA GENMASK(19, 16) 32 #define RTW89_TXWD_BODY0_HDR_LLC_LEN GENMASK(15, 11) 33 #define RTW89_TXWD_BODY0_WD_PAGE BIT(7) 34 #define RTW89_TXWD_BODY0_HW_AMSDU BIT(5) 35 #define RTW89_TXWD_BODY0_HW_SSN_SEL GENMASK(3, 2) 36 #define RTW89_TXWD_BODY0_HW_SSN_MODE GENMASK(1, 0) 37 38 /* TX WD BODY DWORD 1 */ 39 #define RTW89_TXWD_BODY1_ADDR_INFO_NUM GENMASK(31, 26) 40 #define RTW89_TXWD_BODY1_PAYLOAD_ID GENMASK(31, 16) 41 #define RTW89_TXWD_BODY1_SEC_KEYID GENMASK(5, 4) 42 #define RTW89_TXWD_BODY1_SEC_TYPE GENMASK(3, 0) 43 44 /* TX WD BODY DWORD 2 */ 45 #define RTW89_TXWD_BODY2_MACID GENMASK(30, 24) 46 #define RTW89_TXWD_BODY2_TID_INDICATE BIT(23) 47 #define RTW89_TXWD_BODY2_QSEL GENMASK(22, 17) 48 #define RTW89_TXWD_BODY2_TXPKT_SIZE GENMASK(13, 0) 49 50 /* TX WD BODY DWORD 3 */ 51 #define RTW89_TXWD_BODY3_BK BIT(13) 52 #define RTW89_TXWD_BODY3_AGG_EN BIT(12) 53 #define RTW89_TXWD_BODY3_SW_SEQ GENMASK(11, 0) 54 55 /* TX WD BODY DWORD 4 */ 56 #define RTW89_TXWD_BODY4_SEC_IV_L1 GENMASK(31, 24) 57 #define RTW89_TXWD_BODY4_SEC_IV_L0 GENMASK(23, 16) 58 59 /* TX WD BODY DWORD 5 */ 60 #define RTW89_TXWD_BODY5_SEC_IV_H5 GENMASK(31, 24) 61 #define RTW89_TXWD_BODY5_SEC_IV_H4 GENMASK(23, 16) 62 #define RTW89_TXWD_BODY5_SEC_IV_H3 GENMASK(15, 8) 63 #define RTW89_TXWD_BODY5_SEC_IV_H2 GENMASK(7, 0) 64 65 /* TX WD BODY DWORD 6 (V1) */ 66 67 /* TX WD BODY DWORD 7 (V1) */ 68 #define RTW89_TXWD_BODY7_USE_RATE_V1 BIT(31) 69 #define RTW89_TXWD_BODY7_DATA_BW GENMASK(29, 28) 70 #define RTW89_TXWD_BODY7_GI_LTF GENMASK(27, 25) 71 #define RTW89_TXWD_BODY7_DATA_RATE GENMASK(24, 16) 72 73 /* TX WD INFO DWORD 0 */ 74 #define RTW89_TXWD_INFO0_USE_RATE BIT(30) 75 #define RTW89_TXWD_INFO0_DATA_BW GENMASK(29, 28) 76 #define RTW89_TXWD_INFO0_GI_LTF GENMASK(27, 25) 77 #define RTW89_TXWD_INFO0_DATA_RATE GENMASK(24, 16) 78 #define RTW89_TXWD_INFO0_DISDATAFB BIT(10) 79 #define RTW89_TXWD_INFO0_MULTIPORT_ID GENMASK(6, 4) 80 81 /* TX WD INFO DWORD 1 */ 82 #define RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE GENMASK(24, 16) 83 #define RTW89_TXWD_INFO1_A_CTRL_BSR BIT(14) 84 #define RTW89_TXWD_INFO1_MAX_AGGNUM GENMASK(7, 0) 85 86 /* TX WD INFO DWORD 2 */ 87 #define RTW89_TXWD_INFO2_AMPDU_DENSITY GENMASK(20, 18) 88 #define RTW89_TXWD_INFO2_SEC_TYPE GENMASK(12, 9) 89 #define RTW89_TXWD_INFO2_SEC_HW_ENC BIT(8) 90 #define RTW89_TXWD_INFO2_FORCE_KEY_EN BIT(8) 91 #define RTW89_TXWD_INFO2_SEC_CAM_IDX GENMASK(7, 0) 92 93 /* TX WD INFO DWORD 3 */ 94 95 /* TX WD INFO DWORD 4 */ 96 #define RTW89_TXWD_INFO4_RTS_EN BIT(27) 97 #define RTW89_TXWD_INFO4_HW_RTS_EN BIT(31) 98 99 /* TX WD INFO DWORD 5 */ 100 101 /* RX WD dword0 */ 102 #define AX_RXD_RPKT_LEN_MASK GENMASK(13, 0) 103 #define AX_RXD_SHIFT_MASK GENMASK(15, 14) 104 #define AX_RXD_WL_HD_IV_LEN_MASK GENMASK(21, 16) 105 #define AX_RXD_BB_SEL BIT(22) 106 #define AX_RXD_MAC_INFO_VLD BIT(23) 107 #define AX_RXD_RPKT_TYPE_MASK GENMASK(27, 24) 108 #define AX_RXD_DRV_INFO_SIZE_MASK GENMASK(30, 28) 109 #define AX_RXD_LONG_RXD BIT(31) 110 111 /* RX WD dword1 */ 112 #define AX_RXD_PPDU_TYPE_MASK GENMASK(3, 0) 113 #define AX_RXD_PPDU_CNT_MASK GENMASK(6, 4) 114 #define AX_RXD_SR_EN BIT(7) 115 #define AX_RXD_USER_ID_MASK GENMASK(15, 8) 116 #define AX_RXD_USER_ID_v1_MASK GENMASK(13, 8) 117 #define AX_RXD_RX_DATARATE_MASK GENMASK(24, 16) 118 #define AX_RXD_RX_GI_LTF_MASK GENMASK(27, 25) 119 #define AX_RXD_NON_SRG_PPDU BIT(28) 120 #define AX_RXD_INTER_PPDU BIT(29) 121 #define AX_RXD_NON_SRG_PPDU_v1 BIT(14) 122 #define AX_RXD_INTER_PPDU_v1 BIT(15) 123 #define AX_RXD_BW_MASK GENMASK(31, 30) 124 #define AX_RXD_BW_v1_MASK GENMASK(31, 29) 125 126 /* RX WD dword2 */ 127 #define AX_RXD_FREERUN_CNT_MASK GENMASK(31, 0) 128 129 /* RX WD dword3 */ 130 #define AX_RXD_A1_MATCH BIT(0) 131 #define AX_RXD_SW_DEC BIT(1) 132 #define AX_RXD_HW_DEC BIT(2) 133 #define AX_RXD_AMPDU BIT(3) 134 #define AX_RXD_AMPDU_END_PKT BIT(4) 135 #define AX_RXD_AMSDU BIT(5) 136 #define AX_RXD_AMSDU_CUT BIT(6) 137 #define AX_RXD_LAST_MSDU BIT(7) 138 #define AX_RXD_BYPASS BIT(8) 139 #define AX_RXD_CRC32_ERR BIT(9) 140 #define AX_RXD_ICV_ERR BIT(10) 141 #define AX_RXD_MAGIC_WAKE BIT(11) 142 #define AX_RXD_UNICAST_WAKE BIT(12) 143 #define AX_RXD_PATTERN_WAKE BIT(13) 144 #define AX_RXD_GET_CH_INFO_MASK GENMASK(15, 14) 145 #define AX_RXD_PATTERN_IDX_MASK GENMASK(20, 16) 146 #define AX_RXD_TARGET_IDC_MASK GENMASK(23, 21) 147 #define AX_RXD_CHKSUM_OFFLOAD_EN BIT(24) 148 #define AX_RXD_WITH_LLC BIT(25) 149 #define AX_RXD_RX_STATISTICS BIT(26) 150 151 /* RX WD dword4 */ 152 #define AX_RXD_TYPE_MASK GENMASK(1, 0) 153 #define AX_RXD_MC BIT(2) 154 #define AX_RXD_BC BIT(3) 155 #define AX_RXD_MD BIT(4) 156 #define AX_RXD_MF BIT(5) 157 #define AX_RXD_PWR BIT(6) 158 #define AX_RXD_QOS BIT(7) 159 #define AX_RXD_TID_MASK GENMASK(11, 8) 160 #define AX_RXD_EOSP BIT(12) 161 #define AX_RXD_HTC BIT(13) 162 #define AX_RXD_QNULL BIT(14) 163 #define AX_RXD_SEQ_MASK GENMASK(27, 16) 164 #define AX_RXD_FRAG_MASK GENMASK(31, 28) 165 166 /* RX WD dword5 */ 167 #define AX_RXD_SEC_CAM_IDX_MASK GENMASK(7, 0) 168 #define AX_RXD_ADDR_CAM_MASK GENMASK(15, 8) 169 #define AX_RXD_MAC_ID_MASK GENMASK(23, 16) 170 #define AX_RXD_RX_PL_ID_MASK GENMASK(27, 24) 171 #define AX_RXD_ADDR_CAM_VLD BIT(28) 172 #define AX_RXD_ADDR_FWD_EN BIT(29) 173 #define AX_RXD_RX_PL_MATCH BIT(30) 174 175 /* RX WD dword6 */ 176 #define AX_RXD_MAC_ADDR_MASK GENMASK(31, 0) 177 178 /* RX WD dword7 */ 179 #define AX_RXD_MAC_ADDR_H_MASK GENMASK(15, 0) 180 #define AX_RXD_SMART_ANT BIT(16) 181 #define AX_RXD_SEC_TYPE_MASK GENMASK(20, 17) 182 #define AX_RXD_HDR_CNV BIT(21) 183 #define AX_RXD_HDR_OFFSET_MASK GENMASK(26, 22) 184 #define AX_RXD_BIP_KEYID BIT(27) 185 #define AX_RXD_BIP_ENC BIT(28) 186 187 /* RX DESC helpers */ 188 /* Short Descriptor */ 189 #define RTW89_GET_RXWD_LONG_RXD(rxdesc) \ 190 le32_get_bits((rxdesc)->dword0, BIT(31)) 191 #define RTW89_GET_RXWD_DRV_INFO_SIZE(rxdesc) \ 192 le32_get_bits((rxdesc)->dword0, GENMASK(30, 28)) 193 #define RTW89_GET_RXWD_RPKT_TYPE(rxdesc) \ 194 le32_get_bits((rxdesc)->dword0, GENMASK(27, 24)) 195 #define RTW89_GET_RXWD_MAC_INFO_VALID(rxdesc) \ 196 le32_get_bits((rxdesc)->dword0, BIT(23)) 197 #define RTW89_GET_RXWD_BB_SEL(rxdesc) \ 198 le32_get_bits((rxdesc)->dword0, BIT(22)) 199 #define RTW89_GET_RXWD_HD_IV_LEN(rxdesc) \ 200 le32_get_bits((rxdesc)->dword0, GENMASK(21, 16)) 201 #define RTW89_GET_RXWD_SHIFT(rxdesc) \ 202 le32_get_bits((rxdesc)->dword0, GENMASK(15, 14)) 203 #define RTW89_GET_RXWD_PKT_SIZE(rxdesc) \ 204 le32_get_bits((rxdesc)->dword0, GENMASK(13, 0)) 205 #define RTW89_GET_RXWD_BW(rxdesc) \ 206 le32_get_bits((rxdesc)->dword1, GENMASK(31, 30)) 207 #define RTW89_GET_RXWD_BW_V1(rxdesc) \ 208 le32_get_bits((rxdesc)->dword1, GENMASK(31, 29)) 209 #define RTW89_GET_RXWD_GI_LTF(rxdesc) \ 210 le32_get_bits((rxdesc)->dword1, GENMASK(27, 25)) 211 #define RTW89_GET_RXWD_DATA_RATE(rxdesc) \ 212 le32_get_bits((rxdesc)->dword1, GENMASK(24, 16)) 213 #define RTW89_GET_RXWD_USER_ID(rxdesc) \ 214 le32_get_bits((rxdesc)->dword1, GENMASK(15, 8)) 215 #define RTW89_GET_RXWD_SR_EN(rxdesc) \ 216 le32_get_bits((rxdesc)->dword1, BIT(7)) 217 #define RTW89_GET_RXWD_PPDU_CNT(rxdesc) \ 218 le32_get_bits((rxdesc)->dword1, GENMASK(6, 4)) 219 #define RTW89_GET_RXWD_PPDU_TYPE(rxdesc) \ 220 le32_get_bits((rxdesc)->dword1, GENMASK(3, 0)) 221 #define RTW89_GET_RXWD_FREE_RUN_CNT(rxdesc) \ 222 le32_get_bits((rxdesc)->dword2, GENMASK(31, 0)) 223 #define RTW89_GET_RXWD_ICV_ERR(rxdesc) \ 224 le32_get_bits((rxdesc)->dword3, BIT(10)) 225 #define RTW89_GET_RXWD_CRC32_ERR(rxdesc) \ 226 le32_get_bits((rxdesc)->dword3, BIT(9)) 227 #define RTW89_GET_RXWD_HW_DEC(rxdesc) \ 228 le32_get_bits((rxdesc)->dword3, BIT(2)) 229 #define RTW89_GET_RXWD_SW_DEC(rxdesc) \ 230 le32_get_bits((rxdesc)->dword3, BIT(1)) 231 #define RTW89_GET_RXWD_A1_MATCH(rxdesc) \ 232 le32_get_bits((rxdesc)->dword3, BIT(0)) 233 234 /* Long Descriptor */ 235 #define RTW89_GET_RXWD_FRAG(rxdesc) \ 236 le32_get_bits((rxdesc)->dword4, GENMASK(31, 28)) 237 #define RTW89_GET_RXWD_SEQ(rxdesc) \ 238 le32_get_bits((rxdesc)->dword4, GENMASK(27, 16)) 239 #define RTW89_GET_RXWD_TYPE(rxdesc) \ 240 le32_get_bits((rxdesc)->dword4, GENMASK(1, 0)) 241 #define RTW89_GET_RXWD_ADDR_CAM_VLD(rxdesc) \ 242 le32_get_bits((rxdesc)->dword5, BIT(28)) 243 #define RTW89_GET_RXWD_RX_PL_ID(rxdesc) \ 244 le32_get_bits((rxdesc)->dword5, GENMASK(27, 24)) 245 #define RTW89_GET_RXWD_MAC_ID(rxdesc) \ 246 le32_get_bits((rxdesc)->dword5, GENMASK(23, 16)) 247 #define RTW89_GET_RXWD_ADDR_CAM_ID(rxdesc) \ 248 le32_get_bits((rxdesc)->dword5, GENMASK(15, 8)) 249 #define RTW89_GET_RXWD_SEC_CAM_ID(rxdesc) \ 250 le32_get_bits((rxdesc)->dword5, GENMASK(7, 0)) 251 252 #define RTW89_GET_RXINFO_USR_NUM(rpt) \ 253 le32_get_bits(*((const __le32 *)rpt), GENMASK(3, 0)) 254 #define RTW89_GET_RXINFO_FW_DEFINE(rpt) \ 255 le32_get_bits(*((const __le32 *)rpt), GENMASK(15, 8)) 256 #define RTW89_GET_RXINFO_LSIG_LEN(rpt) \ 257 le32_get_bits(*((const __le32 *)rpt), GENMASK(27, 16)) 258 #define RTW89_GET_RXINFO_IS_TO_SELF(rpt) \ 259 le32_get_bits(*((const __le32 *)rpt), BIT(28)) 260 #define RTW89_GET_RXINFO_RX_CNT_VLD(rpt) \ 261 le32_get_bits(*((const __le32 *)rpt), BIT(29)) 262 #define RTW89_GET_RXINFO_LONG_RXD(rpt) \ 263 le32_get_bits(*((const __le32 *)rpt), GENMASK(31, 30)) 264 #define RTW89_GET_RXINFO_SERVICE(rpt) \ 265 le32_get_bits(*((const __le32 *)(rpt) + 1), GENMASK(15, 0)) 266 #define RTW89_GET_RXINFO_PLCP_LEN(rpt) \ 267 le32_get_bits(*((const __le32 *)(rpt) + 1), GENMASK(23, 16)) 268 #define RTW89_GET_RXINFO_MAC_ID_VALID(rpt, usr) \ 269 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(0)) 270 #define RTW89_GET_RXINFO_DATA(rpt, usr) \ 271 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(1)) 272 #define RTW89_GET_RXINFO_CTRL(rpt, usr) \ 273 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(2)) 274 #define RTW89_GET_RXINFO_MGMT(rpt, usr) \ 275 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(3)) 276 #define RTW89_GET_RXINFO_BCM(rpt, usr) \ 277 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), BIT(4)) 278 #define RTW89_GET_RXINFO_MACID(rpt, usr) \ 279 le32_get_bits(*((const __le32 *)(rpt) + (usr) + 2), GENMASK(15, 8)) 280 281 #define RTW89_GET_PHY_STS_IE_MAP(sts) \ 282 le32_get_bits(*((const __le32 *)(sts)), GENMASK(4, 0)) 283 #define RTW89_GET_PHY_STS_RSSI_A(sts) \ 284 le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(7, 0)) 285 #define RTW89_GET_PHY_STS_RSSI_B(sts) \ 286 le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(15, 8)) 287 #define RTW89_GET_PHY_STS_RSSI_C(sts) \ 288 le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(23, 16)) 289 #define RTW89_GET_PHY_STS_RSSI_D(sts) \ 290 le32_get_bits(*((const __le32 *)(sts) + 1), GENMASK(31, 24)) 291 #define RTW89_GET_PHY_STS_LEN(sts) \ 292 le32_get_bits(*((const __le32 *)sts), GENMASK(15, 8)) 293 #define RTW89_GET_PHY_STS_RSSI_AVG(sts) \ 294 le32_get_bits(*((const __le32 *)sts), GENMASK(31, 24)) 295 #define RTW89_GET_PHY_STS_IE_TYPE(ie) \ 296 le32_get_bits(*((const __le32 *)ie), GENMASK(4, 0)) 297 #define RTW89_GET_PHY_STS_IE_LEN(ie) \ 298 le32_get_bits(*((const __le32 *)ie), GENMASK(11, 5)) 299 #define RTW89_GET_PHY_STS_IE01_CH_IDX(ie) \ 300 le32_get_bits(*((const __le32 *)ie), GENMASK(23, 16)) 301 #define RTW89_GET_PHY_STS_IE01_CFO(ie) \ 302 le32_get_bits(*((const __le32 *)(ie) + 1), GENMASK(31, 20)) 303 304 enum rtw89_tx_channel { 305 RTW89_TXCH_ACH0 = 0, 306 RTW89_TXCH_ACH1 = 1, 307 RTW89_TXCH_ACH2 = 2, 308 RTW89_TXCH_ACH3 = 3, 309 RTW89_TXCH_ACH4 = 4, 310 RTW89_TXCH_ACH5 = 5, 311 RTW89_TXCH_ACH6 = 6, 312 RTW89_TXCH_ACH7 = 7, 313 RTW89_TXCH_CH8 = 8, /* MGMT Band 0 */ 314 RTW89_TXCH_CH9 = 9, /* HI Band 0 */ 315 RTW89_TXCH_CH10 = 10, /* MGMT Band 1 */ 316 RTW89_TXCH_CH11 = 11, /* HI Band 1 */ 317 RTW89_TXCH_CH12 = 12, /* FW CMD */ 318 319 /* keep last */ 320 RTW89_TXCH_NUM, 321 RTW89_TXCH_MAX = RTW89_TXCH_NUM - 1 322 }; 323 324 enum rtw89_rx_channel { 325 RTW89_RXCH_RXQ = 0, 326 RTW89_RXCH_RPQ = 1, 327 328 /* keep last */ 329 RTW89_RXCH_NUM, 330 RTW89_RXCH_MAX = RTW89_RXCH_NUM - 1 331 }; 332 333 enum rtw89_tx_qsel { 334 RTW89_TX_QSEL_BE_0 = 0x00, 335 RTW89_TX_QSEL_BK_0 = 0x01, 336 RTW89_TX_QSEL_VI_0 = 0x02, 337 RTW89_TX_QSEL_VO_0 = 0x03, 338 RTW89_TX_QSEL_BE_1 = 0x04, 339 RTW89_TX_QSEL_BK_1 = 0x05, 340 RTW89_TX_QSEL_VI_1 = 0x06, 341 RTW89_TX_QSEL_VO_1 = 0x07, 342 RTW89_TX_QSEL_BE_2 = 0x08, 343 RTW89_TX_QSEL_BK_2 = 0x09, 344 RTW89_TX_QSEL_VI_2 = 0x0a, 345 RTW89_TX_QSEL_VO_2 = 0x0b, 346 RTW89_TX_QSEL_BE_3 = 0x0c, 347 RTW89_TX_QSEL_BK_3 = 0x0d, 348 RTW89_TX_QSEL_VI_3 = 0x0e, 349 RTW89_TX_QSEL_VO_3 = 0x0f, 350 RTW89_TX_QSEL_B0_BCN = 0x10, 351 RTW89_TX_QSEL_B0_HI = 0x11, 352 RTW89_TX_QSEL_B0_MGMT = 0x12, 353 RTW89_TX_QSEL_B0_NOPS = 0x13, 354 RTW89_TX_QSEL_B0_MGMT_FAST = 0x14, 355 /* reserved */ 356 /* reserved */ 357 /* reserved */ 358 RTW89_TX_QSEL_B1_BCN = 0x18, 359 RTW89_TX_QSEL_B1_HI = 0x19, 360 RTW89_TX_QSEL_B1_MGMT = 0x1a, 361 RTW89_TX_QSEL_B1_NOPS = 0x1b, 362 RTW89_TX_QSEL_B1_MGMT_FAST = 0x1c, 363 /* reserved */ 364 /* reserved */ 365 /* reserved */ 366 }; 367 368 static inline u8 rtw89_core_get_qsel(struct rtw89_dev *rtwdev, u8 tid) 369 { 370 switch (tid) { 371 default: 372 rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid); 373 fallthrough; 374 case 0: 375 case 3: 376 return RTW89_TX_QSEL_BE_0; 377 case 1: 378 case 2: 379 return RTW89_TX_QSEL_BK_0; 380 case 4: 381 case 5: 382 return RTW89_TX_QSEL_VI_0; 383 case 6: 384 case 7: 385 return RTW89_TX_QSEL_VO_0; 386 } 387 } 388 389 static inline u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel) 390 { 391 switch (qsel) { 392 default: 393 rtw89_warn(rtwdev, "Cannot map qsel to dma: %d\n", qsel); 394 fallthrough; 395 case RTW89_TX_QSEL_BE_0: 396 return RTW89_TXCH_ACH0; 397 case RTW89_TX_QSEL_BK_0: 398 return RTW89_TXCH_ACH1; 399 case RTW89_TX_QSEL_VI_0: 400 return RTW89_TXCH_ACH2; 401 case RTW89_TX_QSEL_VO_0: 402 return RTW89_TXCH_ACH3; 403 case RTW89_TX_QSEL_B0_MGMT: 404 return RTW89_TXCH_CH8; 405 case RTW89_TX_QSEL_B0_HI: 406 return RTW89_TXCH_CH9; 407 case RTW89_TX_QSEL_B1_MGMT: 408 return RTW89_TXCH_CH10; 409 case RTW89_TX_QSEL_B1_HI: 410 return RTW89_TXCH_CH11; 411 } 412 } 413 414 static inline u8 rtw89_core_get_tid_indicate(struct rtw89_dev *rtwdev, u8 tid) 415 { 416 switch (tid) { 417 case 3: 418 case 2: 419 case 5: 420 case 7: 421 return 1; 422 default: 423 rtw89_warn(rtwdev, "Should use tag 1d: %d\n", tid); 424 fallthrough; 425 case 0: 426 case 1: 427 case 4: 428 case 6: 429 return 0; 430 } 431 } 432 433 #endif 434