1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2022 Realtek Corporation 3 */ 4 5 #include "chan.h" 6 #include "coex.h" 7 #include "debug.h" 8 #include "fw.h" 9 #include "mac.h" 10 #include "phy.h" 11 #include "reg.h" 12 #include "rtw8852c.h" 13 #include "rtw8852c_rfk.h" 14 #include "rtw8852c_table.h" 15 #include "util.h" 16 17 #define RTW8852C_FW_FORMAT_MAX 0 18 #define RTW8852C_FW_BASENAME "rtw89/rtw8852c_fw" 19 #define RTW8852C_MODULE_FIRMWARE \ 20 RTW8852C_FW_BASENAME ".bin" 21 22 static const struct rtw89_hfc_ch_cfg rtw8852c_hfc_chcfg_pcie[] = { 23 {13, 1614, grp_0}, /* ACH 0 */ 24 {13, 1614, grp_0}, /* ACH 1 */ 25 {13, 1614, grp_0}, /* ACH 2 */ 26 {13, 1614, grp_0}, /* ACH 3 */ 27 {13, 1614, grp_1}, /* ACH 4 */ 28 {13, 1614, grp_1}, /* ACH 5 */ 29 {13, 1614, grp_1}, /* ACH 6 */ 30 {13, 1614, grp_1}, /* ACH 7 */ 31 {13, 1614, grp_0}, /* B0MGQ */ 32 {13, 1614, grp_0}, /* B0HIQ */ 33 {13, 1614, grp_1}, /* B1MGQ */ 34 {13, 1614, grp_1}, /* B1HIQ */ 35 {40, 0, 0} /* FWCMDQ */ 36 }; 37 38 static const struct rtw89_hfc_pub_cfg rtw8852c_hfc_pubcfg_pcie = { 39 1614, /* Group 0 */ 40 1614, /* Group 1 */ 41 3228, /* Public Max */ 42 0 /* WP threshold */ 43 }; 44 45 static const struct rtw89_hfc_param_ini rtw8852c_hfc_param_ini_pcie[] = { 46 [RTW89_QTA_SCC] = {rtw8852c_hfc_chcfg_pcie, &rtw8852c_hfc_pubcfg_pcie, 47 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 48 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 49 RTW89_HCIFC_POH}, 50 [RTW89_QTA_INVALID] = {NULL}, 51 }; 52 53 static const struct rtw89_dle_mem rtw8852c_dle_mem_pcie[] = { 54 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size19, 55 &rtw89_mac_size.ple_size19, &rtw89_mac_size.wde_qt18, 56 &rtw89_mac_size.wde_qt18, &rtw89_mac_size.ple_qt46, 57 &rtw89_mac_size.ple_qt47}, 58 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18, 59 &rtw89_mac_size.ple_size18, &rtw89_mac_size.wde_qt17, 60 &rtw89_mac_size.wde_qt17, &rtw89_mac_size.ple_qt44, 61 &rtw89_mac_size.ple_qt45}, 62 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 63 NULL}, 64 }; 65 66 static const u32 rtw8852c_h2c_regs[RTW89_H2CREG_MAX] = { 67 R_AX_H2CREG_DATA0_V1, R_AX_H2CREG_DATA1_V1, R_AX_H2CREG_DATA2_V1, 68 R_AX_H2CREG_DATA3_V1 69 }; 70 71 static const u32 rtw8852c_c2h_regs[RTW89_H2CREG_MAX] = { 72 R_AX_C2HREG_DATA0_V1, R_AX_C2HREG_DATA1_V1, R_AX_C2HREG_DATA2_V1, 73 R_AX_C2HREG_DATA3_V1 74 }; 75 76 static const u32 rtw8852c_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = { 77 R_AX_C2HREG_DATA3_V1 + 3, R_AX_DBG_WOW, 78 }; 79 80 static const struct rtw89_page_regs rtw8852c_page_regs = { 81 .hci_fc_ctrl = R_AX_HCI_FC_CTRL_V1, 82 .ch_page_ctrl = R_AX_CH_PAGE_CTRL_V1, 83 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL_V1, 84 .ach_page_info = R_AX_ACH0_PAGE_INFO_V1, 85 .pub_page_info3 = R_AX_PUB_PAGE_INFO3_V1, 86 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1_V1, 87 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2_V1, 88 .pub_page_info1 = R_AX_PUB_PAGE_INFO1_V1, 89 .pub_page_info2 = R_AX_PUB_PAGE_INFO2_V1, 90 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1_V1, 91 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2_V1, 92 .wp_page_info1 = R_AX_WP_PAGE_INFO1_V1, 93 }; 94 95 static const struct rtw89_reg_def rtw8852c_dcfo_comp = { 96 R_DCFO_COMP_S0_V1, B_DCFO_COMP_S0_V1_MSK 97 }; 98 99 static const struct rtw89_imr_info rtw8852c_imr_info = { 100 .wdrls_imr_set = B_AX_WDRLS_IMR_SET_V1, 101 .wsec_imr_reg = R_AX_SEC_ERROR_FLAG_IMR, 102 .wsec_imr_set = B_AX_TX_HANG_IMR | B_AX_RX_HANG_IMR, 103 .mpdu_tx_imr_set = B_AX_MPDU_TX_IMR_SET_V1, 104 .mpdu_rx_imr_set = B_AX_MPDU_RX_IMR_SET_V1, 105 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 106 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_B0_ERRFLAG_IMR, 107 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR_V1, 108 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET_V1, 109 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_B1_ERRFLAG_IMR, 110 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR_V1, 111 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET_V1, 112 .wde_imr_clr = B_AX_WDE_IMR_CLR_V1, 113 .wde_imr_set = B_AX_WDE_IMR_SET_V1, 114 .ple_imr_clr = B_AX_PLE_IMR_CLR_V1, 115 .ple_imr_set = B_AX_PLE_IMR_SET_V1, 116 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR_V1, 117 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET_V1, 118 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR_V1, 119 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET_V1, 120 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR_V1, 121 .other_disp_imr_set = B_AX_OTHER_DISP_IMR_SET_V1, 122 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR, 123 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR, 124 .bbrpt_err_imr_set = R_AX_BBRPT_CHINFO_IMR_SET_V1, 125 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR, 126 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_V1, 127 .ptcl_imr_set = B_AX_PTCL_IMR_SET_V1, 128 .cdma_imr_0_reg = R_AX_RX_ERR_FLAG_IMR, 129 .cdma_imr_0_clr = B_AX_RX_ERR_IMR_CLR_V1, 130 .cdma_imr_0_set = B_AX_RX_ERR_IMR_SET_V1, 131 .cdma_imr_1_reg = R_AX_TX_ERR_FLAG_IMR, 132 .cdma_imr_1_clr = B_AX_TX_ERR_IMR_CLR_V1, 133 .cdma_imr_1_set = B_AX_TX_ERR_IMR_SET_V1, 134 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR_V1, 135 .phy_intf_imr_clr = B_AX_PHYINFO_IMR_CLR_V1, 136 .phy_intf_imr_set = B_AX_PHYINFO_IMR_SET_V1, 137 .rmac_imr_reg = R_AX_RX_ERR_IMR, 138 .rmac_imr_clr = B_AX_RMAC_IMR_CLR_V1, 139 .rmac_imr_set = B_AX_RMAC_IMR_SET_V1, 140 .tmac_imr_reg = R_AX_TRXPTCL_ERROR_INDICA_MASK, 141 .tmac_imr_clr = B_AX_TMAC_IMR_CLR_V1, 142 .tmac_imr_set = B_AX_TMAC_IMR_SET_V1, 143 }; 144 145 static const struct rtw89_rrsr_cfgs rtw8852c_rrsr_cfgs = { 146 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 147 .rsc = {R_AX_PTCL_RRSR1, B_AX_RSC_MASK, 2}, 148 }; 149 150 static const struct rtw89_dig_regs rtw8852c_dig_regs = { 151 .seg0_pd_reg = R_SEG0R_PD, 152 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 153 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, 154 .bmode_pd_reg = R_BMODE_PDTH_EN_V1, 155 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, 156 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, 157 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, 158 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, 159 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, 160 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, 161 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1}, 162 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1}, 163 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1}, 164 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1, 165 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 166 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1, 167 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 168 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1, 169 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 170 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1, 171 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 172 }; 173 174 static const struct rtw89_edcca_regs rtw8852c_edcca_regs = { 175 .edcca_level = R_SEG0R_EDCCA_LVL, 176 .edcca_mask = B_EDCCA_LVL_MSK0, 177 .edcca_p_mask = B_EDCCA_LVL_MSK1, 178 .ppdu_level = R_SEG0R_EDCCA_LVL, 179 .ppdu_mask = B_EDCCA_LVL_MSK3, 180 .rpt_a = R_EDCCA_RPT_A, 181 .rpt_b = R_EDCCA_RPT_B, 182 .rpt_sel = R_EDCCA_RPT_SEL, 183 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK, 184 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST, 185 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M, 186 }; 187 188 static void rtw8852c_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 189 enum rtw89_phy_idx phy_idx); 190 191 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, 192 enum rtw89_mac_idx mac_idx); 193 194 static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev) 195 { 196 u32 val32; 197 u32 ret; 198 199 val32 = rtw89_read32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_PAD_HCI_SEL_V2_MASK); 200 if (val32 == MAC_AX_HCI_SEL_PCIE_USB) 201 rtw89_write32_set(rtwdev, R_AX_LDO_AON_CTRL0, B_AX_PD_REGU_L); 202 203 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN | 204 B_AX_AFSM_PCIE_SUS_EN); 205 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC); 206 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC); 207 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN); 208 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 209 210 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 211 B_AX_OCP_L1_MASK, 0x7); 212 213 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR, 214 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 215 if (ret) 216 return ret; 217 218 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 219 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 220 221 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC), 222 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 223 if (ret) 224 return ret; 225 226 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 227 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 228 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 229 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 230 231 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 232 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1); 233 234 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_CMAC1_FEN); 235 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_R_SYM_ISO_CMAC12PP); 236 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, B_AX_R_SYM_WLCMAC1_P4_PC_EN | 237 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 238 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 239 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 240 B_AX_R_SYM_WLCMAC1_PC_EN); 241 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 242 243 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 244 XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL); 245 if (ret) 246 return ret; 247 248 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 249 250 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 251 XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL); 252 if (ret) 253 return ret; 254 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI, 255 XTAL_SI_OFF_WEI); 256 if (ret) 257 return ret; 258 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI, 259 XTAL_SI_OFF_EI); 260 if (ret) 261 return ret; 262 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF); 263 if (ret) 264 return ret; 265 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI, 266 XTAL_SI_PON_WEI); 267 if (ret) 268 return ret; 269 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI, 270 XTAL_SI_PON_EI); 271 if (ret) 272 return ret; 273 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC); 274 if (ret) 275 return ret; 276 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0x10, XTAL_SI_LDO_LPS); 277 if (ret) 278 return ret; 279 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP); 280 if (ret) 281 return ret; 282 283 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 284 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE); 285 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15); 286 287 fsleep(1000); 288 289 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14); 290 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 291 rtw89_write32_set(rtwdev, R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN, 292 B_AX_EECS_PULL_LOW_EN | B_AX_EESK_PULL_LOW_EN | 293 B_AX_LED1_PULL_LOW_EN); 294 295 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 296 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN | 297 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN | 298 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN | 299 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN | 300 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN | 301 B_AX_MAC_UN_EN | B_AX_H_AXIDMA_EN); 302 303 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN, 304 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 305 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | 306 B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | 307 B_AX_TMAC_EN | B_AX_RMAC_EN); 308 309 rtw89_write32_mask(rtwdev, R_AX_LED1_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK, 310 PINMUX_EESK_FUNC_SEL_BT_LOG); 311 312 return 0; 313 } 314 315 static int rtw8852c_pwr_off_func(struct rtw89_dev *rtwdev) 316 { 317 u32 val32; 318 u32 ret; 319 320 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF, 321 XTAL_SI_RFC2RF); 322 if (ret) 323 return ret; 324 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI); 325 if (ret) 326 return ret; 327 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI); 328 if (ret) 329 return ret; 330 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00); 331 if (ret) 332 return ret; 333 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10); 334 if (ret) 335 return ret; 336 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC, 337 XTAL_SI_SRAM2RFC); 338 if (ret) 339 return ret; 340 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI); 341 if (ret) 342 return ret; 343 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI); 344 if (ret) 345 return ret; 346 347 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 348 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 349 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB); 350 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 351 B_AX_R_SYM_FEN_WLBBGLB_1 | B_AX_R_SYM_FEN_WLBBFUN_1); 352 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 353 354 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL); 355 if (ret) 356 return ret; 357 358 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 359 360 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL); 361 if (ret) 362 return ret; 363 364 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC); 365 366 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC), 367 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 368 if (ret) 369 return ret; 370 371 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, SW_LPS_OPTION); 372 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE); 373 rtw89_write32_set(rtwdev, R_AX_SYS_SWR_CTRL1, B_AX_SYM_CTRL_SPS_PWMFREQ); 374 rtw89_write32_mask(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 375 B_AX_REG_ZCDC_H_MASK, 0x3); 376 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 377 378 return 0; 379 } 380 381 static void rtw8852c_e_efuse_parsing(struct rtw89_efuse *efuse, 382 struct rtw8852c_efuse *map) 383 { 384 ether_addr_copy(efuse->addr, map->e.mac_addr); 385 efuse->rfe_type = map->rfe_type; 386 efuse->xtal_cap = map->xtal_k; 387 } 388 389 static void rtw8852c_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 390 struct rtw8852c_efuse *map) 391 { 392 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 393 struct rtw8852c_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 394 u8 *bw40_1s_tssi_6g_ofst[] = {map->bw40_1s_tssi_6g_a, map->bw40_1s_tssi_6g_b}; 395 u8 i, j; 396 397 tssi->thermal[RF_PATH_A] = map->path_a_therm; 398 tssi->thermal[RF_PATH_B] = map->path_b_therm; 399 400 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 401 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 402 sizeof(ofst[i]->cck_tssi)); 403 404 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 405 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 406 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 407 i, j, tssi->tssi_cck[i][j]); 408 409 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 410 sizeof(ofst[i]->bw40_tssi)); 411 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 412 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 413 memcpy(tssi->tssi_6g_mcs[i], bw40_1s_tssi_6g_ofst[i], 414 sizeof(tssi->tssi_6g_mcs[i])); 415 416 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 417 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 418 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 419 i, j, tssi->tssi_mcs[i][j]); 420 } 421 } 422 423 static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low) 424 { 425 if (high) 426 *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3); 427 if (low) 428 *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3); 429 430 return data != 0xff; 431 } 432 433 static void rtw8852c_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev, 434 struct rtw8852c_efuse *map) 435 { 436 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 437 bool valid = false; 438 439 valid |= _decode_efuse_gain(map->rx_gain_2g_cck, 440 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK], 441 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]); 442 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm, 443 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM], 444 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]); 445 valid |= _decode_efuse_gain(map->rx_gain_5g_low, 446 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW], 447 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]); 448 valid |= _decode_efuse_gain(map->rx_gain_5g_mid, 449 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID], 450 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]); 451 valid |= _decode_efuse_gain(map->rx_gain_5g_high, 452 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH], 453 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]); 454 valid |= _decode_efuse_gain(map->rx_gain_6g_l0, 455 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_L0], 456 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_L0]); 457 valid |= _decode_efuse_gain(map->rx_gain_6g_l1, 458 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_L1], 459 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_L1]); 460 valid |= _decode_efuse_gain(map->rx_gain_6g_m0, 461 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_M0], 462 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_M0]); 463 valid |= _decode_efuse_gain(map->rx_gain_6g_m1, 464 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_M1], 465 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_M1]); 466 valid |= _decode_efuse_gain(map->rx_gain_6g_h0, 467 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_H0], 468 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_H0]); 469 valid |= _decode_efuse_gain(map->rx_gain_6g_h1, 470 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_H1], 471 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_H1]); 472 valid |= _decode_efuse_gain(map->rx_gain_6g_uh0, 473 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_UH0], 474 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_UH0]); 475 valid |= _decode_efuse_gain(map->rx_gain_6g_uh1, 476 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_6G_UH1], 477 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_6G_UH1]); 478 479 gain->offset_valid = valid; 480 } 481 482 static int rtw8852c_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map, 483 enum rtw89_efuse_block block) 484 { 485 struct rtw89_efuse *efuse = &rtwdev->efuse; 486 struct rtw8852c_efuse *map; 487 488 map = (struct rtw8852c_efuse *)log_map; 489 490 efuse->country_code[0] = map->country_code[0]; 491 efuse->country_code[1] = map->country_code[1]; 492 rtw8852c_efuse_parsing_tssi(rtwdev, map); 493 rtw8852c_efuse_parsing_gain_offset(rtwdev, map); 494 495 switch (rtwdev->hci.type) { 496 case RTW89_HCI_TYPE_PCIE: 497 rtw8852c_e_efuse_parsing(efuse, map); 498 break; 499 default: 500 return -ENOTSUPP; 501 } 502 503 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 504 505 return 0; 506 } 507 508 static void rtw8852c_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 509 { 510 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 511 static const u32 tssi_trim_addr[RF_PATH_NUM_8852C] = {0x5D6, 0x5AB}; 512 static const u32 tssi_trim_addr_6g[RF_PATH_NUM_8852C] = {0x5CE, 0x5A3}; 513 u32 addr = rtwdev->chip->phycap_addr; 514 bool pg = false; 515 u32 ofst; 516 u8 i, j; 517 518 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 519 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 520 /* addrs are in decreasing order */ 521 ofst = tssi_trim_addr[i] - addr - j; 522 tssi->tssi_trim[i][j] = phycap_map[ofst]; 523 524 if (phycap_map[ofst] != 0xff) 525 pg = true; 526 } 527 528 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM_6G; j++) { 529 /* addrs are in decreasing order */ 530 ofst = tssi_trim_addr_6g[i] - addr - j; 531 tssi->tssi_trim_6g[i][j] = phycap_map[ofst]; 532 533 if (phycap_map[ofst] != 0xff) 534 pg = true; 535 } 536 } 537 538 if (!pg) { 539 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 540 memset(tssi->tssi_trim_6g, 0, sizeof(tssi->tssi_trim_6g)); 541 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 542 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 543 } 544 545 for (i = 0; i < RF_PATH_NUM_8852C; i++) 546 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 547 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 548 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 549 i, j, tssi->tssi_trim[i][j], 550 tssi_trim_addr[i] - j); 551 } 552 553 static void rtw8852c_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 554 u8 *phycap_map) 555 { 556 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 557 static const u32 thm_trim_addr[RF_PATH_NUM_8852C] = {0x5DF, 0x5DC}; 558 u32 addr = rtwdev->chip->phycap_addr; 559 u8 i; 560 561 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 562 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 563 564 rtw89_debug(rtwdev, RTW89_DBG_RFK, 565 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 566 i, info->thermal_trim[i]); 567 568 if (info->thermal_trim[i] != 0xff) 569 info->pg_thermal_trim = true; 570 } 571 } 572 573 static void rtw8852c_thermal_trim(struct rtw89_dev *rtwdev) 574 { 575 #define __thm_setting(raw) \ 576 ({ \ 577 u8 __v = (raw); \ 578 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 579 }) 580 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 581 u8 i, val; 582 583 if (!info->pg_thermal_trim) { 584 rtw89_debug(rtwdev, RTW89_DBG_RFK, 585 "[THERMAL][TRIM] no PG, do nothing\n"); 586 587 return; 588 } 589 590 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 591 val = __thm_setting(info->thermal_trim[i]); 592 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 593 594 rtw89_debug(rtwdev, RTW89_DBG_RFK, 595 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 596 i, val); 597 } 598 #undef __thm_setting 599 } 600 601 static void rtw8852c_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 602 u8 *phycap_map) 603 { 604 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 605 static const u32 pabias_trim_addr[RF_PATH_NUM_8852C] = {0x5DE, 0x5DB}; 606 u32 addr = rtwdev->chip->phycap_addr; 607 u8 i; 608 609 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 610 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 611 612 rtw89_debug(rtwdev, RTW89_DBG_RFK, 613 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 614 i, info->pa_bias_trim[i]); 615 616 if (info->pa_bias_trim[i] != 0xff) 617 info->pg_pa_bias_trim = true; 618 } 619 } 620 621 static void rtw8852c_pa_bias_trim(struct rtw89_dev *rtwdev) 622 { 623 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 624 u8 pabias_2g, pabias_5g; 625 u8 i; 626 627 if (!info->pg_pa_bias_trim) { 628 rtw89_debug(rtwdev, RTW89_DBG_RFK, 629 "[PA_BIAS][TRIM] no PG, do nothing\n"); 630 631 return; 632 } 633 634 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 635 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 636 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 637 638 rtw89_debug(rtwdev, RTW89_DBG_RFK, 639 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 640 i, pabias_2g, pabias_5g); 641 642 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 643 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 644 } 645 } 646 647 static int rtw8852c_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 648 { 649 rtw8852c_phycap_parsing_tssi(rtwdev, phycap_map); 650 rtw8852c_phycap_parsing_thermal_trim(rtwdev, phycap_map); 651 rtw8852c_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 652 653 return 0; 654 } 655 656 static void rtw8852c_power_trim(struct rtw89_dev *rtwdev) 657 { 658 rtw8852c_thermal_trim(rtwdev); 659 rtw8852c_pa_bias_trim(rtwdev); 660 } 661 662 static void rtw8852c_set_channel_mac(struct rtw89_dev *rtwdev, 663 const struct rtw89_chan *chan, 664 u8 mac_idx) 665 { 666 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); 667 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 668 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); 669 u8 txsc20 = 0, txsc40 = 0, txsc80 = 0; 670 u8 rf_mod_val = 0, chk_rate_mask = 0; 671 u32 txsc; 672 673 switch (chan->band_width) { 674 case RTW89_CHANNEL_WIDTH_160: 675 txsc80 = rtw89_phy_get_txsc(rtwdev, chan, 676 RTW89_CHANNEL_WIDTH_80); 677 fallthrough; 678 case RTW89_CHANNEL_WIDTH_80: 679 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, 680 RTW89_CHANNEL_WIDTH_40); 681 fallthrough; 682 case RTW89_CHANNEL_WIDTH_40: 683 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, 684 RTW89_CHANNEL_WIDTH_20); 685 break; 686 default: 687 break; 688 } 689 690 switch (chan->band_width) { 691 case RTW89_CHANNEL_WIDTH_160: 692 rf_mod_val = AX_WMAC_RFMOD_160M; 693 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) | 694 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40) | 695 FIELD_PREP(B_AX_TXSC_80M_MASK, txsc80); 696 break; 697 case RTW89_CHANNEL_WIDTH_80: 698 rf_mod_val = AX_WMAC_RFMOD_80M; 699 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) | 700 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40); 701 break; 702 case RTW89_CHANNEL_WIDTH_40: 703 rf_mod_val = AX_WMAC_RFMOD_40M; 704 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20); 705 break; 706 case RTW89_CHANNEL_WIDTH_20: 707 default: 708 rf_mod_val = AX_WMAC_RFMOD_20M; 709 txsc = 0; 710 break; 711 } 712 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, rf_mod_val); 713 rtw89_write32(rtwdev, sub_carr, txsc); 714 715 switch (chan->band_type) { 716 case RTW89_BAND_2G: 717 chk_rate_mask = B_AX_BAND_MODE; 718 break; 719 case RTW89_BAND_5G: 720 case RTW89_BAND_6G: 721 chk_rate_mask = B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6; 722 break; 723 default: 724 rtw89_warn(rtwdev, "Invalid band_type:%d\n", chan->band_type); 725 return; 726 } 727 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE | B_AX_CHECK_CCK_EN | 728 B_AX_RTS_LIMIT_IN_OFDM6); 729 rtw89_write8_set(rtwdev, chk_rate, chk_rate_mask); 730 } 731 732 static const u32 rtw8852c_sco_barker_threshold[14] = { 733 0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6, 734 0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a 735 }; 736 737 static const u32 rtw8852c_sco_cck_threshold[14] = { 738 0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db, 739 0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e 740 }; 741 742 static int rtw8852c_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 743 u8 primary_ch, enum rtw89_bandwidth bw) 744 { 745 u8 ch_element; 746 747 if (bw == RTW89_CHANNEL_WIDTH_20) { 748 ch_element = central_ch - 1; 749 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 750 if (primary_ch == 1) 751 ch_element = central_ch - 1 + 2; 752 else 753 ch_element = central_ch - 1 - 2; 754 } else { 755 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 756 return -EINVAL; 757 } 758 rtw89_phy_write32_mask(rtwdev, R_BK_FC0_INV_V1, B_BK_FC0_INV_MSK_V1, 759 rtw8852c_sco_barker_threshold[ch_element]); 760 rtw89_phy_write32_mask(rtwdev, R_CCK_FC0_INV_V1, B_CCK_FC0_INV_MSK_V1, 761 rtw8852c_sco_cck_threshold[ch_element]); 762 763 return 0; 764 } 765 766 struct rtw8852c_bb_gain { 767 u32 gain_g[BB_PATH_NUM_8852C]; 768 u32 gain_a[BB_PATH_NUM_8852C]; 769 u32 gain_mask; 770 }; 771 772 static const struct rtw8852c_bb_gain bb_gain_lna[LNA_GAIN_NUM] = { 773 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 774 .gain_mask = 0x00ff0000 }, 775 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 776 .gain_mask = 0xff000000 }, 777 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 778 .gain_mask = 0x000000ff }, 779 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 780 .gain_mask = 0x0000ff00 }, 781 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 782 .gain_mask = 0x00ff0000 }, 783 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 784 .gain_mask = 0xff000000 }, 785 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 786 .gain_mask = 0x000000ff }, 787 }; 788 789 static const struct rtw8852c_bb_gain bb_gain_tia[TIA_GAIN_NUM] = { 790 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 791 .gain_mask = 0x00ff0000 }, 792 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 793 .gain_mask = 0xff000000 }, 794 }; 795 796 struct rtw8852c_bb_gain_bypass { 797 u32 gain_g[BB_PATH_NUM_8852C]; 798 u32 gain_a[BB_PATH_NUM_8852C]; 799 u32 gain_mask_g; 800 u32 gain_mask_a; 801 }; 802 803 static 804 const struct rtw8852c_bb_gain_bypass bb_gain_bypass_lna[LNA_GAIN_NUM] = { 805 { .gain_g = {0x4BB8, 0x4C7C}, .gain_a = {0x4BB4, 0x4C78}, 806 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff}, 807 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 808 .gain_mask_g = 0xff, .gain_mask_a = 0xff00}, 809 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 810 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000}, 811 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 812 .gain_mask_g = 0xff0000, .gain_mask_a = 0xff000000}, 813 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB8, 0x4C7C}, 814 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff}, 815 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C}, 816 .gain_mask_g = 0xff, .gain_mask_a = 0xff00}, 817 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C}, 818 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000}, 819 }; 820 821 struct rtw8852c_bb_gain_op1db { 822 struct { 823 u32 lna[BB_PATH_NUM_8852C]; 824 u32 tia_lna[BB_PATH_NUM_8852C]; 825 u32 mask; 826 } reg[LNA_GAIN_NUM]; 827 u32 reg_tia0_lna6[BB_PATH_NUM_8852C]; 828 u32 mask_tia0_lna6; 829 }; 830 831 static const struct rtw8852c_bb_gain_op1db bb_gain_op1db_a = { 832 .reg = { 833 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 834 .mask = 0xff}, 835 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 836 .mask = 0xff00}, 837 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 838 .mask = 0xff0000}, 839 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 840 .mask = 0xff000000}, 841 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 842 .mask = 0xff}, 843 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 844 .mask = 0xff00}, 845 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 846 .mask = 0xff0000}, 847 }, 848 .reg_tia0_lna6 = {0x4674, 0x4758}, 849 .mask_tia0_lna6 = 0xff000000, 850 }; 851 852 static void rtw8852c_set_gain_error(struct rtw89_dev *rtwdev, 853 enum rtw89_subband subband, 854 enum rtw89_rf_path path) 855 { 856 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 857 u8 gain_band = rtw89_subband_to_bb_gain_band(subband); 858 s32 val; 859 u32 reg; 860 u32 mask; 861 int i; 862 863 for (i = 0; i < LNA_GAIN_NUM; i++) { 864 if (subband == RTW89_CH_2G) 865 reg = bb_gain_lna[i].gain_g[path]; 866 else 867 reg = bb_gain_lna[i].gain_a[path]; 868 869 mask = bb_gain_lna[i].gain_mask; 870 val = gain->lna_gain[gain_band][path][i]; 871 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 872 873 if (subband == RTW89_CH_2G) { 874 reg = bb_gain_bypass_lna[i].gain_g[path]; 875 mask = bb_gain_bypass_lna[i].gain_mask_g; 876 } else { 877 reg = bb_gain_bypass_lna[i].gain_a[path]; 878 mask = bb_gain_bypass_lna[i].gain_mask_a; 879 } 880 881 val = gain->lna_gain_bypass[gain_band][path][i]; 882 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 883 884 if (subband != RTW89_CH_2G) { 885 reg = bb_gain_op1db_a.reg[i].lna[path]; 886 mask = bb_gain_op1db_a.reg[i].mask; 887 val = gain->lna_op1db[gain_band][path][i]; 888 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 889 890 reg = bb_gain_op1db_a.reg[i].tia_lna[path]; 891 mask = bb_gain_op1db_a.reg[i].mask; 892 val = gain->tia_lna_op1db[gain_band][path][i]; 893 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 894 } 895 } 896 897 if (subband != RTW89_CH_2G) { 898 reg = bb_gain_op1db_a.reg_tia0_lna6[path]; 899 mask = bb_gain_op1db_a.mask_tia0_lna6; 900 val = gain->tia_lna_op1db[gain_band][path][7]; 901 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 902 } 903 904 for (i = 0; i < TIA_GAIN_NUM; i++) { 905 if (subband == RTW89_CH_2G) 906 reg = bb_gain_tia[i].gain_g[path]; 907 else 908 reg = bb_gain_tia[i].gain_a[path]; 909 910 mask = bb_gain_tia[i].gain_mask; 911 val = gain->tia_gain[gain_band][path][i]; 912 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 913 } 914 } 915 916 static void rtw8852c_set_gain_offset(struct rtw89_dev *rtwdev, 917 const struct rtw89_chan *chan, 918 enum rtw89_phy_idx phy_idx, 919 enum rtw89_rf_path path) 920 { 921 static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA0_LNA6_OP1DB_V1, 922 R_PATH1_G_TIA0_LNA6_OP1DB_V1}; 923 static const u32 rpl_mask[2] = {B_RPL_PATHA_MASK, B_RPL_PATHB_MASK}; 924 static const u32 rpl_tb_mask[2] = {B_RSSI_M_PATHA_MASK, B_RSSI_M_PATHB_MASK}; 925 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain; 926 enum rtw89_gain_offset gain_band; 927 s32 offset_q0, offset_base_q4; 928 s32 tmp = 0; 929 930 if (!efuse_gain->offset_valid) 931 return; 932 933 if (rtwdev->dbcc_en && path == RF_PATH_B) 934 phy_idx = RTW89_PHY_1; 935 936 if (chan->band_type == RTW89_BAND_2G) { 937 offset_q0 = efuse_gain->offset[path][RTW89_GAIN_OFFSET_2G_CCK]; 938 offset_base_q4 = efuse_gain->offset_base[phy_idx]; 939 940 tmp = clamp_t(s32, (-offset_q0 << 3) + (offset_base_q4 >> 1), 941 S8_MIN >> 1, S8_MAX >> 1); 942 rtw89_phy_write32_mask(rtwdev, R_RPL_OFST, B_RPL_OFST_MASK, tmp & 0x7f); 943 } 944 945 gain_band = rtw89_subband_to_gain_offset_band_of_ofdm(chan->subband_type); 946 947 offset_q0 = -efuse_gain->offset[path][gain_band]; 948 offset_base_q4 = efuse_gain->offset_base[phy_idx]; 949 950 tmp = (offset_q0 << 2) + (offset_base_q4 >> 2); 951 tmp = clamp_t(s32, -tmp, S8_MIN, S8_MAX); 952 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], B_PATH0_R_G_OFST_MASK, tmp & 0xff); 953 954 tmp = clamp_t(s32, offset_q0 << 4, S8_MIN, S8_MAX); 955 rtw89_phy_write32_idx(rtwdev, R_RPL_PATHAB, rpl_mask[path], tmp & 0xff, phy_idx); 956 rtw89_phy_write32_idx(rtwdev, R_RSSI_M_PATHAB, rpl_tb_mask[path], tmp & 0xff, phy_idx); 957 } 958 959 static void rtw8852c_ctrl_ch(struct rtw89_dev *rtwdev, 960 const struct rtw89_chan *chan, 961 enum rtw89_phy_idx phy_idx) 962 { 963 u8 sco; 964 u16 central_freq = chan->freq; 965 u8 central_ch = chan->channel; 966 u8 band = chan->band_type; 967 u8 subband = chan->subband_type; 968 bool is_2g = band == RTW89_BAND_2G; 969 u8 chan_idx; 970 971 if (!central_freq) { 972 rtw89_warn(rtwdev, "Invalid central_freq\n"); 973 return; 974 } 975 976 if (phy_idx == RTW89_PHY_0) { 977 /* Path A */ 978 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_A); 979 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_A); 980 981 if (is_2g) 982 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 983 B_PATH0_BAND_SEL_MSK_V1, 1, 984 phy_idx); 985 else 986 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 987 B_PATH0_BAND_SEL_MSK_V1, 0, 988 phy_idx); 989 /* Path B */ 990 if (!rtwdev->dbcc_en) { 991 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B); 992 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B); 993 994 if (is_2g) 995 rtw89_phy_write32_idx(rtwdev, 996 R_PATH1_BAND_SEL_V1, 997 B_PATH1_BAND_SEL_MSK_V1, 998 1, phy_idx); 999 else 1000 rtw89_phy_write32_idx(rtwdev, 1001 R_PATH1_BAND_SEL_V1, 1002 B_PATH1_BAND_SEL_MSK_V1, 1003 0, phy_idx); 1004 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 1005 } else { 1006 if (is_2g) 1007 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 1008 else 1009 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 1010 } 1011 /* SCO compensate FC setting */ 1012 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1, 1013 central_freq, phy_idx); 1014 /* round_up((1/fc0)*pow(2,18)) */ 1015 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq); 1016 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco, 1017 phy_idx); 1018 } else { 1019 /* Path B */ 1020 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B); 1021 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B); 1022 1023 if (is_2g) 1024 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 1025 B_PATH1_BAND_SEL_MSK_V1, 1026 1, phy_idx); 1027 else 1028 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 1029 B_PATH1_BAND_SEL_MSK_V1, 1030 0, phy_idx); 1031 /* SCO compensate FC setting */ 1032 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1, 1033 central_freq, phy_idx); 1034 /* round_up((1/fc0)*pow(2,18)) */ 1035 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq); 1036 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco, 1037 phy_idx); 1038 } 1039 /* CCK parameters */ 1040 if (band == RTW89_BAND_2G) { 1041 if (central_ch == 14) { 1042 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1, 1043 B_PCOEFF01_MSK_V1, 0x3b13ff); 1044 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1, 1045 B_PCOEFF23_MSK_V1, 0x1c42de); 1046 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1, 1047 B_PCOEFF45_MSK_V1, 0xfdb0ad); 1048 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1, 1049 B_PCOEFF67_MSK_V1, 0xf60f6e); 1050 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1, 1051 B_PCOEFF89_MSK_V1, 0xfd8f92); 1052 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1, 1053 B_PCOEFFAB_MSK_V1, 0x2d011); 1054 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1, 1055 B_PCOEFFCD_MSK_V1, 0x1c02c); 1056 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1, 1057 B_PCOEFFEF_MSK_V1, 0xfff00a); 1058 } else { 1059 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1, 1060 B_PCOEFF01_MSK_V1, 0x3d23ff); 1061 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1, 1062 B_PCOEFF23_MSK_V1, 0x29b354); 1063 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1, 1064 B_PCOEFF45_MSK_V1, 0xfc1c8); 1065 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1, 1066 B_PCOEFF67_MSK_V1, 0xfdb053); 1067 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1, 1068 B_PCOEFF89_MSK_V1, 0xf86f9a); 1069 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1, 1070 B_PCOEFFAB_MSK_V1, 0xfaef92); 1071 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1, 1072 B_PCOEFFCD_MSK_V1, 0xfe5fcc); 1073 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1, 1074 B_PCOEFFEF_MSK_V1, 0xffdff5); 1075 } 1076 } 1077 1078 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band); 1079 rtw89_phy_write32_idx(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx, phy_idx); 1080 } 1081 1082 static void rtw8852c_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 1083 { 1084 static const u32 adc_sel[2] = {0xC0EC, 0xC1EC}; 1085 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4}; 1086 1087 switch (bw) { 1088 case RTW89_CHANNEL_WIDTH_5: 1089 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 1090 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 1091 break; 1092 case RTW89_CHANNEL_WIDTH_10: 1093 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 1094 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 1095 break; 1096 case RTW89_CHANNEL_WIDTH_20: 1097 case RTW89_CHANNEL_WIDTH_40: 1098 case RTW89_CHANNEL_WIDTH_80: 1099 case RTW89_CHANNEL_WIDTH_160: 1100 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1101 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1102 break; 1103 default: 1104 rtw89_warn(rtwdev, "Fail to set ADC\n"); 1105 } 1106 } 1107 1108 static void rtw8852c_edcca_per20_bitmap_sifs(struct rtw89_dev *rtwdev, u8 bw, 1109 enum rtw89_phy_idx phy_idx) 1110 { 1111 if (bw == RTW89_CHANNEL_WIDTH_20) { 1112 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0xff, phy_idx); 1113 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx); 1114 } else { 1115 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0, phy_idx); 1116 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx); 1117 } 1118 } 1119 1120 static void 1121 rtw8852c_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 1122 enum rtw89_phy_idx phy_idx) 1123 { 1124 u8 mod_sbw = 0; 1125 1126 switch (bw) { 1127 case RTW89_CHANNEL_WIDTH_5: 1128 case RTW89_CHANNEL_WIDTH_10: 1129 case RTW89_CHANNEL_WIDTH_20: 1130 if (bw == RTW89_CHANNEL_WIDTH_5) 1131 mod_sbw = 0x1; 1132 else if (bw == RTW89_CHANNEL_WIDTH_10) 1133 mod_sbw = 0x2; 1134 else if (bw == RTW89_CHANNEL_WIDTH_20) 1135 mod_sbw = 0x0; 1136 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1137 phy_idx); 1138 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 1139 mod_sbw, phy_idx); 1140 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 0x0, 1141 phy_idx); 1142 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1143 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); 1144 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1145 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); 1146 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1147 B_PATH0_BW_SEL_MSK_V1, 0xf); 1148 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1149 B_PATH1_BW_SEL_MSK_V1, 0xf); 1150 break; 1151 case RTW89_CHANNEL_WIDTH_40: 1152 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 1153 phy_idx); 1154 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1155 phy_idx); 1156 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1157 pri_ch, 1158 phy_idx); 1159 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1160 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); 1161 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1162 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); 1163 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1164 B_PATH0_BW_SEL_MSK_V1, 0xf); 1165 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1166 B_PATH1_BW_SEL_MSK_V1, 0xf); 1167 break; 1168 case RTW89_CHANNEL_WIDTH_80: 1169 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 1170 phy_idx); 1171 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1172 phy_idx); 1173 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1174 pri_ch, 1175 phy_idx); 1176 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1177 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x2); 1178 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1179 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x2); 1180 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1181 B_PATH0_BW_SEL_MSK_V1, 0xd); 1182 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1183 B_PATH1_BW_SEL_MSK_V1, 0xd); 1184 break; 1185 case RTW89_CHANNEL_WIDTH_160: 1186 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x3, 1187 phy_idx); 1188 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1189 phy_idx); 1190 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1191 pri_ch, 1192 phy_idx); 1193 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1194 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x1); 1195 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1196 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x1); 1197 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1198 B_PATH0_BW_SEL_MSK_V1, 0xb); 1199 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1200 B_PATH1_BW_SEL_MSK_V1, 0xb); 1201 break; 1202 default: 1203 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1204 pri_ch); 1205 } 1206 1207 if (bw == RTW89_CHANNEL_WIDTH_40) { 1208 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1, 1209 B_RX_BW40_2XFFT_EN_MSK_V1, 0x1, phy_idx); 1210 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 1, phy_idx); 1211 } else { 1212 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1, 1213 B_RX_BW40_2XFFT_EN_MSK_V1, 0x0, phy_idx); 1214 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 0, phy_idx); 1215 } 1216 1217 if (phy_idx == RTW89_PHY_0) { 1218 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_A); 1219 if (!rtwdev->dbcc_en) 1220 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B); 1221 } else { 1222 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B); 1223 } 1224 1225 rtw8852c_edcca_per20_bitmap_sifs(rtwdev, bw, phy_idx); 1226 } 1227 1228 static u32 rtw8852c_spur_freq(struct rtw89_dev *rtwdev, 1229 const struct rtw89_chan *chan) 1230 { 1231 u8 center_chan = chan->channel; 1232 u8 bw = chan->band_width; 1233 1234 switch (chan->band_type) { 1235 case RTW89_BAND_2G: 1236 if (bw == RTW89_CHANNEL_WIDTH_20) { 1237 if (center_chan >= 5 && center_chan <= 8) 1238 return 2440; 1239 if (center_chan == 13) 1240 return 2480; 1241 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 1242 if (center_chan >= 3 && center_chan <= 10) 1243 return 2440; 1244 } 1245 break; 1246 case RTW89_BAND_5G: 1247 if (center_chan == 151 || center_chan == 153 || 1248 center_chan == 155 || center_chan == 163) 1249 return 5760; 1250 break; 1251 case RTW89_BAND_6G: 1252 if (center_chan == 195 || center_chan == 197 || 1253 center_chan == 199 || center_chan == 207) 1254 return 6920; 1255 break; 1256 default: 1257 break; 1258 } 1259 1260 return 0; 1261 } 1262 1263 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */ 1264 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */ 1265 #define MAX_TONE_NUM 2048 1266 1267 static void rtw8852c_set_csi_tone_idx(struct rtw89_dev *rtwdev, 1268 const struct rtw89_chan *chan, 1269 enum rtw89_phy_idx phy_idx) 1270 { 1271 u32 spur_freq; 1272 s32 freq_diff, csi_idx, csi_tone_idx; 1273 1274 spur_freq = rtw8852c_spur_freq(rtwdev, chan); 1275 if (spur_freq == 0) { 1276 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 0, phy_idx); 1277 return; 1278 } 1279 1280 freq_diff = (spur_freq - chan->freq) * 1000000; 1281 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125); 1282 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx); 1283 1284 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, csi_tone_idx, phy_idx); 1285 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1, phy_idx); 1286 } 1287 1288 static const struct rtw89_nbi_reg_def rtw8852c_nbi_reg_def[] = { 1289 [RF_PATH_A] = { 1290 .notch1_idx = {0x4C14, 0xFF}, 1291 .notch1_frac_idx = {0x4C14, 0xC00}, 1292 .notch1_en = {0x4C14, 0x1000}, 1293 .notch2_idx = {0x4C20, 0xFF}, 1294 .notch2_frac_idx = {0x4C20, 0xC00}, 1295 .notch2_en = {0x4C20, 0x1000}, 1296 }, 1297 [RF_PATH_B] = { 1298 .notch1_idx = {0x4CD8, 0xFF}, 1299 .notch1_frac_idx = {0x4CD8, 0xC00}, 1300 .notch1_en = {0x4CD8, 0x1000}, 1301 .notch2_idx = {0x4CE4, 0xFF}, 1302 .notch2_frac_idx = {0x4CE4, 0xC00}, 1303 .notch2_en = {0x4CE4, 0x1000}, 1304 }, 1305 }; 1306 1307 static void rtw8852c_set_nbi_tone_idx(struct rtw89_dev *rtwdev, 1308 const struct rtw89_chan *chan, 1309 enum rtw89_rf_path path) 1310 { 1311 const struct rtw89_nbi_reg_def *nbi = &rtw8852c_nbi_reg_def[path]; 1312 u32 spur_freq, fc; 1313 s32 freq_diff; 1314 s32 nbi_idx, nbi_tone_idx; 1315 s32 nbi_frac_idx, nbi_frac_tone_idx; 1316 bool notch2_chk = false; 1317 1318 spur_freq = rtw8852c_spur_freq(rtwdev, chan); 1319 if (spur_freq == 0) { 1320 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1321 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1322 return; 1323 } 1324 1325 fc = chan->freq; 1326 if (chan->band_width == RTW89_CHANNEL_WIDTH_160) { 1327 fc = (spur_freq > fc) ? fc + 40 : fc - 40; 1328 if ((fc > spur_freq && 1329 chan->channel < chan->primary_channel) || 1330 (fc < spur_freq && 1331 chan->channel > chan->primary_channel)) 1332 notch2_chk = true; 1333 } 1334 1335 freq_diff = (spur_freq - fc) * 1000000; 1336 nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5, &nbi_frac_idx); 1337 1338 if (chan->band_width == RTW89_CHANNEL_WIDTH_20) { 1339 s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx); 1340 } else { 1341 u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ? 1342 128 : 256; 1343 1344 s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx); 1345 } 1346 nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx, CARRIER_SPACING_78_125); 1347 1348 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) { 1349 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr, 1350 nbi->notch2_idx.mask, nbi_tone_idx); 1351 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr, 1352 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx); 1353 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0); 1354 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 1); 1355 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1356 } else { 1357 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr, 1358 nbi->notch1_idx.mask, nbi_tone_idx); 1359 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr, 1360 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx); 1361 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1362 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 1); 1363 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0); 1364 } 1365 } 1366 1367 static void rtw8852c_spur_notch(struct rtw89_dev *rtwdev, u32 val, 1368 enum rtw89_phy_idx phy_idx) 1369 { 1370 u32 notch; 1371 u32 notch2; 1372 1373 if (phy_idx == RTW89_PHY_0) { 1374 notch = R_PATH0_NOTCH; 1375 notch2 = R_PATH0_NOTCH2; 1376 } else { 1377 notch = R_PATH1_NOTCH; 1378 notch2 = R_PATH1_NOTCH2; 1379 } 1380 1381 rtw89_phy_write32_mask(rtwdev, notch, 1382 B_PATH0_NOTCH_VAL | B_PATH0_NOTCH_EN, val); 1383 rtw89_phy_write32_set(rtwdev, notch, B_PATH0_NOTCH_EN); 1384 rtw89_phy_write32_mask(rtwdev, notch2, 1385 B_PATH0_NOTCH2_VAL | B_PATH0_NOTCH2_EN, val); 1386 rtw89_phy_write32_set(rtwdev, notch2, B_PATH0_NOTCH2_EN); 1387 } 1388 1389 static void rtw8852c_spur_elimination(struct rtw89_dev *rtwdev, 1390 const struct rtw89_chan *chan, 1391 u8 pri_ch_idx, 1392 enum rtw89_phy_idx phy_idx) 1393 { 1394 rtw8852c_set_csi_tone_idx(rtwdev, chan, phy_idx); 1395 1396 if (phy_idx == RTW89_PHY_0) { 1397 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1398 (pri_ch_idx == RTW89_SC_20_LOWER || 1399 pri_ch_idx == RTW89_SC_20_UP3X)) { 1400 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_0); 1401 if (!rtwdev->dbcc_en) 1402 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1); 1403 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1404 (pri_ch_idx == RTW89_SC_20_UPPER || 1405 pri_ch_idx == RTW89_SC_20_LOW3X)) { 1406 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_0); 1407 if (!rtwdev->dbcc_en) 1408 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1); 1409 } else { 1410 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_A); 1411 if (!rtwdev->dbcc_en) 1412 rtw8852c_set_nbi_tone_idx(rtwdev, chan, 1413 RF_PATH_B); 1414 } 1415 } else { 1416 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1417 (pri_ch_idx == RTW89_SC_20_LOWER || 1418 pri_ch_idx == RTW89_SC_20_UP3X)) { 1419 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1); 1420 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1421 (pri_ch_idx == RTW89_SC_20_UPPER || 1422 pri_ch_idx == RTW89_SC_20_LOW3X)) { 1423 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1); 1424 } else { 1425 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_B); 1426 } 1427 } 1428 1429 if (pri_ch_idx == RTW89_SC_20_UP3X || pri_ch_idx == RTW89_SC_20_LOW3X) 1430 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 0, phy_idx); 1431 else 1432 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 1, phy_idx); 1433 } 1434 1435 static void rtw8852c_5m_mask(struct rtw89_dev *rtwdev, 1436 const struct rtw89_chan *chan, 1437 enum rtw89_phy_idx phy_idx) 1438 { 1439 u8 pri_ch = chan->pri_ch_idx; 1440 bool mask_5m_low; 1441 bool mask_5m_en; 1442 1443 switch (chan->band_width) { 1444 case RTW89_CHANNEL_WIDTH_40: 1445 mask_5m_en = true; 1446 mask_5m_low = pri_ch == RTW89_SC_20_LOWER; 1447 break; 1448 case RTW89_CHANNEL_WIDTH_80: 1449 mask_5m_en = pri_ch == RTW89_SC_20_UPMOST || 1450 pri_ch == RTW89_SC_20_LOWEST; 1451 mask_5m_low = pri_ch == RTW89_SC_20_LOWEST; 1452 break; 1453 default: 1454 mask_5m_en = false; 1455 mask_5m_low = false; 1456 break; 1457 } 1458 1459 if (!mask_5m_en) { 1460 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x0); 1461 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x0); 1462 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, 1463 B_ASSIGN_SBD_OPT_EN, 0x0, phy_idx); 1464 } else { 1465 if (mask_5m_low) { 1466 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4); 1467 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1); 1468 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x0); 1469 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x1); 1470 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4); 1471 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1); 1472 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x0); 1473 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x1); 1474 } else { 1475 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4); 1476 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1); 1477 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x1); 1478 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x0); 1479 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4); 1480 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1); 1481 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x1); 1482 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x0); 1483 } 1484 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, B_ASSIGN_SBD_OPT_EN, 0x1, phy_idx); 1485 } 1486 } 1487 1488 static void rtw8852c_bb_reset_all(struct rtw89_dev *rtwdev, 1489 enum rtw89_phy_idx phy_idx) 1490 { 1491 /*HW SI reset*/ 1492 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 1493 0x7); 1494 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 1495 0x7); 1496 1497 udelay(1); 1498 1499 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1500 phy_idx); 1501 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1502 phy_idx); 1503 /*HW SI reset*/ 1504 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 1505 0x0); 1506 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 1507 0x0); 1508 1509 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1510 phy_idx); 1511 } 1512 1513 static void rtw8852c_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band, 1514 enum rtw89_phy_idx phy_idx, bool en) 1515 { 1516 if (en) { 1517 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1518 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1519 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1520 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1521 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1522 phy_idx); 1523 if (band == RTW89_BAND_2G) 1524 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x0); 1525 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0); 1526 } else { 1527 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x1); 1528 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1); 1529 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1530 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1531 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1532 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1533 fsleep(1); 1534 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1535 phy_idx); 1536 } 1537 } 1538 1539 static void rtw8852c_bb_reset(struct rtw89_dev *rtwdev, 1540 enum rtw89_phy_idx phy_idx) 1541 { 1542 rtw8852c_bb_reset_all(rtwdev, phy_idx); 1543 } 1544 1545 static 1546 void rtw8852c_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1547 u8 tx_path_en, u8 trsw_tx, 1548 u8 trsw_rx, u8 trsw, u8 trsw_b) 1549 { 1550 static const u32 path_cr_bases[] = {0x5868, 0x7868}; 1551 u32 mask_ofst = 16; 1552 u32 cr; 1553 u32 val; 1554 1555 if (path >= ARRAY_SIZE(path_cr_bases)) 1556 return; 1557 1558 cr = path_cr_bases[path]; 1559 1560 mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2; 1561 val = FIELD_PREP(B_P0_TRSW_A, trsw) | FIELD_PREP(B_P0_TRSW_B, trsw_b); 1562 1563 rtw89_phy_write32_mask(rtwdev, cr, (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val); 1564 } 1565 1566 enum rtw8852c_rfe_src { 1567 PAPE_RFM, 1568 TRSW_RFM, 1569 LNAON_RFM, 1570 }; 1571 1572 static 1573 void rtw8852c_bb_gpio_rfm(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1574 enum rtw8852c_rfe_src src, u8 dis_tx_gnt_wl, 1575 u8 active_tx_opt, u8 act_bt_en, u8 rfm_output_val) 1576 { 1577 static const u32 path_cr_bases[] = {0x5894, 0x7894}; 1578 static const u32 masks[] = {0, 8, 16}; 1579 u32 mask, mask_ofst; 1580 u32 cr; 1581 u32 val; 1582 1583 if (src >= ARRAY_SIZE(masks) || path >= ARRAY_SIZE(path_cr_bases)) 1584 return; 1585 1586 mask_ofst = masks[src]; 1587 cr = path_cr_bases[path]; 1588 1589 val = FIELD_PREP(B_P0_RFM_DIS_WL, dis_tx_gnt_wl) | 1590 FIELD_PREP(B_P0_RFM_TX_OPT, active_tx_opt) | 1591 FIELD_PREP(B_P0_RFM_BT_EN, act_bt_en) | 1592 FIELD_PREP(B_P0_RFM_OUT, rfm_output_val); 1593 mask = 0xff << mask_ofst; 1594 1595 rtw89_phy_write32_mask(rtwdev, cr, mask, val); 1596 } 1597 1598 static void rtw8852c_bb_gpio_init(struct rtw89_dev *rtwdev) 1599 { 1600 static const u32 cr_bases[] = {0x5800, 0x7800}; 1601 u32 addr; 1602 u8 i; 1603 1604 for (i = 0; i < ARRAY_SIZE(cr_bases); i++) { 1605 addr = cr_bases[i]; 1606 rtw89_phy_write32_set(rtwdev, (addr | 0x68), B_P0_TRSW_A); 1607 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_X); 1608 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_SO_A2); 1609 rtw89_phy_write32(rtwdev, (addr | 0x80), 0x77777777); 1610 rtw89_phy_write32(rtwdev, (addr | 0x84), 0x77777777); 1611 } 1612 1613 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff); 1614 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0); 1615 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0); 1616 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0); 1617 1618 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1); 1619 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0); 1620 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0); 1621 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0); 1622 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1); 1623 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0); 1624 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0); 1625 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0); 1626 1627 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 0, 0, 1); 1628 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 1, 1, 0); 1629 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 0, 1, 0); 1630 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 1, 1, 0); 1631 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 0, 0, 1); 1632 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 1, 1, 0); 1633 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 0, 1, 0); 1634 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 1, 1, 0); 1635 1636 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, PAPE_RFM, 0, 0, 0, 0x0); 1637 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, TRSW_RFM, 0, 0, 0, 0x4); 1638 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, LNAON_RFM, 0, 0, 0, 0x8); 1639 1640 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, PAPE_RFM, 0, 0, 0, 0x0); 1641 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, TRSW_RFM, 0, 0, 0, 0x4); 1642 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, LNAON_RFM, 0, 0, 0, 0x8); 1643 } 1644 1645 static void rtw8852c_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1646 enum rtw89_phy_idx phy_idx) 1647 { 1648 u32 addr; 1649 1650 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1651 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1652 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1653 } 1654 1655 static void rtw8852c_bb_sethw(struct rtw89_dev *rtwdev) 1656 { 1657 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 1658 1659 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT, 1660 B_DBCC_80P80_SEL_EVM_RPT_EN); 1661 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT2, 1662 B_DBCC_80P80_SEL_EVM_RPT2_EN); 1663 1664 rtw8852c_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1665 rtw8852c_bb_gpio_init(rtwdev); 1666 1667 /* read these registers after loading BB parameters */ 1668 gain->offset_base[RTW89_PHY_0] = 1669 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP, B_RPL_BIAS_COMP_MASK); 1670 gain->offset_base[RTW89_PHY_1] = 1671 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP1, B_RPL_BIAS_COMP1_MASK); 1672 } 1673 1674 static void rtw8852c_set_channel_bb(struct rtw89_dev *rtwdev, 1675 const struct rtw89_chan *chan, 1676 enum rtw89_phy_idx phy_idx) 1677 { 1678 static const u32 ru_alloc_msk[2] = {B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0, 1679 B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1}; 1680 struct rtw89_hal *hal = &rtwdev->hal; 1681 bool cck_en = chan->band_type == RTW89_BAND_2G; 1682 u8 pri_ch_idx = chan->pri_ch_idx; 1683 u32 mask, reg; 1684 u8 ntx_path; 1685 1686 if (chan->band_type == RTW89_BAND_2G) 1687 rtw8852c_ctrl_sco_cck(rtwdev, chan->channel, 1688 chan->primary_channel, 1689 chan->band_width); 1690 1691 rtw8852c_ctrl_ch(rtwdev, chan, phy_idx); 1692 rtw8852c_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1693 if (cck_en) { 1694 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1); 1695 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0); 1696 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, 1697 B_PD_ARBITER_OFF, 0x0, phy_idx); 1698 } else { 1699 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0); 1700 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 1); 1701 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, 1702 B_PD_ARBITER_OFF, 0x1, phy_idx); 1703 } 1704 1705 rtw8852c_spur_elimination(rtwdev, chan, pri_ch_idx, phy_idx); 1706 rtw8852c_ctrl_btg_bt_rx(rtwdev, chan->band_type == RTW89_BAND_2G, 1707 RTW89_PHY_0); 1708 rtw8852c_5m_mask(rtwdev, chan, phy_idx); 1709 1710 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1711 rtwdev->hal.cv != CHIP_CAV) { 1712 rtw89_phy_write32_idx(rtwdev, R_P80_AT_HIGH_FREQ, 1713 B_P80_AT_HIGH_FREQ, 0x0, phy_idx); 1714 reg = rtw89_mac_reg_by_idx(rtwdev, R_P80_AT_HIGH_FREQ_BB_WRP, phy_idx); 1715 if (chan->primary_channel > chan->channel) { 1716 rtw89_phy_write32_mask(rtwdev, 1717 R_P80_AT_HIGH_FREQ_RU_ALLOC, 1718 ru_alloc_msk[phy_idx], 1); 1719 rtw89_write32_mask(rtwdev, reg, 1720 B_P80_AT_HIGH_FREQ_BB_WRP, 1); 1721 } else { 1722 rtw89_phy_write32_mask(rtwdev, 1723 R_P80_AT_HIGH_FREQ_RU_ALLOC, 1724 ru_alloc_msk[phy_idx], 0); 1725 rtw89_write32_mask(rtwdev, reg, 1726 B_P80_AT_HIGH_FREQ_BB_WRP, 0); 1727 } 1728 } 1729 1730 if (chan->band_type == RTW89_BAND_6G && 1731 chan->band_width == RTW89_CHANNEL_WIDTH_160) 1732 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN, 1733 B_CDD_EVM_CHK_EN, 0, phy_idx); 1734 else 1735 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN, 1736 B_CDD_EVM_CHK_EN, 1, phy_idx); 1737 1738 if (!rtwdev->dbcc_en) { 1739 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON; 1740 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); 1741 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); 1742 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON; 1743 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1); 1744 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3); 1745 } else { 1746 if (phy_idx == RTW89_PHY_0) { 1747 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON; 1748 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); 1749 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); 1750 } else { 1751 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON; 1752 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1); 1753 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3); 1754 } 1755 } 1756 1757 if (chan->band_type == RTW89_BAND_6G) 1758 rtw89_phy_write32_set(rtwdev, R_MUIC, B_MUIC_EN); 1759 else 1760 rtw89_phy_write32_clr(rtwdev, R_MUIC, B_MUIC_EN); 1761 1762 if (hal->antenna_tx) 1763 ntx_path = hal->antenna_tx; 1764 else 1765 ntx_path = chan->band_type == RTW89_BAND_6G ? RF_B : RF_AB; 1766 1767 rtw8852c_ctrl_tx_path_tmac(rtwdev, ntx_path, (enum rtw89_mac_idx)phy_idx); 1768 1769 rtw8852c_bb_reset_all(rtwdev, phy_idx); 1770 } 1771 1772 static void rtw8852c_set_channel(struct rtw89_dev *rtwdev, 1773 const struct rtw89_chan *chan, 1774 enum rtw89_mac_idx mac_idx, 1775 enum rtw89_phy_idx phy_idx) 1776 { 1777 rtw8852c_set_channel_mac(rtwdev, chan, mac_idx); 1778 rtw8852c_set_channel_bb(rtwdev, chan, phy_idx); 1779 rtw8852c_set_channel_rf(rtwdev, chan, phy_idx); 1780 } 1781 1782 static void rtw8852c_dfs_en(struct rtw89_dev *rtwdev, bool en) 1783 { 1784 if (en) 1785 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1786 else 1787 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1788 } 1789 1790 static void rtw8852c_adc_en(struct rtw89_dev *rtwdev, bool en) 1791 { 1792 if (en) 1793 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1794 0x0); 1795 else 1796 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1797 0xf); 1798 } 1799 1800 static void rtw8852c_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1801 struct rtw89_channel_help_params *p, 1802 const struct rtw89_chan *chan, 1803 enum rtw89_mac_idx mac_idx, 1804 enum rtw89_phy_idx phy_idx) 1805 { 1806 if (enter) { 1807 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en, 1808 RTW89_SCH_TX_SEL_ALL); 1809 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false); 1810 rtw8852c_dfs_en(rtwdev, false); 1811 rtw8852c_tssi_cont_en_phyidx(rtwdev, false, phy_idx); 1812 rtw8852c_adc_en(rtwdev, false); 1813 fsleep(40); 1814 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, false); 1815 } else { 1816 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true); 1817 rtw8852c_adc_en(rtwdev, true); 1818 rtw8852c_dfs_en(rtwdev, true); 1819 rtw8852c_tssi_cont_en_phyidx(rtwdev, true, phy_idx); 1820 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, true); 1821 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en); 1822 } 1823 } 1824 1825 static void rtw8852c_rfk_init(struct rtw89_dev *rtwdev) 1826 { 1827 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc; 1828 1829 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1830 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1831 memset(rfk_mcc, 0, sizeof(*rfk_mcc)); 1832 rtw8852c_lck_init(rtwdev); 1833 rtw8852c_dpk_init(rtwdev); 1834 1835 rtw8852c_rck(rtwdev); 1836 rtw8852c_dack(rtwdev); 1837 rtw8852c_rx_dck(rtwdev, RTW89_PHY_0, false); 1838 } 1839 1840 static void rtw8852c_rfk_channel(struct rtw89_dev *rtwdev) 1841 { 1842 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 1843 1844 rtw8852c_mcc_get_ch_info(rtwdev, phy_idx); 1845 rtw8852c_rx_dck(rtwdev, phy_idx, false); 1846 rtw8852c_iqk(rtwdev, phy_idx); 1847 rtw8852c_tssi(rtwdev, phy_idx); 1848 rtw8852c_dpk(rtwdev, phy_idx); 1849 rtw89_fw_h2c_rf_ntfy_mcc(rtwdev); 1850 } 1851 1852 static void rtw8852c_rfk_band_changed(struct rtw89_dev *rtwdev, 1853 enum rtw89_phy_idx phy_idx) 1854 { 1855 rtw8852c_tssi_scan(rtwdev, phy_idx); 1856 } 1857 1858 static void rtw8852c_rfk_scan(struct rtw89_dev *rtwdev, bool start) 1859 { 1860 rtw8852c_wifi_scan_notify(rtwdev, start, RTW89_PHY_0); 1861 } 1862 1863 static void rtw8852c_rfk_track(struct rtw89_dev *rtwdev) 1864 { 1865 rtw8852c_dpk_track(rtwdev); 1866 rtw8852c_lck_track(rtwdev); 1867 rtw8852c_rx_dck_track(rtwdev); 1868 } 1869 1870 static u32 rtw8852c_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1871 enum rtw89_phy_idx phy_idx, s16 ref) 1872 { 1873 s8 ofst_int = 0; 1874 u8 base_cw_0db = 0x27; 1875 u16 tssi_16dbm_cw = 0x12c; 1876 s16 pwr_s10_3 = 0; 1877 s16 rf_pwr_cw = 0; 1878 u16 bb_pwr_cw = 0; 1879 u32 pwr_cw = 0; 1880 u32 tssi_ofst_cw = 0; 1881 1882 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1883 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1884 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1885 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1886 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1887 1888 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1889 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1890 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1891 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1892 1893 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); 1894 } 1895 1896 static 1897 void rtw8852c_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1898 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1899 { 1900 s8 pw_ofst_2tx; 1901 s8 val_1t; 1902 s8 val_2t; 1903 u32 reg; 1904 u8 i; 1905 1906 if (pw_ofst < -32 || pw_ofst > 31) { 1907 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst); 1908 return; 1909 } 1910 val_1t = pw_ofst << 2; 1911 pw_ofst_2tx = max(pw_ofst - 3, -32); 1912 val_2t = pw_ofst_2tx << 2; 1913 1914 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_1tx=0x%x\n", val_1t); 1915 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_2tx=0x%x\n", val_2t); 1916 1917 for (i = 0; i < 4; i++) { 1918 /* 1TX */ 1919 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); 1920 rtw89_write32_mask(rtwdev, reg, 1921 B_AX_PWR_UL_TB_1T_V1_MASK << (8 * i), 1922 val_1t); 1923 /* 2TX */ 1924 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); 1925 rtw89_write32_mask(rtwdev, reg, 1926 B_AX_PWR_UL_TB_2T_V1_MASK << (8 * i), 1927 val_2t); 1928 } 1929 } 1930 1931 static void rtw8852c_set_txpwr_ref(struct rtw89_dev *rtwdev, 1932 enum rtw89_phy_idx phy_idx) 1933 { 1934 static const u32 addr[RF_PATH_NUM_8852C] = {0x5800, 0x7800}; 1935 const u32 mask = 0x7FFFFFF; 1936 const u8 ofst_ofdm = 0x4; 1937 const u8 ofst_cck = 0x8; 1938 s16 ref_ofdm = 0; 1939 s16 ref_cck = 0; 1940 u32 val; 1941 u8 i; 1942 1943 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1944 1945 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1946 GENMASK(27, 10), 0x0); 1947 1948 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1949 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1950 1951 for (i = 0; i < RF_PATH_NUM_8852C; i++) 1952 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1953 phy_idx); 1954 1955 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1956 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1957 1958 for (i = 0; i < RF_PATH_NUM_8852C; i++) 1959 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1960 phy_idx); 1961 } 1962 1963 static void rtw8852c_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev, 1964 const struct rtw89_chan *chan, 1965 u8 tx_shape_idx, 1966 enum rtw89_phy_idx phy_idx) 1967 { 1968 #define __DFIR_CFG_MASK 0xffffff 1969 #define __DFIR_CFG_NR 8 1970 #if defined(__linux__) 1971 #define __DECL_DFIR_VAR(_prefix, _name, _val...) \ 1972 static const u32 _prefix ## _ ## _name[] = {_val}; \ 1973 static_assert(ARRAY_SIZE(_prefix ## _ ## _name) == __DFIR_CFG_NR) 1974 #elif defined(__FreeBSD__) 1975 #define __DECL_DFIR_VAR(_prefix, _name, _val...) \ 1976 static const u32 _prefix ## _ ## _name[] = {_val}; \ 1977 rtw89_static_assert(ARRAY_SIZE(_prefix ## _ ## _name) == __DFIR_CFG_NR) 1978 #endif 1979 #define __DECL_DFIR_PARAM(_name, _val...) __DECL_DFIR_VAR(param, _name, _val) 1980 #define __DECL_DFIR_ADDR(_name, _val...) __DECL_DFIR_VAR(addr, _name, _val) 1981 1982 __DECL_DFIR_PARAM(flat, 1983 0x003D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053, 1984 0x00F86F9A, 0x00FAEF92, 0x00FE5FCC, 0x00FFDFF5); 1985 __DECL_DFIR_PARAM(sharp, 1986 0x003D83FF, 0x002C636A, 0x0013F204, 0x00008090, 1987 0x00F87FB0, 0x00F99F83, 0x00FDBFBA, 0x00003FF5); 1988 __DECL_DFIR_PARAM(sharp_14, 1989 0x003B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E, 1990 0x00FD8F92, 0x0002D011, 0x0001C02C, 0x00FFF00A); 1991 __DECL_DFIR_ADDR(filter, 1992 0x45BC, 0x45CC, 0x45D0, 0x45D4, 0x45D8, 0x45C0, 1993 0x45C4, 0x45C8); 1994 u8 ch = chan->channel; 1995 const u32 *param; 1996 int i; 1997 1998 if (ch > 14) { 1999 rtw89_warn(rtwdev, 2000 "set tx shape dfir by unknown ch: %d on 2G\n", ch); 2001 return; 2002 } 2003 2004 if (ch == 14) 2005 param = param_sharp_14; 2006 else 2007 param = tx_shape_idx == 0 ? param_flat : param_sharp; 2008 2009 for (i = 0; i < __DFIR_CFG_NR; i++) { 2010 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2011 "set tx shape dfir: 0x%x: 0x%x\n", addr_filter[i], 2012 param[i]); 2013 rtw89_phy_write32_idx(rtwdev, addr_filter[i], __DFIR_CFG_MASK, 2014 param[i], phy_idx); 2015 } 2016 2017 #undef __DECL_DFIR_ADDR 2018 #undef __DECL_DFIR_PARAM 2019 #undef __DECL_DFIR_VAR 2020 #undef __DFIR_CFG_NR 2021 #undef __DFIR_CFG_MASK 2022 } 2023 2024 static void rtw8852c_set_tx_shape(struct rtw89_dev *rtwdev, 2025 const struct rtw89_chan *chan, 2026 enum rtw89_phy_idx phy_idx) 2027 { 2028 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 2029 u8 band = chan->band_type; 2030 u8 regd = rtw89_regd_get(rtwdev, band); 2031 u8 tx_shape_cck = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_CCK][regd]; 2032 u8 tx_shape_ofdm = (*rfe_parms->tx_shape.lmt)[band][RTW89_RS_OFDM][regd]; 2033 2034 if (band == RTW89_BAND_2G) 2035 rtw8852c_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx); 2036 2037 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev, 2038 (enum rtw89_mac_idx)phy_idx, 2039 tx_shape_ofdm); 2040 2041 rtw89_phy_write32_set(rtwdev, R_P0_DAC_COMP_POST_DPD_EN, 2042 B_P0_DAC_COMP_POST_DPD_EN); 2043 rtw89_phy_write32_set(rtwdev, R_P1_DAC_COMP_POST_DPD_EN, 2044 B_P1_DAC_COMP_POST_DPD_EN); 2045 } 2046 2047 static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev, 2048 const struct rtw89_chan *chan, 2049 enum rtw89_phy_idx phy_idx) 2050 { 2051 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 2052 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 2053 rtw8852c_set_tx_shape(rtwdev, chan, phy_idx); 2054 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 2055 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 2056 } 2057 2058 static void rtw8852c_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 2059 enum rtw89_phy_idx phy_idx) 2060 { 2061 rtw8852c_set_txpwr_ref(rtwdev, phy_idx); 2062 } 2063 2064 static void 2065 rtw8852c_init_tssi_ctrl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 2066 { 2067 static const struct rtw89_reg2_def ctrl_ini[] = { 2068 {0xD938, 0x00010100}, 2069 {0xD93C, 0x0500D500}, 2070 {0xD940, 0x00000500}, 2071 {0xD944, 0x00000005}, 2072 {0xD94C, 0x00220000}, 2073 {0xD950, 0x00030000}, 2074 }; 2075 u32 addr; 2076 int i; 2077 2078 for (addr = R_AX_TSSI_CTRL_HEAD; addr <= R_AX_TSSI_CTRL_TAIL; addr += 4) 2079 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 2080 2081 for (i = 0; i < ARRAY_SIZE(ctrl_ini); i++) 2082 rtw89_mac_txpwr_write32(rtwdev, phy_idx, ctrl_ini[i].addr, 2083 ctrl_ini[i].data); 2084 2085 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev, 2086 (enum rtw89_mac_idx)phy_idx, 2087 RTW89_TSSI_BANDEDGE_FLAT); 2088 } 2089 2090 static int 2091 rtw8852c_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 2092 { 2093 int ret; 2094 2095 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 2096 if (ret) 2097 return ret; 2098 2099 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000); 2100 if (ret) 2101 return ret; 2102 2103 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 2104 if (ret) 2105 return ret; 2106 2107 rtw8852c_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ? 2108 RTW89_MAC_1 : 2109 RTW89_MAC_0); 2110 rtw8852c_init_tssi_ctrl(rtwdev, phy_idx); 2111 2112 return 0; 2113 } 2114 2115 static void rtw8852c_bb_cfg_rx_path(struct rtw89_dev *rtwdev, u8 rx_path) 2116 { 2117 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 2118 u8 band = chan->band_type; 2119 u32 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 2120 u32 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 2121 2122 if (rtwdev->dbcc_en) { 2123 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 1); 2124 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 2, 2125 RTW89_PHY_1); 2126 2127 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2128 1); 2129 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2130 1); 2131 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2, 2132 RTW89_PHY_1); 2133 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2, 2134 RTW89_PHY_1); 2135 2136 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2137 B_RXHT_MCS_LIMIT, 0); 2138 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2139 B_RXVHT_MCS_LIMIT, 0); 2140 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8); 2141 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2142 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2143 2144 rtw89_phy_write32_idx(rtwdev, R_RXHT_MCS_LIMIT, 2145 B_RXHT_MCS_LIMIT, 0, RTW89_PHY_1); 2146 rtw89_phy_write32_idx(rtwdev, R_RXVHT_MCS_LIMIT, 2147 B_RXVHT_MCS_LIMIT, 0, RTW89_PHY_1); 2148 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_USER_MAX, 1, 2149 RTW89_PHY_1); 2150 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0, 2151 RTW89_PHY_1); 2152 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0, 2153 RTW89_PHY_1); 2154 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 2155 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 2156 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 2157 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 2158 } else { 2159 if (rx_path == RF_PATH_A) { 2160 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2161 B_ANT_RX_SEG0, 1); 2162 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2163 B_ANT_RX_1RCCA_SEG0, 1); 2164 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2165 B_ANT_RX_1RCCA_SEG1, 1); 2166 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2167 B_RXHT_MCS_LIMIT, 0); 2168 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2169 B_RXVHT_MCS_LIMIT, 0); 2170 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2171 0); 2172 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2173 0); 2174 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2175 rst_mask0, 1); 2176 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2177 rst_mask0, 3); 2178 } else if (rx_path == RF_PATH_B) { 2179 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2180 B_ANT_RX_SEG0, 2); 2181 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2182 B_ANT_RX_1RCCA_SEG0, 2); 2183 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2184 B_ANT_RX_1RCCA_SEG1, 2); 2185 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2186 B_RXHT_MCS_LIMIT, 0); 2187 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2188 B_RXVHT_MCS_LIMIT, 0); 2189 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2190 0); 2191 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2192 0); 2193 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2194 rst_mask1, 1); 2195 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2196 rst_mask1, 3); 2197 } else { 2198 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2199 B_ANT_RX_SEG0, 3); 2200 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2201 B_ANT_RX_1RCCA_SEG0, 3); 2202 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2203 B_ANT_RX_1RCCA_SEG1, 3); 2204 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2205 B_RXHT_MCS_LIMIT, 1); 2206 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2207 B_RXVHT_MCS_LIMIT, 1); 2208 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2209 1); 2210 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2211 1); 2212 rtw8852c_ctrl_btg_bt_rx(rtwdev, band == RTW89_BAND_2G, 2213 RTW89_PHY_0); 2214 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2215 rst_mask0, 1); 2216 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2217 rst_mask0, 3); 2218 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2219 rst_mask1, 1); 2220 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2221 rst_mask1, 3); 2222 } 2223 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8); 2224 } 2225 } 2226 2227 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, 2228 enum rtw89_mac_idx mac_idx) 2229 { 2230 struct rtw89_reg2_def path_com[] = { 2231 {R_AX_PATH_COM0, AX_PATH_COM0_DFVAL}, 2232 {R_AX_PATH_COM1, AX_PATH_COM1_DFVAL}, 2233 {R_AX_PATH_COM2, AX_PATH_COM2_DFVAL}, 2234 {R_AX_PATH_COM3, AX_PATH_COM3_DFVAL}, 2235 {R_AX_PATH_COM4, AX_PATH_COM4_DFVAL}, 2236 {R_AX_PATH_COM5, AX_PATH_COM5_DFVAL}, 2237 {R_AX_PATH_COM6, AX_PATH_COM6_DFVAL}, 2238 {R_AX_PATH_COM7, AX_PATH_COM7_DFVAL}, 2239 {R_AX_PATH_COM8, AX_PATH_COM8_DFVAL}, 2240 {R_AX_PATH_COM9, AX_PATH_COM9_DFVAL}, 2241 {R_AX_PATH_COM10, AX_PATH_COM10_DFVAL}, 2242 {R_AX_PATH_COM11, AX_PATH_COM11_DFVAL}, 2243 }; 2244 u32 addr; 2245 u32 reg; 2246 u8 cr_size = ARRAY_SIZE(path_com); 2247 u8 i = 0; 2248 2249 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_0); 2250 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_1); 2251 2252 for (addr = R_AX_MACID_ANT_TABLE; 2253 addr <= R_AX_MACID_ANT_TABLE_LAST; addr += 4) { 2254 reg = rtw89_mac_reg_by_idx(rtwdev, addr, mac_idx); 2255 rtw89_write32(rtwdev, reg, 0); 2256 } 2257 2258 if (tx_path == RF_A) { 2259 path_com[0].data = AX_PATH_COM0_PATHA; 2260 path_com[1].data = AX_PATH_COM1_PATHA; 2261 path_com[2].data = AX_PATH_COM2_PATHA; 2262 path_com[7].data = AX_PATH_COM7_PATHA; 2263 path_com[8].data = AX_PATH_COM8_PATHA; 2264 } else if (tx_path == RF_B) { 2265 path_com[0].data = AX_PATH_COM0_PATHB; 2266 path_com[1].data = AX_PATH_COM1_PATHB; 2267 path_com[2].data = AX_PATH_COM2_PATHB; 2268 path_com[7].data = AX_PATH_COM7_PATHB; 2269 path_com[8].data = AX_PATH_COM8_PATHB; 2270 } else if (tx_path == RF_AB) { 2271 path_com[0].data = AX_PATH_COM0_PATHAB; 2272 path_com[1].data = AX_PATH_COM1_PATHAB; 2273 path_com[2].data = AX_PATH_COM2_PATHAB; 2274 path_com[7].data = AX_PATH_COM7_PATHAB; 2275 path_com[8].data = AX_PATH_COM8_PATHAB; 2276 } else { 2277 rtw89_warn(rtwdev, "[Invalid Tx Path]Tx Path: %d\n", tx_path); 2278 return; 2279 } 2280 2281 for (i = 0; i < cr_size; i++) { 2282 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "0x%x = 0x%x\n", 2283 path_com[i].addr, path_com[i].data); 2284 reg = rtw89_mac_reg_by_idx(rtwdev, path_com[i].addr, mac_idx); 2285 rtw89_write32(rtwdev, reg, path_com[i].data); 2286 } 2287 } 2288 2289 static void rtw8852c_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 2290 enum rtw89_phy_idx phy_idx) 2291 { 2292 if (en) { 2293 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1, 2294 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x3); 2295 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1, 2296 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x3); 2297 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1, 2298 B_PATH0_RXBB_MSK_V1, 0xf); 2299 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1, 2300 B_PATH1_RXBB_MSK_V1, 0xf); 2301 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 2302 B_PATH0_G_LNA6_OP1DB_V1, 0x80); 2303 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2304 B_PATH1_G_LNA6_OP1DB_V1, 0x80); 2305 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 2306 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x80); 2307 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1, 2308 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x80); 2309 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2310 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x80); 2311 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1, 2312 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x80); 2313 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1, 2314 B_PATH0_BT_BACKOFF_V1, 0x780D1E); 2315 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1, 2316 B_PATH1_BT_BACKOFF_V1, 0x780D1E); 2317 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1, 2318 B_P0_BACKOFF_IBADC_V1, 0x34); 2319 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1, 2320 B_P1_BACKOFF_IBADC_V1, 0x34); 2321 } else { 2322 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1, 2323 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x0); 2324 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1, 2325 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x0); 2326 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1, 2327 B_PATH0_RXBB_MSK_V1, 0x60); 2328 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1, 2329 B_PATH1_RXBB_MSK_V1, 0x60); 2330 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 2331 B_PATH0_G_LNA6_OP1DB_V1, 0x1a); 2332 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2333 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 2334 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 2335 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2336 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1, 2337 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x2a); 2338 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2339 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2340 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1, 2341 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x2a); 2342 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1, 2343 B_PATH0_BT_BACKOFF_V1, 0x79E99E); 2344 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1, 2345 B_PATH1_BT_BACKOFF_V1, 0x79E99E); 2346 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1, 2347 B_P0_BACKOFF_IBADC_V1, 0x26); 2348 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1, 2349 B_P1_BACKOFF_IBADC_V1, 0x26); 2350 } 2351 } 2352 2353 static void rtw8852c_bb_cfg_txrx_path(struct rtw89_dev *rtwdev) 2354 { 2355 struct rtw89_hal *hal = &rtwdev->hal; 2356 2357 rtw8852c_bb_cfg_rx_path(rtwdev, RF_PATH_AB); 2358 2359 if (hal->rx_nss == 1) { 2360 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 2361 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 2362 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2363 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2364 } else { 2365 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1); 2366 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1); 2367 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1); 2368 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1); 2369 } 2370 } 2371 2372 static u8 rtw8852c_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 2373 { 2374 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2375 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 2376 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2377 2378 fsleep(200); 2379 2380 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 2381 } 2382 2383 static void rtw8852c_btc_set_rfe(struct rtw89_dev *rtwdev) 2384 { 2385 const struct rtw89_btc_ver *ver = rtwdev->btc.ver; 2386 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; 2387 2388 if (ver->fcxinit == 7) { 2389 md->md_v7.rfe_type = rtwdev->efuse.rfe_type; 2390 md->md_v7.kt_ver = rtwdev->hal.cv; 2391 md->md_v7.bt_solo = 0; 2392 md->md_v7.switch_type = BTC_SWITCH_INTERNAL; 2393 2394 if (md->md_v7.rfe_type > 0) 2395 md->md_v7.ant.num = (md->md_v7.rfe_type % 2 ? 2 : 3); 2396 else 2397 md->md_v7.ant.num = 2; 2398 2399 md->md_v7.ant.diversity = 0; 2400 md->md_v7.ant.isolation = 10; 2401 2402 if (md->md_v7.ant.num == 3) { 2403 md->md_v7.ant.type = BTC_ANT_DEDICATED; 2404 md->md_v7.bt_pos = BTC_BT_ALONE; 2405 } else { 2406 md->md_v7.ant.type = BTC_ANT_SHARED; 2407 md->md_v7.bt_pos = BTC_BT_BTG; 2408 } 2409 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos; 2410 rtwdev->btc.ant_type = md->md_v7.ant.type; 2411 } else { 2412 md->md.rfe_type = rtwdev->efuse.rfe_type; 2413 md->md.cv = rtwdev->hal.cv; 2414 md->md.bt_solo = 0; 2415 md->md.switch_type = BTC_SWITCH_INTERNAL; 2416 2417 if (md->md.rfe_type > 0) 2418 md->md.ant.num = (md->md.rfe_type % 2 ? 2 : 3); 2419 else 2420 md->md.ant.num = 2; 2421 2422 md->md.ant.diversity = 0; 2423 md->md.ant.isolation = 10; 2424 2425 if (md->md.ant.num == 3) { 2426 md->md.ant.type = BTC_ANT_DEDICATED; 2427 md->md.bt_pos = BTC_BT_ALONE; 2428 } else { 2429 md->md.ant.type = BTC_ANT_SHARED; 2430 md->md.bt_pos = BTC_BT_BTG; 2431 } 2432 rtwdev->btc.btg_pos = md->md.ant.btg_pos; 2433 rtwdev->btc.ant_type = md->md.ant.type; 2434 } 2435 } 2436 2437 static void rtw8852c_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 2438 enum rtw89_phy_idx phy_idx) 2439 { 2440 if (en) { 2441 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 2442 B_PATH0_BT_SHARE_V1, 0x1); 2443 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 2444 B_PATH0_BTG_PATH_V1, 0x0); 2445 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2446 B_PATH1_G_LNA6_OP1DB_V1, 0x20); 2447 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2448 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30); 2449 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 2450 B_PATH1_BT_SHARE_V1, 0x1); 2451 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2452 B_PATH1_BTG_PATH_V1, 0x1); 2453 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 2454 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x1); 2455 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x2); 2456 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN, 2457 B_BT_DYN_DC_EST_EN_MSK, 0x1); 2458 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 2459 0x1); 2460 } else { 2461 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 2462 B_PATH0_BT_SHARE_V1, 0x0); 2463 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 2464 B_PATH0_BTG_PATH_V1, 0x0); 2465 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2466 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 2467 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2468 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2469 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 2470 B_PATH1_BT_SHARE_V1, 0x0); 2471 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2472 B_PATH1_BTG_PATH_V1, 0x0); 2473 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 2474 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 2475 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x0); 2476 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x0); 2477 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN, 2478 B_BT_DYN_DC_EST_EN_MSK, 0x0); 2479 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 2480 0x0); 2481 } 2482 } 2483 2484 static 2485 void rtw8852c_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 2486 { 2487 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000); 2488 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group); 2489 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val); 2490 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); 2491 } 2492 2493 static void rtw8852c_btc_init_cfg(struct rtw89_dev *rtwdev) 2494 { 2495 struct rtw89_btc *btc = &rtwdev->btc; 2496 const struct rtw89_chip_info *chip = rtwdev->chip; 2497 const struct rtw89_mac_ax_coex coex_params = { 2498 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 2499 .direction = RTW89_MAC_AX_COEX_INNER, 2500 }; 2501 2502 /* PTA init */ 2503 rtw89_mac_coex_init_v1(rtwdev, &coex_params); 2504 2505 /* set WL Tx response = Hi-Pri */ 2506 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 2507 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 2508 2509 /* set rf gnt debug off */ 2510 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0); 2511 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0); 2512 2513 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 2514 if (btc->ant_type == BTC_ANT_SHARED) { 2515 rtw8852c_set_trx_mask(rtwdev, 2516 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 2517 rtw8852c_set_trx_mask(rtwdev, 2518 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 2519 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 2520 rtw8852c_set_trx_mask(rtwdev, 2521 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 2522 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 2523 rtw8852c_set_trx_mask(rtwdev, 2524 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 2525 rtw8852c_set_trx_mask(rtwdev, 2526 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 2527 } 2528 2529 /* set PTA break table */ 2530 rtw89_write32(rtwdev, R_AX_BT_BREAK_TABLE, BTC_BREAK_PARAM); 2531 2532 /* enable BT counter 0xda10[1:0] = 2b'11 */ 2533 rtw89_write32_set(rtwdev, 2534 R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN | 2535 B_AX_BT_CNT_RST_V1); 2536 btc->cx.wl.status.map.init_ok = true; 2537 } 2538 2539 static 2540 void rtw8852c_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 2541 { 2542 u32 bitmap = 0; 2543 u32 reg = 0; 2544 2545 switch (map) { 2546 case BTC_PRI_MASK_TX_RESP: 2547 reg = R_BTC_COEX_WL_REQ; 2548 bitmap = B_BTC_RSP_ACK_HI; 2549 break; 2550 case BTC_PRI_MASK_BEACON: 2551 reg = R_BTC_COEX_WL_REQ; 2552 bitmap = B_BTC_TX_BCN_HI; 2553 break; 2554 default: 2555 return; 2556 } 2557 2558 if (state) 2559 rtw89_write32_set(rtwdev, reg, bitmap); 2560 else 2561 rtw89_write32_clr(rtwdev, reg, bitmap); 2562 } 2563 2564 union rtw8852c_btc_wl_txpwr_ctrl { 2565 u32 txpwr_val; 2566 struct { 2567 union { 2568 u16 ctrl_all_time; 2569 struct { 2570 s16 data:9; 2571 u16 rsvd:6; 2572 u16 flag:1; 2573 } all_time; 2574 }; 2575 union { 2576 u16 ctrl_gnt_bt; 2577 struct { 2578 s16 data:9; 2579 u16 rsvd:7; 2580 } gnt_bt; 2581 }; 2582 }; 2583 } __packed; 2584 2585 static void 2586 rtw8852c_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 2587 { 2588 union rtw8852c_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val }; 2589 s32 val; 2590 2591 #define __write_ctrl(_reg, _msk, _val, _en, _cond) \ 2592 do { \ 2593 u32 _wrt = FIELD_PREP(_msk, _val); \ 2594 BUILD_BUG_ON((_msk & _en) != 0); \ 2595 if (_cond) \ 2596 _wrt |= _en; \ 2597 else \ 2598 _wrt &= ~_en; \ 2599 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \ 2600 _msk | _en, _wrt); \ 2601 } while (0) 2602 2603 switch (arg.ctrl_all_time) { 2604 case 0xffff: 2605 val = 0; 2606 break; 2607 default: 2608 val = arg.all_time.data; 2609 break; 2610 } 2611 2612 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK, 2613 val, B_AX_FORCE_PWR_BY_RATE_EN, 2614 arg.ctrl_all_time != 0xffff); 2615 2616 switch (arg.ctrl_gnt_bt) { 2617 case 0xffff: 2618 val = 0; 2619 break; 2620 default: 2621 val = arg.gnt_bt.data; 2622 break; 2623 } 2624 2625 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val, 2626 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff); 2627 2628 #undef __write_ctrl 2629 } 2630 2631 static 2632 s8 rtw8852c_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 2633 { 2634 /* +6 for compensate offset */ 2635 return clamp_t(s8, val + 6, -100, 0) + 100; 2636 } 2637 2638 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_ul[] = { 2639 {255, 0, 0, 7}, /* 0 -> original */ 2640 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 2641 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 2642 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 2643 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 2644 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 2645 {6, 1, 0, 7}, 2646 {13, 1, 0, 7}, 2647 {13, 1, 0, 7} 2648 }; 2649 2650 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_dl[] = { 2651 {255, 0, 0, 7}, /* 0 -> original */ 2652 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 2653 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 2654 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 2655 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 2656 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 2657 {255, 1, 0, 7}, 2658 {255, 1, 0, 7}, 2659 {255, 1, 0, 7} 2660 }; 2661 2662 static const u8 rtw89_btc_8852c_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; 2663 static const u8 rtw89_btc_8852c_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; 2664 2665 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852c_mon_reg[] = { 2666 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda00), 2667 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda04), 2668 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 2669 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 2670 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 2671 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda38), 2672 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda44), 2673 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda48), 2674 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 2675 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200), 2676 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220), 2677 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 2678 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4aa4), 2679 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4778), 2680 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x476c), 2681 }; 2682 2683 static 2684 void rtw8852c_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 2685 { 2686 /* Feature move to firmware */ 2687 } 2688 2689 static 2690 void rtw8852c_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 2691 { 2692 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 2693 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2694 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x620); 2695 2696 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 2697 if (state) 2698 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2699 RFREG_MASK, 0x179c); 2700 else 2701 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2702 RFREG_MASK, 0x208); 2703 2704 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2705 } 2706 2707 static void rtw8852c_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) 2708 { 2709 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB 2710 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB 2711 * To improve BT ACI in co-rx 2712 */ 2713 2714 switch (level) { 2715 case 0: /* default */ 2716 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2717 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2718 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2719 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2720 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2721 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2722 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2723 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2724 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2725 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2726 break; 2727 case 1: /* Fix LNA2=5 */ 2728 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2729 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2730 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2731 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2732 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2733 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2734 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2735 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2736 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2737 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2738 break; 2739 } 2740 } 2741 2742 static void rtw8852c_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 2743 { 2744 struct rtw89_btc *btc = &rtwdev->btc; 2745 2746 switch (level) { 2747 case 0: /* original */ 2748 default: 2749 rtw8852c_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 2750 btc->dm.wl_lna2 = 0; 2751 break; 2752 case 1: /* for FDD free-run */ 2753 rtw8852c_ctrl_nbtg_bt_tx(rtwdev, true, RTW89_PHY_0); 2754 btc->dm.wl_lna2 = 0; 2755 break; 2756 case 2: /* for BTG Co-Rx*/ 2757 rtw8852c_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 2758 btc->dm.wl_lna2 = 1; 2759 break; 2760 } 2761 2762 rtw8852c_set_wl_lna2(rtwdev, btc->dm.wl_lna2); 2763 } 2764 2765 static void rtw8852c_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 2766 struct rtw89_rx_phy_ppdu *phy_ppdu, 2767 struct ieee80211_rx_status *status) 2768 { 2769 u8 chan_idx = phy_ppdu->chan_idx; 2770 enum nl80211_band band; 2771 u8 ch; 2772 2773 if (chan_idx == 0) 2774 return; 2775 2776 rtw89_decode_chan_idx(rtwdev, chan_idx, &ch, &band); 2777 status->freq = ieee80211_channel_to_frequency(ch, band); 2778 status->band = band; 2779 } 2780 2781 static void rtw8852c_query_ppdu(struct rtw89_dev *rtwdev, 2782 struct rtw89_rx_phy_ppdu *phy_ppdu, 2783 struct ieee80211_rx_status *status) 2784 { 2785 u8 path; 2786 u8 *rx_power = phy_ppdu->rssi; 2787 2788 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B])); 2789 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2790 status->chains |= BIT(path); 2791 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 2792 } 2793 if (phy_ppdu->valid) 2794 rtw8852c_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2795 } 2796 2797 static int rtw8852c_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 2798 { 2799 int ret; 2800 2801 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 2802 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2803 2804 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2805 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2806 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2807 2808 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S0_LDO_VSEL_F_MASK, 0x1); 2809 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S1_LDO_VSEL_F_MASK, 0x1); 2810 2811 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL0, 0x7, FULL_BIT_MASK); 2812 if (ret) 2813 return ret; 2814 2815 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x6c, FULL_BIT_MASK); 2816 if (ret) 2817 return ret; 2818 2819 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xc7, FULL_BIT_MASK); 2820 if (ret) 2821 return ret; 2822 2823 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xc7, FULL_BIT_MASK); 2824 if (ret) 2825 return ret; 2826 2827 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL3, 0xd, FULL_BIT_MASK); 2828 if (ret) 2829 return ret; 2830 2831 return 0; 2832 } 2833 2834 static int rtw8852c_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 2835 { 2836 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2837 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 2838 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2839 2840 return 0; 2841 } 2842 2843 static const struct rtw89_chanctx_listener rtw8852c_chanctx_listener = { 2844 .callbacks[RTW89_CHANCTX_CALLBACK_RFK] = rtw8852c_rfk_chanctx_cb, 2845 }; 2846 2847 #ifdef CONFIG_PM 2848 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852c = { 2849 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 2850 .n_patterns = RTW89_MAX_PATTERN_NUM, 2851 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 2852 .pattern_min_len = 1, 2853 }; 2854 #endif 2855 2856 static const struct rtw89_chip_ops rtw8852c_chip_ops = { 2857 .enable_bb_rf = rtw8852c_mac_enable_bb_rf, 2858 .disable_bb_rf = rtw8852c_mac_disable_bb_rf, 2859 .bb_preinit = NULL, 2860 .bb_postinit = NULL, 2861 .bb_reset = rtw8852c_bb_reset, 2862 .bb_sethw = rtw8852c_bb_sethw, 2863 .read_rf = rtw89_phy_read_rf_v1, 2864 .write_rf = rtw89_phy_write_rf_v1, 2865 .set_channel = rtw8852c_set_channel, 2866 .set_channel_help = rtw8852c_set_channel_help, 2867 .read_efuse = rtw8852c_read_efuse, 2868 .read_phycap = rtw8852c_read_phycap, 2869 .fem_setup = NULL, 2870 .rfe_gpio = NULL, 2871 .rfk_hw_init = NULL, 2872 .rfk_init = rtw8852c_rfk_init, 2873 .rfk_init_late = NULL, 2874 .rfk_channel = rtw8852c_rfk_channel, 2875 .rfk_band_changed = rtw8852c_rfk_band_changed, 2876 .rfk_scan = rtw8852c_rfk_scan, 2877 .rfk_track = rtw8852c_rfk_track, 2878 .power_trim = rtw8852c_power_trim, 2879 .set_txpwr = rtw8852c_set_txpwr, 2880 .set_txpwr_ctrl = rtw8852c_set_txpwr_ctrl, 2881 .init_txpwr_unit = rtw8852c_init_txpwr_unit, 2882 .get_thermal = rtw8852c_get_thermal, 2883 .ctrl_btg_bt_rx = rtw8852c_ctrl_btg_bt_rx, 2884 .query_ppdu = rtw8852c_query_ppdu, 2885 .ctrl_nbtg_bt_tx = rtw8852c_ctrl_nbtg_bt_tx, 2886 .cfg_txrx_path = rtw8852c_bb_cfg_txrx_path, 2887 .set_txpwr_ul_tb_offset = rtw8852c_set_txpwr_ul_tb_offset, 2888 .pwr_on_func = rtw8852c_pwr_on_func, 2889 .pwr_off_func = rtw8852c_pwr_off_func, 2890 .query_rxdesc = rtw89_core_query_rxdesc, 2891 .fill_txdesc = rtw89_core_fill_txdesc_v1, 2892 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v1, 2893 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v1, 2894 .mac_cfg_gnt = rtw89_mac_cfg_gnt_v1, 2895 .stop_sch_tx = rtw89_mac_stop_sch_tx_v1, 2896 .resume_sch_tx = rtw89_mac_resume_sch_tx_v1, 2897 .h2c_dctl_sec_cam = rtw89_fw_h2c_dctl_sec_cam_v1, 2898 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl, 2899 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl, 2900 .h2c_ampdu_cmac_tbl = NULL, 2901 .h2c_default_dmac_tbl = NULL, 2902 .h2c_update_beacon = rtw89_fw_h2c_update_beacon, 2903 .h2c_ba_cam = rtw89_fw_h2c_ba_cam, 2904 2905 .btc_set_rfe = rtw8852c_btc_set_rfe, 2906 .btc_init_cfg = rtw8852c_btc_init_cfg, 2907 .btc_set_wl_pri = rtw8852c_btc_set_wl_pri, 2908 .btc_set_wl_txpwr_ctrl = rtw8852c_btc_set_wl_txpwr_ctrl, 2909 .btc_get_bt_rssi = rtw8852c_btc_get_bt_rssi, 2910 .btc_update_bt_cnt = rtw8852c_btc_update_bt_cnt, 2911 .btc_wl_s1_standby = rtw8852c_btc_wl_s1_standby, 2912 .btc_set_wl_rx_gain = rtw8852c_btc_set_wl_rx_gain, 2913 .btc_set_policy = rtw89_btc_set_policy_v1, 2914 }; 2915 2916 const struct rtw89_chip_info rtw8852c_chip_info = { 2917 .chip_id = RTL8852C, 2918 .chip_gen = RTW89_CHIP_AX, 2919 .ops = &rtw8852c_chip_ops, 2920 .mac_def = &rtw89_mac_gen_ax, 2921 .phy_def = &rtw89_phy_gen_ax, 2922 .fw_basename = RTW8852C_FW_BASENAME, 2923 .fw_format_max = RTW8852C_FW_FORMAT_MAX, 2924 .try_ce_fw = false, 2925 .bbmcu_nr = 0, 2926 .needed_fw_elms = 0, 2927 .fifo_size = 458752, 2928 .small_fifo_size = false, 2929 .dle_scc_rsvd_size = 0, 2930 .max_amsdu_limit = 8000, 2931 .dis_2g_40m_ul_ofdma = false, 2932 .rsvd_ple_ofst = 0x6f800, 2933 .hfc_param_ini = rtw8852c_hfc_param_ini_pcie, 2934 .dle_mem = rtw8852c_dle_mem_pcie, 2935 .wde_qempty_acq_grpnum = 16, 2936 .wde_qempty_mgq_grpsel = 16, 2937 .rf_base_addr = {0xe000, 0xf000}, 2938 .pwr_on_seq = NULL, 2939 .pwr_off_seq = NULL, 2940 .bb_table = &rtw89_8852c_phy_bb_table, 2941 .bb_gain_table = &rtw89_8852c_phy_bb_gain_table, 2942 .rf_table = {&rtw89_8852c_phy_radiob_table, 2943 &rtw89_8852c_phy_radioa_table,}, 2944 .nctl_table = &rtw89_8852c_phy_nctl_table, 2945 .nctl_post_table = NULL, 2946 .dflt_parms = &rtw89_8852c_dflt_parms, 2947 .rfe_parms_conf = NULL, 2948 .chanctx_listener = &rtw8852c_chanctx_listener, 2949 .txpwr_factor_rf = 2, 2950 .txpwr_factor_mac = 1, 2951 .dig_table = NULL, 2952 .dig_regs = &rtw8852c_dig_regs, 2953 .tssi_dbw_table = &rtw89_8852c_tssi_dbw_table, 2954 .support_macid_num = RTW89_MAX_MAC_ID_NUM, 2955 .support_chanctx_num = 2, 2956 .support_rnr = false, 2957 .support_bands = BIT(NL80211_BAND_2GHZ) | 2958 BIT(NL80211_BAND_5GHZ) | 2959 BIT(NL80211_BAND_6GHZ), 2960 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) | 2961 BIT(NL80211_CHAN_WIDTH_40) | 2962 BIT(NL80211_CHAN_WIDTH_80) | 2963 BIT(NL80211_CHAN_WIDTH_160), 2964 .support_unii4 = true, 2965 .ul_tb_waveform_ctrl = false, 2966 .ul_tb_pwr_diff = true, 2967 .hw_sec_hdr = true, 2968 .rf_path_num = 2, 2969 .tx_nss = 2, 2970 .rx_nss = 2, 2971 .acam_num = 128, 2972 .bcam_num = 20, 2973 .scam_num = 128, 2974 .bacam_num = 8, 2975 .bacam_dynamic_num = 8, 2976 .bacam_ver = RTW89_BACAM_V0_EXT, 2977 .ppdu_max_usr = 8, 2978 .sec_ctrl_efuse_size = 4, 2979 .physical_efuse_size = 1216, 2980 .logical_efuse_size = 2048, 2981 .limit_efuse_size = 1280, 2982 .dav_phy_efuse_size = 96, 2983 .dav_log_efuse_size = 16, 2984 .efuse_blocks = NULL, 2985 .phycap_addr = 0x590, 2986 .phycap_size = 0x60, 2987 .para_ver = 0x1, 2988 .wlcx_desired = 0x06000000, 2989 .btcx_desired = 0x7, 2990 .scbd = 0x1, 2991 .mailbox = 0x1, 2992 2993 .afh_guard_ch = 6, 2994 .wl_rssi_thres = rtw89_btc_8852c_wl_rssi_thres, 2995 .bt_rssi_thres = rtw89_btc_8852c_bt_rssi_thres, 2996 .rssi_tol = 2, 2997 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852c_mon_reg), 2998 .mon_reg = rtw89_btc_8852c_mon_reg, 2999 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_ul), 3000 .rf_para_ulink = rtw89_btc_8852c_rf_ul, 3001 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_dl), 3002 .rf_para_dlink = rtw89_btc_8852c_rf_dl, 3003 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 3004 BIT(RTW89_PS_MODE_CLK_GATED) | 3005 BIT(RTW89_PS_MODE_PWR_GATED), 3006 .low_power_hci_modes = BIT(RTW89_PS_MODE_CLK_GATED) | 3007 BIT(RTW89_PS_MODE_PWR_GATED), 3008 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD_V1, 3009 .hci_func_en_addr = R_AX_HCI_FUNC_EN_V1, 3010 .h2c_desc_size = sizeof(struct rtw89_rxdesc_short), 3011 .txwd_body_size = sizeof(struct rtw89_txwd_body_v1), 3012 .txwd_info_size = sizeof(struct rtw89_txwd_info), 3013 .h2c_ctrl_reg = R_AX_H2CREG_CTRL_V1, 3014 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 3015 .h2c_regs = rtw8852c_h2c_regs, 3016 .c2h_ctrl_reg = R_AX_C2HREG_CTRL_V1, 3017 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 3018 .c2h_regs = rtw8852c_c2h_regs, 3019 .page_regs = &rtw8852c_page_regs, 3020 .wow_reason_reg = rtw8852c_wow_wakeup_regs, 3021 .cfo_src_fd = false, 3022 .cfo_hw_comp = false, 3023 .dcfo_comp = &rtw8852c_dcfo_comp, 3024 .dcfo_comp_sft = 12, 3025 .imr_info = &rtw8852c_imr_info, 3026 .imr_dmac_table = NULL, 3027 .imr_cmac_table = NULL, 3028 .rrsr_cfgs = &rtw8852c_rrsr_cfgs, 3029 .bss_clr_vld = {R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0}, 3030 .bss_clr_map_reg = R_BSS_CLR_MAP, 3031 .dma_ch_mask = 0, 3032 .edcca_regs = &rtw8852c_edcca_regs, 3033 #ifdef CONFIG_PM 3034 .wowlan_stub = &rtw_wowlan_stub_8852c, 3035 #endif 3036 .xtal_info = NULL, 3037 }; 3038 EXPORT_SYMBOL(rtw8852c_chip_info); 3039 3040 MODULE_FIRMWARE(RTW8852C_MODULE_FIRMWARE); 3041 MODULE_AUTHOR("Realtek Corporation"); 3042 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852C driver"); 3043 MODULE_LICENSE("Dual BSD/GPL"); 3044