1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2022 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "debug.h" 7 #include "fw.h" 8 #include "mac.h" 9 #include "phy.h" 10 #include "reg.h" 11 #include "rtw8852c.h" 12 #include "rtw8852c_rfk.h" 13 #include "rtw8852c_table.h" 14 #include "util.h" 15 16 #define RTW8852C_FW_FORMAT_MAX 0 17 #define RTW8852C_FW_BASENAME "rtw89/rtw8852c_fw" 18 #define RTW8852C_MODULE_FIRMWARE \ 19 RTW8852C_FW_BASENAME ".bin" 20 21 static const struct rtw89_hfc_ch_cfg rtw8852c_hfc_chcfg_pcie[] = { 22 {13, 1614, grp_0}, /* ACH 0 */ 23 {13, 1614, grp_0}, /* ACH 1 */ 24 {13, 1614, grp_0}, /* ACH 2 */ 25 {13, 1614, grp_0}, /* ACH 3 */ 26 {13, 1614, grp_1}, /* ACH 4 */ 27 {13, 1614, grp_1}, /* ACH 5 */ 28 {13, 1614, grp_1}, /* ACH 6 */ 29 {13, 1614, grp_1}, /* ACH 7 */ 30 {13, 1614, grp_0}, /* B0MGQ */ 31 {13, 1614, grp_0}, /* B0HIQ */ 32 {13, 1614, grp_1}, /* B1MGQ */ 33 {13, 1614, grp_1}, /* B1HIQ */ 34 {40, 0, 0} /* FWCMDQ */ 35 }; 36 37 static const struct rtw89_hfc_pub_cfg rtw8852c_hfc_pubcfg_pcie = { 38 1614, /* Group 0 */ 39 1614, /* Group 1 */ 40 3228, /* Public Max */ 41 0 /* WP threshold */ 42 }; 43 44 static const struct rtw89_hfc_param_ini rtw8852c_hfc_param_ini_pcie[] = { 45 [RTW89_QTA_SCC] = {rtw8852c_hfc_chcfg_pcie, &rtw8852c_hfc_pubcfg_pcie, 46 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 47 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 48 RTW89_HCIFC_POH}, 49 [RTW89_QTA_INVALID] = {NULL}, 50 }; 51 52 static const struct rtw89_dle_mem rtw8852c_dle_mem_pcie[] = { 53 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size19, 54 &rtw89_mac_size.ple_size19, &rtw89_mac_size.wde_qt18, 55 &rtw89_mac_size.wde_qt18, &rtw89_mac_size.ple_qt46, 56 &rtw89_mac_size.ple_qt47}, 57 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size18, 58 &rtw89_mac_size.ple_size18, &rtw89_mac_size.wde_qt17, 59 &rtw89_mac_size.wde_qt17, &rtw89_mac_size.ple_qt44, 60 &rtw89_mac_size.ple_qt45}, 61 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 62 NULL}, 63 }; 64 65 static const u32 rtw8852c_h2c_regs[RTW89_H2CREG_MAX] = { 66 R_AX_H2CREG_DATA0_V1, R_AX_H2CREG_DATA1_V1, R_AX_H2CREG_DATA2_V1, 67 R_AX_H2CREG_DATA3_V1 68 }; 69 70 static const u32 rtw8852c_c2h_regs[RTW89_H2CREG_MAX] = { 71 R_AX_C2HREG_DATA0_V1, R_AX_C2HREG_DATA1_V1, R_AX_C2HREG_DATA2_V1, 72 R_AX_C2HREG_DATA3_V1 73 }; 74 75 static const struct rtw89_page_regs rtw8852c_page_regs = { 76 .hci_fc_ctrl = R_AX_HCI_FC_CTRL_V1, 77 .ch_page_ctrl = R_AX_CH_PAGE_CTRL_V1, 78 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL_V1, 79 .ach_page_info = R_AX_ACH0_PAGE_INFO_V1, 80 .pub_page_info3 = R_AX_PUB_PAGE_INFO3_V1, 81 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1_V1, 82 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2_V1, 83 .pub_page_info1 = R_AX_PUB_PAGE_INFO1_V1, 84 .pub_page_info2 = R_AX_PUB_PAGE_INFO2_V1, 85 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1_V1, 86 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2_V1, 87 .wp_page_info1 = R_AX_WP_PAGE_INFO1_V1, 88 }; 89 90 static const struct rtw89_reg_def rtw8852c_dcfo_comp = { 91 R_DCFO_COMP_S0_V1, B_DCFO_COMP_S0_V1_MSK 92 }; 93 94 static const struct rtw89_imr_info rtw8852c_imr_info = { 95 .wdrls_imr_set = B_AX_WDRLS_IMR_SET_V1, 96 .wsec_imr_reg = R_AX_SEC_ERROR_FLAG_IMR, 97 .wsec_imr_set = B_AX_TX_HANG_IMR | B_AX_RX_HANG_IMR, 98 .mpdu_tx_imr_set = B_AX_MPDU_TX_IMR_SET_V1, 99 .mpdu_rx_imr_set = B_AX_MPDU_RX_IMR_SET_V1, 100 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 101 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_B0_ERRFLAG_IMR, 102 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR_V1, 103 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET_V1, 104 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_B1_ERRFLAG_IMR, 105 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR_V1, 106 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET_V1, 107 .wde_imr_clr = B_AX_WDE_IMR_CLR_V1, 108 .wde_imr_set = B_AX_WDE_IMR_SET_V1, 109 .ple_imr_clr = B_AX_PLE_IMR_CLR_V1, 110 .ple_imr_set = B_AX_PLE_IMR_SET_V1, 111 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR_V1, 112 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET_V1, 113 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR_V1, 114 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET_V1, 115 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR_V1, 116 .other_disp_imr_set = B_AX_OTHER_DISP_IMR_SET_V1, 117 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR, 118 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR, 119 .bbrpt_err_imr_set = R_AX_BBRPT_CHINFO_IMR_SET_V1, 120 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR, 121 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR_V1, 122 .ptcl_imr_set = B_AX_PTCL_IMR_SET_V1, 123 .cdma_imr_0_reg = R_AX_RX_ERR_FLAG_IMR, 124 .cdma_imr_0_clr = B_AX_RX_ERR_IMR_CLR_V1, 125 .cdma_imr_0_set = B_AX_RX_ERR_IMR_SET_V1, 126 .cdma_imr_1_reg = R_AX_TX_ERR_FLAG_IMR, 127 .cdma_imr_1_clr = B_AX_TX_ERR_IMR_CLR_V1, 128 .cdma_imr_1_set = B_AX_TX_ERR_IMR_SET_V1, 129 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR_V1, 130 .phy_intf_imr_clr = B_AX_PHYINFO_IMR_CLR_V1, 131 .phy_intf_imr_set = B_AX_PHYINFO_IMR_SET_V1, 132 .rmac_imr_reg = R_AX_RX_ERR_IMR, 133 .rmac_imr_clr = B_AX_RMAC_IMR_CLR_V1, 134 .rmac_imr_set = B_AX_RMAC_IMR_SET_V1, 135 .tmac_imr_reg = R_AX_TRXPTCL_ERROR_INDICA_MASK, 136 .tmac_imr_clr = B_AX_TMAC_IMR_CLR_V1, 137 .tmac_imr_set = B_AX_TMAC_IMR_SET_V1, 138 }; 139 140 static const struct rtw89_rrsr_cfgs rtw8852c_rrsr_cfgs = { 141 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 142 .rsc = {R_AX_PTCL_RRSR1, B_AX_RSC_MASK, 2}, 143 }; 144 145 static const struct rtw89_dig_regs rtw8852c_dig_regs = { 146 .seg0_pd_reg = R_SEG0R_PD, 147 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 148 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, 149 .p0_lna_init = {R_PATH0_LNA_INIT_V1, B_PATH0_LNA_INIT_IDX_MSK}, 150 .p1_lna_init = {R_PATH1_LNA_INIT_V1, B_PATH1_LNA_INIT_IDX_MSK}, 151 .p0_tia_init = {R_PATH0_TIA_INIT_V1, B_PATH0_TIA_INIT_IDX_MSK_V1}, 152 .p1_tia_init = {R_PATH1_TIA_INIT_V1, B_PATH1_TIA_INIT_IDX_MSK_V1}, 153 .p0_rxb_init = {R_PATH0_RXB_INIT_V1, B_PATH0_RXB_INIT_IDX_MSK_V1}, 154 .p1_rxb_init = {R_PATH1_RXB_INIT_V1, B_PATH1_RXB_INIT_IDX_MSK_V1}, 155 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC_V1, 156 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 157 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC_V1, 158 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 159 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC_V1, 160 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 161 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC_V1, 162 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 163 }; 164 165 static void rtw8852c_ctrl_btg(struct rtw89_dev *rtwdev, bool btg); 166 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, 167 enum rtw89_mac_idx mac_idx); 168 169 static int rtw8852c_pwr_on_func(struct rtw89_dev *rtwdev) 170 { 171 u32 val32; 172 u32 ret; 173 174 val32 = rtw89_read32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_PAD_HCI_SEL_V2_MASK); 175 if (val32 == MAC_AX_HCI_SEL_PCIE_USB) 176 rtw89_write32_set(rtwdev, R_AX_LDO_AON_CTRL0, B_AX_PD_REGU_L); 177 178 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_AFSM_WLSUS_EN | 179 B_AX_AFSM_PCIE_SUS_EN); 180 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_DIS_WLBT_PDNSUSEN_SOPC); 181 rtw89_write32_set(rtwdev, R_AX_WLLPS_CTRL, B_AX_DIS_WLBT_LPSEN_LOPC); 182 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APDM_HPDN); 183 rtw89_write32_clr(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 184 185 ret = read_poll_timeout(rtw89_read32, val32, val32 & B_AX_RDY_SYSPWR, 186 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 187 if (ret) 188 return ret; 189 190 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 191 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFN_ONMAC); 192 193 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFN_ONMAC), 194 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 195 if (ret) 196 return ret; 197 198 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 199 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 200 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 201 rtw89_write8_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 202 203 rtw89_write8_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 204 rtw89_write32_clr(rtwdev, R_AX_SYS_SDIO_CTRL, B_AX_PCIE_CALIB_EN_V1); 205 206 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_CMAC1_FEN); 207 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, B_AX_R_SYM_ISO_CMAC12PP); 208 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, B_AX_R_SYM_WLCMAC1_P4_PC_EN | 209 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 210 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 211 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 212 B_AX_R_SYM_WLCMAC1_PC_EN); 213 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 214 215 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 216 XTAL_SI_GND_SHDN_WL, XTAL_SI_GND_SHDN_WL); 217 if (ret) 218 return ret; 219 220 rtw89_write32_set(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 221 222 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 223 XTAL_SI_SHDN_WL, XTAL_SI_SHDN_WL); 224 if (ret) 225 return ret; 226 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_WEI, 227 XTAL_SI_OFF_WEI); 228 if (ret) 229 return ret; 230 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_OFF_EI, 231 XTAL_SI_OFF_EI); 232 if (ret) 233 return ret; 234 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_RFC2RF); 235 if (ret) 236 return ret; 237 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_WEI, 238 XTAL_SI_PON_WEI); 239 if (ret) 240 return ret; 241 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_PON_EI, 242 XTAL_SI_PON_EI); 243 if (ret) 244 return ret; 245 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SRAM2RFC); 246 if (ret) 247 return ret; 248 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_2, 0, XTAL_SI_LDO_LPS); 249 if (ret) 250 return ret; 251 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_XMD_4, 0, XTAL_SI_LPS_CAP); 252 if (ret) 253 return ret; 254 255 rtw89_write32_set(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 256 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_ISO_EB2CORE); 257 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B15); 258 259 fsleep(1000); 260 261 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL, B_AX_PWC_EV2EF_B14); 262 rtw89_write32_clr(rtwdev, R_AX_PMC_DBG_CTRL2, B_AX_SYSON_DIS_PMCR_AX_WRMSK); 263 rtw89_write32_set(rtwdev, R_AX_GPIO0_15_EECS_EESK_LED1_PULL_LOW_EN, 264 B_AX_EECS_PULL_LOW_EN | B_AX_EESK_PULL_LOW_EN | 265 B_AX_LED1_PULL_LOW_EN); 266 267 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 268 B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_MPDU_PROC_EN | 269 B_AX_WD_RLS_EN | B_AX_DLE_WDE_EN | B_AX_TXPKT_CTRL_EN | 270 B_AX_STA_SCH_EN | B_AX_DLE_PLE_EN | B_AX_PKT_BUF_EN | 271 B_AX_DMAC_TBL_EN | B_AX_PKT_IN_EN | B_AX_DLE_CPUIO_EN | 272 B_AX_DISPATCHER_EN | B_AX_BBRPT_EN | B_AX_MAC_SEC_EN | 273 B_AX_MAC_UN_EN | B_AX_H_AXIDMA_EN); 274 275 rtw89_write32_set(rtwdev, R_AX_CMAC_FUNC_EN, 276 B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 277 B_AX_FORCE_CMACREG_GCKEN | B_AX_PHYINTF_EN | 278 B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | B_AX_SCHEDULER_EN | 279 B_AX_TMAC_EN | B_AX_RMAC_EN); 280 281 rtw89_write32_mask(rtwdev, R_AX_LED1_FUNC_SEL, B_AX_PINMUX_EESK_FUNC_SEL_V1_MASK, 282 PINMUX_EESK_FUNC_SEL_BT_LOG); 283 284 return 0; 285 } 286 287 static int rtw8852c_pwr_off_func(struct rtw89_dev *rtwdev) 288 { 289 u32 val32; 290 u32 ret; 291 292 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_RFC2RF, 293 XTAL_SI_RFC2RF); 294 if (ret) 295 return ret; 296 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_EI); 297 if (ret) 298 return ret; 299 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_OFF_WEI); 300 if (ret) 301 return ret; 302 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0, XTAL_SI_RF00); 303 if (ret) 304 return ret; 305 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0, XTAL_SI_RF10); 306 if (ret) 307 return ret; 308 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, XTAL_SI_SRAM2RFC, 309 XTAL_SI_SRAM2RFC); 310 if (ret) 311 return ret; 312 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_EI); 313 if (ret) 314 return ret; 315 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_PON_WEI); 316 if (ret) 317 return ret; 318 319 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_EN_WLON); 320 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, B_AX_FEN_BB_GLB_RSTN | B_AX_FEN_BBRSTB); 321 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 322 B_AX_R_SYM_FEN_WLBBGLB_1 | B_AX_R_SYM_FEN_WLBBFUN_1); 323 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_RFC_1P3); 324 325 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_SHDN_WL); 326 if (ret) 327 return ret; 328 329 rtw89_write32_clr(rtwdev, R_AX_SYS_ADIE_PAD_PWR_CTRL, B_AX_SYM_PADPDN_WL_PTA_1P3); 330 331 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, XTAL_SI_GND_SHDN_WL); 332 if (ret) 333 return ret; 334 335 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_OFFMAC); 336 337 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_APFM_OFFMAC), 338 1000, 20000, false, rtwdev, R_AX_SYS_PW_CTRL); 339 if (ret) 340 return ret; 341 342 rtw89_write32(rtwdev, R_AX_WLLPS_CTRL, 0x0001A0B0); 343 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_XTAL_OFF_A_DIE); 344 rtw89_write32_set(rtwdev, R_AX_SYS_PW_CTRL, B_AX_APFM_SWLPS); 345 346 return 0; 347 } 348 349 static void rtw8852c_e_efuse_parsing(struct rtw89_efuse *efuse, 350 struct rtw8852c_efuse *map) 351 { 352 ether_addr_copy(efuse->addr, map->e.mac_addr); 353 efuse->rfe_type = map->rfe_type; 354 efuse->xtal_cap = map->xtal_k; 355 } 356 357 static void rtw8852c_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 358 struct rtw8852c_efuse *map) 359 { 360 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 361 struct rtw8852c_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 362 u8 *bw40_1s_tssi_6g_ofst[] = {map->bw40_1s_tssi_6g_a, map->bw40_1s_tssi_6g_b}; 363 u8 i, j; 364 365 tssi->thermal[RF_PATH_A] = map->path_a_therm; 366 tssi->thermal[RF_PATH_B] = map->path_b_therm; 367 368 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 369 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 370 sizeof(ofst[i]->cck_tssi)); 371 372 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 373 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 374 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 375 i, j, tssi->tssi_cck[i][j]); 376 377 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 378 sizeof(ofst[i]->bw40_tssi)); 379 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 380 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 381 memcpy(tssi->tssi_6g_mcs[i], bw40_1s_tssi_6g_ofst[i], 382 sizeof(tssi->tssi_6g_mcs[i])); 383 384 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 385 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 386 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 387 i, j, tssi->tssi_mcs[i][j]); 388 } 389 } 390 391 static bool _decode_efuse_gain(u8 data, s8 *high, s8 *low) 392 { 393 if (high) 394 *high = sign_extend32(FIELD_GET(GENMASK(7, 4), data), 3); 395 if (low) 396 *low = sign_extend32(FIELD_GET(GENMASK(3, 0), data), 3); 397 398 return data != 0xff; 399 } 400 401 static void rtw8852c_efuse_parsing_gain_offset(struct rtw89_dev *rtwdev, 402 struct rtw8852c_efuse *map) 403 { 404 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 405 bool valid = false; 406 407 valid |= _decode_efuse_gain(map->rx_gain_2g_cck, 408 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_CCK], 409 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_CCK]); 410 valid |= _decode_efuse_gain(map->rx_gain_2g_ofdm, 411 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_2G_OFDM], 412 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_2G_OFDM]); 413 valid |= _decode_efuse_gain(map->rx_gain_5g_low, 414 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_LOW], 415 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_LOW]); 416 valid |= _decode_efuse_gain(map->rx_gain_5g_mid, 417 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_MID], 418 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_MID]); 419 valid |= _decode_efuse_gain(map->rx_gain_5g_high, 420 &gain->offset[RF_PATH_A][RTW89_GAIN_OFFSET_5G_HIGH], 421 &gain->offset[RF_PATH_B][RTW89_GAIN_OFFSET_5G_HIGH]); 422 423 gain->offset_valid = valid; 424 } 425 426 static int rtw8852c_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map) 427 { 428 struct rtw89_efuse *efuse = &rtwdev->efuse; 429 struct rtw8852c_efuse *map; 430 431 map = (struct rtw8852c_efuse *)log_map; 432 433 efuse->country_code[0] = map->country_code[0]; 434 efuse->country_code[1] = map->country_code[1]; 435 rtw8852c_efuse_parsing_tssi(rtwdev, map); 436 rtw8852c_efuse_parsing_gain_offset(rtwdev, map); 437 438 switch (rtwdev->hci.type) { 439 case RTW89_HCI_TYPE_PCIE: 440 rtw8852c_e_efuse_parsing(efuse, map); 441 break; 442 default: 443 return -ENOTSUPP; 444 } 445 446 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 447 448 return 0; 449 } 450 451 static void rtw8852c_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 452 { 453 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 454 static const u32 tssi_trim_addr[RF_PATH_NUM_8852C] = {0x5D6, 0x5AB}; 455 static const u32 tssi_trim_addr_6g[RF_PATH_NUM_8852C] = {0x5CE, 0x5A3}; 456 u32 addr = rtwdev->chip->phycap_addr; 457 bool pg = false; 458 u32 ofst; 459 u8 i, j; 460 461 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 462 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 463 /* addrs are in decreasing order */ 464 ofst = tssi_trim_addr[i] - addr - j; 465 tssi->tssi_trim[i][j] = phycap_map[ofst]; 466 467 if (phycap_map[ofst] != 0xff) 468 pg = true; 469 } 470 471 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM_6G; j++) { 472 /* addrs are in decreasing order */ 473 ofst = tssi_trim_addr_6g[i] - addr - j; 474 tssi->tssi_trim_6g[i][j] = phycap_map[ofst]; 475 476 if (phycap_map[ofst] != 0xff) 477 pg = true; 478 } 479 } 480 481 if (!pg) { 482 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 483 memset(tssi->tssi_trim_6g, 0, sizeof(tssi->tssi_trim_6g)); 484 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 485 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 486 } 487 488 for (i = 0; i < RF_PATH_NUM_8852C; i++) 489 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 490 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 491 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 492 i, j, tssi->tssi_trim[i][j], 493 tssi_trim_addr[i] - j); 494 } 495 496 static void rtw8852c_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 497 u8 *phycap_map) 498 { 499 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 500 static const u32 thm_trim_addr[RF_PATH_NUM_8852C] = {0x5DF, 0x5DC}; 501 u32 addr = rtwdev->chip->phycap_addr; 502 u8 i; 503 504 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 505 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 506 507 rtw89_debug(rtwdev, RTW89_DBG_RFK, 508 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 509 i, info->thermal_trim[i]); 510 511 if (info->thermal_trim[i] != 0xff) 512 info->pg_thermal_trim = true; 513 } 514 } 515 516 static void rtw8852c_thermal_trim(struct rtw89_dev *rtwdev) 517 { 518 #define __thm_setting(raw) \ 519 ({ \ 520 u8 __v = (raw); \ 521 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 522 }) 523 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 524 u8 i, val; 525 526 if (!info->pg_thermal_trim) { 527 rtw89_debug(rtwdev, RTW89_DBG_RFK, 528 "[THERMAL][TRIM] no PG, do nothing\n"); 529 530 return; 531 } 532 533 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 534 val = __thm_setting(info->thermal_trim[i]); 535 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 536 537 rtw89_debug(rtwdev, RTW89_DBG_RFK, 538 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 539 i, val); 540 } 541 #undef __thm_setting 542 } 543 544 static void rtw8852c_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 545 u8 *phycap_map) 546 { 547 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 548 static const u32 pabias_trim_addr[RF_PATH_NUM_8852C] = {0x5DE, 0x5DB}; 549 u32 addr = rtwdev->chip->phycap_addr; 550 u8 i; 551 552 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 553 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 554 555 rtw89_debug(rtwdev, RTW89_DBG_RFK, 556 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 557 i, info->pa_bias_trim[i]); 558 559 if (info->pa_bias_trim[i] != 0xff) 560 info->pg_pa_bias_trim = true; 561 } 562 } 563 564 static void rtw8852c_pa_bias_trim(struct rtw89_dev *rtwdev) 565 { 566 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 567 u8 pabias_2g, pabias_5g; 568 u8 i; 569 570 if (!info->pg_pa_bias_trim) { 571 rtw89_debug(rtwdev, RTW89_DBG_RFK, 572 "[PA_BIAS][TRIM] no PG, do nothing\n"); 573 574 return; 575 } 576 577 for (i = 0; i < RF_PATH_NUM_8852C; i++) { 578 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 579 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 580 581 rtw89_debug(rtwdev, RTW89_DBG_RFK, 582 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 583 i, pabias_2g, pabias_5g); 584 585 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 586 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 587 } 588 } 589 590 static int rtw8852c_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 591 { 592 rtw8852c_phycap_parsing_tssi(rtwdev, phycap_map); 593 rtw8852c_phycap_parsing_thermal_trim(rtwdev, phycap_map); 594 rtw8852c_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 595 596 return 0; 597 } 598 599 static void rtw8852c_power_trim(struct rtw89_dev *rtwdev) 600 { 601 rtw8852c_thermal_trim(rtwdev); 602 rtw8852c_pa_bias_trim(rtwdev); 603 } 604 605 static void rtw8852c_set_channel_mac(struct rtw89_dev *rtwdev, 606 const struct rtw89_chan *chan, 607 u8 mac_idx) 608 { 609 u32 rf_mod = rtw89_mac_reg_by_idx(R_AX_WMAC_RFMOD, mac_idx); 610 u32 sub_carr = rtw89_mac_reg_by_idx(R_AX_TX_SUB_CARRIER_VALUE, 611 mac_idx); 612 u32 chk_rate = rtw89_mac_reg_by_idx(R_AX_TXRATE_CHK, mac_idx); 613 u8 txsc20 = 0, txsc40 = 0, txsc80 = 0; 614 u8 rf_mod_val = 0, chk_rate_mask = 0; 615 u32 txsc; 616 617 switch (chan->band_width) { 618 case RTW89_CHANNEL_WIDTH_160: 619 txsc80 = rtw89_phy_get_txsc(rtwdev, chan, 620 RTW89_CHANNEL_WIDTH_80); 621 fallthrough; 622 case RTW89_CHANNEL_WIDTH_80: 623 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, 624 RTW89_CHANNEL_WIDTH_40); 625 fallthrough; 626 case RTW89_CHANNEL_WIDTH_40: 627 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, 628 RTW89_CHANNEL_WIDTH_20); 629 break; 630 default: 631 break; 632 } 633 634 switch (chan->band_width) { 635 case RTW89_CHANNEL_WIDTH_160: 636 rf_mod_val = AX_WMAC_RFMOD_160M; 637 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) | 638 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40) | 639 FIELD_PREP(B_AX_TXSC_80M_MASK, txsc80); 640 break; 641 case RTW89_CHANNEL_WIDTH_80: 642 rf_mod_val = AX_WMAC_RFMOD_80M; 643 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20) | 644 FIELD_PREP(B_AX_TXSC_40M_MASK, txsc40); 645 break; 646 case RTW89_CHANNEL_WIDTH_40: 647 rf_mod_val = AX_WMAC_RFMOD_40M; 648 txsc = FIELD_PREP(B_AX_TXSC_20M_MASK, txsc20); 649 break; 650 case RTW89_CHANNEL_WIDTH_20: 651 default: 652 rf_mod_val = AX_WMAC_RFMOD_20M; 653 txsc = 0; 654 break; 655 } 656 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, rf_mod_val); 657 rtw89_write32(rtwdev, sub_carr, txsc); 658 659 switch (chan->band_type) { 660 case RTW89_BAND_2G: 661 chk_rate_mask = B_AX_BAND_MODE; 662 break; 663 case RTW89_BAND_5G: 664 case RTW89_BAND_6G: 665 chk_rate_mask = B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6; 666 break; 667 default: 668 rtw89_warn(rtwdev, "Invalid band_type:%d\n", chan->band_type); 669 return; 670 } 671 rtw89_write8_clr(rtwdev, chk_rate, B_AX_BAND_MODE | B_AX_CHECK_CCK_EN | 672 B_AX_RTS_LIMIT_IN_OFDM6); 673 rtw89_write8_set(rtwdev, chk_rate, chk_rate_mask); 674 } 675 676 static const u32 rtw8852c_sco_barker_threshold[14] = { 677 0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6, 678 0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a 679 }; 680 681 static const u32 rtw8852c_sco_cck_threshold[14] = { 682 0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db, 683 0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e 684 }; 685 686 static int rtw8852c_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 687 u8 primary_ch, enum rtw89_bandwidth bw) 688 { 689 u8 ch_element; 690 691 if (bw == RTW89_CHANNEL_WIDTH_20) { 692 ch_element = central_ch - 1; 693 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 694 if (primary_ch == 1) 695 ch_element = central_ch - 1 + 2; 696 else 697 ch_element = central_ch - 1 - 2; 698 } else { 699 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 700 return -EINVAL; 701 } 702 rtw89_phy_write32_mask(rtwdev, R_BK_FC0_INV_V1, B_BK_FC0_INV_MSK_V1, 703 rtw8852c_sco_barker_threshold[ch_element]); 704 rtw89_phy_write32_mask(rtwdev, R_CCK_FC0_INV_V1, B_CCK_FC0_INV_MSK_V1, 705 rtw8852c_sco_cck_threshold[ch_element]); 706 707 return 0; 708 } 709 710 struct rtw8852c_bb_gain { 711 u32 gain_g[BB_PATH_NUM_8852C]; 712 u32 gain_a[BB_PATH_NUM_8852C]; 713 u32 gain_mask; 714 }; 715 716 static const struct rtw8852c_bb_gain bb_gain_lna[LNA_GAIN_NUM] = { 717 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 718 .gain_mask = 0x00ff0000 }, 719 { .gain_g = {0x4678, 0x475C}, .gain_a = {0x45DC, 0x4740}, 720 .gain_mask = 0xff000000 }, 721 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 722 .gain_mask = 0x000000ff }, 723 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 724 .gain_mask = 0x0000ff00 }, 725 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 726 .gain_mask = 0x00ff0000 }, 727 { .gain_g = {0x467C, 0x4760}, .gain_a = {0x4660, 0x4744}, 728 .gain_mask = 0xff000000 }, 729 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 730 .gain_mask = 0x000000ff }, 731 }; 732 733 static const struct rtw8852c_bb_gain bb_gain_tia[TIA_GAIN_NUM] = { 734 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 735 .gain_mask = 0x00ff0000 }, 736 { .gain_g = {0x4680, 0x4764}, .gain_a = {0x4664, 0x4748}, 737 .gain_mask = 0xff000000 }, 738 }; 739 740 struct rtw8852c_bb_gain_bypass { 741 u32 gain_g[BB_PATH_NUM_8852C]; 742 u32 gain_a[BB_PATH_NUM_8852C]; 743 u32 gain_mask_g; 744 u32 gain_mask_a; 745 }; 746 747 static 748 const struct rtw8852c_bb_gain_bypass bb_gain_bypass_lna[LNA_GAIN_NUM] = { 749 { .gain_g = {0x4BB8, 0x4C7C}, .gain_a = {0x4BB4, 0x4C78}, 750 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff}, 751 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 752 .gain_mask_g = 0xff, .gain_mask_a = 0xff00}, 753 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 754 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000}, 755 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB4, 0x4C78}, 756 .gain_mask_g = 0xff0000, .gain_mask_a = 0xff000000}, 757 { .gain_g = {0x4BBC, 0x4C80}, .gain_a = {0x4BB8, 0x4C7C}, 758 .gain_mask_g = 0xff000000, .gain_mask_a = 0xff}, 759 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C}, 760 .gain_mask_g = 0xff, .gain_mask_a = 0xff00}, 761 { .gain_g = {0x4BC0, 0x4C84}, .gain_a = {0x4BB8, 0x4C7C}, 762 .gain_mask_g = 0xff00, .gain_mask_a = 0xff0000}, 763 }; 764 765 struct rtw8852c_bb_gain_op1db { 766 struct { 767 u32 lna[BB_PATH_NUM_8852C]; 768 u32 tia_lna[BB_PATH_NUM_8852C]; 769 u32 mask; 770 } reg[LNA_GAIN_NUM]; 771 u32 reg_tia0_lna6[BB_PATH_NUM_8852C]; 772 u32 mask_tia0_lna6; 773 }; 774 775 static const struct rtw8852c_bb_gain_op1db bb_gain_op1db_a = { 776 .reg = { 777 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 778 .mask = 0xff}, 779 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 780 .mask = 0xff00}, 781 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 782 .mask = 0xff0000}, 783 { .lna = {0x4668, 0x474c}, .tia_lna = {0x4670, 0x4754}, 784 .mask = 0xff000000}, 785 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 786 .mask = 0xff}, 787 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 788 .mask = 0xff00}, 789 { .lna = {0x466c, 0x4750}, .tia_lna = {0x4674, 0x4758}, 790 .mask = 0xff0000}, 791 }, 792 .reg_tia0_lna6 = {0x4674, 0x4758}, 793 .mask_tia0_lna6 = 0xff000000, 794 }; 795 796 static void rtw8852c_set_gain_error(struct rtw89_dev *rtwdev, 797 enum rtw89_subband subband, 798 enum rtw89_rf_path path) 799 { 800 const struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 801 u8 gain_band = rtw89_subband_to_bb_gain_band(subband); 802 s32 val; 803 u32 reg; 804 u32 mask; 805 int i; 806 807 for (i = 0; i < LNA_GAIN_NUM; i++) { 808 if (subband == RTW89_CH_2G) 809 reg = bb_gain_lna[i].gain_g[path]; 810 else 811 reg = bb_gain_lna[i].gain_a[path]; 812 813 mask = bb_gain_lna[i].gain_mask; 814 val = gain->lna_gain[gain_band][path][i]; 815 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 816 817 if (subband == RTW89_CH_2G) { 818 reg = bb_gain_bypass_lna[i].gain_g[path]; 819 mask = bb_gain_bypass_lna[i].gain_mask_g; 820 } else { 821 reg = bb_gain_bypass_lna[i].gain_a[path]; 822 mask = bb_gain_bypass_lna[i].gain_mask_a; 823 } 824 825 val = gain->lna_gain_bypass[gain_band][path][i]; 826 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 827 828 if (subband != RTW89_CH_2G) { 829 reg = bb_gain_op1db_a.reg[i].lna[path]; 830 mask = bb_gain_op1db_a.reg[i].mask; 831 val = gain->lna_op1db[gain_band][path][i]; 832 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 833 834 reg = bb_gain_op1db_a.reg[i].tia_lna[path]; 835 mask = bb_gain_op1db_a.reg[i].mask; 836 val = gain->tia_lna_op1db[gain_band][path][i]; 837 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 838 } 839 } 840 841 if (subband != RTW89_CH_2G) { 842 reg = bb_gain_op1db_a.reg_tia0_lna6[path]; 843 mask = bb_gain_op1db_a.mask_tia0_lna6; 844 val = gain->tia_lna_op1db[gain_band][path][7]; 845 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 846 } 847 848 for (i = 0; i < TIA_GAIN_NUM; i++) { 849 if (subband == RTW89_CH_2G) 850 reg = bb_gain_tia[i].gain_g[path]; 851 else 852 reg = bb_gain_tia[i].gain_a[path]; 853 854 mask = bb_gain_tia[i].gain_mask; 855 val = gain->tia_gain[gain_band][path][i]; 856 rtw89_phy_write32_mask(rtwdev, reg, mask, val); 857 } 858 } 859 860 static void rtw8852c_set_gain_offset(struct rtw89_dev *rtwdev, 861 const struct rtw89_chan *chan, 862 enum rtw89_phy_idx phy_idx, 863 enum rtw89_rf_path path) 864 { 865 static const u32 rssi_ofst_addr[2] = {R_PATH0_G_TIA0_LNA6_OP1DB_V1, 866 R_PATH1_G_TIA0_LNA6_OP1DB_V1}; 867 static const u32 rpl_mask[2] = {B_RPL_PATHA_MASK, B_RPL_PATHB_MASK}; 868 static const u32 rpl_tb_mask[2] = {B_RSSI_M_PATHA_MASK, B_RSSI_M_PATHB_MASK}; 869 struct rtw89_phy_efuse_gain *efuse_gain = &rtwdev->efuse_gain; 870 enum rtw89_gain_offset gain_band; 871 s32 offset_q0, offset_base_q4; 872 s32 tmp = 0; 873 874 if (!efuse_gain->offset_valid) 875 return; 876 877 if (rtwdev->dbcc_en && path == RF_PATH_B) 878 phy_idx = RTW89_PHY_1; 879 880 if (chan->band_type == RTW89_BAND_2G) { 881 offset_q0 = efuse_gain->offset[path][RTW89_GAIN_OFFSET_2G_CCK]; 882 offset_base_q4 = efuse_gain->offset_base[phy_idx]; 883 884 tmp = clamp_t(s32, (-offset_q0 << 3) + (offset_base_q4 >> 1), 885 S8_MIN >> 1, S8_MAX >> 1); 886 rtw89_phy_write32_mask(rtwdev, R_RPL_OFST, B_RPL_OFST_MASK, tmp & 0x7f); 887 } 888 889 gain_band = rtw89_subband_to_gain_offset_band_of_ofdm(chan->subband_type); 890 891 offset_q0 = -efuse_gain->offset[path][gain_band]; 892 offset_base_q4 = efuse_gain->offset_base[phy_idx]; 893 894 tmp = (offset_q0 << 2) + (offset_base_q4 >> 2); 895 tmp = clamp_t(s32, -tmp, S8_MIN, S8_MAX); 896 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], B_PATH0_R_G_OFST_MASK, tmp & 0xff); 897 898 tmp = clamp_t(s32, offset_q0 << 4, S8_MIN, S8_MAX); 899 rtw89_phy_write32_idx(rtwdev, R_RPL_PATHAB, rpl_mask[path], tmp & 0xff, phy_idx); 900 rtw89_phy_write32_idx(rtwdev, R_RSSI_M_PATHAB, rpl_tb_mask[path], tmp & 0xff, phy_idx); 901 } 902 903 static void rtw8852c_ctrl_ch(struct rtw89_dev *rtwdev, 904 const struct rtw89_chan *chan, 905 enum rtw89_phy_idx phy_idx) 906 { 907 u8 sco; 908 u16 central_freq = chan->freq; 909 u8 central_ch = chan->channel; 910 u8 band = chan->band_type; 911 u8 subband = chan->subband_type; 912 bool is_2g = band == RTW89_BAND_2G; 913 u8 chan_idx; 914 915 if (!central_freq) { 916 rtw89_warn(rtwdev, "Invalid central_freq\n"); 917 return; 918 } 919 920 if (phy_idx == RTW89_PHY_0) { 921 /* Path A */ 922 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_A); 923 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_A); 924 925 if (is_2g) 926 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 927 B_PATH0_BAND_SEL_MSK_V1, 1, 928 phy_idx); 929 else 930 rtw89_phy_write32_idx(rtwdev, R_PATH0_BAND_SEL_V1, 931 B_PATH0_BAND_SEL_MSK_V1, 0, 932 phy_idx); 933 /* Path B */ 934 if (!rtwdev->dbcc_en) { 935 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B); 936 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B); 937 938 if (is_2g) 939 rtw89_phy_write32_idx(rtwdev, 940 R_PATH1_BAND_SEL_V1, 941 B_PATH1_BAND_SEL_MSK_V1, 942 1, phy_idx); 943 else 944 rtw89_phy_write32_idx(rtwdev, 945 R_PATH1_BAND_SEL_V1, 946 B_PATH1_BAND_SEL_MSK_V1, 947 0, phy_idx); 948 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 949 } else { 950 if (is_2g) 951 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 952 else 953 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, B_2P4G_BAND_SEL); 954 } 955 /* SCO compensate FC setting */ 956 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1, 957 central_freq, phy_idx); 958 /* round_up((1/fc0)*pow(2,18)) */ 959 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq); 960 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco, 961 phy_idx); 962 } else { 963 /* Path B */ 964 rtw8852c_set_gain_error(rtwdev, subband, RF_PATH_B); 965 rtw8852c_set_gain_offset(rtwdev, chan, phy_idx, RF_PATH_B); 966 967 if (is_2g) 968 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 969 B_PATH1_BAND_SEL_MSK_V1, 970 1, phy_idx); 971 else 972 rtw89_phy_write32_idx(rtwdev, R_PATH1_BAND_SEL_V1, 973 B_PATH1_BAND_SEL_MSK_V1, 974 0, phy_idx); 975 /* SCO compensate FC setting */ 976 rtw89_phy_write32_idx(rtwdev, R_FC0_V1, B_FC0_MSK_V1, 977 central_freq, phy_idx); 978 /* round_up((1/fc0)*pow(2,18)) */ 979 sco = DIV_ROUND_CLOSEST(1 << 18, central_freq); 980 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, sco, 981 phy_idx); 982 } 983 /* CCK parameters */ 984 if (band == RTW89_BAND_2G) { 985 if (central_ch == 14) { 986 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1, 987 B_PCOEFF01_MSK_V1, 0x3b13ff); 988 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1, 989 B_PCOEFF23_MSK_V1, 0x1c42de); 990 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1, 991 B_PCOEFF45_MSK_V1, 0xfdb0ad); 992 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1, 993 B_PCOEFF67_MSK_V1, 0xf60f6e); 994 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1, 995 B_PCOEFF89_MSK_V1, 0xfd8f92); 996 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1, 997 B_PCOEFFAB_MSK_V1, 0x2d011); 998 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1, 999 B_PCOEFFCD_MSK_V1, 0x1c02c); 1000 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1, 1001 B_PCOEFFEF_MSK_V1, 0xfff00a); 1002 } else { 1003 rtw89_phy_write32_mask(rtwdev, R_PCOEFF0_V1, 1004 B_PCOEFF01_MSK_V1, 0x3d23ff); 1005 rtw89_phy_write32_mask(rtwdev, R_PCOEFF2_V1, 1006 B_PCOEFF23_MSK_V1, 0x29b354); 1007 rtw89_phy_write32_mask(rtwdev, R_PCOEFF4_V1, 1008 B_PCOEFF45_MSK_V1, 0xfc1c8); 1009 rtw89_phy_write32_mask(rtwdev, R_PCOEFF6_V1, 1010 B_PCOEFF67_MSK_V1, 0xfdb053); 1011 rtw89_phy_write32_mask(rtwdev, R_PCOEFF8_V1, 1012 B_PCOEFF89_MSK_V1, 0xf86f9a); 1013 rtw89_phy_write32_mask(rtwdev, R_PCOEFFA_V1, 1014 B_PCOEFFAB_MSK_V1, 0xfaef92); 1015 rtw89_phy_write32_mask(rtwdev, R_PCOEFFC_V1, 1016 B_PCOEFFCD_MSK_V1, 0xfe5fcc); 1017 rtw89_phy_write32_mask(rtwdev, R_PCOEFFE_V1, 1018 B_PCOEFFEF_MSK_V1, 0xffdff5); 1019 } 1020 } 1021 1022 chan_idx = rtw89_encode_chan_idx(rtwdev, chan->primary_channel, band); 1023 rtw89_phy_write32_idx(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, chan_idx, phy_idx); 1024 } 1025 1026 static void rtw8852c_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 1027 { 1028 static const u32 adc_sel[2] = {0xC0EC, 0xC1EC}; 1029 static const u32 wbadc_sel[2] = {0xC0E4, 0xC1E4}; 1030 1031 switch (bw) { 1032 case RTW89_CHANNEL_WIDTH_5: 1033 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 1034 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 1035 break; 1036 case RTW89_CHANNEL_WIDTH_10: 1037 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 1038 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 1039 break; 1040 case RTW89_CHANNEL_WIDTH_20: 1041 case RTW89_CHANNEL_WIDTH_40: 1042 case RTW89_CHANNEL_WIDTH_80: 1043 case RTW89_CHANNEL_WIDTH_160: 1044 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 1045 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 1046 break; 1047 default: 1048 rtw89_warn(rtwdev, "Fail to set ADC\n"); 1049 } 1050 } 1051 1052 static void rtw8852c_edcca_per20_bitmap_sifs(struct rtw89_dev *rtwdev, u8 bw, 1053 enum rtw89_phy_idx phy_idx) 1054 { 1055 if (bw == RTW89_CHANNEL_WIDTH_20) { 1056 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0xff, phy_idx); 1057 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx); 1058 } else { 1059 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A1, B_SNDCCA_A1_EN, 0, phy_idx); 1060 rtw89_phy_write32_idx(rtwdev, R_SNDCCA_A2, B_SNDCCA_A2_VAL, 0, phy_idx); 1061 } 1062 } 1063 1064 static void 1065 rtw8852c_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 1066 enum rtw89_phy_idx phy_idx) 1067 { 1068 u8 mod_sbw = 0; 1069 1070 switch (bw) { 1071 case RTW89_CHANNEL_WIDTH_5: 1072 case RTW89_CHANNEL_WIDTH_10: 1073 case RTW89_CHANNEL_WIDTH_20: 1074 if (bw == RTW89_CHANNEL_WIDTH_5) 1075 mod_sbw = 0x1; 1076 else if (bw == RTW89_CHANNEL_WIDTH_10) 1077 mod_sbw = 0x2; 1078 else if (bw == RTW89_CHANNEL_WIDTH_20) 1079 mod_sbw = 0x0; 1080 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1081 phy_idx); 1082 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 1083 mod_sbw, phy_idx); 1084 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 0x0, 1085 phy_idx); 1086 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1087 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); 1088 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1089 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); 1090 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1091 B_PATH0_BW_SEL_MSK_V1, 0xf); 1092 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1093 B_PATH1_BW_SEL_MSK_V1, 0xf); 1094 break; 1095 case RTW89_CHANNEL_WIDTH_40: 1096 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 1097 phy_idx); 1098 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1099 phy_idx); 1100 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1101 pri_ch, 1102 phy_idx); 1103 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1104 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x3); 1105 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1106 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x3); 1107 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1108 B_PATH0_BW_SEL_MSK_V1, 0xf); 1109 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1110 B_PATH1_BW_SEL_MSK_V1, 0xf); 1111 break; 1112 case RTW89_CHANNEL_WIDTH_80: 1113 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 1114 phy_idx); 1115 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1116 phy_idx); 1117 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1118 pri_ch, 1119 phy_idx); 1120 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1121 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x2); 1122 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1123 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x2); 1124 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1125 B_PATH0_BW_SEL_MSK_V1, 0xd); 1126 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1127 B_PATH1_BW_SEL_MSK_V1, 0xd); 1128 break; 1129 case RTW89_CHANNEL_WIDTH_160: 1130 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x3, 1131 phy_idx); 1132 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1133 phy_idx); 1134 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1135 pri_ch, 1136 phy_idx); 1137 rtw89_phy_write32_mask(rtwdev, R_PATH0_SAMPL_DLY_T_V1, 1138 B_PATH0_SAMPL_DLY_T_MSK_V1, 0x1); 1139 rtw89_phy_write32_mask(rtwdev, R_PATH1_SAMPL_DLY_T_V1, 1140 B_PATH1_SAMPL_DLY_T_MSK_V1, 0x1); 1141 rtw89_phy_write32_mask(rtwdev, R_PATH0_BW_SEL_V1, 1142 B_PATH0_BW_SEL_MSK_V1, 0xb); 1143 rtw89_phy_write32_mask(rtwdev, R_PATH1_BW_SEL_V1, 1144 B_PATH1_BW_SEL_MSK_V1, 0xb); 1145 break; 1146 default: 1147 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1148 pri_ch); 1149 } 1150 1151 if (bw == RTW89_CHANNEL_WIDTH_40) { 1152 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1, 1153 B_RX_BW40_2XFFT_EN_MSK_V1, 0x1, phy_idx); 1154 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 1, phy_idx); 1155 } else { 1156 rtw89_phy_write32_idx(rtwdev, R_RX_BW40_2XFFT_EN_V1, 1157 B_RX_BW40_2XFFT_EN_MSK_V1, 0x0, phy_idx); 1158 rtw89_phy_write32_idx(rtwdev, R_T2F_GI_COMB, B_T2F_GI_COMB_EN, 0, phy_idx); 1159 } 1160 1161 if (phy_idx == RTW89_PHY_0) { 1162 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_A); 1163 if (!rtwdev->dbcc_en) 1164 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B); 1165 } else { 1166 rtw8852c_bw_setting(rtwdev, bw, RF_PATH_B); 1167 } 1168 1169 rtw8852c_edcca_per20_bitmap_sifs(rtwdev, bw, phy_idx); 1170 } 1171 1172 static u32 rtw8852c_spur_freq(struct rtw89_dev *rtwdev, 1173 const struct rtw89_chan *chan) 1174 { 1175 u8 center_chan = chan->channel; 1176 u8 bw = chan->band_width; 1177 1178 switch (chan->band_type) { 1179 case RTW89_BAND_2G: 1180 if (bw == RTW89_CHANNEL_WIDTH_20) { 1181 if (center_chan >= 5 && center_chan <= 8) 1182 return 2440; 1183 if (center_chan == 13) 1184 return 2480; 1185 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 1186 if (center_chan >= 3 && center_chan <= 10) 1187 return 2440; 1188 } 1189 break; 1190 case RTW89_BAND_5G: 1191 if (center_chan == 151 || center_chan == 153 || 1192 center_chan == 155 || center_chan == 163) 1193 return 5760; 1194 break; 1195 case RTW89_BAND_6G: 1196 if (center_chan == 195 || center_chan == 197 || 1197 center_chan == 199 || center_chan == 207) 1198 return 6920; 1199 break; 1200 default: 1201 break; 1202 } 1203 1204 return 0; 1205 } 1206 1207 #define CARRIER_SPACING_312_5 312500 /* 312.5 kHz */ 1208 #define CARRIER_SPACING_78_125 78125 /* 78.125 kHz */ 1209 #define MAX_TONE_NUM 2048 1210 1211 static void rtw8852c_set_csi_tone_idx(struct rtw89_dev *rtwdev, 1212 const struct rtw89_chan *chan, 1213 enum rtw89_phy_idx phy_idx) 1214 { 1215 u32 spur_freq; 1216 s32 freq_diff, csi_idx, csi_tone_idx; 1217 1218 spur_freq = rtw8852c_spur_freq(rtwdev, chan); 1219 if (spur_freq == 0) { 1220 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 0, phy_idx); 1221 return; 1222 } 1223 1224 freq_diff = (spur_freq - chan->freq) * 1000000; 1225 csi_idx = s32_div_u32_round_closest(freq_diff, CARRIER_SPACING_78_125); 1226 s32_div_u32_round_down(csi_idx, MAX_TONE_NUM, &csi_tone_idx); 1227 1228 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, csi_tone_idx, phy_idx); 1229 rtw89_phy_write32_idx(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1, phy_idx); 1230 } 1231 1232 static const struct rtw89_nbi_reg_def rtw8852c_nbi_reg_def[] = { 1233 [RF_PATH_A] = { 1234 .notch1_idx = {0x4C14, 0xFF}, 1235 .notch1_frac_idx = {0x4C14, 0xC00}, 1236 .notch1_en = {0x4C14, 0x1000}, 1237 .notch2_idx = {0x4C20, 0xFF}, 1238 .notch2_frac_idx = {0x4C20, 0xC00}, 1239 .notch2_en = {0x4C20, 0x1000}, 1240 }, 1241 [RF_PATH_B] = { 1242 .notch1_idx = {0x4CD8, 0xFF}, 1243 .notch1_frac_idx = {0x4CD8, 0xC00}, 1244 .notch1_en = {0x4CD8, 0x1000}, 1245 .notch2_idx = {0x4CE4, 0xFF}, 1246 .notch2_frac_idx = {0x4CE4, 0xC00}, 1247 .notch2_en = {0x4CE4, 0x1000}, 1248 }, 1249 }; 1250 1251 static void rtw8852c_set_nbi_tone_idx(struct rtw89_dev *rtwdev, 1252 const struct rtw89_chan *chan, 1253 enum rtw89_rf_path path) 1254 { 1255 const struct rtw89_nbi_reg_def *nbi = &rtw8852c_nbi_reg_def[path]; 1256 u32 spur_freq, fc; 1257 s32 freq_diff; 1258 s32 nbi_idx, nbi_tone_idx; 1259 s32 nbi_frac_idx, nbi_frac_tone_idx; 1260 bool notch2_chk = false; 1261 1262 spur_freq = rtw8852c_spur_freq(rtwdev, chan); 1263 if (spur_freq == 0) { 1264 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1265 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1266 return; 1267 } 1268 1269 fc = chan->freq; 1270 if (chan->band_width == RTW89_CHANNEL_WIDTH_160) { 1271 fc = (spur_freq > fc) ? fc + 40 : fc - 40; 1272 if ((fc > spur_freq && 1273 chan->channel < chan->primary_channel) || 1274 (fc < spur_freq && 1275 chan->channel > chan->primary_channel)) 1276 notch2_chk = true; 1277 } 1278 1279 freq_diff = (spur_freq - fc) * 1000000; 1280 nbi_idx = s32_div_u32_round_down(freq_diff, CARRIER_SPACING_312_5, &nbi_frac_idx); 1281 1282 if (chan->band_width == RTW89_CHANNEL_WIDTH_20) { 1283 s32_div_u32_round_down(nbi_idx + 32, 64, &nbi_tone_idx); 1284 } else { 1285 u16 tone_para = (chan->band_width == RTW89_CHANNEL_WIDTH_40) ? 1286 128 : 256; 1287 1288 s32_div_u32_round_down(nbi_idx, tone_para, &nbi_tone_idx); 1289 } 1290 nbi_frac_tone_idx = s32_div_u32_round_closest(nbi_frac_idx, CARRIER_SPACING_78_125); 1291 1292 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && notch2_chk) { 1293 rtw89_phy_write32_mask(rtwdev, nbi->notch2_idx.addr, 1294 nbi->notch2_idx.mask, nbi_tone_idx); 1295 rtw89_phy_write32_mask(rtwdev, nbi->notch2_frac_idx.addr, 1296 nbi->notch2_frac_idx.mask, nbi_frac_tone_idx); 1297 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0); 1298 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 1); 1299 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1300 } else { 1301 rtw89_phy_write32_mask(rtwdev, nbi->notch1_idx.addr, 1302 nbi->notch1_idx.mask, nbi_tone_idx); 1303 rtw89_phy_write32_mask(rtwdev, nbi->notch1_frac_idx.addr, 1304 nbi->notch1_frac_idx.mask, nbi_frac_tone_idx); 1305 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 0); 1306 rtw89_phy_write32_mask(rtwdev, nbi->notch1_en.addr, nbi->notch1_en.mask, 1); 1307 rtw89_phy_write32_mask(rtwdev, nbi->notch2_en.addr, nbi->notch2_en.mask, 0); 1308 } 1309 } 1310 1311 static void rtw8852c_spur_notch(struct rtw89_dev *rtwdev, u32 val, 1312 enum rtw89_phy_idx phy_idx) 1313 { 1314 u32 notch; 1315 u32 notch2; 1316 1317 if (phy_idx == RTW89_PHY_0) { 1318 notch = R_PATH0_NOTCH; 1319 notch2 = R_PATH0_NOTCH2; 1320 } else { 1321 notch = R_PATH1_NOTCH; 1322 notch2 = R_PATH1_NOTCH2; 1323 } 1324 1325 rtw89_phy_write32_mask(rtwdev, notch, 1326 B_PATH0_NOTCH_VAL | B_PATH0_NOTCH_EN, val); 1327 rtw89_phy_write32_set(rtwdev, notch, B_PATH0_NOTCH_EN); 1328 rtw89_phy_write32_mask(rtwdev, notch2, 1329 B_PATH0_NOTCH2_VAL | B_PATH0_NOTCH2_EN, val); 1330 rtw89_phy_write32_set(rtwdev, notch2, B_PATH0_NOTCH2_EN); 1331 } 1332 1333 static void rtw8852c_spur_elimination(struct rtw89_dev *rtwdev, 1334 const struct rtw89_chan *chan, 1335 u8 pri_ch_idx, 1336 enum rtw89_phy_idx phy_idx) 1337 { 1338 rtw8852c_set_csi_tone_idx(rtwdev, chan, phy_idx); 1339 1340 if (phy_idx == RTW89_PHY_0) { 1341 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1342 (pri_ch_idx == RTW89_SC_20_LOWER || 1343 pri_ch_idx == RTW89_SC_20_UP3X)) { 1344 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_0); 1345 if (!rtwdev->dbcc_en) 1346 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1); 1347 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1348 (pri_ch_idx == RTW89_SC_20_UPPER || 1349 pri_ch_idx == RTW89_SC_20_LOW3X)) { 1350 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_0); 1351 if (!rtwdev->dbcc_en) 1352 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1); 1353 } else { 1354 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_A); 1355 if (!rtwdev->dbcc_en) 1356 rtw8852c_set_nbi_tone_idx(rtwdev, chan, 1357 RF_PATH_B); 1358 } 1359 } else { 1360 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1361 (pri_ch_idx == RTW89_SC_20_LOWER || 1362 pri_ch_idx == RTW89_SC_20_UP3X)) { 1363 rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1); 1364 } else if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1365 (pri_ch_idx == RTW89_SC_20_UPPER || 1366 pri_ch_idx == RTW89_SC_20_LOW3X)) { 1367 rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1); 1368 } else { 1369 rtw8852c_set_nbi_tone_idx(rtwdev, chan, RF_PATH_B); 1370 } 1371 } 1372 1373 if (pri_ch_idx == RTW89_SC_20_UP3X || pri_ch_idx == RTW89_SC_20_LOW3X) 1374 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 0, phy_idx); 1375 else 1376 rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 1, phy_idx); 1377 } 1378 1379 static void rtw8852c_5m_mask(struct rtw89_dev *rtwdev, 1380 const struct rtw89_chan *chan, 1381 enum rtw89_phy_idx phy_idx) 1382 { 1383 u8 pri_ch = chan->pri_ch_idx; 1384 bool mask_5m_low; 1385 bool mask_5m_en; 1386 1387 switch (chan->band_width) { 1388 case RTW89_CHANNEL_WIDTH_40: 1389 mask_5m_en = true; 1390 mask_5m_low = pri_ch == RTW89_SC_20_LOWER; 1391 break; 1392 case RTW89_CHANNEL_WIDTH_80: 1393 mask_5m_en = pri_ch == RTW89_SC_20_UPMOST || 1394 pri_ch == RTW89_SC_20_LOWEST; 1395 mask_5m_low = pri_ch == RTW89_SC_20_LOWEST; 1396 break; 1397 default: 1398 mask_5m_en = false; 1399 mask_5m_low = false; 1400 break; 1401 } 1402 1403 if (!mask_5m_en) { 1404 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x0); 1405 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x0); 1406 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, 1407 B_ASSIGN_SBD_OPT_EN, 0x0, phy_idx); 1408 } else { 1409 if (mask_5m_low) { 1410 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4); 1411 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1); 1412 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x0); 1413 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x1); 1414 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4); 1415 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1); 1416 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x0); 1417 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x1); 1418 } else { 1419 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_TH, 0x4); 1420 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_EN, 0x1); 1421 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB2, 0x1); 1422 rtw89_phy_write32_mask(rtwdev, R_PATH0_5MDET, B_PATH0_5MDET_SB0, 0x0); 1423 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_TH, 0x4); 1424 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_EN, 0x1); 1425 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB2, 0x1); 1426 rtw89_phy_write32_mask(rtwdev, R_PATH1_5MDET, B_PATH1_5MDET_SB0, 0x0); 1427 } 1428 rtw89_phy_write32_idx(rtwdev, R_ASSIGN_SBD_OPT, B_ASSIGN_SBD_OPT_EN, 0x1, phy_idx); 1429 } 1430 } 1431 1432 static void rtw8852c_bb_reset_all(struct rtw89_dev *rtwdev, 1433 enum rtw89_phy_idx phy_idx) 1434 { 1435 /*HW SI reset*/ 1436 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 1437 0x7); 1438 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 1439 0x7); 1440 1441 udelay(1); 1442 1443 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1444 phy_idx); 1445 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1446 phy_idx); 1447 /*HW SI reset*/ 1448 rtw89_phy_write32_mask(rtwdev, R_S0_HW_SI_DIS, B_S0_HW_SI_DIS_W_R_TRIG, 1449 0x0); 1450 rtw89_phy_write32_mask(rtwdev, R_S1_HW_SI_DIS, B_S1_HW_SI_DIS_W_R_TRIG, 1451 0x0); 1452 1453 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1454 phy_idx); 1455 } 1456 1457 static void rtw8852c_bb_reset_en(struct rtw89_dev *rtwdev, enum rtw89_band band, 1458 enum rtw89_phy_idx phy_idx, bool en) 1459 { 1460 if (en) { 1461 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1462 B_S0_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1463 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1464 B_S1_HW_SI_DIS_W_R_TRIG, 0x0, phy_idx); 1465 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1466 phy_idx); 1467 if (band == RTW89_BAND_2G) 1468 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x0); 1469 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0); 1470 } else { 1471 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0x1); 1472 rtw89_phy_write32_mask(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1); 1473 rtw89_phy_write32_idx(rtwdev, R_S0_HW_SI_DIS, 1474 B_S0_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1475 rtw89_phy_write32_idx(rtwdev, R_S1_HW_SI_DIS, 1476 B_S1_HW_SI_DIS_W_R_TRIG, 0x7, phy_idx); 1477 fsleep(1); 1478 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1479 phy_idx); 1480 } 1481 } 1482 1483 static void rtw8852c_bb_reset(struct rtw89_dev *rtwdev, 1484 enum rtw89_phy_idx phy_idx) 1485 { 1486 rtw8852c_bb_reset_all(rtwdev, phy_idx); 1487 } 1488 1489 static 1490 void rtw8852c_bb_gpio_trsw(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1491 u8 tx_path_en, u8 trsw_tx, 1492 u8 trsw_rx, u8 trsw, u8 trsw_b) 1493 { 1494 static const u32 path_cr_bases[] = {0x5868, 0x7868}; 1495 u32 mask_ofst = 16; 1496 u32 cr; 1497 u32 val; 1498 1499 if (path >= ARRAY_SIZE(path_cr_bases)) 1500 return; 1501 1502 cr = path_cr_bases[path]; 1503 1504 mask_ofst += (tx_path_en * 4 + trsw_tx * 2 + trsw_rx) * 2; 1505 val = FIELD_PREP(B_P0_TRSW_A, trsw) | FIELD_PREP(B_P0_TRSW_B, trsw_b); 1506 1507 rtw89_phy_write32_mask(rtwdev, cr, (B_P0_TRSW_A | B_P0_TRSW_B) << mask_ofst, val); 1508 } 1509 1510 enum rtw8852c_rfe_src { 1511 PAPE_RFM, 1512 TRSW_RFM, 1513 LNAON_RFM, 1514 }; 1515 1516 static 1517 void rtw8852c_bb_gpio_rfm(struct rtw89_dev *rtwdev, enum rtw89_rf_path path, 1518 enum rtw8852c_rfe_src src, u8 dis_tx_gnt_wl, 1519 u8 active_tx_opt, u8 act_bt_en, u8 rfm_output_val) 1520 { 1521 static const u32 path_cr_bases[] = {0x5894, 0x7894}; 1522 static const u32 masks[] = {0, 8, 16}; 1523 u32 mask, mask_ofst; 1524 u32 cr; 1525 u32 val; 1526 1527 if (src >= ARRAY_SIZE(masks) || path >= ARRAY_SIZE(path_cr_bases)) 1528 return; 1529 1530 mask_ofst = masks[src]; 1531 cr = path_cr_bases[path]; 1532 1533 val = FIELD_PREP(B_P0_RFM_DIS_WL, dis_tx_gnt_wl) | 1534 FIELD_PREP(B_P0_RFM_TX_OPT, active_tx_opt) | 1535 FIELD_PREP(B_P0_RFM_BT_EN, act_bt_en) | 1536 FIELD_PREP(B_P0_RFM_OUT, rfm_output_val); 1537 mask = 0xff << mask_ofst; 1538 1539 rtw89_phy_write32_mask(rtwdev, cr, mask, val); 1540 } 1541 1542 static void rtw8852c_bb_gpio_init(struct rtw89_dev *rtwdev) 1543 { 1544 static const u32 cr_bases[] = {0x5800, 0x7800}; 1545 u32 addr; 1546 u8 i; 1547 1548 for (i = 0; i < ARRAY_SIZE(cr_bases); i++) { 1549 addr = cr_bases[i]; 1550 rtw89_phy_write32_set(rtwdev, (addr | 0x68), B_P0_TRSW_A); 1551 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_X); 1552 rtw89_phy_write32_clr(rtwdev, (addr | 0x68), B_P0_TRSW_SO_A2); 1553 rtw89_phy_write32(rtwdev, (addr | 0x80), 0x77777777); 1554 rtw89_phy_write32(rtwdev, (addr | 0x84), 0x77777777); 1555 } 1556 1557 rtw89_phy_write32(rtwdev, R_RFE_E_A2, 0xffffffff); 1558 rtw89_phy_write32(rtwdev, R_RFE_O_SEL_A2, 0); 1559 rtw89_phy_write32(rtwdev, R_RFE_SEL0_A2, 0); 1560 rtw89_phy_write32(rtwdev, R_RFE_SEL32_A2, 0); 1561 1562 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 0, 0, 1); 1563 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 0, 1, 1, 0); 1564 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 0, 1, 0); 1565 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 0, 1, 1, 1, 0); 1566 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 0, 0, 1); 1567 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 0, 1, 1, 0); 1568 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 0, 1, 0); 1569 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_A, 1, 1, 1, 1, 0); 1570 1571 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 0, 0, 1); 1572 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 0, 1, 1, 0); 1573 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 0, 1, 0); 1574 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 0, 1, 1, 1, 0); 1575 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 0, 0, 1); 1576 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 0, 1, 1, 0); 1577 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 0, 1, 0); 1578 rtw8852c_bb_gpio_trsw(rtwdev, RF_PATH_B, 1, 1, 1, 1, 0); 1579 1580 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, PAPE_RFM, 0, 0, 0, 0x0); 1581 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, TRSW_RFM, 0, 0, 0, 0x4); 1582 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_A, LNAON_RFM, 0, 0, 0, 0x8); 1583 1584 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, PAPE_RFM, 0, 0, 0, 0x0); 1585 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, TRSW_RFM, 0, 0, 0, 0x4); 1586 rtw8852c_bb_gpio_rfm(rtwdev, RF_PATH_B, LNAON_RFM, 0, 0, 0, 0x8); 1587 } 1588 1589 static void rtw8852c_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1590 enum rtw89_phy_idx phy_idx) 1591 { 1592 u32 addr; 1593 1594 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1595 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1596 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1597 } 1598 1599 static void rtw8852c_bb_sethw(struct rtw89_dev *rtwdev) 1600 { 1601 struct rtw89_phy_efuse_gain *gain = &rtwdev->efuse_gain; 1602 1603 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT, 1604 B_DBCC_80P80_SEL_EVM_RPT_EN); 1605 rtw89_phy_write32_set(rtwdev, R_DBCC_80P80_SEL_EVM_RPT2, 1606 B_DBCC_80P80_SEL_EVM_RPT2_EN); 1607 1608 rtw8852c_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1609 rtw8852c_bb_gpio_init(rtwdev); 1610 1611 /* read these registers after loading BB parameters */ 1612 gain->offset_base[RTW89_PHY_0] = 1613 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP, B_RPL_BIAS_COMP_MASK); 1614 gain->offset_base[RTW89_PHY_1] = 1615 rtw89_phy_read32_mask(rtwdev, R_RPL_BIAS_COMP1, B_RPL_BIAS_COMP1_MASK); 1616 } 1617 1618 static void rtw8852c_set_channel_bb(struct rtw89_dev *rtwdev, 1619 const struct rtw89_chan *chan, 1620 enum rtw89_phy_idx phy_idx) 1621 { 1622 static const u32 ru_alloc_msk[2] = {B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY0, 1623 B_P80_AT_HIGH_FREQ_RU_ALLOC_PHY1}; 1624 struct rtw89_hal *hal = &rtwdev->hal; 1625 bool cck_en = chan->band_type == RTW89_BAND_2G; 1626 u8 pri_ch_idx = chan->pri_ch_idx; 1627 u32 mask, reg; 1628 u8 ntx_path; 1629 1630 if (chan->band_type == RTW89_BAND_2G) 1631 rtw8852c_ctrl_sco_cck(rtwdev, chan->channel, 1632 chan->primary_channel, 1633 chan->band_width); 1634 1635 rtw8852c_ctrl_ch(rtwdev, chan, phy_idx); 1636 rtw8852c_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1637 if (cck_en) { 1638 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 1); 1639 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 0); 1640 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, 1641 B_PD_ARBITER_OFF, 0x0, phy_idx); 1642 } else { 1643 rtw89_phy_write32_mask(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0); 1644 rtw89_phy_write32_mask(rtwdev, R_RXCCA_V1, B_RXCCA_DIS_V1, 1); 1645 rtw89_phy_write32_idx(rtwdev, R_PD_ARBITER_OFF, 1646 B_PD_ARBITER_OFF, 0x1, phy_idx); 1647 } 1648 1649 rtw8852c_spur_elimination(rtwdev, chan, pri_ch_idx, phy_idx); 1650 rtw8852c_ctrl_btg(rtwdev, chan->band_type == RTW89_BAND_2G); 1651 rtw8852c_5m_mask(rtwdev, chan, phy_idx); 1652 1653 if (chan->band_width == RTW89_CHANNEL_WIDTH_160 && 1654 rtwdev->hal.cv != CHIP_CAV) { 1655 rtw89_phy_write32_idx(rtwdev, R_P80_AT_HIGH_FREQ, 1656 B_P80_AT_HIGH_FREQ, 0x0, phy_idx); 1657 reg = rtw89_mac_reg_by_idx(R_P80_AT_HIGH_FREQ_BB_WRP, 1658 phy_idx); 1659 if (chan->primary_channel > chan->channel) { 1660 rtw89_phy_write32_mask(rtwdev, 1661 R_P80_AT_HIGH_FREQ_RU_ALLOC, 1662 ru_alloc_msk[phy_idx], 1); 1663 rtw89_write32_mask(rtwdev, reg, 1664 B_P80_AT_HIGH_FREQ_BB_WRP, 1); 1665 } else { 1666 rtw89_phy_write32_mask(rtwdev, 1667 R_P80_AT_HIGH_FREQ_RU_ALLOC, 1668 ru_alloc_msk[phy_idx], 0); 1669 rtw89_write32_mask(rtwdev, reg, 1670 B_P80_AT_HIGH_FREQ_BB_WRP, 0); 1671 } 1672 } 1673 1674 if (chan->band_type == RTW89_BAND_6G && 1675 chan->band_width == RTW89_CHANNEL_WIDTH_160) 1676 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN, 1677 B_CDD_EVM_CHK_EN, 0, phy_idx); 1678 else 1679 rtw89_phy_write32_idx(rtwdev, R_CDD_EVM_CHK_EN, 1680 B_CDD_EVM_CHK_EN, 1, phy_idx); 1681 1682 if (!rtwdev->dbcc_en) { 1683 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON; 1684 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); 1685 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); 1686 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON; 1687 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1); 1688 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3); 1689 } else { 1690 if (phy_idx == RTW89_PHY_0) { 1691 mask = B_P0_TXPW_RSTB_TSSI | B_P0_TXPW_RSTB_MANON; 1692 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x1); 1693 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, mask, 0x3); 1694 } else { 1695 mask = B_P1_TXPW_RSTB_TSSI | B_P1_TXPW_RSTB_MANON; 1696 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x1); 1697 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, mask, 0x3); 1698 } 1699 } 1700 1701 if (chan->band_type == RTW89_BAND_6G) 1702 rtw89_phy_write32_set(rtwdev, R_MUIC, B_MUIC_EN); 1703 else 1704 rtw89_phy_write32_clr(rtwdev, R_MUIC, B_MUIC_EN); 1705 1706 if (hal->antenna_tx) 1707 ntx_path = hal->antenna_tx; 1708 else 1709 ntx_path = chan->band_type == RTW89_BAND_6G ? RF_B : RF_AB; 1710 1711 rtw8852c_ctrl_tx_path_tmac(rtwdev, ntx_path, (enum rtw89_mac_idx)phy_idx); 1712 1713 rtw8852c_bb_reset_all(rtwdev, phy_idx); 1714 } 1715 1716 static void rtw8852c_set_channel(struct rtw89_dev *rtwdev, 1717 const struct rtw89_chan *chan, 1718 enum rtw89_mac_idx mac_idx, 1719 enum rtw89_phy_idx phy_idx) 1720 { 1721 rtw8852c_set_channel_mac(rtwdev, chan, mac_idx); 1722 rtw8852c_set_channel_bb(rtwdev, chan, phy_idx); 1723 rtw8852c_set_channel_rf(rtwdev, chan, phy_idx); 1724 } 1725 1726 static void rtw8852c_dfs_en(struct rtw89_dev *rtwdev, bool en) 1727 { 1728 if (en) 1729 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1730 else 1731 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1732 } 1733 1734 static void rtw8852c_adc_en(struct rtw89_dev *rtwdev, bool en) 1735 { 1736 if (en) 1737 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1738 0x0); 1739 else 1740 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1741 0xf); 1742 } 1743 1744 static void rtw8852c_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1745 struct rtw89_channel_help_params *p, 1746 const struct rtw89_chan *chan, 1747 enum rtw89_mac_idx mac_idx, 1748 enum rtw89_phy_idx phy_idx) 1749 { 1750 if (enter) { 1751 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en, 1752 RTW89_SCH_TX_SEL_ALL); 1753 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false); 1754 rtw8852c_dfs_en(rtwdev, false); 1755 rtw8852c_tssi_cont_en_phyidx(rtwdev, false, phy_idx); 1756 rtw8852c_adc_en(rtwdev, false); 1757 fsleep(40); 1758 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, false); 1759 } else { 1760 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true); 1761 rtw8852c_adc_en(rtwdev, true); 1762 rtw8852c_dfs_en(rtwdev, true); 1763 rtw8852c_tssi_cont_en_phyidx(rtwdev, true, phy_idx); 1764 rtw8852c_bb_reset_en(rtwdev, chan->band_type, phy_idx, true); 1765 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en); 1766 } 1767 } 1768 1769 static void rtw8852c_rfk_init(struct rtw89_dev *rtwdev) 1770 { 1771 struct rtw89_rfk_mcc_info *rfk_mcc = &rtwdev->rfk_mcc; 1772 1773 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1774 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1775 memset(rfk_mcc, 0, sizeof(*rfk_mcc)); 1776 rtw8852c_lck_init(rtwdev); 1777 1778 rtw8852c_rck(rtwdev); 1779 rtw8852c_dack(rtwdev); 1780 rtw8852c_rx_dck(rtwdev, RTW89_PHY_0, false); 1781 } 1782 1783 static void rtw8852c_rfk_channel(struct rtw89_dev *rtwdev) 1784 { 1785 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 1786 1787 rtw8852c_mcc_get_ch_info(rtwdev, phy_idx); 1788 rtw8852c_rx_dck(rtwdev, phy_idx, false); 1789 rtw8852c_iqk(rtwdev, phy_idx); 1790 rtw8852c_tssi(rtwdev, phy_idx); 1791 rtw8852c_dpk(rtwdev, phy_idx); 1792 rtw89_fw_h2c_rf_ntfy_mcc(rtwdev); 1793 } 1794 1795 static void rtw8852c_rfk_band_changed(struct rtw89_dev *rtwdev, 1796 enum rtw89_phy_idx phy_idx) 1797 { 1798 rtw8852c_tssi_scan(rtwdev, phy_idx); 1799 } 1800 1801 static void rtw8852c_rfk_scan(struct rtw89_dev *rtwdev, bool start) 1802 { 1803 rtw8852c_wifi_scan_notify(rtwdev, start, RTW89_PHY_0); 1804 } 1805 1806 static void rtw8852c_rfk_track(struct rtw89_dev *rtwdev) 1807 { 1808 rtw8852c_dpk_track(rtwdev); 1809 rtw8852c_lck_track(rtwdev); 1810 rtw8852c_rx_dck_track(rtwdev); 1811 } 1812 1813 static u32 rtw8852c_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1814 enum rtw89_phy_idx phy_idx, s16 ref) 1815 { 1816 s8 ofst_int = 0; 1817 u8 base_cw_0db = 0x27; 1818 u16 tssi_16dbm_cw = 0x12c; 1819 s16 pwr_s10_3 = 0; 1820 s16 rf_pwr_cw = 0; 1821 u16 bb_pwr_cw = 0; 1822 u32 pwr_cw = 0; 1823 u32 tssi_ofst_cw = 0; 1824 1825 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1826 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1827 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1828 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1829 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1830 1831 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1832 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1833 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1834 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1835 1836 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); 1837 } 1838 1839 static 1840 void rtw8852c_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1841 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1842 { 1843 s8 pw_ofst_2tx; 1844 s8 val_1t; 1845 s8 val_2t; 1846 u32 reg; 1847 u8 i; 1848 1849 if (pw_ofst < -32 || pw_ofst > 31) { 1850 rtw89_warn(rtwdev, "[ULTB] Err pwr_offset=%d\n", pw_ofst); 1851 return; 1852 } 1853 val_1t = pw_ofst << 2; 1854 pw_ofst_2tx = max(pw_ofst - 3, -32); 1855 val_2t = pw_ofst_2tx << 2; 1856 1857 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_1tx=0x%x\n", val_1t); 1858 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] val_2tx=0x%x\n", val_2t); 1859 1860 for (i = 0; i < 4; i++) { 1861 /* 1TX */ 1862 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_1T, mac_idx); 1863 rtw89_write32_mask(rtwdev, reg, 1864 B_AX_PWR_UL_TB_1T_V1_MASK << (8 * i), 1865 val_1t); 1866 /* 2TX */ 1867 reg = rtw89_mac_reg_by_idx(R_AX_PWR_UL_TB_2T, mac_idx); 1868 rtw89_write32_mask(rtwdev, reg, 1869 B_AX_PWR_UL_TB_2T_V1_MASK << (8 * i), 1870 val_2t); 1871 } 1872 } 1873 1874 static void rtw8852c_set_txpwr_ref(struct rtw89_dev *rtwdev, 1875 enum rtw89_phy_idx phy_idx) 1876 { 1877 static const u32 addr[RF_PATH_NUM_8852C] = {0x5800, 0x7800}; 1878 const u32 mask = 0x7FFFFFF; 1879 const u8 ofst_ofdm = 0x4; 1880 const u8 ofst_cck = 0x8; 1881 s16 ref_ofdm = 0; 1882 s16 ref_cck = 0; 1883 u32 val; 1884 u8 i; 1885 1886 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1887 1888 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1889 GENMASK(27, 10), 0x0); 1890 1891 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1892 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1893 1894 for (i = 0; i < RF_PATH_NUM_8852C; i++) 1895 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1896 phy_idx); 1897 1898 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1899 val = rtw8852c_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1900 1901 for (i = 0; i < RF_PATH_NUM_8852C; i++) 1902 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1903 phy_idx); 1904 } 1905 1906 static void rtw8852c_bb_set_tx_shape_dfir(struct rtw89_dev *rtwdev, 1907 const struct rtw89_chan *chan, 1908 u8 tx_shape_idx, 1909 enum rtw89_phy_idx phy_idx) 1910 { 1911 #define __DFIR_CFG_MASK 0xffffff 1912 #define __DFIR_CFG_NR 8 1913 #if defined(__linux__) 1914 #define __DECL_DFIR_VAR(_prefix, _name, _val...) \ 1915 static const u32 _prefix ## _ ## _name[] = {_val}; \ 1916 static_assert(ARRAY_SIZE(_prefix ## _ ## _name) == __DFIR_CFG_NR) 1917 #elif defined(__FreeBSD__) 1918 #define __DECL_DFIR_VAR(_prefix, _name, _val...) \ 1919 static const u32 _prefix ## _ ## _name[] = {_val}; \ 1920 rtw89_static_assert(ARRAY_SIZE(_prefix ## _ ## _name) == __DFIR_CFG_NR) 1921 #endif 1922 #define __DECL_DFIR_PARAM(_name, _val...) __DECL_DFIR_VAR(param, _name, _val) 1923 #define __DECL_DFIR_ADDR(_name, _val...) __DECL_DFIR_VAR(addr, _name, _val) 1924 1925 __DECL_DFIR_PARAM(flat, 1926 0x003D23FF, 0x0029B354, 0x000FC1C8, 0x00FDB053, 1927 0x00F86F9A, 0x00FAEF92, 0x00FE5FCC, 0x00FFDFF5); 1928 __DECL_DFIR_PARAM(sharp, 1929 0x003D83FF, 0x002C636A, 0x0013F204, 0x00008090, 1930 0x00F87FB0, 0x00F99F83, 0x00FDBFBA, 0x00003FF5); 1931 __DECL_DFIR_PARAM(sharp_14, 1932 0x003B13FF, 0x001C42DE, 0x00FDB0AD, 0x00F60F6E, 1933 0x00FD8F92, 0x0002D011, 0x0001C02C, 0x00FFF00A); 1934 __DECL_DFIR_ADDR(filter, 1935 0x45BC, 0x45CC, 0x45D0, 0x45D4, 0x45D8, 0x45C0, 1936 0x45C4, 0x45C8); 1937 u8 ch = chan->channel; 1938 const u32 *param; 1939 int i; 1940 1941 if (ch > 14) { 1942 rtw89_warn(rtwdev, 1943 "set tx shape dfir by unknown ch: %d on 2G\n", ch); 1944 return; 1945 } 1946 1947 if (ch == 14) 1948 param = param_sharp_14; 1949 else 1950 param = tx_shape_idx == 0 ? param_flat : param_sharp; 1951 1952 for (i = 0; i < __DFIR_CFG_NR; i++) { 1953 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1954 "set tx shape dfir: 0x%x: 0x%x\n", addr_filter[i], 1955 param[i]); 1956 rtw89_phy_write32_idx(rtwdev, addr_filter[i], __DFIR_CFG_MASK, 1957 param[i], phy_idx); 1958 } 1959 1960 #undef __DECL_DFIR_ADDR 1961 #undef __DECL_DFIR_PARAM 1962 #undef __DECL_DFIR_VAR 1963 #undef __DFIR_CFG_NR 1964 #undef __DFIR_CFG_MASK 1965 } 1966 1967 static void rtw8852c_set_tx_shape(struct rtw89_dev *rtwdev, 1968 const struct rtw89_chan *chan, 1969 enum rtw89_phy_idx phy_idx) 1970 { 1971 u8 band = chan->band_type; 1972 u8 regd = rtw89_regd_get(rtwdev, band); 1973 u8 tx_shape_cck = rtw89_8852c_tx_shape[band][RTW89_RS_CCK][regd]; 1974 u8 tx_shape_ofdm = rtw89_8852c_tx_shape[band][RTW89_RS_OFDM][regd]; 1975 1976 if (band == RTW89_BAND_2G) 1977 rtw8852c_bb_set_tx_shape_dfir(rtwdev, chan, tx_shape_cck, phy_idx); 1978 1979 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev, 1980 (enum rtw89_mac_idx)phy_idx, 1981 tx_shape_ofdm); 1982 } 1983 1984 static void rtw8852c_set_txpwr(struct rtw89_dev *rtwdev, 1985 const struct rtw89_chan *chan, 1986 enum rtw89_phy_idx phy_idx) 1987 { 1988 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 1989 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 1990 rtw8852c_set_tx_shape(rtwdev, chan, phy_idx); 1991 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 1992 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 1993 } 1994 1995 static void rtw8852c_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 1996 enum rtw89_phy_idx phy_idx) 1997 { 1998 rtw8852c_set_txpwr_ref(rtwdev, phy_idx); 1999 } 2000 2001 static void 2002 rtw8852c_init_tssi_ctrl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 2003 { 2004 static const struct rtw89_reg2_def ctrl_ini[] = { 2005 {0xD938, 0x00010100}, 2006 {0xD93C, 0x0500D500}, 2007 {0xD940, 0x00000500}, 2008 {0xD944, 0x00000005}, 2009 {0xD94C, 0x00220000}, 2010 {0xD950, 0x00030000}, 2011 }; 2012 u32 addr; 2013 int i; 2014 2015 for (addr = R_AX_TSSI_CTRL_HEAD; addr <= R_AX_TSSI_CTRL_TAIL; addr += 4) 2016 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 2017 2018 for (i = 0; i < ARRAY_SIZE(ctrl_ini); i++) 2019 rtw89_mac_txpwr_write32(rtwdev, phy_idx, ctrl_ini[i].addr, 2020 ctrl_ini[i].data); 2021 2022 rtw89_phy_tssi_ctrl_set_bandedge_cfg(rtwdev, 2023 (enum rtw89_mac_idx)phy_idx, 2024 RTW89_TSSI_BANDEDGE_FLAT); 2025 } 2026 2027 static int 2028 rtw8852c_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 2029 { 2030 int ret; 2031 2032 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 2033 if (ret) 2034 return ret; 2035 2036 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf000); 2037 if (ret) 2038 return ret; 2039 2040 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 2041 if (ret) 2042 return ret; 2043 2044 rtw8852c_set_txpwr_ul_tb_offset(rtwdev, 0, phy_idx == RTW89_PHY_1 ? 2045 RTW89_MAC_1 : 2046 RTW89_MAC_0); 2047 rtw8852c_init_tssi_ctrl(rtwdev, phy_idx); 2048 2049 return 0; 2050 } 2051 2052 static void rtw8852c_bb_cfg_rx_path(struct rtw89_dev *rtwdev, u8 rx_path) 2053 { 2054 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 2055 u8 band = chan->band_type; 2056 u32 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 2057 u32 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 2058 2059 if (rtwdev->dbcc_en) { 2060 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 1); 2061 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_ANT_RX_SEG0, 2, 2062 RTW89_PHY_1); 2063 2064 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2065 1); 2066 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2067 1); 2068 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG0, 2, 2069 RTW89_PHY_1); 2070 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_ANT_RX_1RCCA_SEG1, 2, 2071 RTW89_PHY_1); 2072 2073 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2074 B_RXHT_MCS_LIMIT, 0); 2075 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2076 B_RXVHT_MCS_LIMIT, 0); 2077 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8); 2078 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2079 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2080 2081 rtw89_phy_write32_idx(rtwdev, R_RXHT_MCS_LIMIT, 2082 B_RXHT_MCS_LIMIT, 0, RTW89_PHY_1); 2083 rtw89_phy_write32_idx(rtwdev, R_RXVHT_MCS_LIMIT, 2084 B_RXVHT_MCS_LIMIT, 0, RTW89_PHY_1); 2085 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_USER_MAX, 1, 2086 RTW89_PHY_1); 2087 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0, 2088 RTW89_PHY_1); 2089 rtw89_phy_write32_idx(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0, 2090 RTW89_PHY_1); 2091 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 2092 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 2093 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 2094 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 2095 } else { 2096 if (rx_path == RF_PATH_A) { 2097 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2098 B_ANT_RX_SEG0, 1); 2099 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2100 B_ANT_RX_1RCCA_SEG0, 1); 2101 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2102 B_ANT_RX_1RCCA_SEG1, 1); 2103 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2104 B_RXHT_MCS_LIMIT, 0); 2105 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2106 B_RXVHT_MCS_LIMIT, 0); 2107 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2108 0); 2109 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2110 0); 2111 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2112 rst_mask0, 1); 2113 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2114 rst_mask0, 3); 2115 } else if (rx_path == RF_PATH_B) { 2116 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2117 B_ANT_RX_SEG0, 2); 2118 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2119 B_ANT_RX_1RCCA_SEG0, 2); 2120 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2121 B_ANT_RX_1RCCA_SEG1, 2); 2122 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2123 B_RXHT_MCS_LIMIT, 0); 2124 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2125 B_RXVHT_MCS_LIMIT, 0); 2126 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2127 0); 2128 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2129 0); 2130 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2131 rst_mask1, 1); 2132 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2133 rst_mask1, 3); 2134 } else { 2135 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, 2136 B_ANT_RX_SEG0, 3); 2137 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2138 B_ANT_RX_1RCCA_SEG0, 3); 2139 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, 2140 B_ANT_RX_1RCCA_SEG1, 3); 2141 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, 2142 B_RXHT_MCS_LIMIT, 1); 2143 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, 2144 B_RXVHT_MCS_LIMIT, 1); 2145 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 2146 1); 2147 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 2148 1); 2149 rtw8852c_ctrl_btg(rtwdev, band == RTW89_BAND_2G); 2150 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2151 rst_mask0, 1); 2152 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, 2153 rst_mask0, 3); 2154 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2155 rst_mask1, 1); 2156 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, 2157 rst_mask1, 3); 2158 } 2159 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_USER_MAX, 8); 2160 } 2161 } 2162 2163 static void rtw8852c_ctrl_tx_path_tmac(struct rtw89_dev *rtwdev, u8 tx_path, 2164 enum rtw89_mac_idx mac_idx) 2165 { 2166 struct rtw89_reg2_def path_com[] = { 2167 {R_AX_PATH_COM0, AX_PATH_COM0_DFVAL}, 2168 {R_AX_PATH_COM1, AX_PATH_COM1_DFVAL}, 2169 {R_AX_PATH_COM2, AX_PATH_COM2_DFVAL}, 2170 {R_AX_PATH_COM3, AX_PATH_COM3_DFVAL}, 2171 {R_AX_PATH_COM4, AX_PATH_COM4_DFVAL}, 2172 {R_AX_PATH_COM5, AX_PATH_COM5_DFVAL}, 2173 {R_AX_PATH_COM6, AX_PATH_COM6_DFVAL}, 2174 {R_AX_PATH_COM7, AX_PATH_COM7_DFVAL}, 2175 {R_AX_PATH_COM8, AX_PATH_COM8_DFVAL}, 2176 {R_AX_PATH_COM9, AX_PATH_COM9_DFVAL}, 2177 {R_AX_PATH_COM10, AX_PATH_COM10_DFVAL}, 2178 {R_AX_PATH_COM11, AX_PATH_COM11_DFVAL}, 2179 }; 2180 u32 addr; 2181 u32 reg; 2182 u8 cr_size = ARRAY_SIZE(path_com); 2183 u8 i = 0; 2184 2185 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_0); 2186 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, RTW89_PHY_1); 2187 2188 for (addr = R_AX_MACID_ANT_TABLE; 2189 addr <= R_AX_MACID_ANT_TABLE_LAST; addr += 4) { 2190 reg = rtw89_mac_reg_by_idx(addr, mac_idx); 2191 rtw89_write32(rtwdev, reg, 0); 2192 } 2193 2194 if (tx_path == RF_A) { 2195 path_com[0].data = AX_PATH_COM0_PATHA; 2196 path_com[1].data = AX_PATH_COM1_PATHA; 2197 path_com[2].data = AX_PATH_COM2_PATHA; 2198 path_com[7].data = AX_PATH_COM7_PATHA; 2199 path_com[8].data = AX_PATH_COM8_PATHA; 2200 } else if (tx_path == RF_B) { 2201 path_com[0].data = AX_PATH_COM0_PATHB; 2202 path_com[1].data = AX_PATH_COM1_PATHB; 2203 path_com[2].data = AX_PATH_COM2_PATHB; 2204 path_com[7].data = AX_PATH_COM7_PATHB; 2205 path_com[8].data = AX_PATH_COM8_PATHB; 2206 } else if (tx_path == RF_AB) { 2207 path_com[0].data = AX_PATH_COM0_PATHAB; 2208 path_com[1].data = AX_PATH_COM1_PATHAB; 2209 path_com[2].data = AX_PATH_COM2_PATHAB; 2210 path_com[7].data = AX_PATH_COM7_PATHAB; 2211 path_com[8].data = AX_PATH_COM8_PATHAB; 2212 } else { 2213 rtw89_warn(rtwdev, "[Invalid Tx Path]Tx Path: %d\n", tx_path); 2214 return; 2215 } 2216 2217 for (i = 0; i < cr_size; i++) { 2218 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "0x%x = 0x%x\n", 2219 path_com[i].addr, path_com[i].data); 2220 reg = rtw89_mac_reg_by_idx(path_com[i].addr, mac_idx); 2221 rtw89_write32(rtwdev, reg, path_com[i].data); 2222 } 2223 } 2224 2225 static void rtw8852c_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, bool bt_en) 2226 { 2227 if (bt_en) { 2228 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1, 2229 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x3); 2230 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1, 2231 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x3); 2232 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1, 2233 B_PATH0_RXBB_MSK_V1, 0xf); 2234 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1, 2235 B_PATH1_RXBB_MSK_V1, 0xf); 2236 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 2237 B_PATH0_G_LNA6_OP1DB_V1, 0x80); 2238 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2239 B_PATH1_G_LNA6_OP1DB_V1, 0x80); 2240 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 2241 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x80); 2242 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1, 2243 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x80); 2244 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2245 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x80); 2246 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1, 2247 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x80); 2248 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1, 2249 B_PATH0_BT_BACKOFF_V1, 0x780D1E); 2250 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1, 2251 B_PATH1_BT_BACKOFF_V1, 0x780D1E); 2252 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1, 2253 B_P0_BACKOFF_IBADC_V1, 0x34); 2254 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1, 2255 B_P1_BACKOFF_IBADC_V1, 0x34); 2256 } else { 2257 rtw89_phy_write32_mask(rtwdev, R_PATH0_FRC_FIR_TYPE_V1, 2258 B_PATH0_FRC_FIR_TYPE_MSK_V1, 0x0); 2259 rtw89_phy_write32_mask(rtwdev, R_PATH1_FRC_FIR_TYPE_V1, 2260 B_PATH1_FRC_FIR_TYPE_MSK_V1, 0x0); 2261 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXBB_V1, 2262 B_PATH0_RXBB_MSK_V1, 0x60); 2263 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXBB_V1, 2264 B_PATH1_RXBB_MSK_V1, 0x60); 2265 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_LNA6_OP1DB_V1, 2266 B_PATH0_G_LNA6_OP1DB_V1, 0x1a); 2267 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2268 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 2269 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA0_LNA6_OP1DB_V1, 2270 B_PATH0_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2271 rtw89_phy_write32_mask(rtwdev, R_PATH0_G_TIA1_LNA6_OP1DB_V1, 2272 B_PATH0_G_TIA1_LNA6_OP1DB_V1, 0x2a); 2273 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2274 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2275 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA1_LNA6_OP1DB_V1, 2276 B_PATH1_G_TIA1_LNA6_OP1DB_V1, 0x2a); 2277 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_BACKOFF_V1, 2278 B_PATH0_BT_BACKOFF_V1, 0x79E99E); 2279 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_BACKOFF_V1, 2280 B_PATH1_BT_BACKOFF_V1, 0x79E99E); 2281 rtw89_phy_write32_mask(rtwdev, R_P0_BACKOFF_IBADC_V1, 2282 B_P0_BACKOFF_IBADC_V1, 0x26); 2283 rtw89_phy_write32_mask(rtwdev, R_P1_BACKOFF_IBADC_V1, 2284 B_P1_BACKOFF_IBADC_V1, 0x26); 2285 } 2286 } 2287 2288 static void rtw8852c_bb_cfg_txrx_path(struct rtw89_dev *rtwdev) 2289 { 2290 struct rtw89_hal *hal = &rtwdev->hal; 2291 2292 rtw8852c_bb_cfg_rx_path(rtwdev, RF_PATH_AB); 2293 2294 if (hal->rx_nss == 1) { 2295 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 0); 2296 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 0); 2297 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 0); 2298 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 0); 2299 } else { 2300 rtw89_phy_write32_mask(rtwdev, R_RXHT_MCS_LIMIT, B_RXHT_MCS_LIMIT, 1); 2301 rtw89_phy_write32_mask(rtwdev, R_RXVHT_MCS_LIMIT, B_RXVHT_MCS_LIMIT, 1); 2302 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHE_MAX_NSS, 1); 2303 rtw89_phy_write32_mask(rtwdev, R_RXHE, B_RXHETB_MAX_NSS, 1); 2304 } 2305 } 2306 2307 static u8 rtw8852c_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 2308 { 2309 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2310 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 2311 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 2312 2313 fsleep(200); 2314 2315 return rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 2316 } 2317 2318 static void rtw8852c_btc_set_rfe(struct rtw89_dev *rtwdev) 2319 { 2320 struct rtw89_btc *btc = &rtwdev->btc; 2321 struct rtw89_btc_module *module = &btc->mdinfo; 2322 2323 module->rfe_type = rtwdev->efuse.rfe_type; 2324 module->cv = rtwdev->hal.cv; 2325 module->bt_solo = 0; 2326 module->switch_type = BTC_SWITCH_INTERNAL; 2327 2328 if (module->rfe_type > 0) 2329 module->ant.num = (module->rfe_type % 2 ? 2 : 3); 2330 else 2331 module->ant.num = 2; 2332 2333 module->ant.diversity = 0; 2334 module->ant.isolation = 10; 2335 2336 if (module->ant.num == 3) { 2337 module->ant.type = BTC_ANT_DEDICATED; 2338 module->bt_pos = BTC_BT_ALONE; 2339 } else { 2340 module->ant.type = BTC_ANT_SHARED; 2341 module->bt_pos = BTC_BT_BTG; 2342 } 2343 } 2344 2345 static void rtw8852c_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 2346 { 2347 if (btg) { 2348 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 2349 B_PATH0_BT_SHARE_V1, 0x1); 2350 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 2351 B_PATH0_BTG_PATH_V1, 0x0); 2352 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2353 B_PATH1_G_LNA6_OP1DB_V1, 0x20); 2354 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2355 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x30); 2356 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 2357 B_PATH1_BT_SHARE_V1, 0x1); 2358 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2359 B_PATH1_BTG_PATH_V1, 0x1); 2360 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 2361 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x1); 2362 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x2); 2363 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN, 2364 B_BT_DYN_DC_EST_EN_MSK, 0x1); 2365 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 2366 0x1); 2367 } else { 2368 rtw89_phy_write32_mask(rtwdev, R_PATH0_BT_SHARE_V1, 2369 B_PATH0_BT_SHARE_V1, 0x0); 2370 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG_PATH_V1, 2371 B_PATH0_BTG_PATH_V1, 0x0); 2372 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_LNA6_OP1DB_V1, 2373 B_PATH1_G_LNA6_OP1DB_V1, 0x1a); 2374 rtw89_phy_write32_mask(rtwdev, R_PATH1_G_TIA0_LNA6_OP1DB_V1, 2375 B_PATH1_G_TIA0_LNA6_OP1DB_V1, 0x2a); 2376 rtw89_phy_write32_mask(rtwdev, R_PATH1_BT_SHARE_V1, 2377 B_PATH1_BT_SHARE_V1, 0x0); 2378 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG_PATH_V1, 2379 B_PATH1_BTG_PATH_V1, 0x0); 2380 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 2381 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 2382 rtw89_phy_write32_mask(rtwdev, R_CHBW_MOD, B_BT_SHARE, 0x0); 2383 rtw89_phy_write32_mask(rtwdev, R_FC0_BW, B_ANT_RX_BT_SEG0, 0x0); 2384 rtw89_phy_write32_mask(rtwdev, R_BT_DYN_DC_EST_EN, 2385 B_BT_DYN_DC_EST_EN_MSK, 0x0); 2386 rtw89_phy_write32_mask(rtwdev, R_GNT_BT_WGT_EN, B_GNT_BT_WGT_EN, 2387 0x0); 2388 } 2389 } 2390 2391 static 2392 void rtw8852c_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 2393 { 2394 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x20000); 2395 rtw89_write_rf(rtwdev, path, RR_LUTWA, RFREG_MASK, group); 2396 rtw89_write_rf(rtwdev, path, RR_LUTWD0, RFREG_MASK, val); 2397 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0x0); 2398 } 2399 2400 static void rtw8852c_btc_init_cfg(struct rtw89_dev *rtwdev) 2401 { 2402 struct rtw89_btc *btc = &rtwdev->btc; 2403 struct rtw89_btc_module *module = &btc->mdinfo; 2404 const struct rtw89_chip_info *chip = rtwdev->chip; 2405 const struct rtw89_mac_ax_coex coex_params = { 2406 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 2407 .direction = RTW89_MAC_AX_COEX_INNER, 2408 }; 2409 2410 /* PTA init */ 2411 rtw89_mac_coex_init_v1(rtwdev, &coex_params); 2412 2413 /* set WL Tx response = Hi-Pri */ 2414 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 2415 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 2416 2417 /* set rf gnt debug off */ 2418 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, RFREG_MASK, 0x0); 2419 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, RFREG_MASK, 0x0); 2420 2421 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 2422 if (module->ant.type == BTC_ANT_SHARED) { 2423 rtw8852c_set_trx_mask(rtwdev, 2424 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 2425 rtw8852c_set_trx_mask(rtwdev, 2426 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 2427 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 2428 rtw8852c_set_trx_mask(rtwdev, 2429 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 2430 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 2431 rtw8852c_set_trx_mask(rtwdev, 2432 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 2433 rtw8852c_set_trx_mask(rtwdev, 2434 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 2435 } 2436 2437 /* set PTA break table */ 2438 rtw89_write32(rtwdev, R_AX_BT_BREAK_TABLE, BTC_BREAK_PARAM); 2439 2440 /* enable BT counter 0xda10[1:0] = 2b'11 */ 2441 rtw89_write32_set(rtwdev, 2442 R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN | 2443 B_AX_BT_CNT_RST_V1); 2444 btc->cx.wl.status.map.init_ok = true; 2445 } 2446 2447 static 2448 void rtw8852c_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 2449 { 2450 u32 bitmap = 0; 2451 u32 reg = 0; 2452 2453 switch (map) { 2454 case BTC_PRI_MASK_TX_RESP: 2455 reg = R_BTC_COEX_WL_REQ; 2456 bitmap = B_BTC_RSP_ACK_HI; 2457 break; 2458 case BTC_PRI_MASK_BEACON: 2459 reg = R_BTC_COEX_WL_REQ; 2460 bitmap = B_BTC_TX_BCN_HI; 2461 break; 2462 default: 2463 return; 2464 } 2465 2466 if (state) 2467 rtw89_write32_set(rtwdev, reg, bitmap); 2468 else 2469 rtw89_write32_clr(rtwdev, reg, bitmap); 2470 } 2471 2472 union rtw8852c_btc_wl_txpwr_ctrl { 2473 u32 txpwr_val; 2474 struct { 2475 union { 2476 u16 ctrl_all_time; 2477 struct { 2478 s16 data:9; 2479 u16 rsvd:6; 2480 u16 flag:1; 2481 } all_time; 2482 }; 2483 union { 2484 u16 ctrl_gnt_bt; 2485 struct { 2486 s16 data:9; 2487 u16 rsvd:7; 2488 } gnt_bt; 2489 }; 2490 }; 2491 } __packed; 2492 2493 static void 2494 rtw8852c_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 2495 { 2496 union rtw8852c_btc_wl_txpwr_ctrl arg = { .txpwr_val = txpwr_val }; 2497 s32 val; 2498 2499 #define __write_ctrl(_reg, _msk, _val, _en, _cond) \ 2500 do { \ 2501 u32 _wrt = FIELD_PREP(_msk, _val); \ 2502 BUILD_BUG_ON((_msk & _en) != 0); \ 2503 if (_cond) \ 2504 _wrt |= _en; \ 2505 else \ 2506 _wrt &= ~_en; \ 2507 rtw89_mac_txpwr_write32_mask(rtwdev, RTW89_PHY_0, _reg, \ 2508 _msk | _en, _wrt); \ 2509 } while (0) 2510 2511 switch (arg.ctrl_all_time) { 2512 case 0xffff: 2513 val = 0; 2514 break; 2515 default: 2516 val = arg.all_time.data; 2517 break; 2518 } 2519 2520 __write_ctrl(R_AX_PWR_RATE_CTRL, B_AX_FORCE_PWR_BY_RATE_VALUE_MASK, 2521 val, B_AX_FORCE_PWR_BY_RATE_EN, 2522 arg.ctrl_all_time != 0xffff); 2523 2524 switch (arg.ctrl_gnt_bt) { 2525 case 0xffff: 2526 val = 0; 2527 break; 2528 default: 2529 val = arg.gnt_bt.data; 2530 break; 2531 } 2532 2533 __write_ctrl(R_AX_PWR_COEXT_CTRL, B_AX_TXAGC_BT_MASK, val, 2534 B_AX_TXAGC_BT_EN, arg.ctrl_gnt_bt != 0xffff); 2535 2536 #undef __write_ctrl 2537 } 2538 2539 static 2540 s8 rtw8852c_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 2541 { 2542 /* +6 for compensate offset */ 2543 return clamp_t(s8, val + 6, -100, 0) + 100; 2544 } 2545 2546 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_ul[] = { 2547 {255, 0, 0, 7}, /* 0 -> original */ 2548 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 2549 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 2550 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 2551 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 2552 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 2553 {6, 1, 0, 7}, 2554 {13, 1, 0, 7}, 2555 {13, 1, 0, 7} 2556 }; 2557 2558 static const struct rtw89_btc_rf_trx_para rtw89_btc_8852c_rf_dl[] = { 2559 {255, 0, 0, 7}, /* 0 -> original */ 2560 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 2561 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 2562 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 2563 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 2564 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */ 2565 {255, 1, 0, 7}, 2566 {255, 1, 0, 7}, 2567 {255, 1, 0, 7} 2568 }; 2569 2570 static const u8 rtw89_btc_8852c_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; 2571 static const u8 rtw89_btc_8852c_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; 2572 2573 static const struct rtw89_btc_fbtc_mreg rtw89_btc_8852c_mon_reg[] = { 2574 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda00), 2575 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda04), 2576 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 2577 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 2578 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 2579 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda38), 2580 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda44), 2581 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda48), 2582 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 2583 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd200), 2584 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xd220), 2585 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 2586 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4aa4), 2587 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x4778), 2588 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x476c), 2589 }; 2590 2591 static 2592 void rtw8852c_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 2593 { 2594 /* Feature move to firmware */ 2595 } 2596 2597 static 2598 void rtw8852c_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 2599 { 2600 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 2601 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2602 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x620); 2603 2604 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 2605 if (state) 2606 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2607 RFREG_MASK, 0x179c); 2608 else 2609 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 2610 RFREG_MASK, 0x208); 2611 2612 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2613 } 2614 2615 static void rtw8852c_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) 2616 { 2617 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB 2618 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB 2619 * To improve BT ACI in co-rx 2620 */ 2621 2622 switch (level) { 2623 case 0: /* default */ 2624 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2625 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2626 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2627 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2628 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2629 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2630 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2631 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2632 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 2633 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2634 break; 2635 case 1: /* Fix LNA2=5 */ 2636 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2637 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x0); 2638 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2639 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 2640 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2641 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2642 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2643 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2644 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2645 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2646 break; 2647 } 2648 } 2649 2650 static void rtw8852c_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 2651 { 2652 struct rtw89_btc *btc = &rtwdev->btc; 2653 2654 switch (level) { 2655 case 0: /* original */ 2656 default: 2657 rtw8852c_bb_ctrl_btc_preagc(rtwdev, false); 2658 btc->dm.wl_lna2 = 0; 2659 break; 2660 case 1: /* for FDD free-run */ 2661 rtw8852c_bb_ctrl_btc_preagc(rtwdev, true); 2662 btc->dm.wl_lna2 = 0; 2663 break; 2664 case 2: /* for BTG Co-Rx*/ 2665 rtw8852c_bb_ctrl_btc_preagc(rtwdev, false); 2666 btc->dm.wl_lna2 = 1; 2667 break; 2668 } 2669 2670 rtw8852c_set_wl_lna2(rtwdev, btc->dm.wl_lna2); 2671 } 2672 2673 static void rtw8852c_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 2674 struct rtw89_rx_phy_ppdu *phy_ppdu, 2675 struct ieee80211_rx_status *status) 2676 { 2677 u8 chan_idx = phy_ppdu->chan_idx; 2678 enum nl80211_band band; 2679 u8 ch; 2680 2681 if (chan_idx == 0) 2682 return; 2683 2684 rtw89_decode_chan_idx(rtwdev, chan_idx, &ch, &band); 2685 status->freq = ieee80211_channel_to_frequency(ch, band); 2686 status->band = band; 2687 } 2688 2689 static void rtw8852c_query_ppdu(struct rtw89_dev *rtwdev, 2690 struct rtw89_rx_phy_ppdu *phy_ppdu, 2691 struct ieee80211_rx_status *status) 2692 { 2693 u8 path; 2694 u8 *rx_power = phy_ppdu->rssi; 2695 2696 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B])); 2697 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2698 status->chains |= BIT(path); 2699 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 2700 } 2701 if (phy_ppdu->valid) 2702 rtw8852c_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2703 } 2704 2705 static int rtw8852c_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 2706 { 2707 int ret; 2708 2709 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 2710 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2711 2712 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2713 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2714 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, B_AX_AFC_AFEDIG); 2715 2716 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S0_LDO_VSEL_F_MASK, 0x1); 2717 rtw89_write32_mask(rtwdev, R_AX_AFE_OFF_CTRL1, B_AX_S1_LDO_VSEL_F_MASK, 0x1); 2718 2719 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL0, 0x7, FULL_BIT_MASK); 2720 if (ret) 2721 return ret; 2722 2723 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x6c, FULL_BIT_MASK); 2724 if (ret) 2725 return ret; 2726 2727 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xc7, FULL_BIT_MASK); 2728 if (ret) 2729 return ret; 2730 2731 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xc7, FULL_BIT_MASK); 2732 if (ret) 2733 return ret; 2734 2735 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL3, 0xd, FULL_BIT_MASK); 2736 if (ret) 2737 return ret; 2738 2739 return 0; 2740 } 2741 2742 static int rtw8852c_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 2743 { 2744 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 2745 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 2746 2747 return 0; 2748 } 2749 2750 #ifdef CONFIG_PM 2751 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852c = { 2752 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 2753 .n_patterns = RTW89_MAX_PATTERN_NUM, 2754 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 2755 .pattern_min_len = 1, 2756 }; 2757 #endif 2758 2759 static const struct rtw89_chip_ops rtw8852c_chip_ops = { 2760 .enable_bb_rf = rtw8852c_mac_enable_bb_rf, 2761 .disable_bb_rf = rtw8852c_mac_disable_bb_rf, 2762 .bb_reset = rtw8852c_bb_reset, 2763 .bb_sethw = rtw8852c_bb_sethw, 2764 .read_rf = rtw89_phy_read_rf_v1, 2765 .write_rf = rtw89_phy_write_rf_v1, 2766 .set_channel = rtw8852c_set_channel, 2767 .set_channel_help = rtw8852c_set_channel_help, 2768 .read_efuse = rtw8852c_read_efuse, 2769 .read_phycap = rtw8852c_read_phycap, 2770 .fem_setup = NULL, 2771 .rfe_gpio = NULL, 2772 .rfk_init = rtw8852c_rfk_init, 2773 .rfk_channel = rtw8852c_rfk_channel, 2774 .rfk_band_changed = rtw8852c_rfk_band_changed, 2775 .rfk_scan = rtw8852c_rfk_scan, 2776 .rfk_track = rtw8852c_rfk_track, 2777 .power_trim = rtw8852c_power_trim, 2778 .set_txpwr = rtw8852c_set_txpwr, 2779 .set_txpwr_ctrl = rtw8852c_set_txpwr_ctrl, 2780 .init_txpwr_unit = rtw8852c_init_txpwr_unit, 2781 .get_thermal = rtw8852c_get_thermal, 2782 .ctrl_btg = rtw8852c_ctrl_btg, 2783 .query_ppdu = rtw8852c_query_ppdu, 2784 .bb_ctrl_btc_preagc = rtw8852c_bb_ctrl_btc_preagc, 2785 .cfg_txrx_path = rtw8852c_bb_cfg_txrx_path, 2786 .set_txpwr_ul_tb_offset = rtw8852c_set_txpwr_ul_tb_offset, 2787 .pwr_on_func = rtw8852c_pwr_on_func, 2788 .pwr_off_func = rtw8852c_pwr_off_func, 2789 .query_rxdesc = rtw89_core_query_rxdesc, 2790 .fill_txdesc = rtw89_core_fill_txdesc_v1, 2791 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc_fwcmd_v1, 2792 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path_v1, 2793 .mac_cfg_gnt = rtw89_mac_cfg_gnt_v1, 2794 .stop_sch_tx = rtw89_mac_stop_sch_tx_v1, 2795 .resume_sch_tx = rtw89_mac_resume_sch_tx_v1, 2796 .h2c_dctl_sec_cam = rtw89_fw_h2c_dctl_sec_cam_v1, 2797 2798 .btc_set_rfe = rtw8852c_btc_set_rfe, 2799 .btc_init_cfg = rtw8852c_btc_init_cfg, 2800 .btc_set_wl_pri = rtw8852c_btc_set_wl_pri, 2801 .btc_set_wl_txpwr_ctrl = rtw8852c_btc_set_wl_txpwr_ctrl, 2802 .btc_get_bt_rssi = rtw8852c_btc_get_bt_rssi, 2803 .btc_update_bt_cnt = rtw8852c_btc_update_bt_cnt, 2804 .btc_wl_s1_standby = rtw8852c_btc_wl_s1_standby, 2805 .btc_set_wl_rx_gain = rtw8852c_btc_set_wl_rx_gain, 2806 .btc_set_policy = rtw89_btc_set_policy_v1, 2807 }; 2808 2809 const struct rtw89_chip_info rtw8852c_chip_info = { 2810 .chip_id = RTL8852C, 2811 .chip_gen = RTW89_CHIP_AX, 2812 .ops = &rtw8852c_chip_ops, 2813 .fw_basename = RTW8852C_FW_BASENAME, 2814 .fw_format_max = RTW8852C_FW_FORMAT_MAX, 2815 .try_ce_fw = false, 2816 .needed_fw_elms = 0, 2817 .fifo_size = 458752, 2818 .small_fifo_size = false, 2819 .dle_scc_rsvd_size = 0, 2820 .max_amsdu_limit = 8000, 2821 .dis_2g_40m_ul_ofdma = false, 2822 .rsvd_ple_ofst = 0x6f800, 2823 .hfc_param_ini = rtw8852c_hfc_param_ini_pcie, 2824 .dle_mem = rtw8852c_dle_mem_pcie, 2825 .wde_qempty_acq_num = 16, 2826 .wde_qempty_mgq_sel = 16, 2827 .rf_base_addr = {0xe000, 0xf000}, 2828 .pwr_on_seq = NULL, 2829 .pwr_off_seq = NULL, 2830 .bb_table = &rtw89_8852c_phy_bb_table, 2831 .bb_gain_table = &rtw89_8852c_phy_bb_gain_table, 2832 .rf_table = {&rtw89_8852c_phy_radiob_table, 2833 &rtw89_8852c_phy_radioa_table,}, 2834 .nctl_table = &rtw89_8852c_phy_nctl_table, 2835 .nctl_post_table = NULL, 2836 .byr_table = &rtw89_8852c_byr_table, 2837 .dflt_parms = &rtw89_8852c_dflt_parms, 2838 .rfe_parms_conf = NULL, 2839 .txpwr_factor_rf = 2, 2840 .txpwr_factor_mac = 1, 2841 .dig_table = NULL, 2842 .dig_regs = &rtw8852c_dig_regs, 2843 .tssi_dbw_table = &rtw89_8852c_tssi_dbw_table, 2844 .support_chanctx_num = 1, 2845 .support_bands = BIT(NL80211_BAND_2GHZ) | 2846 BIT(NL80211_BAND_5GHZ) | 2847 BIT(NL80211_BAND_6GHZ), 2848 .support_bw160 = true, 2849 .support_unii4 = true, 2850 .support_ul_tb_ctrl = false, 2851 .hw_sec_hdr = true, 2852 .rf_path_num = 2, 2853 .tx_nss = 2, 2854 .rx_nss = 2, 2855 .acam_num = 128, 2856 .bcam_num = 20, 2857 .scam_num = 128, 2858 .bacam_num = 8, 2859 .bacam_dynamic_num = 8, 2860 .bacam_ver = RTW89_BACAM_V0_EXT, 2861 .sec_ctrl_efuse_size = 4, 2862 .physical_efuse_size = 1216, 2863 .logical_efuse_size = 2048, 2864 .limit_efuse_size = 1280, 2865 .dav_phy_efuse_size = 96, 2866 .dav_log_efuse_size = 16, 2867 .phycap_addr = 0x590, 2868 .phycap_size = 0x60, 2869 .para_ver = 0x1, 2870 .wlcx_desired = 0x06000000, 2871 .btcx_desired = 0x7, 2872 .scbd = 0x1, 2873 .mailbox = 0x1, 2874 2875 .afh_guard_ch = 6, 2876 .wl_rssi_thres = rtw89_btc_8852c_wl_rssi_thres, 2877 .bt_rssi_thres = rtw89_btc_8852c_bt_rssi_thres, 2878 .rssi_tol = 2, 2879 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852c_mon_reg), 2880 .mon_reg = rtw89_btc_8852c_mon_reg, 2881 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_ul), 2882 .rf_para_ulink = rtw89_btc_8852c_rf_ul, 2883 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852c_rf_dl), 2884 .rf_para_dlink = rtw89_btc_8852c_rf_dl, 2885 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2886 BIT(RTW89_PS_MODE_CLK_GATED) | 2887 BIT(RTW89_PS_MODE_PWR_GATED), 2888 .low_power_hci_modes = BIT(RTW89_PS_MODE_CLK_GATED) | 2889 BIT(RTW89_PS_MODE_PWR_GATED), 2890 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD_V1, 2891 .hci_func_en_addr = R_AX_HCI_FUNC_EN_V1, 2892 .h2c_desc_size = sizeof(struct rtw89_rxdesc_short), 2893 .txwd_body_size = sizeof(struct rtw89_txwd_body_v1), 2894 .h2c_ctrl_reg = R_AX_H2CREG_CTRL_V1, 2895 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 2896 .h2c_regs = rtw8852c_h2c_regs, 2897 .c2h_ctrl_reg = R_AX_C2HREG_CTRL_V1, 2898 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 2899 .c2h_regs = rtw8852c_c2h_regs, 2900 .page_regs = &rtw8852c_page_regs, 2901 .cfo_src_fd = false, 2902 .cfo_hw_comp = false, 2903 .dcfo_comp = &rtw8852c_dcfo_comp, 2904 .dcfo_comp_sft = 12, 2905 .imr_info = &rtw8852c_imr_info, 2906 .rrsr_cfgs = &rtw8852c_rrsr_cfgs, 2907 .bss_clr_map_reg = R_BSS_CLR_MAP, 2908 .dma_ch_mask = 0, 2909 .edcca_lvl_reg = R_SEG0R_EDCCA_LVL, 2910 #ifdef CONFIG_PM 2911 .wowlan_stub = &rtw_wowlan_stub_8852c, 2912 #endif 2913 .xtal_info = NULL, 2914 }; 2915 EXPORT_SYMBOL(rtw8852c_chip_info); 2916 2917 MODULE_FIRMWARE(RTW8852C_MODULE_FIRMWARE); 2918 MODULE_AUTHOR("Realtek Corporation"); 2919 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852C driver"); 2920 MODULE_LICENSE("Dual BSD/GPL"); 2921