1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2024 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_8852BX_H__ 6 #define __RTW89_8852BX_H__ 7 8 #include "core.h" 9 10 #define RF_PATH_NUM_8852BX 2 11 #define BB_PATH_NUM_8852BX 2 12 13 enum rtw8852bx_pmac_mode { 14 NONE_TEST, 15 PKTS_TX, 16 PKTS_RX, 17 CONT_TX 18 }; 19 20 struct rtw8852bx_u_efuse { 21 u8 rsvd[0x88]; 22 u8 mac_addr[ETH_ALEN]; 23 }; 24 25 struct rtw8852bx_e_efuse { 26 u8 mac_addr[ETH_ALEN]; 27 }; 28 29 struct rtw8852bx_tssi_offset { 30 u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM]; 31 u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM]; 32 u8 rsvd[7]; 33 u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM]; 34 } __packed; 35 36 struct rtw8852bx_efuse { 37 u8 rsvd[0x210]; 38 struct rtw8852bx_tssi_offset path_a_tssi; 39 u8 rsvd1[10]; 40 struct rtw8852bx_tssi_offset path_b_tssi; 41 u8 rsvd2[94]; 42 u8 channel_plan; 43 u8 xtal_k; 44 u8 rsvd3; 45 u8 iqk_lck; 46 u8 rsvd4[5]; 47 u8 reg_setting:2; 48 u8 tx_diversity:1; 49 u8 rx_diversity:2; 50 u8 ac_mode:1; 51 u8 module_type:2; 52 u8 rsvd5; 53 u8 shared_ant:1; 54 u8 coex_type:3; 55 u8 ant_iso:1; 56 u8 radio_on_off:1; 57 u8 rsvd6:2; 58 u8 eeprom_version; 59 u8 customer_id; 60 u8 tx_bb_swing_2g; 61 u8 tx_bb_swing_5g; 62 u8 tx_cali_pwr_trk_mode; 63 u8 trx_path_selection; 64 u8 rfe_type; 65 u8 country_code[2]; 66 u8 rsvd7[3]; 67 u8 path_a_therm; 68 u8 path_b_therm; 69 u8 rsvd8[2]; 70 u8 rx_gain_2g_ofdm; 71 u8 rsvd9; 72 u8 rx_gain_2g_cck; 73 u8 rsvd10; 74 u8 rx_gain_5g_low; 75 u8 rsvd11; 76 u8 rx_gain_5g_mid; 77 u8 rsvd12; 78 u8 rx_gain_5g_high; 79 u8 rsvd13[35]; 80 u8 path_a_cck_pwr_idx[6]; 81 u8 path_a_bw40_1tx_pwr_idx[5]; 82 u8 path_a_ofdm_1tx_pwr_idx_diff:4; 83 u8 path_a_bw20_1tx_pwr_idx_diff:4; 84 u8 path_a_bw20_2tx_pwr_idx_diff:4; 85 u8 path_a_bw40_2tx_pwr_idx_diff:4; 86 u8 path_a_cck_2tx_pwr_idx_diff:4; 87 u8 path_a_ofdm_2tx_pwr_idx_diff:4; 88 u8 rsvd14[0xf2]; 89 union { 90 struct rtw8852bx_u_efuse u; 91 struct rtw8852bx_e_efuse e; 92 }; 93 } __packed; 94 95 struct rtw8852bx_bb_pmac_info { 96 u8 en_pmac_tx:1; 97 u8 is_cck:1; 98 u8 mode:3; 99 u8 rsvd:3; 100 u16 tx_cnt; 101 u16 period; 102 u16 tx_time; 103 u8 duty_cycle; 104 }; 105 106 struct rtw8852bx_bb_tssi_bak { 107 u8 tx_path; 108 u8 rx_path; 109 u32 p0_rfmode; 110 u32 p0_rfmode_ftm; 111 u32 p1_rfmode; 112 u32 p1_rfmode_ftm; 113 s16 tx_pwr; /* S9 */ 114 }; 115 116 struct rtw8852bx_info { 117 int (*mac_enable_bb_rf)(struct rtw89_dev *rtwdev); 118 int (*mac_disable_bb_rf)(struct rtw89_dev *rtwdev); 119 void (*bb_sethw)(struct rtw89_dev *rtwdev); 120 void (*bb_reset_all)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 121 void (*bb_cfg_txrx_path)(struct rtw89_dev *rtwdev); 122 void (*bb_cfg_tx_path)(struct rtw89_dev *rtwdev, u8 tx_path); 123 void (*bb_ctrl_rx_path)(struct rtw89_dev *rtwdev, 124 enum rtw89_rf_path_bit rx_path); 125 void (*bb_set_plcp_tx)(struct rtw89_dev *rtwdev); 126 void (*bb_set_power)(struct rtw89_dev *rtwdev, s16 pwr_dbm, 127 enum rtw89_phy_idx idx); 128 void (*bb_set_pmac_pkt_tx)(struct rtw89_dev *rtwdev, u8 enable, 129 u16 tx_cnt, u16 period, u16 tx_time, 130 enum rtw89_phy_idx idx); 131 void (*bb_backup_tssi)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx, 132 struct rtw8852bx_bb_tssi_bak *bak); 133 void (*bb_restore_tssi)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx, 134 const struct rtw8852bx_bb_tssi_bak *bak); 135 void (*bb_tx_mode_switch)(struct rtw89_dev *rtwdev, 136 enum rtw89_phy_idx idx, u8 mode); 137 void (*set_channel_mac)(struct rtw89_dev *rtwdev, 138 const struct rtw89_chan *chan, u8 mac_idx); 139 void (*set_channel_bb)(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 140 enum rtw89_phy_idx phy_idx); 141 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 142 enum rtw89_phy_idx phy_idx); 143 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 144 enum rtw89_phy_idx phy_idx); 145 void (*query_ppdu)(struct rtw89_dev *rtwdev, 146 struct rtw89_rx_phy_ppdu *phy_ppdu, 147 struct ieee80211_rx_status *status); 148 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 149 enum rtw89_efuse_block block); 150 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 151 void (*power_trim)(struct rtw89_dev *rtwdev); 152 void (*set_txpwr)(struct rtw89_dev *rtwdev, 153 const struct rtw89_chan *chan, 154 enum rtw89_phy_idx phy_idx); 155 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 156 enum rtw89_phy_idx phy_idx); 157 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 158 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 159 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 160 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 161 void (*adc_cfg)(struct rtw89_dev *rtwdev, u8 bw, u8 path); 162 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 163 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 164 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 165 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 166 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 167 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 168 }; 169 170 extern const struct rtw8852bx_info rtw8852bx_info; 171 172 static inline 173 int rtw8852bx_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 174 { 175 return rtw8852bx_info.mac_enable_bb_rf(rtwdev); 176 } 177 178 static inline 179 int rtw8852bx_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 180 { 181 return rtw8852bx_info.mac_disable_bb_rf(rtwdev); 182 } 183 184 static inline 185 void rtw8852bx_bb_sethw(struct rtw89_dev *rtwdev) 186 { 187 rtw8852bx_info.bb_sethw(rtwdev); 188 } 189 190 static inline 191 void rtw8852bx_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 192 { 193 rtw8852bx_info.bb_reset_all(rtwdev, phy_idx); 194 } 195 196 static inline 197 void rtw8852bx_bb_cfg_txrx_path(struct rtw89_dev *rtwdev) 198 { 199 rtw8852bx_info.bb_cfg_txrx_path(rtwdev); 200 } 201 202 static inline 203 void rtw8852bx_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path) 204 { 205 rtw8852bx_info.bb_cfg_tx_path(rtwdev, tx_path); 206 } 207 208 static inline 209 void rtw8852bx_bb_ctrl_rx_path(struct rtw89_dev *rtwdev, 210 enum rtw89_rf_path_bit rx_path) 211 { 212 rtw8852bx_info.bb_ctrl_rx_path(rtwdev, rx_path); 213 } 214 215 static inline 216 void rtw8852bx_bb_set_plcp_tx(struct rtw89_dev *rtwdev) 217 { 218 rtw8852bx_info.bb_set_plcp_tx(rtwdev); 219 } 220 221 static inline 222 void rtw8852bx_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, 223 enum rtw89_phy_idx idx) 224 { 225 rtw8852bx_info.bb_set_power(rtwdev, pwr_dbm, idx); 226 } 227 228 static inline 229 void rtw8852bx_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, 230 u16 tx_cnt, u16 period, u16 tx_time, 231 enum rtw89_phy_idx idx) 232 { 233 rtw8852bx_info.bb_set_pmac_pkt_tx(rtwdev, enable, tx_cnt, period, tx_time, idx); 234 } 235 236 static inline 237 void rtw8852bx_bb_backup_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx, 238 struct rtw8852bx_bb_tssi_bak *bak) 239 { 240 rtw8852bx_info.bb_backup_tssi(rtwdev, idx, bak); 241 } 242 243 static inline 244 void rtw8852bx_bb_restore_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx, 245 const struct rtw8852bx_bb_tssi_bak *bak) 246 { 247 rtw8852bx_info.bb_restore_tssi(rtwdev, idx, bak); 248 } 249 250 static inline 251 void rtw8852bx_bb_tx_mode_switch(struct rtw89_dev *rtwdev, 252 enum rtw89_phy_idx idx, u8 mode) 253 { 254 rtw8852bx_info.bb_tx_mode_switch(rtwdev, idx, mode); 255 } 256 257 static inline 258 void rtw8852bx_set_channel_mac(struct rtw89_dev *rtwdev, 259 const struct rtw89_chan *chan, u8 mac_idx) 260 { 261 rtw8852bx_info.set_channel_mac(rtwdev, chan, mac_idx); 262 } 263 264 static inline 265 void rtw8852bx_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 266 enum rtw89_phy_idx phy_idx) 267 { 268 rtw8852bx_info.set_channel_bb(rtwdev, chan, phy_idx); 269 } 270 271 static inline 272 void rtw8852bx_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 273 enum rtw89_phy_idx phy_idx) 274 { 275 rtw8852bx_info.ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 276 } 277 278 static inline 279 void rtw8852bx_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 280 enum rtw89_phy_idx phy_idx) 281 { 282 rtw8852bx_info.ctrl_btg_bt_rx(rtwdev, en, phy_idx); 283 } 284 285 static inline 286 void rtw8852bx_query_ppdu(struct rtw89_dev *rtwdev, 287 struct rtw89_rx_phy_ppdu *phy_ppdu, 288 struct ieee80211_rx_status *status) 289 { 290 rtw8852bx_info.query_ppdu(rtwdev, phy_ppdu, status); 291 } 292 293 static inline 294 int rtw8852bx_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map, 295 enum rtw89_efuse_block block) 296 { 297 return rtw8852bx_info.read_efuse(rtwdev, log_map, block); 298 } 299 300 static inline 301 int rtw8852bx_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 302 { 303 return rtw8852bx_info.read_phycap(rtwdev, phycap_map); 304 } 305 306 static inline 307 void rtw8852bx_power_trim(struct rtw89_dev *rtwdev) 308 { 309 rtw8852bx_info.power_trim(rtwdev); 310 } 311 312 static inline 313 void rtw8852bx_set_txpwr(struct rtw89_dev *rtwdev, 314 const struct rtw89_chan *chan, 315 enum rtw89_phy_idx phy_idx) 316 { 317 rtw8852bx_info.set_txpwr(rtwdev, chan, phy_idx); 318 } 319 320 static inline 321 void rtw8852bx_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 322 enum rtw89_phy_idx phy_idx) 323 { 324 rtw8852bx_info.set_txpwr_ctrl(rtwdev, phy_idx); 325 } 326 327 static inline 328 int rtw8852bx_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 329 { 330 return rtw8852bx_info.init_txpwr_unit(rtwdev, phy_idx); 331 } 332 333 static inline 334 void rtw8852bx_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 335 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 336 { 337 rtw8852bx_info.set_txpwr_ul_tb_offset(rtwdev, pw_ofst, mac_idx); 338 } 339 340 static inline 341 u8 rtw8852bx_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 342 { 343 return rtw8852bx_info.get_thermal(rtwdev, rf_path); 344 } 345 346 static inline 347 void rtw8852bx_adc_cfg(struct rtw89_dev *rtwdev, u8 bw, u8 path) 348 { 349 rtw8852bx_info.adc_cfg(rtwdev, bw, path); 350 } 351 352 static inline 353 void rtw8852bx_btc_init_cfg(struct rtw89_dev *rtwdev) 354 { 355 rtw8852bx_info.btc_init_cfg(rtwdev); 356 } 357 358 static inline 359 void rtw8852bx_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 360 { 361 rtw8852bx_info.btc_set_wl_pri(rtwdev, map, state); 362 } 363 364 static inline 365 s8 rtw8852bx_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 366 { 367 return rtw8852bx_info.btc_get_bt_rssi(rtwdev, val); 368 } 369 370 static inline 371 void rtw8852bx_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 372 { 373 rtw8852bx_info.btc_update_bt_cnt(rtwdev); 374 } 375 376 static inline 377 void rtw8852bx_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 378 { 379 rtw8852bx_info.btc_wl_s1_standby(rtwdev, state); 380 } 381 382 static inline 383 void rtw8852bx_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 384 { 385 rtw8852bx_info.btc_set_wl_rx_gain(rtwdev, level); 386 } 387 388 #endif 389