1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "reg.h" 10 #include "rtw8852a.h" 11 #include "rtw8852a_rfk.h" 12 #include "rtw8852a_table.h" 13 #include "txrx.h" 14 15 #define RTW8852A_FW_FORMAT_MAX 0 16 #define RTW8852A_FW_BASENAME "rtw89/rtw8852a_fw" 17 #define RTW8852A_MODULE_FIRMWARE \ 18 RTW8852A_FW_BASENAME ".bin" 19 20 static const struct rtw89_hfc_ch_cfg rtw8852a_hfc_chcfg_pcie[] = { 21 {128, 1896, grp_0}, /* ACH 0 */ 22 {128, 1896, grp_0}, /* ACH 1 */ 23 {128, 1896, grp_0}, /* ACH 2 */ 24 {128, 1896, grp_0}, /* ACH 3 */ 25 {128, 1896, grp_1}, /* ACH 4 */ 26 {128, 1896, grp_1}, /* ACH 5 */ 27 {128, 1896, grp_1}, /* ACH 6 */ 28 {128, 1896, grp_1}, /* ACH 7 */ 29 {32, 1896, grp_0}, /* B0MGQ */ 30 {128, 1896, grp_0}, /* B0HIQ */ 31 {32, 1896, grp_1}, /* B1MGQ */ 32 {128, 1896, grp_1}, /* B1HIQ */ 33 {40, 0, 0} /* FWCMDQ */ 34 }; 35 36 static const struct rtw89_hfc_pub_cfg rtw8852a_hfc_pubcfg_pcie = { 37 1896, /* Group 0 */ 38 1896, /* Group 1 */ 39 3792, /* Public Max */ 40 0 /* WP threshold */ 41 }; 42 43 static const struct rtw89_hfc_param_ini rtw8852a_hfc_param_ini_pcie[] = { 44 [RTW89_QTA_SCC] = {rtw8852a_hfc_chcfg_pcie, &rtw8852a_hfc_pubcfg_pcie, 45 &rtw89_mac_size.hfc_preccfg_pcie, RTW89_HCIFC_POH}, 46 [RTW89_QTA_DLFW] = {NULL, NULL, &rtw89_mac_size.hfc_preccfg_pcie, 47 RTW89_HCIFC_POH}, 48 [RTW89_QTA_INVALID] = {NULL}, 49 }; 50 51 static const struct rtw89_dle_mem rtw8852a_dle_mem_pcie[] = { 52 [RTW89_QTA_SCC] = {RTW89_QTA_SCC, &rtw89_mac_size.wde_size0, 53 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0, 54 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4, 55 &rtw89_mac_size.ple_qt5}, 56 [RTW89_QTA_WOW] = {RTW89_QTA_WOW, &rtw89_mac_size.wde_size0, 57 &rtw89_mac_size.ple_size0, &rtw89_mac_size.wde_qt0, 58 &rtw89_mac_size.wde_qt0, &rtw89_mac_size.ple_qt4, 59 &rtw89_mac_size.ple_qt_52a_wow}, 60 [RTW89_QTA_DLFW] = {RTW89_QTA_DLFW, &rtw89_mac_size.wde_size4, 61 &rtw89_mac_size.ple_size4, &rtw89_mac_size.wde_qt4, 62 &rtw89_mac_size.wde_qt4, &rtw89_mac_size.ple_qt13, 63 &rtw89_mac_size.ple_qt13}, 64 [RTW89_QTA_INVALID] = {RTW89_QTA_INVALID, NULL, NULL, NULL, NULL, NULL, 65 NULL}, 66 }; 67 68 static const struct rtw89_reg2_def rtw8852a_pmac_ht20_mcs7_tbl[] = { 69 {0x44AC, 0x00000000}, 70 {0x44B0, 0x00000000}, 71 {0x44B4, 0x00000000}, 72 {0x44B8, 0x00000000}, 73 {0x44BC, 0x00000000}, 74 {0x44C0, 0x00000000}, 75 {0x44C4, 0x00000000}, 76 {0x44C8, 0x00000000}, 77 {0x44CC, 0x00000000}, 78 {0x44D0, 0x00000000}, 79 {0x44D4, 0x00000000}, 80 {0x44D8, 0x00000000}, 81 {0x44DC, 0x00000000}, 82 {0x44E0, 0x00000000}, 83 {0x44E4, 0x00000000}, 84 {0x44E8, 0x00000000}, 85 {0x44EC, 0x00000000}, 86 {0x44F0, 0x00000000}, 87 {0x44F4, 0x00000000}, 88 {0x44F8, 0x00000000}, 89 {0x44FC, 0x00000000}, 90 {0x4500, 0x00000000}, 91 {0x4504, 0x00000000}, 92 {0x4508, 0x00000000}, 93 {0x450C, 0x00000000}, 94 {0x4510, 0x00000000}, 95 {0x4514, 0x00000000}, 96 {0x4518, 0x00000000}, 97 {0x451C, 0x00000000}, 98 {0x4520, 0x00000000}, 99 {0x4524, 0x00000000}, 100 {0x4528, 0x00000000}, 101 {0x452C, 0x00000000}, 102 {0x4530, 0x4E1F3E81}, 103 {0x4534, 0x00000000}, 104 {0x4538, 0x0000005A}, 105 {0x453C, 0x00000000}, 106 {0x4540, 0x00000000}, 107 {0x4544, 0x00000000}, 108 {0x4548, 0x00000000}, 109 {0x454C, 0x00000000}, 110 {0x4550, 0x00000000}, 111 {0x4554, 0x00000000}, 112 {0x4558, 0x00000000}, 113 {0x455C, 0x00000000}, 114 {0x4560, 0x4060001A}, 115 {0x4564, 0x40000000}, 116 {0x4568, 0x00000000}, 117 {0x456C, 0x00000000}, 118 {0x4570, 0x04000007}, 119 {0x4574, 0x0000DC87}, 120 {0x4578, 0x00000BAB}, 121 {0x457C, 0x03E00000}, 122 {0x4580, 0x00000048}, 123 {0x4584, 0x00000000}, 124 {0x4588, 0x000003E8}, 125 {0x458C, 0x30000000}, 126 {0x4590, 0x00000000}, 127 {0x4594, 0x10000000}, 128 {0x4598, 0x00000001}, 129 {0x459C, 0x00030000}, 130 {0x45A0, 0x01000000}, 131 {0x45A4, 0x03000200}, 132 {0x45A8, 0xC00001C0}, 133 {0x45AC, 0x78018000}, 134 {0x45B0, 0x80000000}, 135 {0x45B4, 0x01C80600}, 136 {0x45B8, 0x00000002}, 137 {0x4594, 0x10000000} 138 }; 139 140 static const struct rtw89_reg3_def rtw8852a_btc_preagc_en_defs[] = { 141 {0x4624, GENMASK(20, 14), 0x40}, 142 {0x46f8, GENMASK(20, 14), 0x40}, 143 {0x4674, GENMASK(20, 19), 0x2}, 144 {0x4748, GENMASK(20, 19), 0x2}, 145 {0x4650, GENMASK(14, 10), 0x18}, 146 {0x4724, GENMASK(14, 10), 0x18}, 147 {0x4688, GENMASK(1, 0), 0x3}, 148 {0x475c, GENMASK(1, 0), 0x3}, 149 }; 150 151 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_en_defs); 152 153 static const struct rtw89_reg3_def rtw8852a_btc_preagc_dis_defs[] = { 154 {0x4624, GENMASK(20, 14), 0x1a}, 155 {0x46f8, GENMASK(20, 14), 0x1a}, 156 {0x4674, GENMASK(20, 19), 0x1}, 157 {0x4748, GENMASK(20, 19), 0x1}, 158 {0x4650, GENMASK(14, 10), 0x12}, 159 {0x4724, GENMASK(14, 10), 0x12}, 160 {0x4688, GENMASK(1, 0), 0x0}, 161 {0x475c, GENMASK(1, 0), 0x0}, 162 }; 163 164 static DECLARE_PHY_REG3_TBL(rtw8852a_btc_preagc_dis_defs); 165 166 static const struct rtw89_pwr_cfg rtw8852a_pwron[] = { 167 {0x00C6, 168 PWR_CV_MSK_B, 169 PWR_INTF_MSK_PCIE, 170 PWR_BASE_MAC, 171 PWR_CMD_WRITE, BIT(6), BIT(6)}, 172 {0x1086, 173 PWR_CV_MSK_ALL, 174 PWR_INTF_MSK_SDIO, 175 PWR_BASE_MAC, 176 PWR_CMD_WRITE, BIT(0), 0}, 177 {0x1086, 178 PWR_CV_MSK_ALL, 179 PWR_INTF_MSK_SDIO, 180 PWR_BASE_MAC, 181 PWR_CMD_POLL, BIT(1), BIT(1)}, 182 {0x0005, 183 PWR_CV_MSK_ALL, 184 PWR_INTF_MSK_ALL, 185 PWR_BASE_MAC, 186 PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, 187 {0x0005, 188 PWR_CV_MSK_ALL, 189 PWR_INTF_MSK_ALL, 190 PWR_BASE_MAC, 191 PWR_CMD_WRITE, BIT(7), 0}, 192 {0x0005, 193 PWR_CV_MSK_ALL, 194 PWR_INTF_MSK_ALL, 195 PWR_BASE_MAC, 196 PWR_CMD_WRITE, BIT(2), 0}, 197 {0x0006, 198 PWR_CV_MSK_ALL, 199 PWR_INTF_MSK_ALL, 200 PWR_BASE_MAC, 201 PWR_CMD_POLL, BIT(1), BIT(1)}, 202 {0x0006, 203 PWR_CV_MSK_ALL, 204 PWR_INTF_MSK_ALL, 205 PWR_BASE_MAC, 206 PWR_CMD_WRITE, BIT(0), BIT(0)}, 207 {0x0005, 208 PWR_CV_MSK_ALL, 209 PWR_INTF_MSK_ALL, 210 PWR_BASE_MAC, 211 PWR_CMD_WRITE, BIT(0), BIT(0)}, 212 {0x0005, 213 PWR_CV_MSK_ALL, 214 PWR_INTF_MSK_ALL, 215 PWR_BASE_MAC, 216 PWR_CMD_POLL, BIT(0), 0}, 217 {0x106D, 218 PWR_CV_MSK_B | PWR_CV_MSK_C, 219 PWR_INTF_MSK_USB, 220 PWR_BASE_MAC, 221 PWR_CMD_WRITE, BIT(6), 0}, 222 {0x0088, 223 PWR_CV_MSK_ALL, 224 PWR_INTF_MSK_ALL, 225 PWR_BASE_MAC, 226 PWR_CMD_WRITE, BIT(0), BIT(0)}, 227 {0x0088, 228 PWR_CV_MSK_ALL, 229 PWR_INTF_MSK_ALL, 230 PWR_BASE_MAC, 231 PWR_CMD_WRITE, BIT(0), 0}, 232 {0x0088, 233 PWR_CV_MSK_ALL, 234 PWR_INTF_MSK_ALL, 235 PWR_BASE_MAC, 236 PWR_CMD_WRITE, BIT(0), BIT(0)}, 237 {0x0088, 238 PWR_CV_MSK_ALL, 239 PWR_INTF_MSK_ALL, 240 PWR_BASE_MAC, 241 PWR_CMD_WRITE, BIT(0), 0}, 242 {0x0088, 243 PWR_CV_MSK_ALL, 244 PWR_INTF_MSK_ALL, 245 PWR_BASE_MAC, 246 PWR_CMD_WRITE, BIT(0), BIT(0)}, 247 {0x0083, 248 PWR_CV_MSK_ALL, 249 PWR_INTF_MSK_ALL, 250 PWR_BASE_MAC, 251 PWR_CMD_WRITE, BIT(6), 0}, 252 {0x0080, 253 PWR_CV_MSK_ALL, 254 PWR_INTF_MSK_ALL, 255 PWR_BASE_MAC, 256 PWR_CMD_WRITE, BIT(5), BIT(5)}, 257 {0x0024, 258 PWR_CV_MSK_ALL, 259 PWR_INTF_MSK_ALL, 260 PWR_BASE_MAC, 261 PWR_CMD_WRITE, BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0}, 262 {0x02A0, 263 PWR_CV_MSK_ALL, 264 PWR_INTF_MSK_ALL, 265 PWR_BASE_MAC, 266 PWR_CMD_WRITE, BIT(1), BIT(1)}, 267 {0x02A2, 268 PWR_CV_MSK_ALL, 269 PWR_INTF_MSK_ALL, 270 PWR_BASE_MAC, 271 PWR_CMD_WRITE, BIT(7) | BIT(6) | BIT(5), 0}, 272 {0x0071, 273 PWR_CV_MSK_ALL, 274 PWR_INTF_MSK_PCIE, 275 PWR_BASE_MAC, 276 PWR_CMD_WRITE, BIT(4), 0}, 277 {0x0010, 278 PWR_CV_MSK_A, 279 PWR_INTF_MSK_PCIE, 280 PWR_BASE_MAC, 281 PWR_CMD_WRITE, BIT(2), BIT(2)}, 282 {0x02A0, 283 PWR_CV_MSK_A, 284 PWR_INTF_MSK_ALL, 285 PWR_BASE_MAC, 286 PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 287 {0xFFFF, 288 PWR_CV_MSK_ALL, 289 PWR_INTF_MSK_ALL, 290 0, 291 PWR_CMD_END, 0, 0}, 292 }; 293 294 static const struct rtw89_pwr_cfg rtw8852a_pwroff[] = { 295 {0x02F0, 296 PWR_CV_MSK_ALL, 297 PWR_INTF_MSK_ALL, 298 PWR_BASE_MAC, 299 PWR_CMD_WRITE, 0xFF, 0}, 300 {0x02F1, 301 PWR_CV_MSK_ALL, 302 PWR_INTF_MSK_ALL, 303 PWR_BASE_MAC, 304 PWR_CMD_WRITE, 0xFF, 0}, 305 {0x0006, 306 PWR_CV_MSK_ALL, 307 PWR_INTF_MSK_ALL, 308 PWR_BASE_MAC, 309 PWR_CMD_WRITE, BIT(0), BIT(0)}, 310 {0x0002, 311 PWR_CV_MSK_ALL, 312 PWR_INTF_MSK_ALL, 313 PWR_BASE_MAC, 314 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 315 {0x0082, 316 PWR_CV_MSK_ALL, 317 PWR_INTF_MSK_ALL, 318 PWR_BASE_MAC, 319 PWR_CMD_WRITE, BIT(1) | BIT(0), 0}, 320 {0x106D, 321 PWR_CV_MSK_B | PWR_CV_MSK_C, 322 PWR_INTF_MSK_USB, 323 PWR_BASE_MAC, 324 PWR_CMD_WRITE, BIT(6), BIT(6)}, 325 {0x0005, 326 PWR_CV_MSK_ALL, 327 PWR_INTF_MSK_ALL, 328 PWR_BASE_MAC, 329 PWR_CMD_WRITE, BIT(1), BIT(1)}, 330 {0x0005, 331 PWR_CV_MSK_ALL, 332 PWR_INTF_MSK_ALL, 333 PWR_BASE_MAC, 334 PWR_CMD_POLL, BIT(1), 0}, 335 {0x0091, 336 PWR_CV_MSK_ALL, 337 PWR_INTF_MSK_PCIE, 338 PWR_BASE_MAC, 339 PWR_CMD_WRITE, BIT(0), 0}, 340 {0x0005, 341 PWR_CV_MSK_ALL, 342 PWR_INTF_MSK_PCIE, 343 PWR_BASE_MAC, 344 PWR_CMD_WRITE, BIT(2), BIT(2)}, 345 {0x0007, 346 PWR_CV_MSK_ALL, 347 PWR_INTF_MSK_USB, 348 PWR_BASE_MAC, 349 PWR_CMD_WRITE, BIT(4), 0}, 350 {0x0007, 351 PWR_CV_MSK_ALL, 352 PWR_INTF_MSK_SDIO, 353 PWR_BASE_MAC, 354 PWR_CMD_WRITE, BIT(6) | BIT(4), 0}, 355 {0x0005, 356 PWR_CV_MSK_ALL, 357 PWR_INTF_MSK_SDIO, 358 PWR_BASE_MAC, 359 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 360 {0x0005, 361 PWR_CV_MSK_C | PWR_CV_MSK_D | PWR_CV_MSK_E | PWR_CV_MSK_F | 362 PWR_CV_MSK_G, 363 PWR_INTF_MSK_USB, 364 PWR_BASE_MAC, 365 PWR_CMD_WRITE, BIT(4) | BIT(3), BIT(3)}, 366 {0x1086, 367 PWR_CV_MSK_ALL, 368 PWR_INTF_MSK_SDIO, 369 PWR_BASE_MAC, 370 PWR_CMD_WRITE, BIT(0), BIT(0)}, 371 {0x1086, 372 PWR_CV_MSK_ALL, 373 PWR_INTF_MSK_SDIO, 374 PWR_BASE_MAC, 375 PWR_CMD_POLL, BIT(1), 0}, 376 {0xFFFF, 377 PWR_CV_MSK_ALL, 378 PWR_INTF_MSK_ALL, 379 0, 380 PWR_CMD_END, 0, 0}, 381 }; 382 383 static const struct rtw89_pwr_cfg * const pwr_on_seq_8852a[] = { 384 rtw8852a_pwron, NULL 385 }; 386 387 static const struct rtw89_pwr_cfg * const pwr_off_seq_8852a[] = { 388 rtw8852a_pwroff, NULL 389 }; 390 391 static const u32 rtw8852a_h2c_regs[RTW89_H2CREG_MAX] = { 392 R_AX_H2CREG_DATA0, R_AX_H2CREG_DATA1, R_AX_H2CREG_DATA2, 393 R_AX_H2CREG_DATA3 394 }; 395 396 static const u32 rtw8852a_c2h_regs[RTW89_C2HREG_MAX] = { 397 R_AX_C2HREG_DATA0, R_AX_C2HREG_DATA1, R_AX_C2HREG_DATA2, 398 R_AX_C2HREG_DATA3 399 }; 400 401 static const u32 rtw8852a_wow_wakeup_regs[RTW89_WOW_REASON_NUM] = { 402 R_AX_C2HREG_DATA3 + 3, R_AX_C2HREG_DATA3 + 3, 403 }; 404 405 static const struct rtw89_page_regs rtw8852a_page_regs = { 406 .hci_fc_ctrl = R_AX_HCI_FC_CTRL, 407 .ch_page_ctrl = R_AX_CH_PAGE_CTRL, 408 .ach_page_ctrl = R_AX_ACH0_PAGE_CTRL, 409 .ach_page_info = R_AX_ACH0_PAGE_INFO, 410 .pub_page_info3 = R_AX_PUB_PAGE_INFO3, 411 .pub_page_ctrl1 = R_AX_PUB_PAGE_CTRL1, 412 .pub_page_ctrl2 = R_AX_PUB_PAGE_CTRL2, 413 .pub_page_info1 = R_AX_PUB_PAGE_INFO1, 414 .pub_page_info2 = R_AX_PUB_PAGE_INFO2, 415 .wp_page_ctrl1 = R_AX_WP_PAGE_CTRL1, 416 .wp_page_ctrl2 = R_AX_WP_PAGE_CTRL2, 417 .wp_page_info1 = R_AX_WP_PAGE_INFO1, 418 }; 419 420 static const struct rtw89_reg_def rtw8852a_dcfo_comp = { 421 R_DCFO_COMP_S0, B_DCFO_COMP_S0_MSK 422 }; 423 424 static const struct rtw89_imr_info rtw8852a_imr_info = { 425 .wdrls_imr_set = B_AX_WDRLS_IMR_SET, 426 .wsec_imr_reg = R_AX_SEC_DEBUG, 427 .wsec_imr_set = B_AX_IMR_ERROR, 428 .mpdu_tx_imr_set = 0, 429 .mpdu_rx_imr_set = 0, 430 .sta_sch_imr_set = B_AX_STA_SCHEDULER_IMR_SET, 431 .txpktctl_imr_b0_reg = R_AX_TXPKTCTL_ERR_IMR_ISR, 432 .txpktctl_imr_b0_clr = B_AX_TXPKTCTL_IMR_B0_CLR, 433 .txpktctl_imr_b0_set = B_AX_TXPKTCTL_IMR_B0_SET, 434 .txpktctl_imr_b1_reg = R_AX_TXPKTCTL_ERR_IMR_ISR_B1, 435 .txpktctl_imr_b1_clr = B_AX_TXPKTCTL_IMR_B1_CLR, 436 .txpktctl_imr_b1_set = B_AX_TXPKTCTL_IMR_B1_SET, 437 .wde_imr_clr = B_AX_WDE_IMR_CLR, 438 .wde_imr_set = B_AX_WDE_IMR_SET, 439 .ple_imr_clr = B_AX_PLE_IMR_CLR, 440 .ple_imr_set = B_AX_PLE_IMR_SET, 441 .host_disp_imr_clr = B_AX_HOST_DISP_IMR_CLR, 442 .host_disp_imr_set = B_AX_HOST_DISP_IMR_SET, 443 .cpu_disp_imr_clr = B_AX_CPU_DISP_IMR_CLR, 444 .cpu_disp_imr_set = B_AX_CPU_DISP_IMR_SET, 445 .other_disp_imr_clr = B_AX_OTHER_DISP_IMR_CLR, 446 .other_disp_imr_set = 0, 447 .bbrpt_com_err_imr_reg = R_AX_BBRPT_COM_ERR_IMR_ISR, 448 .bbrpt_chinfo_err_imr_reg = R_AX_BBRPT_CHINFO_ERR_IMR_ISR, 449 .bbrpt_err_imr_set = 0, 450 .bbrpt_dfs_err_imr_reg = R_AX_BBRPT_DFS_ERR_IMR_ISR, 451 .ptcl_imr_clr = B_AX_PTCL_IMR_CLR, 452 .ptcl_imr_set = B_AX_PTCL_IMR_SET, 453 .cdma_imr_0_reg = R_AX_DLE_CTRL, 454 .cdma_imr_0_clr = B_AX_DLE_IMR_CLR, 455 .cdma_imr_0_set = B_AX_DLE_IMR_SET, 456 .cdma_imr_1_reg = 0, 457 .cdma_imr_1_clr = 0, 458 .cdma_imr_1_set = 0, 459 .phy_intf_imr_reg = R_AX_PHYINFO_ERR_IMR, 460 .phy_intf_imr_clr = 0, 461 .phy_intf_imr_set = 0, 462 .rmac_imr_reg = R_AX_RMAC_ERR_ISR, 463 .rmac_imr_clr = B_AX_RMAC_IMR_CLR, 464 .rmac_imr_set = B_AX_RMAC_IMR_SET, 465 .tmac_imr_reg = R_AX_TMAC_ERR_IMR_ISR, 466 .tmac_imr_clr = B_AX_TMAC_IMR_CLR, 467 .tmac_imr_set = B_AX_TMAC_IMR_SET, 468 }; 469 470 static const struct rtw89_xtal_info rtw8852a_xtal_info = { 471 .xcap_reg = R_AX_XTAL_ON_CTRL0, 472 .sc_xo_mask = B_AX_XTAL_SC_XO_MASK, 473 .sc_xi_mask = B_AX_XTAL_SC_XI_MASK, 474 }; 475 476 static const struct rtw89_rrsr_cfgs rtw8852a_rrsr_cfgs = { 477 .ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0}, 478 .rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2}, 479 }; 480 481 static const struct rtw89_dig_regs rtw8852a_dig_regs = { 482 .seg0_pd_reg = R_SEG0R_PD, 483 .pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK, 484 .pd_spatial_reuse_en = B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, 485 .bmode_pd_reg = R_BMODE_PDTH_EN_V1, 486 .bmode_cca_rssi_limit_en = B_BMODE_PDTH_LIMIT_EN_MSK_V1, 487 .bmode_pd_lower_bound_reg = R_BMODE_PDTH_V1, 488 .bmode_rssi_nocca_low_th_mask = B_BMODE_PDTH_LOWER_BOUND_MSK_V1, 489 .p0_lna_init = {R_PATH0_LNA_INIT, B_PATH0_LNA_INIT_IDX_MSK}, 490 .p1_lna_init = {R_PATH1_LNA_INIT, B_PATH1_LNA_INIT_IDX_MSK}, 491 .p0_tia_init = {R_PATH0_TIA_INIT, B_PATH0_TIA_INIT_IDX_MSK}, 492 .p1_tia_init = {R_PATH1_TIA_INIT, B_PATH1_TIA_INIT_IDX_MSK}, 493 .p0_rxb_init = {R_PATH0_RXB_INIT, B_PATH0_RXB_INIT_IDX_MSK}, 494 .p1_rxb_init = {R_PATH1_RXB_INIT, B_PATH1_RXB_INIT_IDX_MSK}, 495 .p0_p20_pagcugc_en = {R_PATH0_P20_FOLLOW_BY_PAGCUGC, 496 B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 497 .p0_s20_pagcugc_en = {R_PATH0_S20_FOLLOW_BY_PAGCUGC, 498 B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 499 .p1_p20_pagcugc_en = {R_PATH1_P20_FOLLOW_BY_PAGCUGC, 500 B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 501 .p1_s20_pagcugc_en = {R_PATH1_S20_FOLLOW_BY_PAGCUGC, 502 B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 503 }; 504 505 static const struct rtw89_edcca_regs rtw8852a_edcca_regs = { 506 .edcca_level = R_SEG0R_EDCCA_LVL, 507 .edcca_mask = B_EDCCA_LVL_MSK0, 508 .edcca_p_mask = B_EDCCA_LVL_MSK1, 509 .ppdu_level = R_SEG0R_EDCCA_LVL, 510 .ppdu_mask = B_EDCCA_LVL_MSK3, 511 .rpt_a = R_EDCCA_RPT_A, 512 .rpt_b = R_EDCCA_RPT_B, 513 .rpt_sel = R_EDCCA_RPT_SEL, 514 .rpt_sel_mask = B_EDCCA_RPT_SEL_MSK, 515 .tx_collision_t2r_st = R_TX_COLLISION_T2R_ST, 516 .tx_collision_t2r_st_mask = B_TX_COLLISION_T2R_ST_M, 517 }; 518 519 static void rtw8852ae_efuse_parsing(struct rtw89_efuse *efuse, 520 struct rtw8852a_efuse *map) 521 { 522 ether_addr_copy(efuse->addr, map->e.mac_addr); 523 efuse->rfe_type = map->rfe_type; 524 efuse->xtal_cap = map->xtal_k; 525 } 526 527 static void rtw8852a_efuse_parsing_tssi(struct rtw89_dev *rtwdev, 528 struct rtw8852a_efuse *map) 529 { 530 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 531 struct rtw8852a_tssi_offset *ofst[] = {&map->path_a_tssi, &map->path_b_tssi}; 532 u8 i, j; 533 534 tssi->thermal[RF_PATH_A] = map->path_a_therm; 535 tssi->thermal[RF_PATH_B] = map->path_b_therm; 536 537 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 538 memcpy(tssi->tssi_cck[i], ofst[i]->cck_tssi, 539 sizeof(ofst[i]->cck_tssi)); 540 541 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) 542 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 543 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", 544 i, j, tssi->tssi_cck[i][j]); 545 546 memcpy(tssi->tssi_mcs[i], ofst[i]->bw40_tssi, 547 sizeof(ofst[i]->bw40_tssi)); 548 memcpy(tssi->tssi_mcs[i] + TSSI_MCS_2G_CH_GROUP_NUM, 549 ofst[i]->bw40_1s_tssi_5g, sizeof(ofst[i]->bw40_1s_tssi_5g)); 550 551 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) 552 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 553 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", 554 i, j, tssi->tssi_mcs[i][j]); 555 } 556 } 557 558 static int rtw8852a_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map, 559 enum rtw89_efuse_block block) 560 { 561 struct rtw89_efuse *efuse = &rtwdev->efuse; 562 struct rtw8852a_efuse *map; 563 564 map = (struct rtw8852a_efuse *)log_map; 565 566 efuse->country_code[0] = map->country_code[0]; 567 efuse->country_code[1] = map->country_code[1]; 568 rtw8852a_efuse_parsing_tssi(rtwdev, map); 569 570 switch (rtwdev->hci.type) { 571 case RTW89_HCI_TYPE_PCIE: 572 rtw8852ae_efuse_parsing(efuse, map); 573 break; 574 default: 575 return -ENOTSUPP; 576 } 577 578 rtw89_info(rtwdev, "chip rfe_type is %d\n", efuse->rfe_type); 579 580 return 0; 581 } 582 583 static void rtw8852a_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map) 584 { 585 struct rtw89_tssi_info *tssi = &rtwdev->tssi; 586 static const u32 tssi_trim_addr[RF_PATH_NUM_8852A] = {0x5D6, 0x5AB}; 587 u32 addr = rtwdev->chip->phycap_addr; 588 bool pg = false; 589 u32 ofst; 590 u8 i, j; 591 592 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 593 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) { 594 /* addrs are in decreasing order */ 595 ofst = tssi_trim_addr[i] - addr - j; 596 tssi->tssi_trim[i][j] = phycap_map[ofst]; 597 598 if (phycap_map[ofst] != 0xff) 599 pg = true; 600 } 601 } 602 603 if (!pg) { 604 memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim)); 605 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 606 "[TSSI][TRIM] no PG, set all trim info to 0\n"); 607 } 608 609 for (i = 0; i < RF_PATH_NUM_8852A; i++) 610 for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) 611 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 612 "[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n", 613 i, j, tssi->tssi_trim[i][j], 614 tssi_trim_addr[i] - j); 615 } 616 617 static void rtw8852a_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev, 618 u8 *phycap_map) 619 { 620 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 621 static const u32 thm_trim_addr[RF_PATH_NUM_8852A] = {0x5DF, 0x5DC}; 622 u32 addr = rtwdev->chip->phycap_addr; 623 u8 i; 624 625 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 626 info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr]; 627 628 rtw89_debug(rtwdev, RTW89_DBG_RFK, 629 "[THERMAL][TRIM] path=%d thermal_trim=0x%x\n", 630 i, info->thermal_trim[i]); 631 632 if (info->thermal_trim[i] != 0xff) 633 info->pg_thermal_trim = true; 634 } 635 } 636 637 static void rtw8852a_thermal_trim(struct rtw89_dev *rtwdev) 638 { 639 #define __thm_setting(raw) \ 640 ({ \ 641 u8 __v = (raw); \ 642 ((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \ 643 }) 644 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 645 u8 i, val; 646 647 if (!info->pg_thermal_trim) { 648 rtw89_debug(rtwdev, RTW89_DBG_RFK, 649 "[THERMAL][TRIM] no PG, do nothing\n"); 650 651 return; 652 } 653 654 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 655 val = __thm_setting(info->thermal_trim[i]); 656 rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val); 657 658 rtw89_debug(rtwdev, RTW89_DBG_RFK, 659 "[THERMAL][TRIM] path=%d thermal_setting=0x%x\n", 660 i, val); 661 } 662 #undef __thm_setting 663 } 664 665 static void rtw8852a_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev, 666 u8 *phycap_map) 667 { 668 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 669 static const u32 pabias_trim_addr[RF_PATH_NUM_8852A] = {0x5DE, 0x5DB}; 670 u32 addr = rtwdev->chip->phycap_addr; 671 u8 i; 672 673 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 674 info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr]; 675 676 rtw89_debug(rtwdev, RTW89_DBG_RFK, 677 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", 678 i, info->pa_bias_trim[i]); 679 680 if (info->pa_bias_trim[i] != 0xff) 681 info->pg_pa_bias_trim = true; 682 } 683 } 684 685 static void rtw8852a_pa_bias_trim(struct rtw89_dev *rtwdev) 686 { 687 struct rtw89_power_trim_info *info = &rtwdev->pwr_trim; 688 u8 pabias_2g, pabias_5g; 689 u8 i; 690 691 if (!info->pg_pa_bias_trim) { 692 rtw89_debug(rtwdev, RTW89_DBG_RFK, 693 "[PA_BIAS][TRIM] no PG, do nothing\n"); 694 695 return; 696 } 697 698 for (i = 0; i < RF_PATH_NUM_8852A; i++) { 699 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); 700 pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]); 701 702 rtw89_debug(rtwdev, RTW89_DBG_RFK, 703 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", 704 i, pabias_2g, pabias_5g); 705 706 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g); 707 rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g); 708 } 709 } 710 711 static int rtw8852a_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 712 { 713 rtw8852a_phycap_parsing_tssi(rtwdev, phycap_map); 714 rtw8852a_phycap_parsing_thermal_trim(rtwdev, phycap_map); 715 rtw8852a_phycap_parsing_pa_bias_trim(rtwdev, phycap_map); 716 717 return 0; 718 } 719 720 static void rtw8852a_power_trim(struct rtw89_dev *rtwdev) 721 { 722 rtw8852a_thermal_trim(rtwdev); 723 rtw8852a_pa_bias_trim(rtwdev); 724 } 725 726 static void rtw8852a_set_channel_mac(struct rtw89_dev *rtwdev, 727 const struct rtw89_chan *chan, 728 u8 mac_idx) 729 { 730 u32 rf_mod = rtw89_mac_reg_by_idx(rtwdev, R_AX_WMAC_RFMOD, mac_idx); 731 u32 sub_carr = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 732 u32 chk_rate = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXRATE_CHK, mac_idx); 733 u8 txsc20 = 0, txsc40 = 0; 734 735 switch (chan->band_width) { 736 case RTW89_CHANNEL_WIDTH_80: 737 txsc40 = rtw89_phy_get_txsc(rtwdev, chan, 738 RTW89_CHANNEL_WIDTH_40); 739 fallthrough; 740 case RTW89_CHANNEL_WIDTH_40: 741 txsc20 = rtw89_phy_get_txsc(rtwdev, chan, 742 RTW89_CHANNEL_WIDTH_20); 743 break; 744 default: 745 break; 746 } 747 748 switch (chan->band_width) { 749 case RTW89_CHANNEL_WIDTH_80: 750 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(1)); 751 rtw89_write32(rtwdev, sub_carr, txsc20 | (txsc40 << 4)); 752 break; 753 case RTW89_CHANNEL_WIDTH_40: 754 rtw89_write8_mask(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK, BIT(0)); 755 rtw89_write32(rtwdev, sub_carr, txsc20); 756 break; 757 case RTW89_CHANNEL_WIDTH_20: 758 rtw89_write8_clr(rtwdev, rf_mod, B_AX_WMAC_RFMOD_MASK); 759 rtw89_write32(rtwdev, sub_carr, 0); 760 break; 761 default: 762 break; 763 } 764 765 if (chan->channel > 14) 766 rtw89_write8_set(rtwdev, chk_rate, 767 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 768 else 769 rtw89_write8_clr(rtwdev, chk_rate, 770 B_AX_CHECK_CCK_EN | B_AX_RTS_LIMIT_IN_OFDM6); 771 } 772 773 static const u32 rtw8852a_sco_barker_threshold[14] = { 774 0x1cfea, 0x1d0e1, 0x1d1d7, 0x1d2cd, 0x1d3c3, 0x1d4b9, 0x1d5b0, 0x1d6a6, 775 0x1d79c, 0x1d892, 0x1d988, 0x1da7f, 0x1db75, 0x1ddc4 776 }; 777 778 static const u32 rtw8852a_sco_cck_threshold[14] = { 779 0x27de3, 0x27f35, 0x28088, 0x281da, 0x2832d, 0x2847f, 0x285d2, 0x28724, 780 0x28877, 0x289c9, 0x28b1c, 0x28c6e, 0x28dc1, 0x290ed 781 }; 782 783 static int rtw8852a_ctrl_sco_cck(struct rtw89_dev *rtwdev, u8 central_ch, 784 u8 primary_ch, enum rtw89_bandwidth bw) 785 { 786 u8 ch_element; 787 788 if (bw == RTW89_CHANNEL_WIDTH_20) { 789 ch_element = central_ch - 1; 790 } else if (bw == RTW89_CHANNEL_WIDTH_40) { 791 if (primary_ch == 1) 792 ch_element = central_ch - 1 + 2; 793 else 794 ch_element = central_ch - 1 - 2; 795 } else { 796 rtw89_warn(rtwdev, "Invalid BW:%d for CCK\n", bw); 797 return -EINVAL; 798 } 799 rtw89_phy_write32_mask(rtwdev, R_RXSCOBC, B_RXSCOBC_TH, 800 rtw8852a_sco_barker_threshold[ch_element]); 801 rtw89_phy_write32_mask(rtwdev, R_RXSCOCCK, B_RXSCOCCK_TH, 802 rtw8852a_sco_cck_threshold[ch_element]); 803 804 return 0; 805 } 806 807 static void rtw8852a_ch_setting(struct rtw89_dev *rtwdev, u8 central_ch, 808 u8 path) 809 { 810 u32 val; 811 812 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 813 if (val == INV_RF_DATA) { 814 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 815 return; 816 } 817 val &= ~0x303ff; 818 val |= central_ch; 819 if (central_ch > 14) 820 val |= (BIT(16) | BIT(8)); 821 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 822 } 823 824 static u8 rtw8852a_sco_mapping(u8 central_ch) 825 { 826 if (central_ch == 1) 827 return 109; 828 else if (central_ch >= 2 && central_ch <= 6) 829 return 108; 830 else if (central_ch >= 7 && central_ch <= 10) 831 return 107; 832 else if (central_ch >= 11 && central_ch <= 14) 833 return 106; 834 else if (central_ch == 36 || central_ch == 38) 835 return 51; 836 else if (central_ch >= 40 && central_ch <= 58) 837 return 50; 838 else if (central_ch >= 60 && central_ch <= 64) 839 return 49; 840 else if (central_ch == 100 || central_ch == 102) 841 return 48; 842 else if (central_ch >= 104 && central_ch <= 126) 843 return 47; 844 else if (central_ch >= 128 && central_ch <= 151) 845 return 46; 846 else if (central_ch >= 153 && central_ch <= 177) 847 return 45; 848 else 849 return 0; 850 } 851 852 static void rtw8852a_ctrl_ch(struct rtw89_dev *rtwdev, u8 central_ch, 853 enum rtw89_phy_idx phy_idx) 854 { 855 u8 sco_comp; 856 bool is_2g = central_ch <= 14; 857 858 if (phy_idx == RTW89_PHY_0) { 859 /* Path A */ 860 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_A); 861 if (is_2g) 862 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 863 B_PATH0_TIA_ERR_G1_SEL, 1, 864 phy_idx); 865 else 866 rtw89_phy_write32_idx(rtwdev, R_PATH0_TIA_ERR_G1, 867 B_PATH0_TIA_ERR_G1_SEL, 0, 868 phy_idx); 869 870 /* Path B */ 871 if (!rtwdev->dbcc_en) { 872 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 873 if (is_2g) 874 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 875 B_P1_MODE_SEL, 876 1, phy_idx); 877 else 878 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 879 B_P1_MODE_SEL, 880 0, phy_idx); 881 } else { 882 if (is_2g) 883 rtw89_phy_write32_clr(rtwdev, R_2P4G_BAND, 884 B_2P4G_BAND_SEL); 885 else 886 rtw89_phy_write32_set(rtwdev, R_2P4G_BAND, 887 B_2P4G_BAND_SEL); 888 } 889 /* SCO compensate FC setting */ 890 sco_comp = rtw8852a_sco_mapping(central_ch); 891 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 892 sco_comp, phy_idx); 893 } else { 894 /* Path B */ 895 rtw8852a_ch_setting(rtwdev, central_ch, RF_PATH_B); 896 if (is_2g) 897 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 898 B_P1_MODE_SEL, 899 1, phy_idx); 900 else 901 rtw89_phy_write32_idx(rtwdev, R_P1_MODE, 902 B_P1_MODE_SEL, 903 0, phy_idx); 904 /* SCO compensate FC setting */ 905 sco_comp = rtw8852a_sco_mapping(central_ch); 906 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_INV, 907 sco_comp, phy_idx); 908 } 909 910 /* Band edge */ 911 if (is_2g) 912 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 1, 913 phy_idx); 914 else 915 rtw89_phy_write32_idx(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0, 916 phy_idx); 917 918 /* CCK parameters */ 919 if (central_ch == 14) { 920 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 921 0x3b13ff); 922 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 923 0x1c42de); 924 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 925 0xfdb0ad); 926 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 927 0xf60f6e); 928 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 929 0xfd8f92); 930 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 0x2d011); 931 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 0x1c02c); 932 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 933 0xfff00a); 934 } else { 935 rtw89_phy_write32_mask(rtwdev, R_TXFIR0, B_TXFIR_C01, 936 0x3d23ff); 937 rtw89_phy_write32_mask(rtwdev, R_TXFIR2, B_TXFIR_C23, 938 0x29b354); 939 rtw89_phy_write32_mask(rtwdev, R_TXFIR4, B_TXFIR_C45, 0xfc1c8); 940 rtw89_phy_write32_mask(rtwdev, R_TXFIR6, B_TXFIR_C67, 941 0xfdb053); 942 rtw89_phy_write32_mask(rtwdev, R_TXFIR8, B_TXFIR_C89, 943 0xf86f9a); 944 rtw89_phy_write32_mask(rtwdev, R_TXFIRA, B_TXFIR_CAB, 945 0xfaef92); 946 rtw89_phy_write32_mask(rtwdev, R_TXFIRC, B_TXFIR_CCD, 947 0xfe5fcc); 948 rtw89_phy_write32_mask(rtwdev, R_TXFIRE, B_TXFIR_CEF, 949 0xffdff5); 950 } 951 } 952 953 static void rtw8852a_bw_setting(struct rtw89_dev *rtwdev, u8 bw, u8 path) 954 { 955 u32 val = 0; 956 u32 adc_sel[2] = {0x12d0, 0x32d0}; 957 u32 wbadc_sel[2] = {0x12ec, 0x32ec}; 958 959 val = rtw89_read_rf(rtwdev, path, RR_CFGCH, RFREG_MASK); 960 if (val == INV_RF_DATA) { 961 rtw89_warn(rtwdev, "Invalid RF_0x18 for Path-%d\n", path); 962 return; 963 } 964 val &= ~(BIT(11) | BIT(10)); 965 switch (bw) { 966 case RTW89_CHANNEL_WIDTH_5: 967 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x1); 968 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x0); 969 val |= (BIT(11) | BIT(10)); 970 break; 971 case RTW89_CHANNEL_WIDTH_10: 972 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x2); 973 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x1); 974 val |= (BIT(11) | BIT(10)); 975 break; 976 case RTW89_CHANNEL_WIDTH_20: 977 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 978 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 979 val |= (BIT(11) | BIT(10)); 980 break; 981 case RTW89_CHANNEL_WIDTH_40: 982 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 983 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 984 val |= BIT(11); 985 break; 986 case RTW89_CHANNEL_WIDTH_80: 987 rtw89_phy_write32_mask(rtwdev, adc_sel[path], 0x6000, 0x0); 988 rtw89_phy_write32_mask(rtwdev, wbadc_sel[path], 0x30, 0x2); 989 val |= BIT(10); 990 break; 991 default: 992 rtw89_warn(rtwdev, "Fail to set ADC\n"); 993 } 994 995 rtw89_write_rf(rtwdev, path, RR_CFGCH, RFREG_MASK, val); 996 } 997 998 static void 999 rtw8852a_ctrl_bw(struct rtw89_dev *rtwdev, u8 pri_ch, u8 bw, 1000 enum rtw89_phy_idx phy_idx) 1001 { 1002 /* Switch bandwidth */ 1003 switch (bw) { 1004 case RTW89_CHANNEL_WIDTH_5: 1005 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1006 phy_idx); 1007 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x1, 1008 phy_idx); 1009 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1010 0x0, phy_idx); 1011 break; 1012 case RTW89_CHANNEL_WIDTH_10: 1013 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1014 phy_idx); 1015 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x2, 1016 phy_idx); 1017 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1018 0x0, phy_idx); 1019 break; 1020 case RTW89_CHANNEL_WIDTH_20: 1021 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x0, 1022 phy_idx); 1023 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1024 phy_idx); 1025 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1026 0x0, phy_idx); 1027 break; 1028 case RTW89_CHANNEL_WIDTH_40: 1029 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x1, 1030 phy_idx); 1031 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1032 phy_idx); 1033 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1034 pri_ch, 1035 phy_idx); 1036 if (pri_ch == RTW89_SC_20_UPPER) 1037 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 1); 1038 else 1039 rtw89_phy_write32_mask(rtwdev, R_RXSC, B_RXSC_EN, 0); 1040 break; 1041 case RTW89_CHANNEL_WIDTH_80: 1042 rtw89_phy_write32_idx(rtwdev, R_FC0_BW, B_FC0_BW_SET, 0x2, 1043 phy_idx); 1044 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_SBW, 0x0, 1045 phy_idx); 1046 rtw89_phy_write32_idx(rtwdev, R_CHBW_MOD, B_CHBW_MOD_PRICH, 1047 pri_ch, 1048 phy_idx); 1049 break; 1050 default: 1051 rtw89_warn(rtwdev, "Fail to switch bw (bw:%d, pri ch:%d)\n", bw, 1052 pri_ch); 1053 } 1054 1055 if (phy_idx == RTW89_PHY_0) { 1056 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_A); 1057 if (!rtwdev->dbcc_en) 1058 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 1059 } else { 1060 rtw8852a_bw_setting(rtwdev, bw, RF_PATH_B); 1061 } 1062 } 1063 1064 static void rtw8852a_spur_elimination(struct rtw89_dev *rtwdev, u8 central_ch) 1065 { 1066 if (central_ch == 153) { 1067 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1068 0x210); 1069 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1070 0x210); 1071 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x7c0); 1072 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1073 B_P0_NBIIDX_NOTCH_EN, 0x1); 1074 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1075 B_P1_NBIIDX_NOTCH_EN, 0x1); 1076 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1077 0x1); 1078 } else if (central_ch == 151) { 1079 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1080 0x210); 1081 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1082 0x210); 1083 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x40); 1084 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1085 B_P0_NBIIDX_NOTCH_EN, 0x1); 1086 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1087 B_P1_NBIIDX_NOTCH_EN, 0x1); 1088 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1089 0x1); 1090 } else if (central_ch == 155) { 1091 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, B_P0_NBIIDX_VAL, 1092 0x2d0); 1093 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, B_P1_NBIIDX_VAL, 1094 0x2d0); 1095 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI, B_SEG0CSI_IDX, 0x740); 1096 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1097 B_P0_NBIIDX_NOTCH_EN, 0x1); 1098 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1099 B_P1_NBIIDX_NOTCH_EN, 0x1); 1100 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1101 0x1); 1102 } else { 1103 rtw89_phy_write32_mask(rtwdev, R_P0_NBIIDX, 1104 B_P0_NBIIDX_NOTCH_EN, 0x0); 1105 rtw89_phy_write32_mask(rtwdev, R_P1_NBIIDX, 1106 B_P1_NBIIDX_NOTCH_EN, 0x0); 1107 rtw89_phy_write32_mask(rtwdev, R_SEG0CSI_EN, B_SEG0CSI_EN, 1108 0x0); 1109 } 1110 } 1111 1112 static void rtw8852a_bb_reset_all(struct rtw89_dev *rtwdev, 1113 enum rtw89_phy_idx phy_idx) 1114 { 1115 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1116 phy_idx); 1117 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, 1118 phy_idx); 1119 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, 1120 phy_idx); 1121 } 1122 1123 static void rtw8852a_bb_reset_en(struct rtw89_dev *rtwdev, 1124 enum rtw89_phy_idx phy_idx, bool en) 1125 { 1126 if (en) 1127 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1128 1, 1129 phy_idx); 1130 else 1131 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1132 0, 1133 phy_idx); 1134 } 1135 1136 static void rtw8852a_bb_reset(struct rtw89_dev *rtwdev, 1137 enum rtw89_phy_idx phy_idx) 1138 { 1139 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1140 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1141 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1142 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1143 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1144 rtw89_phy_write32_clr(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1145 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1146 rtw89_phy_write32_clr(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1147 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1148 } 1149 1150 static void rtw8852a_bb_macid_ctrl_init(struct rtw89_dev *rtwdev, 1151 enum rtw89_phy_idx phy_idx) 1152 { 1153 u32 addr; 1154 1155 for (addr = R_AX_PWR_MACID_LMT_TABLE0; 1156 addr <= R_AX_PWR_MACID_LMT_TABLE127; addr += 4) 1157 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 0); 1158 } 1159 1160 static void rtw8852a_bb_sethw(struct rtw89_dev *rtwdev) 1161 { 1162 rtw89_phy_write32_clr(rtwdev, R_P0_EN_SOUND_WO_NDP, B_P0_EN_SOUND_WO_NDP); 1163 rtw89_phy_write32_clr(rtwdev, R_P1_EN_SOUND_WO_NDP, B_P1_EN_SOUND_WO_NDP); 1164 1165 if (rtwdev->hal.cv <= CHIP_CCV) { 1166 rtw89_phy_write32_set(rtwdev, R_RSTB_WATCH_DOG, B_P0_RSTB_WATCH_DOG); 1167 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_1, 0x864FA000); 1168 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_2, 0x43F); 1169 rtw89_phy_write32(rtwdev, R_BRK_ASYNC_RST_EN_3, 0x7FFF); 1170 rtw89_phy_write32_set(rtwdev, R_SPOOF_ASYNC_RST, B_SPOOF_ASYNC_RST); 1171 rtw89_phy_write32_set(rtwdev, R_P0_TXPW_RSTB, B_P0_TXPW_RSTB_MANON); 1172 rtw89_phy_write32_set(rtwdev, R_P1_TXPW_RSTB, B_P1_TXPW_RSTB_MANON); 1173 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, B_STS_PARSING_TIME); 1174 } 1175 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK0, B_CFO_TRK_MSK, 0x1f); 1176 rtw89_phy_write32_mask(rtwdev, R_CFO_TRK1, B_CFO_TRK_MSK, 0x0c); 1177 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_0); 1178 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0x0, RTW89_PHY_1); 1179 rtw89_phy_write32_clr(rtwdev, R_NDP_BRK0, B_NDP_RU_BRK); 1180 rtw89_phy_write32_set(rtwdev, R_NDP_BRK1, B_NDP_RU_BRK); 1181 1182 rtw8852a_bb_macid_ctrl_init(rtwdev, RTW89_PHY_0); 1183 } 1184 1185 static void rtw8852a_bbrst_for_rfk(struct rtw89_dev *rtwdev, 1186 enum rtw89_phy_idx phy_idx) 1187 { 1188 rtw89_phy_write32_set(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1189 rtw89_phy_write32_set(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1190 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1191 rtw89_phy_write32_clr(rtwdev, R_P0_TSSI_TRK, B_P0_TSSI_TRK_EN); 1192 rtw89_phy_write32_clr(rtwdev, R_P1_TSSI_TRK, B_P1_TSSI_TRK_EN); 1193 udelay(1); 1194 } 1195 1196 static void rtw8852a_set_channel_bb(struct rtw89_dev *rtwdev, 1197 const struct rtw89_chan *chan, 1198 enum rtw89_phy_idx phy_idx) 1199 { 1200 bool cck_en = chan->channel <= 14; 1201 u8 pri_ch_idx = chan->pri_ch_idx; 1202 1203 if (cck_en) 1204 rtw8852a_ctrl_sco_cck(rtwdev, chan->channel, 1205 chan->primary_channel, 1206 chan->band_width); 1207 1208 rtw8852a_ctrl_ch(rtwdev, chan->channel, phy_idx); 1209 rtw8852a_ctrl_bw(rtwdev, pri_ch_idx, chan->band_width, phy_idx); 1210 if (cck_en) { 1211 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 0); 1212 } else { 1213 rtw89_phy_write32_mask(rtwdev, R_RXCCA, B_RXCCA_DIS, 1); 1214 rtw8852a_bbrst_for_rfk(rtwdev, phy_idx); 1215 } 1216 rtw8852a_spur_elimination(rtwdev, chan->channel); 1217 rtw89_phy_write32_mask(rtwdev, R_MAC_PIN_SEL, B_CH_IDX_SEG0, 1218 chan->primary_channel); 1219 rtw8852a_bb_reset_all(rtwdev, phy_idx); 1220 } 1221 1222 static void rtw8852a_set_channel(struct rtw89_dev *rtwdev, 1223 const struct rtw89_chan *chan, 1224 enum rtw89_mac_idx mac_idx, 1225 enum rtw89_phy_idx phy_idx) 1226 { 1227 rtw8852a_set_channel_mac(rtwdev, chan, mac_idx); 1228 rtw8852a_set_channel_bb(rtwdev, chan, phy_idx); 1229 } 1230 1231 static void rtw8852a_dfs_en(struct rtw89_dev *rtwdev, bool en) 1232 { 1233 if (en) 1234 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 1); 1235 else 1236 rtw89_phy_write32_mask(rtwdev, R_UPD_P0, B_UPD_P0_EN, 0); 1237 } 1238 1239 static void rtw8852a_tssi_cont_en(struct rtw89_dev *rtwdev, bool en, 1240 enum rtw89_rf_path path) 1241 { 1242 static const u32 tssi_trk[2] = {0x5818, 0x7818}; 1243 static const u32 ctrl_bbrst[2] = {0x58dc, 0x78dc}; 1244 1245 if (en) { 1246 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x0); 1247 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x0); 1248 } else { 1249 rtw89_phy_write32_mask(rtwdev, ctrl_bbrst[path], BIT(30), 0x1); 1250 rtw89_phy_write32_mask(rtwdev, tssi_trk[path], BIT(30), 0x1); 1251 } 1252 } 1253 1254 static void rtw8852a_tssi_cont_en_phyidx(struct rtw89_dev *rtwdev, bool en, 1255 u8 phy_idx) 1256 { 1257 if (!rtwdev->dbcc_en) { 1258 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1259 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1260 } else { 1261 if (phy_idx == RTW89_PHY_0) 1262 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_A); 1263 else 1264 rtw8852a_tssi_cont_en(rtwdev, en, RF_PATH_B); 1265 } 1266 } 1267 1268 static void rtw8852a_adc_en(struct rtw89_dev *rtwdev, bool en) 1269 { 1270 if (en) 1271 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1272 0x0); 1273 else 1274 rtw89_phy_write32_mask(rtwdev, R_ADC_FIFO, B_ADC_FIFO_RST, 1275 0xf); 1276 } 1277 1278 static void rtw8852a_set_channel_help(struct rtw89_dev *rtwdev, bool enter, 1279 struct rtw89_channel_help_params *p, 1280 const struct rtw89_chan *chan, 1281 enum rtw89_mac_idx mac_idx, 1282 enum rtw89_phy_idx phy_idx) 1283 { 1284 if (enter) { 1285 rtw89_chip_stop_sch_tx(rtwdev, mac_idx, &p->tx_en, 1286 RTW89_SCH_TX_SEL_ALL); 1287 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, false); 1288 rtw8852a_dfs_en(rtwdev, false); 1289 rtw8852a_tssi_cont_en_phyidx(rtwdev, false, phy_idx); 1290 rtw8852a_adc_en(rtwdev, false); 1291 fsleep(40); 1292 rtw8852a_bb_reset_en(rtwdev, phy_idx, false); 1293 } else { 1294 rtw89_mac_cfg_ppdu_status(rtwdev, mac_idx, true); 1295 rtw8852a_adc_en(rtwdev, true); 1296 rtw8852a_dfs_en(rtwdev, true); 1297 rtw8852a_tssi_cont_en_phyidx(rtwdev, true, phy_idx); 1298 rtw8852a_bb_reset_en(rtwdev, phy_idx, true); 1299 rtw89_chip_resume_sch_tx(rtwdev, mac_idx, p->tx_en); 1300 } 1301 } 1302 1303 static void rtw8852a_fem_setup(struct rtw89_dev *rtwdev) 1304 { 1305 struct rtw89_efuse *efuse = &rtwdev->efuse; 1306 1307 switch (efuse->rfe_type) { 1308 case 11: 1309 case 12: 1310 case 17: 1311 case 18: 1312 case 51: 1313 case 53: 1314 rtwdev->fem.epa_2g = true; 1315 rtwdev->fem.elna_2g = true; 1316 fallthrough; 1317 case 9: 1318 case 10: 1319 case 15: 1320 case 16: 1321 rtwdev->fem.epa_5g = true; 1322 rtwdev->fem.elna_5g = true; 1323 break; 1324 default: 1325 break; 1326 } 1327 } 1328 1329 static void rtw8852a_rfk_init(struct rtw89_dev *rtwdev) 1330 { 1331 rtwdev->is_tssi_mode[RF_PATH_A] = false; 1332 rtwdev->is_tssi_mode[RF_PATH_B] = false; 1333 1334 rtw8852a_rck(rtwdev); 1335 rtw8852a_dack(rtwdev); 1336 rtw8852a_rx_dck(rtwdev, RTW89_PHY_0, true); 1337 } 1338 1339 static void rtw8852a_rfk_channel(struct rtw89_dev *rtwdev) 1340 { 1341 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 1342 1343 rtw8852a_rx_dck(rtwdev, phy_idx, true); 1344 rtw8852a_iqk(rtwdev, phy_idx); 1345 rtw8852a_tssi(rtwdev, phy_idx); 1346 rtw8852a_dpk(rtwdev, phy_idx); 1347 } 1348 1349 static void rtw8852a_rfk_band_changed(struct rtw89_dev *rtwdev, 1350 enum rtw89_phy_idx phy_idx) 1351 { 1352 rtw8852a_tssi_scan(rtwdev, phy_idx); 1353 } 1354 1355 static void rtw8852a_rfk_scan(struct rtw89_dev *rtwdev, bool start) 1356 { 1357 rtw8852a_wifi_scan_notify(rtwdev, start, RTW89_PHY_0); 1358 } 1359 1360 static void rtw8852a_rfk_track(struct rtw89_dev *rtwdev) 1361 { 1362 rtw8852a_dpk_track(rtwdev); 1363 rtw8852a_tssi_track(rtwdev); 1364 } 1365 1366 static u32 rtw8852a_bb_cal_txpwr_ref(struct rtw89_dev *rtwdev, 1367 enum rtw89_phy_idx phy_idx, s16 ref) 1368 { 1369 s8 ofst_int = 0; 1370 u8 base_cw_0db = 0x27; 1371 u16 tssi_16dbm_cw = 0x12c; 1372 s16 pwr_s10_3 = 0; 1373 s16 rf_pwr_cw = 0; 1374 u16 bb_pwr_cw = 0; 1375 u32 pwr_cw = 0; 1376 u32 tssi_ofst_cw = 0; 1377 1378 pwr_s10_3 = (ref << 1) + (s16)(ofst_int) + (s16)(base_cw_0db << 3); 1379 bb_pwr_cw = FIELD_GET(GENMASK(2, 0), pwr_s10_3); 1380 rf_pwr_cw = FIELD_GET(GENMASK(8, 3), pwr_s10_3); 1381 rf_pwr_cw = clamp_t(s16, rf_pwr_cw, 15, 63); 1382 pwr_cw = (rf_pwr_cw << 3) | bb_pwr_cw; 1383 1384 tssi_ofst_cw = (u32)((s16)tssi_16dbm_cw + (ref << 1) - (16 << 3)); 1385 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1386 "[TXPWR] tssi_ofst_cw=%d rf_cw=0x%x bb_cw=0x%x\n", 1387 tssi_ofst_cw, rf_pwr_cw, bb_pwr_cw); 1388 1389 return (tssi_ofst_cw << 18) | (pwr_cw << 9) | (ref & GENMASK(8, 0)); 1390 } 1391 1392 static 1393 void rtw8852a_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 1394 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 1395 { 1396 s8 val_1t = 0; 1397 s8 val_2t = 0; 1398 u32 reg; 1399 1400 if (pw_ofst < -16 || pw_ofst > 15) { 1401 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Err pwr_offset=%d\n", 1402 pw_ofst); 1403 return; 1404 } 1405 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_CTRL, mac_idx); 1406 rtw89_write32_set(rtwdev, reg, B_AX_PWR_UL_TB_CTRL_EN); 1407 val_1t = pw_ofst; 1408 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, mac_idx); 1409 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_MASK, val_1t); 1410 val_2t = max(val_1t - 3, -16); 1411 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, mac_idx); 1412 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_MASK, val_2t); 1413 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[ULTB] Set TB pwr_offset=(%d, %d)\n", 1414 val_1t, val_2t); 1415 } 1416 1417 static void rtw8852a_set_txpwr_ref(struct rtw89_dev *rtwdev, 1418 enum rtw89_phy_idx phy_idx) 1419 { 1420 static const u32 addr[RF_PATH_NUM_8852A] = {0x5800, 0x7800}; 1421 const u32 mask = 0x7FFFFFF; 1422 const u8 ofst_ofdm = 0x4; 1423 const u8 ofst_cck = 0x8; 1424 s16 ref_ofdm = 0; 1425 s16 ref_cck = 0; 1426 u32 val; 1427 u8 i; 1428 1429 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr reference\n"); 1430 1431 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_CTRL, 1432 GENMASK(27, 10), 0x0); 1433 1434 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb ofdm txpwr ref\n"); 1435 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_ofdm); 1436 1437 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1438 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_ofdm, mask, val, 1439 phy_idx); 1440 1441 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set bb cck txpwr ref\n"); 1442 val = rtw8852a_bb_cal_txpwr_ref(rtwdev, phy_idx, ref_cck); 1443 1444 for (i = 0; i < RF_PATH_NUM_8852A; i++) 1445 rtw89_phy_write32_idx(rtwdev, addr[i] + ofst_cck, mask, val, 1446 phy_idx); 1447 } 1448 1449 static void rtw8852a_set_txpwr(struct rtw89_dev *rtwdev, 1450 const struct rtw89_chan *chan, 1451 enum rtw89_phy_idx phy_idx) 1452 { 1453 rtw89_phy_set_txpwr_byrate(rtwdev, chan, phy_idx); 1454 rtw89_phy_set_txpwr_offset(rtwdev, chan, phy_idx); 1455 rtw89_phy_set_txpwr_limit(rtwdev, chan, phy_idx); 1456 rtw89_phy_set_txpwr_limit_ru(rtwdev, chan, phy_idx); 1457 } 1458 1459 static void rtw8852a_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 1460 enum rtw89_phy_idx phy_idx) 1461 { 1462 rtw8852a_set_txpwr_ref(rtwdev, phy_idx); 1463 } 1464 1465 static int 1466 rtw8852a_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 1467 { 1468 int ret; 1469 1470 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL2, 0x07763333); 1471 if (ret) 1472 return ret; 1473 1474 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_COEXT_CTRL, 0x01ebf004); 1475 if (ret) 1476 return ret; 1477 1478 ret = rtw89_mac_txpwr_write32(rtwdev, phy_idx, R_AX_PWR_UL_CTRL0, 0x0002f8ff); 1479 if (ret) 1480 return ret; 1481 1482 return 0; 1483 } 1484 1485 void rtw8852a_bb_set_plcp_tx(struct rtw89_dev *rtwdev) 1486 { 1487 u8 i = 0; 1488 u32 addr, val; 1489 1490 for (i = 0; i < ARRAY_SIZE(rtw8852a_pmac_ht20_mcs7_tbl); i++) { 1491 addr = rtw8852a_pmac_ht20_mcs7_tbl[i].addr; 1492 val = rtw8852a_pmac_ht20_mcs7_tbl[i].data; 1493 rtw89_phy_write32(rtwdev, addr, val); 1494 } 1495 } 1496 1497 static void rtw8852a_stop_pmac_tx(struct rtw89_dev *rtwdev, 1498 struct rtw8852a_bb_pmac_info *tx_info, 1499 enum rtw89_phy_idx idx) 1500 { 1501 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Stop Tx"); 1502 if (tx_info->mode == CONT_TX) 1503 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 0, 1504 idx); 1505 else if (tx_info->mode == PKTS_TX) 1506 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 0, 1507 idx); 1508 } 1509 1510 static void rtw8852a_start_pmac_tx(struct rtw89_dev *rtwdev, 1511 struct rtw8852a_bb_pmac_info *tx_info, 1512 enum rtw89_phy_idx idx) 1513 { 1514 enum rtw8852a_pmac_mode mode = tx_info->mode; 1515 u32 pkt_cnt = tx_info->tx_cnt; 1516 u16 period = tx_info->period; 1517 1518 if (mode == CONT_TX && !tx_info->is_cck) { 1519 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_CTX_EN, 1, 1520 idx); 1521 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CTx Start"); 1522 } else if (mode == PKTS_TX) { 1523 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, B_PMAC_PTX_EN, 1, 1524 idx); 1525 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_PRD, 1526 B_PMAC_TX_PRD_MSK, period, idx); 1527 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CNT, B_PMAC_TX_CNT_MSK, 1528 pkt_cnt, idx); 1529 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC PTx Start"); 1530 } 1531 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 1, idx); 1532 rtw89_phy_write32_idx(rtwdev, R_PMAC_TX_CTRL, B_PMAC_TXEN_DIS, 0, idx); 1533 } 1534 1535 void rtw8852a_bb_set_pmac_tx(struct rtw89_dev *rtwdev, 1536 struct rtw8852a_bb_pmac_info *tx_info, 1537 enum rtw89_phy_idx idx) 1538 { 1539 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 1540 1541 if (!tx_info->en_pmac_tx) { 1542 rtw8852a_stop_pmac_tx(rtwdev, tx_info, idx); 1543 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0, idx); 1544 if (chan->band_type == RTW89_BAND_2G) 1545 rtw89_phy_write32_clr(rtwdev, R_RXCCA, B_RXCCA_DIS); 1546 return; 1547 } 1548 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC Tx Enable"); 1549 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 1, idx); 1550 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 1, idx); 1551 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0x3f, 1552 idx); 1553 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, idx); 1554 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 1, idx); 1555 rtw89_phy_write32_set(rtwdev, R_RXCCA, B_RXCCA_DIS); 1556 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 1, idx); 1557 rtw8852a_start_pmac_tx(rtwdev, tx_info, idx); 1558 } 1559 1560 void rtw8852a_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, 1561 u16 tx_cnt, u16 period, u16 tx_time, 1562 enum rtw89_phy_idx idx) 1563 { 1564 struct rtw8852a_bb_pmac_info tx_info = {0}; 1565 1566 tx_info.en_pmac_tx = enable; 1567 tx_info.is_cck = 0; 1568 tx_info.mode = PKTS_TX; 1569 tx_info.tx_cnt = tx_cnt; 1570 tx_info.period = period; 1571 tx_info.tx_time = tx_time; 1572 rtw8852a_bb_set_pmac_tx(rtwdev, &tx_info, idx); 1573 } 1574 1575 void rtw8852a_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, 1576 enum rtw89_phy_idx idx) 1577 { 1578 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx PWR = %d", pwr_dbm); 1579 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 1, idx); 1580 rtw89_phy_write32_idx(rtwdev, R_TXPWR, B_TXPWR_MSK, pwr_dbm, idx); 1581 } 1582 1583 void rtw8852a_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path) 1584 { 1585 u32 rst_mask0 = 0; 1586 u32 rst_mask1 = 0; 1587 1588 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_0); 1589 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 7, RTW89_PHY_1); 1590 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "PMAC CFG Tx Path = %d", tx_path); 1591 if (!rtwdev->dbcc_en) { 1592 if (tx_path == RF_PATH_A) { 1593 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1594 B_TXPATH_SEL_MSK, 1); 1595 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1596 B_TXNSS_MAP_MSK, 0); 1597 } else if (tx_path == RF_PATH_B) { 1598 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1599 B_TXPATH_SEL_MSK, 2); 1600 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1601 B_TXNSS_MAP_MSK, 0); 1602 } else if (tx_path == RF_PATH_AB) { 1603 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, 1604 B_TXPATH_SEL_MSK, 3); 1605 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, 1606 B_TXNSS_MAP_MSK, 4); 1607 } else { 1608 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Error Tx Path"); 1609 } 1610 } else { 1611 rtw89_phy_write32_mask(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 1612 1); 1613 rtw89_phy_write32_idx(rtwdev, R_TXPATH_SEL, B_TXPATH_SEL_MSK, 2, 1614 RTW89_PHY_1); 1615 rtw89_phy_write32_mask(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 1616 0); 1617 rtw89_phy_write32_idx(rtwdev, R_TXNSS_MAP, B_TXNSS_MAP_MSK, 4, 1618 RTW89_PHY_1); 1619 } 1620 rst_mask0 = B_P0_TXPW_RSTB_MANON | B_P0_TXPW_RSTB_TSSI; 1621 rst_mask1 = B_P1_TXPW_RSTB_MANON | B_P1_TXPW_RSTB_TSSI; 1622 if (tx_path == RF_PATH_A) { 1623 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 1); 1624 rtw89_phy_write32_mask(rtwdev, R_P0_TXPW_RSTB, rst_mask0, 3); 1625 } else { 1626 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 1); 1627 rtw89_phy_write32_mask(rtwdev, R_P1_TXPW_RSTB, rst_mask1, 3); 1628 } 1629 } 1630 1631 void rtw8852a_bb_tx_mode_switch(struct rtw89_dev *rtwdev, 1632 enum rtw89_phy_idx idx, u8 mode) 1633 { 1634 if (mode != 0) 1635 return; 1636 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "Tx mode switch"); 1637 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_TXEN, 0, idx); 1638 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_RXEN, 0, idx); 1639 rtw89_phy_write32_idx(rtwdev, R_PMAC_RX_CFG1, B_PMAC_OPT1_MSK, 0, idx); 1640 rtw89_phy_write32_idx(rtwdev, R_PMAC_RXMOD, B_PMAC_RXMOD_MSK, 0, idx); 1641 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_DPD_EN, 0, idx); 1642 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_MOD, 0, idx); 1643 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL_PWR_EN, 0, idx); 1644 } 1645 1646 static void rtw8852a_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 1647 enum rtw89_phy_idx phy_idx) 1648 { 1649 rtw89_phy_write_reg3_tbl(rtwdev, en ? &rtw8852a_btc_preagc_en_defs_tbl : 1650 &rtw8852a_btc_preagc_dis_defs_tbl); 1651 } 1652 1653 static u8 rtw8852a_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 1654 { 1655 if (rtwdev->is_tssi_mode[rf_path]) { 1656 u32 addr = 0x1c10 + (rf_path << 13); 1657 1658 return (u8)rtw89_phy_read32_mask(rtwdev, addr, 0x3F000000); 1659 } 1660 1661 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1662 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); 1663 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); 1664 1665 fsleep(200); 1666 1667 return (u8)rtw89_read_rf(rtwdev, rf_path, RR_TM, RR_TM_VAL); 1668 } 1669 1670 static void rtw8852a_btc_set_rfe(struct rtw89_dev *rtwdev) 1671 { 1672 const struct rtw89_btc_ver *ver = rtwdev->btc.ver; 1673 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; 1674 1675 if (ver->fcxinit == 7) { 1676 md->md_v7.rfe_type = rtwdev->efuse.rfe_type; 1677 md->md_v7.kt_ver = rtwdev->hal.cv; 1678 md->md_v7.bt_solo = 0; 1679 md->md_v7.switch_type = BTC_SWITCH_INTERNAL; 1680 1681 if (md->md_v7.rfe_type > 0) 1682 md->md_v7.ant.num = (md->md_v7.rfe_type % 2 ? 2 : 3); 1683 else 1684 md->md_v7.ant.num = 2; 1685 1686 md->md_v7.ant.diversity = 0; 1687 md->md_v7.ant.isolation = 10; 1688 1689 if (md->md_v7.ant.num == 3) { 1690 md->md_v7.ant.type = BTC_ANT_DEDICATED; 1691 md->md_v7.bt_pos = BTC_BT_ALONE; 1692 } else { 1693 md->md_v7.ant.type = BTC_ANT_SHARED; 1694 md->md_v7.bt_pos = BTC_BT_BTG; 1695 } 1696 rtwdev->btc.btg_pos = md->md_v7.ant.btg_pos; 1697 rtwdev->btc.ant_type = md->md_v7.ant.type; 1698 } else { 1699 md->md.rfe_type = rtwdev->efuse.rfe_type; 1700 md->md.cv = rtwdev->hal.cv; 1701 md->md.bt_solo = 0; 1702 md->md.switch_type = BTC_SWITCH_INTERNAL; 1703 1704 if (md->md.rfe_type > 0) 1705 md->md.ant.num = (md->md.rfe_type % 2 ? 2 : 3); 1706 else 1707 md->md.ant.num = 2; 1708 1709 md->md.ant.diversity = 0; 1710 md->md.ant.isolation = 10; 1711 1712 if (md->md.ant.num == 3) { 1713 md->md.ant.type = BTC_ANT_DEDICATED; 1714 md->md.bt_pos = BTC_BT_ALONE; 1715 } else { 1716 md->md.ant.type = BTC_ANT_SHARED; 1717 md->md.bt_pos = BTC_BT_BTG; 1718 } 1719 rtwdev->btc.btg_pos = md->md.ant.btg_pos; 1720 rtwdev->btc.ant_type = md->md.ant.type; 1721 } 1722 } 1723 1724 static 1725 void rtw8852a_set_trx_mask(struct rtw89_dev *rtwdev, u8 path, u8 group, u32 val) 1726 { 1727 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x20000); 1728 rtw89_write_rf(rtwdev, path, RR_LUTWA, 0xfffff, group); 1729 rtw89_write_rf(rtwdev, path, RR_LUTWD0, 0xfffff, val); 1730 rtw89_write_rf(rtwdev, path, RR_LUTWE, 0xfffff, 0x0); 1731 } 1732 1733 static void rtw8852a_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 1734 enum rtw89_phy_idx phy_idx) 1735 { 1736 if (en) { 1737 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x1); 1738 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x3); 1739 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0); 1740 } else { 1741 rtw89_phy_write32_mask(rtwdev, R_PATH0_BTG, B_PATH0_BTG_SHEN, 0x0); 1742 rtw89_phy_write32_mask(rtwdev, R_PATH1_BTG, B_PATH1_BTG_SHEN, 0x0); 1743 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xf); 1744 rtw89_phy_write32_mask(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P2, 0x4); 1745 } 1746 } 1747 1748 static void rtw8852a_btc_init_cfg(struct rtw89_dev *rtwdev) 1749 { 1750 struct rtw89_btc *btc = &rtwdev->btc; 1751 const struct rtw89_chip_info *chip = rtwdev->chip; 1752 const struct rtw89_mac_ax_coex coex_params = { 1753 .pta_mode = RTW89_MAC_AX_COEX_RTK_MODE, 1754 .direction = RTW89_MAC_AX_COEX_INNER, 1755 }; 1756 1757 /* PTA init */ 1758 rtw89_mac_coex_init(rtwdev, &coex_params); 1759 1760 /* set WL Tx response = Hi-Pri */ 1761 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_TX_RESP, true); 1762 chip->ops->btc_set_wl_pri(rtwdev, BTC_PRI_MASK_BEACON, true); 1763 1764 /* set rf gnt debug off */ 1765 rtw89_write_rf(rtwdev, RF_PATH_A, RR_WLSEL, 0xfffff, 0x0); 1766 rtw89_write_rf(rtwdev, RF_PATH_B, RR_WLSEL, 0xfffff, 0x0); 1767 1768 /* set WL Tx thru in TRX mask table if GNT_WL = 0 && BT_S1 = ss group */ 1769 if (btc->ant_type == BTC_ANT_SHARED) { 1770 rtw8852a_set_trx_mask(rtwdev, 1771 RF_PATH_A, BTC_BT_SS_GROUP, 0x5ff); 1772 rtw8852a_set_trx_mask(rtwdev, 1773 RF_PATH_B, BTC_BT_SS_GROUP, 0x5ff); 1774 /* set path-A(S0) Tx/Rx no-mask if GNT_WL=0 && BT_S1=tx group */ 1775 rtw8852a_set_trx_mask(rtwdev, 1776 RF_PATH_A, BTC_BT_TX_GROUP, 0x5ff); 1777 } else { /* set WL Tx stb if GNT_WL = 0 && BT_S1 = ss group for 3-ant */ 1778 rtw8852a_set_trx_mask(rtwdev, 1779 RF_PATH_A, BTC_BT_SS_GROUP, 0x5df); 1780 rtw8852a_set_trx_mask(rtwdev, 1781 RF_PATH_B, BTC_BT_SS_GROUP, 0x5df); 1782 } 1783 1784 /* set PTA break table */ 1785 rtw89_write32(rtwdev, R_BTC_BREAK_TABLE, BTC_BREAK_PARAM); 1786 1787 /* enable BT counter 0xda40[16,2] = 2b'11 */ 1788 rtw89_write32_set(rtwdev, 1789 R_AX_CSR_MODE, B_AX_BT_CNT_RST | B_AX_STATIS_BT_EN); 1790 btc->cx.wl.status.map.init_ok = true; 1791 } 1792 1793 static 1794 void rtw8852a_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 1795 { 1796 u32 bitmap = 0; 1797 u32 reg = 0; 1798 1799 switch (map) { 1800 case BTC_PRI_MASK_TX_RESP: 1801 reg = R_BTC_BT_COEX_MSK_TABLE; 1802 bitmap = B_BTC_PRI_MASK_TX_RESP_V1; 1803 break; 1804 case BTC_PRI_MASK_BEACON: 1805 reg = R_AX_WL_PRI_MSK; 1806 bitmap = B_AX_PTA_WL_PRI_MASK_BCNQ; 1807 break; 1808 default: 1809 return; 1810 } 1811 1812 if (state) 1813 rtw89_write32_set(rtwdev, reg, bitmap); 1814 else 1815 rtw89_write32_clr(rtwdev, reg, bitmap); 1816 } 1817 1818 static inline u32 __btc_ctrl_val_all_time(u32 ctrl) 1819 { 1820 return FIELD_GET(GENMASK(15, 0), ctrl); 1821 } 1822 1823 static inline u32 __btc_ctrl_rst_all_time(u32 cur) 1824 { 1825 return cur & ~B_AX_FORCE_PWR_BY_RATE_EN; 1826 } 1827 1828 static inline u32 __btc_ctrl_gen_all_time(u32 cur, u32 val) 1829 { 1830 u32 hv = cur & ~B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1831 u32 lv = val & B_AX_FORCE_PWR_BY_RATE_VALUE_MASK; 1832 1833 return hv | lv | B_AX_FORCE_PWR_BY_RATE_EN; 1834 } 1835 1836 static inline u32 __btc_ctrl_val_gnt_bt(u32 ctrl) 1837 { 1838 return FIELD_GET(GENMASK(31, 16), ctrl); 1839 } 1840 1841 static inline u32 __btc_ctrl_rst_gnt_bt(u32 cur) 1842 { 1843 return cur & ~B_AX_TXAGC_BT_EN; 1844 } 1845 1846 static inline u32 __btc_ctrl_gen_gnt_bt(u32 cur, u32 val) 1847 { 1848 u32 ov = cur & ~B_AX_TXAGC_BT_MASK; 1849 u32 iv = FIELD_PREP(B_AX_TXAGC_BT_MASK, val); 1850 1851 return ov | iv | B_AX_TXAGC_BT_EN; 1852 } 1853 1854 static void 1855 rtw8852a_btc_set_wl_txpwr_ctrl(struct rtw89_dev *rtwdev, u32 txpwr_val) 1856 { 1857 const u32 __btc_cr_all_time = R_AX_PWR_RATE_CTRL; 1858 const u32 __btc_cr_gnt_bt = R_AX_PWR_COEXT_CTRL; 1859 1860 #define __do_clr(_chk) ((_chk) == GENMASK(15, 0)) 1861 #define __handle(_case) \ 1862 do { \ 1863 const u32 _reg = __btc_cr_ ## _case; \ 1864 u32 _val = __btc_ctrl_val_ ## _case(txpwr_val); \ 1865 u32 _cur, _wrt; \ 1866 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1867 "btc ctrl %s: 0x%x\n", #_case, _val); \ 1868 if (rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, _reg, &_cur))\ 1869 break; \ 1870 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1871 "btc ctrl ori 0x%x: 0x%x\n", _reg, _cur); \ 1872 _wrt = __do_clr(_val) ? \ 1873 __btc_ctrl_rst_ ## _case(_cur) : \ 1874 __btc_ctrl_gen_ ## _case(_cur, _val); \ 1875 rtw89_mac_txpwr_write32(rtwdev, RTW89_PHY_0, _reg, _wrt);\ 1876 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, \ 1877 "btc ctrl set 0x%x: 0x%x\n", _reg, _wrt); \ 1878 } while (0) 1879 1880 __handle(all_time); 1881 __handle(gnt_bt); 1882 1883 #undef __handle 1884 #undef __do_clr 1885 } 1886 1887 static 1888 s8 rtw8852a_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 1889 { 1890 /* +6 for compensate offset */ 1891 return clamp_t(s8, val + 6, -100, 0) + 100; 1892 } 1893 1894 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_ul[] = { 1895 {255, 0, 0, 7}, /* 0 -> original */ 1896 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */ 1897 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 1898 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 1899 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 1900 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 1901 {6, 1, 0, 7}, 1902 {13, 1, 0, 7}, 1903 {13, 1, 0, 7} 1904 }; 1905 1906 static struct rtw89_btc_rf_trx_para rtw89_btc_8852a_rf_dl[] = { 1907 {255, 0, 0, 7}, /* 0 -> original */ 1908 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */ 1909 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */ 1910 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */ 1911 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */ 1912 {255, 0, 0, 7}, /* the below id is for non-shared-antenna free-run */ 1913 {255, 1, 0, 7}, 1914 {255, 1, 0, 7}, 1915 {255, 1, 0, 7} 1916 }; 1917 1918 static const 1919 u8 rtw89_btc_8852a_wl_rssi_thres[BTC_WL_RSSI_THMAX] = {60, 50, 40, 30}; 1920 static const 1921 u8 rtw89_btc_8852a_bt_rssi_thres[BTC_BT_RSSI_THMAX] = {40, 36, 31, 28}; 1922 1923 static struct rtw89_btc_fbtc_mreg rtw89_btc_8852a_mon_reg[] = { 1924 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda24), 1925 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda28), 1926 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda2c), 1927 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda30), 1928 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda4c), 1929 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda10), 1930 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda20), 1931 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xda34), 1932 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xcef4), 1933 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x8424), 1934 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980), 1935 RTW89_DEF_FBTC_MREG(REG_BT_MODEM, 4, 0x178), 1936 }; 1937 1938 static 1939 void rtw8852a_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 1940 { 1941 struct rtw89_btc *btc = &rtwdev->btc; 1942 const struct rtw89_btc_ver *ver = btc->ver; 1943 struct rtw89_btc_cx *cx = &btc->cx; 1944 u32 val; 1945 1946 if (ver->fcxbtcrpt != 1) 1947 return; 1948 1949 val = rtw89_read32(rtwdev, R_AX_BT_STAST_HIGH); 1950 cx->cnt_bt[BTC_BCNT_HIPRI_TX] = FIELD_GET(B_AX_STATIS_BT_HI_TX_MASK, val); 1951 cx->cnt_bt[BTC_BCNT_HIPRI_RX] = FIELD_GET(B_AX_STATIS_BT_HI_RX_MASK, val); 1952 1953 val = rtw89_read32(rtwdev, R_AX_BT_STAST_LOW); 1954 cx->cnt_bt[BTC_BCNT_LOPRI_TX] = FIELD_GET(B_AX_STATIS_BT_LO_TX_1_MASK, val); 1955 cx->cnt_bt[BTC_BCNT_LOPRI_RX] = FIELD_GET(B_AX_STATIS_BT_LO_RX_1_MASK, val); 1956 1957 /* clock-gate off before reset counter*/ 1958 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 1959 rtw89_write32_clr(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 1960 rtw89_write32_set(rtwdev, R_AX_CSR_MODE, B_AX_BT_CNT_RST); 1961 rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_DIS_BTC_CLK_G); 1962 } 1963 1964 static 1965 void rtw8852a_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 1966 { 1967 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); 1968 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); 1969 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x1); 1970 1971 /* set WL standby = Rx for GNT_BT_Tx = 1->0 settle issue */ 1972 if (state) 1973 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 1974 RFREG_MASK, 0xa2d7c); 1975 else 1976 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, 1977 RFREG_MASK, 0xa2020); 1978 1979 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 1980 } 1981 1982 static void rtw8852a_set_wl_lna2(struct rtw89_dev *rtwdev, u8 level) 1983 { 1984 /* level=0 Default: TIA 1/0= (LNA2,TIAN6) = (7,1)/(5,1) = 21dB/12dB 1985 * level=1 Fix LNA2=5: TIA 1/0= (LNA2,TIAN6) = (5,0)/(5,1) = 18dB/12dB 1986 * To improve BT ACI in co-rx 1987 */ 1988 1989 switch (level) { 1990 case 0: /* default */ 1991 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 1992 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 1993 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x17); 1994 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 1995 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 1996 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 1997 break; 1998 case 1: /* Fix LNA2=5 */ 1999 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x1000); 2000 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x3); 2001 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x5); 2002 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x2); 2003 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x15); 2004 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x0); 2005 break; 2006 } 2007 } 2008 2009 static void rtw8852a_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 2010 { 2011 struct rtw89_btc *btc = &rtwdev->btc; 2012 2013 switch (level) { 2014 case 0: /* original */ 2015 default: 2016 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 2017 btc->dm.wl_lna2 = 0; 2018 break; 2019 case 1: /* for FDD free-run */ 2020 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, true, RTW89_PHY_0); 2021 btc->dm.wl_lna2 = 0; 2022 break; 2023 case 2: /* for BTG Co-Rx*/ 2024 rtw8852a_ctrl_nbtg_bt_tx(rtwdev, false, RTW89_PHY_0); 2025 btc->dm.wl_lna2 = 1; 2026 break; 2027 } 2028 2029 rtw8852a_set_wl_lna2(rtwdev, btc->dm.wl_lna2); 2030 } 2031 2032 static void rtw8852a_fill_freq_with_ppdu(struct rtw89_dev *rtwdev, 2033 struct rtw89_rx_phy_ppdu *phy_ppdu, 2034 struct ieee80211_rx_status *status) 2035 { 2036 u16 chan = phy_ppdu->chan_idx; 2037 u8 band; 2038 2039 if (chan == 0) 2040 return; 2041 2042 band = chan <= 14 ? NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 2043 status->freq = ieee80211_channel_to_frequency(chan, band); 2044 status->band = band; 2045 } 2046 2047 static void rtw8852a_query_ppdu(struct rtw89_dev *rtwdev, 2048 struct rtw89_rx_phy_ppdu *phy_ppdu, 2049 struct ieee80211_rx_status *status) 2050 { 2051 u8 path; 2052 u8 *rx_power = phy_ppdu->rssi; 2053 2054 status->signal = RTW89_RSSI_RAW_TO_DBM(max(rx_power[RF_PATH_A], rx_power[RF_PATH_B])); 2055 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { 2056 status->chains |= BIT(path); 2057 status->chain_signal[path] = RTW89_RSSI_RAW_TO_DBM(rx_power[path]); 2058 } 2059 if (phy_ppdu->valid) 2060 rtw8852a_fill_freq_with_ppdu(rtwdev, phy_ppdu, status); 2061 } 2062 2063 #ifdef CONFIG_PM 2064 static const struct wiphy_wowlan_support rtw_wowlan_stub_8852a = { 2065 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_DISCONNECT, 2066 .n_patterns = RTW89_MAX_PATTERN_NUM, 2067 .pattern_max_len = RTW89_MAX_PATTERN_SIZE, 2068 .pattern_min_len = 1, 2069 }; 2070 #endif 2071 2072 static const struct rtw89_chip_ops rtw8852a_chip_ops = { 2073 .enable_bb_rf = rtw89_mac_enable_bb_rf, 2074 .disable_bb_rf = rtw89_mac_disable_bb_rf, 2075 .bb_preinit = NULL, 2076 .bb_postinit = NULL, 2077 .bb_reset = rtw8852a_bb_reset, 2078 .bb_sethw = rtw8852a_bb_sethw, 2079 .read_rf = rtw89_phy_read_rf, 2080 .write_rf = rtw89_phy_write_rf, 2081 .set_channel = rtw8852a_set_channel, 2082 .set_channel_help = rtw8852a_set_channel_help, 2083 .read_efuse = rtw8852a_read_efuse, 2084 .read_phycap = rtw8852a_read_phycap, 2085 .fem_setup = rtw8852a_fem_setup, 2086 .rfe_gpio = NULL, 2087 .rfk_hw_init = NULL, 2088 .rfk_init = rtw8852a_rfk_init, 2089 .rfk_init_late = NULL, 2090 .rfk_channel = rtw8852a_rfk_channel, 2091 .rfk_band_changed = rtw8852a_rfk_band_changed, 2092 .rfk_scan = rtw8852a_rfk_scan, 2093 .rfk_track = rtw8852a_rfk_track, 2094 .power_trim = rtw8852a_power_trim, 2095 .set_txpwr = rtw8852a_set_txpwr, 2096 .set_txpwr_ctrl = rtw8852a_set_txpwr_ctrl, 2097 .init_txpwr_unit = rtw8852a_init_txpwr_unit, 2098 .get_thermal = rtw8852a_get_thermal, 2099 .ctrl_btg_bt_rx = rtw8852a_ctrl_btg_bt_rx, 2100 .query_ppdu = rtw8852a_query_ppdu, 2101 .ctrl_nbtg_bt_tx = rtw8852a_ctrl_nbtg_bt_tx, 2102 .cfg_txrx_path = NULL, 2103 .set_txpwr_ul_tb_offset = rtw8852a_set_txpwr_ul_tb_offset, 2104 .pwr_on_func = NULL, 2105 .pwr_off_func = NULL, 2106 .query_rxdesc = rtw89_core_query_rxdesc, 2107 .fill_txdesc = rtw89_core_fill_txdesc, 2108 .fill_txdesc_fwcmd = rtw89_core_fill_txdesc, 2109 .cfg_ctrl_path = rtw89_mac_cfg_ctrl_path, 2110 .mac_cfg_gnt = rtw89_mac_cfg_gnt, 2111 .stop_sch_tx = rtw89_mac_stop_sch_tx, 2112 .resume_sch_tx = rtw89_mac_resume_sch_tx, 2113 .h2c_dctl_sec_cam = NULL, 2114 .h2c_default_cmac_tbl = rtw89_fw_h2c_default_cmac_tbl, 2115 .h2c_assoc_cmac_tbl = rtw89_fw_h2c_assoc_cmac_tbl, 2116 .h2c_ampdu_cmac_tbl = NULL, 2117 .h2c_default_dmac_tbl = NULL, 2118 .h2c_update_beacon = rtw89_fw_h2c_update_beacon, 2119 .h2c_ba_cam = rtw89_fw_h2c_ba_cam, 2120 2121 .btc_set_rfe = rtw8852a_btc_set_rfe, 2122 .btc_init_cfg = rtw8852a_btc_init_cfg, 2123 .btc_set_wl_pri = rtw8852a_btc_set_wl_pri, 2124 .btc_set_wl_txpwr_ctrl = rtw8852a_btc_set_wl_txpwr_ctrl, 2125 .btc_get_bt_rssi = rtw8852a_btc_get_bt_rssi, 2126 .btc_update_bt_cnt = rtw8852a_btc_update_bt_cnt, 2127 .btc_wl_s1_standby = rtw8852a_btc_wl_s1_standby, 2128 .btc_set_wl_rx_gain = rtw8852a_btc_set_wl_rx_gain, 2129 .btc_set_policy = rtw89_btc_set_policy, 2130 }; 2131 2132 const struct rtw89_chip_info rtw8852a_chip_info = { 2133 .chip_id = RTL8852A, 2134 .chip_gen = RTW89_CHIP_AX, 2135 .ops = &rtw8852a_chip_ops, 2136 .mac_def = &rtw89_mac_gen_ax, 2137 .phy_def = &rtw89_phy_gen_ax, 2138 .fw_basename = RTW8852A_FW_BASENAME, 2139 .fw_format_max = RTW8852A_FW_FORMAT_MAX, 2140 .try_ce_fw = false, 2141 .bbmcu_nr = 0, 2142 .needed_fw_elms = 0, 2143 .fifo_size = 458752, 2144 .small_fifo_size = false, 2145 .dle_scc_rsvd_size = 0, 2146 .max_amsdu_limit = 3500, 2147 .dis_2g_40m_ul_ofdma = true, 2148 .rsvd_ple_ofst = 0x6f800, 2149 .hfc_param_ini = rtw8852a_hfc_param_ini_pcie, 2150 .dle_mem = rtw8852a_dle_mem_pcie, 2151 .wde_qempty_acq_grpnum = 16, 2152 .wde_qempty_mgq_grpsel = 16, 2153 .rf_base_addr = {0xc000, 0xd000}, 2154 .pwr_on_seq = pwr_on_seq_8852a, 2155 .pwr_off_seq = pwr_off_seq_8852a, 2156 .bb_table = &rtw89_8852a_phy_bb_table, 2157 .bb_gain_table = NULL, 2158 .rf_table = {&rtw89_8852a_phy_radioa_table, 2159 &rtw89_8852a_phy_radiob_table,}, 2160 .nctl_table = &rtw89_8852a_phy_nctl_table, 2161 .nctl_post_table = NULL, 2162 .dflt_parms = &rtw89_8852a_dflt_parms, 2163 .rfe_parms_conf = NULL, 2164 .txpwr_factor_rf = 2, 2165 .txpwr_factor_mac = 1, 2166 .dig_table = &rtw89_8852a_phy_dig_table, 2167 .dig_regs = &rtw8852a_dig_regs, 2168 .tssi_dbw_table = NULL, 2169 .support_macid_num = RTW89_MAX_MAC_ID_NUM, 2170 .support_chanctx_num = 1, 2171 .support_rnr = false, 2172 .support_bands = BIT(NL80211_BAND_2GHZ) | 2173 BIT(NL80211_BAND_5GHZ), 2174 .support_bandwidths = BIT(NL80211_CHAN_WIDTH_20) | 2175 BIT(NL80211_CHAN_WIDTH_40) | 2176 BIT(NL80211_CHAN_WIDTH_80), 2177 .support_unii4 = false, 2178 .ul_tb_waveform_ctrl = false, 2179 .ul_tb_pwr_diff = false, 2180 .hw_sec_hdr = false, 2181 .rf_path_num = 2, 2182 .tx_nss = 2, 2183 .rx_nss = 2, 2184 .acam_num = 128, 2185 .bcam_num = 10, 2186 .scam_num = 128, 2187 .bacam_num = 2, 2188 .bacam_dynamic_num = 4, 2189 .bacam_ver = RTW89_BACAM_V0, 2190 .ppdu_max_usr = 4, 2191 .sec_ctrl_efuse_size = 4, 2192 .physical_efuse_size = 1216, 2193 .logical_efuse_size = 1536, 2194 .limit_efuse_size = 1152, 2195 .dav_phy_efuse_size = 0, 2196 .dav_log_efuse_size = 0, 2197 .efuse_blocks = NULL, 2198 .phycap_addr = 0x580, 2199 .phycap_size = 128, 2200 .para_ver = 0x0, 2201 .wlcx_desired = 0x06000000, 2202 .btcx_desired = 0x7, 2203 .scbd = 0x1, 2204 .mailbox = 0x1, 2205 2206 .afh_guard_ch = 6, 2207 .wl_rssi_thres = rtw89_btc_8852a_wl_rssi_thres, 2208 .bt_rssi_thres = rtw89_btc_8852a_bt_rssi_thres, 2209 .rssi_tol = 2, 2210 .mon_reg_num = ARRAY_SIZE(rtw89_btc_8852a_mon_reg), 2211 .mon_reg = rtw89_btc_8852a_mon_reg, 2212 .rf_para_ulink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_ul), 2213 .rf_para_ulink = rtw89_btc_8852a_rf_ul, 2214 .rf_para_dlink_num = ARRAY_SIZE(rtw89_btc_8852a_rf_dl), 2215 .rf_para_dlink = rtw89_btc_8852a_rf_dl, 2216 .ps_mode_supported = BIT(RTW89_PS_MODE_RFOFF) | 2217 BIT(RTW89_PS_MODE_CLK_GATED) | 2218 BIT(RTW89_PS_MODE_PWR_GATED), 2219 .low_power_hci_modes = 0, 2220 .h2c_cctl_func_id = H2C_FUNC_MAC_CCTLINFO_UD, 2221 .hci_func_en_addr = R_AX_HCI_FUNC_EN, 2222 .h2c_desc_size = sizeof(struct rtw89_txwd_body), 2223 .txwd_body_size = sizeof(struct rtw89_txwd_body), 2224 .txwd_info_size = sizeof(struct rtw89_txwd_info), 2225 .h2c_ctrl_reg = R_AX_H2CREG_CTRL, 2226 .h2c_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_H2C_DEQ_CNT_MASK >> 8}, 2227 .h2c_regs = rtw8852a_h2c_regs, 2228 .c2h_ctrl_reg = R_AX_C2HREG_CTRL, 2229 .c2h_regs = rtw8852a_c2h_regs, 2230 .c2h_counter_reg = {R_AX_UDM1 + 1, B_AX_UDM1_HALMAC_C2H_ENQ_CNT_MASK >> 8}, 2231 .page_regs = &rtw8852a_page_regs, 2232 .wow_reason_reg = rtw8852a_wow_wakeup_regs, 2233 .cfo_src_fd = false, 2234 .cfo_hw_comp = false, 2235 .dcfo_comp = &rtw8852a_dcfo_comp, 2236 .dcfo_comp_sft = 10, 2237 .imr_info = &rtw8852a_imr_info, 2238 .imr_dmac_table = NULL, 2239 .imr_cmac_table = NULL, 2240 .rrsr_cfgs = &rtw8852a_rrsr_cfgs, 2241 .bss_clr_vld = {R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0}, 2242 .bss_clr_map_reg = R_BSS_CLR_MAP, 2243 .dma_ch_mask = 0, 2244 .edcca_regs = &rtw8852a_edcca_regs, 2245 #ifdef CONFIG_PM 2246 .wowlan_stub = &rtw_wowlan_stub_8852a, 2247 #endif 2248 .xtal_info = &rtw8852a_xtal_info, 2249 }; 2250 EXPORT_SYMBOL(rtw8852a_chip_info); 2251 2252 MODULE_FIRMWARE(RTW8852A_MODULE_FIRMWARE); 2253 MODULE_AUTHOR("Realtek Corporation"); 2254 MODULE_DESCRIPTION("Realtek 802.11ax wireless 8852A driver"); 2255 MODULE_LICENSE("Dual BSD/GPL"); 2256