1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2022-2023 Realtek Corporation 3 */ 4 5 #include "rtw8851b_rfk_table.h" 6 7 static const struct rtw89_reg5_def rtw8851b_dadck_setup_defs[] = { 8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80), 9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80), 10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3), 11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1), 12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f), 13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0), 14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0), 15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1), 16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0), 17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1), 18 RTW89_DECL_RFK_WM(0x030c, 0x0f000000, 0x3), 19 RTW89_DECL_RFK_WM(0xc0f4, BIT(2), 0x0), 20 RTW89_DECL_RFK_WM(0xc0f4, BIT(4), 0x0), 21 RTW89_DECL_RFK_WM(0xc0f4, BIT(11), 0x1), 22 RTW89_DECL_RFK_WM(0xc0f4, BIT(11), 0x0), 23 RTW89_DECL_RFK_DELAY(1), 24 RTW89_DECL_RFK_WM(0xc0f4, 0x300, 0x1), 25 }; 26 27 RTW89_DECLARE_RFK_TBL(rtw8851b_dadck_setup_defs); 28 29 static const struct rtw89_reg5_def rtw8851b_dadck_post_defs[] = { 30 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x1), 31 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x0), 32 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0xc), 33 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x1), 34 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x0), 35 }; 36 37 RTW89_DECLARE_RFK_TBL(rtw8851b_dadck_post_defs); 38 39 static const struct rtw89_reg5_def rtw8851b_dack_s0_1_defs[] = { 40 RTW89_DECL_RFK_WM(0x12a0, BIT(15), 0x1), 41 RTW89_DECL_RFK_WM(0x12a0, 0x7000, 0x3), 42 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1), 43 RTW89_DECL_RFK_WM(0x030c, BIT(28), 0x1), 44 RTW89_DECL_RFK_WM(0x032c, 0x80000000, 0x0), 45 }; 46 47 RTW89_DECLARE_RFK_TBL(rtw8851b_dack_s0_1_defs); 48 49 static const struct rtw89_reg5_def rtw8851b_dack_s0_2_defs[] = { 50 RTW89_DECL_RFK_WM(0xc004, BIT(0), 0x0), 51 RTW89_DECL_RFK_WM(0x12a0, BIT(15), 0x0), 52 RTW89_DECL_RFK_WM(0x12a0, 0x7000, 0x7), 53 }; 54 55 RTW89_DECLARE_RFK_TBL(rtw8851b_dack_s0_2_defs); 56 57 static const struct rtw89_reg5_def rtw8851b_dack_manual_off_defs[] = { 58 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x0), 59 RTW89_DECL_RFK_WM(0xc210, BIT(0), 0x0), 60 RTW89_DECL_RFK_WM(0xc224, BIT(0), 0x0), 61 }; 62 63 RTW89_DECLARE_RFK_TBL(rtw8851b_dack_manual_off_defs); 64 65 static const struct rtw89_reg5_def rtw8851b_iqk_rxclk_80_defs[] = { 66 RTW89_DECL_RFK_WM(0x20fc, 0xffff0000, 0x0101), 67 RTW89_DECL_RFK_WM(0x5670, 0x00002000, 0x1), 68 RTW89_DECL_RFK_WM(0x12a0, 0x00080000, 0x1), 69 RTW89_DECL_RFK_WM(0x12a0, 0x00070000, 0x2), 70 RTW89_DECL_RFK_WM(0x5670, 0x60000000, 0x1), 71 RTW89_DECL_RFK_WM(0xc0d4, 0x00000780, 0x8), 72 RTW89_DECL_RFK_WM(0xc0d4, 0x00007800, 0x2), 73 RTW89_DECL_RFK_WM(0xc0d4, 0x0c000000, 0x2), 74 RTW89_DECL_RFK_WM(0xc0d8, 0x000001e0, 0x5), 75 RTW89_DECL_RFK_WM(0xc0c4, 0x003e0000, 0xf), 76 RTW89_DECL_RFK_WM(0xc0ec, 0x00006000, 0x0), 77 RTW89_DECL_RFK_WM(0x12b8, 0x40000000, 0x1), 78 RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x0f), 79 RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x03), 80 RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0001), 81 RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0041), 82 RTW89_DECL_RFK_WM(0x20fc, 0xffff0000, 0x1101), 83 }; 84 85 RTW89_DECLARE_RFK_TBL(rtw8851b_iqk_rxclk_80_defs); 86 87 static const struct rtw89_reg5_def rtw8851b_iqk_rxclk_others_defs[] = { 88 RTW89_DECL_RFK_WM(0x20fc, 0xffff0000, 0x0101), 89 RTW89_DECL_RFK_WM(0x5670, 0x00002000, 0x1), 90 RTW89_DECL_RFK_WM(0x12a0, 0x00080000, 0x1), 91 RTW89_DECL_RFK_WM(0x12a0, 0x00070000, 0x2), 92 RTW89_DECL_RFK_WM(0x5670, 0x60000000, 0x0), 93 RTW89_DECL_RFK_WM(0xc0d4, 0x00000780, 0x8), 94 RTW89_DECL_RFK_WM(0xc0d4, 0x00007800, 0x2), 95 RTW89_DECL_RFK_WM(0xc0d4, 0x0c000000, 0x2), 96 RTW89_DECL_RFK_WM(0xc0d8, 0x000001e0, 0x5), 97 RTW89_DECL_RFK_WM(0xc0c4, 0x003e0000, 0xf), 98 RTW89_DECL_RFK_WM(0xc0ec, 0x00006000, 0x2), 99 RTW89_DECL_RFK_WM(0x12b8, 0x40000000, 0x1), 100 RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x0f), 101 RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x03), 102 RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0001), 103 RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0041), 104 RTW89_DECL_RFK_WM(0x20fc, 0xffff0000, 0x1101), 105 }; 106 107 RTW89_DECLARE_RFK_TBL(rtw8851b_iqk_rxclk_others_defs); 108 109 static const struct rtw89_reg5_def rtw8851b_iqk_txk_2ghz_defs[] = { 110 RTW89_DECL_RFK_WRF(RF_PATH_A, 0x51, 0x80000, 0x0), 111 RTW89_DECL_RFK_WRF(RF_PATH_A, 0x51, 0x00800, 0x0), 112 RTW89_DECL_RFK_WRF(RF_PATH_A, 0x52, 0x00800, 0x0), 113 RTW89_DECL_RFK_WRF(RF_PATH_A, 0x55, 0x0001f, 0x4), 114 RTW89_DECL_RFK_WRF(RF_PATH_A, 0xef, 0x00004, 0x1), 115 RTW89_DECL_RFK_WRF(RF_PATH_A, 0x00, 0xffff0, 0x403e), 116 RTW89_DECL_RFK_WRF(RF_PATH_A, 0x11, 0x00003, 0x0), 117 RTW89_DECL_RFK_WRF(RF_PATH_A, 0x11, 0x00070, 0x6), 118 RTW89_DECL_RFK_WRF(RF_PATH_A, 0x11, 0x1f000, 0x10), 119 RTW89_DECL_RFK_DELAY(1), 120 }; 121 122 RTW89_DECLARE_RFK_TBL(rtw8851b_iqk_txk_2ghz_defs); 123 124 static const struct rtw89_reg5_def rtw8851b_iqk_txk_5ghz_defs[] = { 125 RTW89_DECL_RFK_WRF(RF_PATH_A, 0x60, 0x00007, 0x0), 126 RTW89_DECL_RFK_WRF(RF_PATH_A, 0x55, 0x0001f, 0x4), 127 RTW89_DECL_RFK_WRF(RF_PATH_A, 0xef, 0x00004, 0x1), 128 RTW89_DECL_RFK_WRF(RF_PATH_A, 0x00, 0xffff0, 0x403e), 129 RTW89_DECL_RFK_WRF(RF_PATH_A, 0x11, 0x00003, 0x0), 130 RTW89_DECL_RFK_WRF(RF_PATH_A, 0x11, 0x00070, 0x7), 131 RTW89_DECL_RFK_WRF(RF_PATH_A, 0x11, 0x1f000, 0x7), 132 RTW89_DECL_RFK_DELAY(1), 133 }; 134 135 RTW89_DECLARE_RFK_TBL(rtw8851b_iqk_txk_5ghz_defs); 136 137 static const struct rtw89_reg5_def rtw8851b_iqk_afebb_restore_defs[] = { 138 RTW89_DECL_RFK_WM(0x12b8, 0x40000000, 0x0), 139 RTW89_DECL_RFK_WM(0x20fc, 0x00010000, 0x1), 140 RTW89_DECL_RFK_WM(0x20fc, 0x00100000, 0x0), 141 RTW89_DECL_RFK_WM(0x20fc, 0x01000000, 0x1), 142 RTW89_DECL_RFK_WM(0x20fc, 0x10000000, 0x0), 143 RTW89_DECL_RFK_WM(0x5670, MASKDWORD, 0x00000000), 144 RTW89_DECL_RFK_WM(0x12a0, 0x000ff000, 0x00), 145 RTW89_DECL_RFK_WM(0x20fc, 0x00010000, 0x0), 146 RTW89_DECL_RFK_WM(0x20fc, 0x01000000, 0x0), 147 RTW89_DECL_RFK_WRF(RF_PATH_A, 0x10005, 0x00001, 0x1), 148 }; 149 150 RTW89_DECLARE_RFK_TBL(rtw8851b_iqk_afebb_restore_defs); 151 152 static const struct rtw89_reg5_def rtw8851b_iqk_macbb_defs[] = { 153 RTW89_DECL_RFK_WRF(RF_PATH_A, 0x10005, 0x00001, 0x0), 154 RTW89_DECL_RFK_WM(0x20fc, 0x00010000, 0x1), 155 RTW89_DECL_RFK_WM(0x20fc, 0x00100000, 0x0), 156 RTW89_DECL_RFK_WM(0x20fc, 0x01000000, 0x1), 157 RTW89_DECL_RFK_WM(0x20fc, 0x10000000, 0x0), 158 RTW89_DECL_RFK_WM(0x5670, MASKDWORD, 0xf801fffd), 159 RTW89_DECL_RFK_WM(0x5670, 0x00004000, 0x1), 160 RTW89_DECL_RFK_WM(0x12a0, 0x00008000, 0x1), 161 RTW89_DECL_RFK_WM(0x5670, 0x80000000, 0x1), 162 RTW89_DECL_RFK_WM(0x12a0, 0x00007000, 0x7), 163 RTW89_DECL_RFK_WM(0x5670, 0x00002000, 0x1), 164 RTW89_DECL_RFK_WM(0x12a0, 0x00080000, 0x1), 165 RTW89_DECL_RFK_WM(0x12a0, 0x00070000, 0x3), 166 RTW89_DECL_RFK_WM(0x5670, 0x60000000, 0x2), 167 RTW89_DECL_RFK_WM(0xc0d4, 0x00000780, 0x9), 168 RTW89_DECL_RFK_WM(0xc0d4, 0x00007800, 0x1), 169 RTW89_DECL_RFK_WM(0xc0d4, 0x0c000000, 0x0), 170 RTW89_DECL_RFK_WM(0xc0d8, 0x000001e0, 0x3), 171 RTW89_DECL_RFK_WM(0xc0c4, 0x003e0000, 0xa), 172 RTW89_DECL_RFK_WM(0xc0ec, 0x00006000, 0x0), 173 RTW89_DECL_RFK_WM(0xc0e8, 0x00000040, 0x1), 174 RTW89_DECL_RFK_WM(0x12b8, 0x40000000, 0x1), 175 RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x1f), 176 RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x13), 177 RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0001), 178 RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0041), 179 RTW89_DECL_RFK_WM(0x20fc, 0x00100000, 0x1), 180 RTW89_DECL_RFK_WM(0x20fc, 0x10000000, 0x1), 181 }; 182 183 RTW89_DECLARE_RFK_TBL(rtw8851b_iqk_macbb_defs); 184 185 static const struct rtw89_reg5_def rtw8851b_iqk_bb_afe_defs[] = { 186 RTW89_DECL_RFK_WM(0x5670, 0x00004000, 0x1), 187 RTW89_DECL_RFK_WM(0x12a0, 0x00008000, 0x1), 188 RTW89_DECL_RFK_WM(0x5670, 0x80000000, 0x1), 189 RTW89_DECL_RFK_WM(0x12a0, 0x00007000, 0x7), 190 RTW89_DECL_RFK_WM(0x5670, 0x00002000, 0x1), 191 RTW89_DECL_RFK_WM(0x12a0, 0x00080000, 0x1), 192 RTW89_DECL_RFK_WM(0x12a0, 0x00070000, 0x3), 193 RTW89_DECL_RFK_WM(0x5670, 0x60000000, 0x2), 194 RTW89_DECL_RFK_WM(0xc0d4, 0x00000780, 0x9), 195 RTW89_DECL_RFK_WM(0xc0d4, 0x00007800, 0x1), 196 RTW89_DECL_RFK_WM(0xc0d4, 0x0c000000, 0x0), 197 RTW89_DECL_RFK_WM(0xc0d8, 0x000001e0, 0x3), 198 RTW89_DECL_RFK_WM(0xc0c4, 0x003e0000, 0xa), 199 RTW89_DECL_RFK_WM(0xc0ec, 0x00006000, 0x0), 200 RTW89_DECL_RFK_WM(0xc0e8, 0x00000040, 0x1), 201 RTW89_DECL_RFK_WM(0x12b8, 0x40000000, 0x1), 202 RTW89_DECL_RFK_WM(0x030c, MASKBYTE3, 0x1f), 203 RTW89_DECL_RFK_WM(0x030c, MASKBYTE3, 0x13), 204 RTW89_DECL_RFK_WM(0x032c, MASKHWORD, 0x0001), 205 RTW89_DECL_RFK_WM(0x032c, MASKHWORD, 0x0041), 206 }; 207 208 RTW89_DECLARE_RFK_TBL(rtw8851b_iqk_bb_afe_defs); 209 210 static const struct rtw89_reg5_def rtw8851b_tssi_sys_defs[] = { 211 RTW89_DECL_RFK_WM(0x12bc, 0x000ffff0, 0xb5b5), 212 RTW89_DECL_RFK_WM(0x32bc, 0x000ffff0, 0xb5b5), 213 RTW89_DECL_RFK_WM(0x0300, 0xff000000, 0x16), 214 RTW89_DECL_RFK_WM(0x0304, 0x0000ffff, 0x1f19), 215 RTW89_DECL_RFK_WM(0x0308, 0xff000000, 0x1c), 216 RTW89_DECL_RFK_WM(0x0314, 0xffff0000, 0x2041), 217 RTW89_DECL_RFK_WM(0x0318, 0xffffffff, 0x20012041), 218 RTW89_DECL_RFK_WM(0x0324, 0xffff0000, 0x2001), 219 RTW89_DECL_RFK_WM(0x0020, 0x00006000, 0x3), 220 RTW89_DECL_RFK_WM(0x0024, 0x00006000, 0x3), 221 RTW89_DECL_RFK_WM(0x0704, 0xffff0000, 0x601e), 222 RTW89_DECL_RFK_WM(0x2704, 0xffff0000, 0x601e), 223 RTW89_DECL_RFK_WM(0x0700, 0xf0000000, 0x4), 224 RTW89_DECL_RFK_WM(0x2700, 0xf0000000, 0x4), 225 RTW89_DECL_RFK_WM(0x0650, 0x3c000000, 0x0), 226 RTW89_DECL_RFK_WM(0x2650, 0x3c000000, 0x0), 227 }; 228 229 RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_sys_defs); 230 231 static const struct rtw89_reg5_def rtw8851b_tssi_sys_a_defs_2g[] = { 232 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x33), 233 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x33), 234 RTW89_DECL_RFK_WM(0x58f8, 0x40000000, 0x1), 235 RTW89_DECL_RFK_WM(0x5814, 0x20000000, 0x0), 236 }; 237 238 RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_sys_a_defs_2g); 239 240 static const struct rtw89_reg5_def rtw8851b_tssi_sys_a_defs_5g[] = { 241 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x44), 242 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x44), 243 RTW89_DECL_RFK_WM(0x58f8, 0x40000000, 0x0), 244 RTW89_DECL_RFK_WM(0x5814, 0x20000000, 0x0), 245 }; 246 247 RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_sys_a_defs_5g); 248 249 static const struct rtw89_reg5_def rtw8851b_tssi_init_txpwr_defs_a[] = { 250 RTW89_DECL_RFK_WM(0x566c, 0x00001000, 0x0), 251 RTW89_DECL_RFK_WM(0x5800, 0xffffffff, 0x003f807f), 252 RTW89_DECL_RFK_WM(0x580c, 0x0000007f, 0x40), 253 RTW89_DECL_RFK_WM(0x580c, 0x0fffff00, 0x00040), 254 RTW89_DECL_RFK_WM(0x5810, 0xffffffff, 0x59010000), 255 RTW89_DECL_RFK_WM(0x5814, 0x01ffffff, 0x026d000), 256 RTW89_DECL_RFK_WM(0x5814, 0xf8000000, 0x00), 257 RTW89_DECL_RFK_WM(0x5818, 0x00ffffff, 0x2c18e8), 258 RTW89_DECL_RFK_WM(0x5818, 0x07000000, 0x0), 259 RTW89_DECL_RFK_WM(0x5818, 0xf0000000, 0x0), 260 RTW89_DECL_RFK_WM(0x581c, 0x3fffffff, 0x3dc80280), 261 RTW89_DECL_RFK_WM(0x5820, 0xffffffff, 0x00000080), 262 RTW89_DECL_RFK_WM(0x58e8, 0x0000003f, 0x04), 263 RTW89_DECL_RFK_WM(0x580c, 0x10000000, 0x1), 264 RTW89_DECL_RFK_WM(0x580c, 0x40000000, 0x1), 265 RTW89_DECL_RFK_WM(0x5834, 0x3fffffff, 0x000115f2), 266 RTW89_DECL_RFK_WM(0x5838, 0x7fffffff, 0x0000121), 267 RTW89_DECL_RFK_WM(0x5854, 0x3fffffff, 0x000115f2), 268 RTW89_DECL_RFK_WM(0x5858, 0x7fffffff, 0x0000121), 269 RTW89_DECL_RFK_WM(0x5860, 0x80000000, 0x0), 270 RTW89_DECL_RFK_WM(0x5864, 0x07ffffff, 0x00801ff), 271 RTW89_DECL_RFK_WM(0x5898, MASKDWORD, 0x00000000), 272 RTW89_DECL_RFK_WM(0x589c, MASKDWORD, 0x00000000), 273 RTW89_DECL_RFK_WM(0x58a4, 0x000000ff, 0x16), 274 RTW89_DECL_RFK_WM(0x58b0, MASKDWORD, 0x00000000), 275 RTW89_DECL_RFK_WM(0x58b4, 0x7fffffff, 0x0a002000), 276 RTW89_DECL_RFK_WM(0x58b8, 0x7fffffff, 0x00007628), 277 RTW89_DECL_RFK_WM(0x58bc, 0x07ffffff, 0x7a7807f), 278 RTW89_DECL_RFK_WM(0x58c0, 0xfffe0000, 0x003f), 279 RTW89_DECL_RFK_WM(0x58c4, 0xffffffff, 0x0003ffff), 280 RTW89_DECL_RFK_WM(0x58c8, 0x00ffffff, 0x000000), 281 RTW89_DECL_RFK_WM(0x58c8, 0xf0000000, 0x0), 282 RTW89_DECL_RFK_WM(0x58cc, MASKDWORD, 0x00000000), 283 RTW89_DECL_RFK_WM(0x58d0, 0x07ffffff, 0x2008101), 284 RTW89_DECL_RFK_WM(0x58d4, 0x000000ff, 0x00), 285 RTW89_DECL_RFK_WM(0x58d4, 0x0003fe00, 0x0ff), 286 RTW89_DECL_RFK_WM(0x58d4, 0x07fc0000, 0x100), 287 RTW89_DECL_RFK_WM(0x58d8, 0xffffffff, 0x8008016c), 288 RTW89_DECL_RFK_WM(0x58dc, 0x0001ffff, 0x0807f), 289 RTW89_DECL_RFK_WM(0x58dc, 0xfff00000, 0x800), 290 RTW89_DECL_RFK_WM(0x58f0, 0x0003ffff, 0x001ff), 291 RTW89_DECL_RFK_WM(0x58f4, 0x000fffff, 0x00000), 292 RTW89_DECL_RFK_WM(0x58f8, 0x000fffff, 0x00000), 293 }; 294 295 RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_init_txpwr_defs_a); 296 297 static const struct rtw89_reg5_def rtw8851b_tssi_init_txpwr_he_tb_defs_a[] = { 298 RTW89_DECL_RFK_WM(0x58a0, MASKDWORD, 0x000000fe), 299 RTW89_DECL_RFK_WM(0x58e4, 0x0000007f, 0x1f), 300 }; 301 302 RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_init_txpwr_he_tb_defs_a); 303 304 static const struct rtw89_reg5_def rtw8851b_tssi_dck_defs_a[] = { 305 RTW89_DECL_RFK_WM(0x580c, 0x0fff0000, 0x000), 306 RTW89_DECL_RFK_WM(0x5814, 0x00001000, 0x1), 307 RTW89_DECL_RFK_WM(0x5814, 0x00002000, 0x1), 308 RTW89_DECL_RFK_WM(0x5814, 0x00004000, 0x1), 309 RTW89_DECL_RFK_WM(0x5814, 0x00038000, 0x3), 310 RTW89_DECL_RFK_WM(0x5814, 0x003c0000, 0x5), 311 RTW89_DECL_RFK_WM(0x5814, 0x18000000, 0x0), 312 }; 313 314 RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_dck_defs_a); 315 316 static const struct rtw89_reg5_def rtw8851b_tssi_dac_gain_defs_a[] = { 317 RTW89_DECL_RFK_WM(0x58b0, 0x00000fff, 0x000), 318 RTW89_DECL_RFK_WM(0x5a00, MASKDWORD, 0x00000000), 319 RTW89_DECL_RFK_WM(0x5a04, MASKDWORD, 0x00000000), 320 RTW89_DECL_RFK_WM(0x5a08, MASKDWORD, 0x00000000), 321 RTW89_DECL_RFK_WM(0x5a0c, MASKDWORD, 0x00000000), 322 RTW89_DECL_RFK_WM(0x5a10, MASKDWORD, 0x00000000), 323 RTW89_DECL_RFK_WM(0x5a14, MASKDWORD, 0x00000000), 324 RTW89_DECL_RFK_WM(0x5a18, MASKDWORD, 0x00000000), 325 RTW89_DECL_RFK_WM(0x5a1c, MASKDWORD, 0x00000000), 326 RTW89_DECL_RFK_WM(0x5a20, MASKDWORD, 0x00000000), 327 RTW89_DECL_RFK_WM(0x5a24, MASKDWORD, 0x00000000), 328 RTW89_DECL_RFK_WM(0x5a28, MASKDWORD, 0x00000000), 329 RTW89_DECL_RFK_WM(0x5a2c, MASKDWORD, 0x00000000), 330 RTW89_DECL_RFK_WM(0x5a30, MASKDWORD, 0x00000000), 331 RTW89_DECL_RFK_WM(0x5a34, MASKDWORD, 0x00000000), 332 RTW89_DECL_RFK_WM(0x5a38, MASKDWORD, 0x00000000), 333 RTW89_DECL_RFK_WM(0x5a3c, MASKDWORD, 0x00000000), 334 RTW89_DECL_RFK_WM(0x5a40, MASKDWORD, 0x00000000), 335 RTW89_DECL_RFK_WM(0x5a44, MASKDWORD, 0x00000000), 336 RTW89_DECL_RFK_WM(0x5a48, MASKDWORD, 0x00000000), 337 RTW89_DECL_RFK_WM(0x5a4c, MASKDWORD, 0x00000000), 338 RTW89_DECL_RFK_WM(0x5a50, MASKDWORD, 0x00000000), 339 RTW89_DECL_RFK_WM(0x5a54, MASKDWORD, 0x00000000), 340 RTW89_DECL_RFK_WM(0x5a58, MASKDWORD, 0x00000000), 341 RTW89_DECL_RFK_WM(0x5a5c, MASKDWORD, 0x00000000), 342 RTW89_DECL_RFK_WM(0x5a60, MASKDWORD, 0x00000000), 343 RTW89_DECL_RFK_WM(0x5a64, MASKDWORD, 0x00000000), 344 RTW89_DECL_RFK_WM(0x5a68, MASKDWORD, 0x00000000), 345 RTW89_DECL_RFK_WM(0x5a6c, MASKDWORD, 0x00000000), 346 RTW89_DECL_RFK_WM(0x5a70, MASKDWORD, 0x00000000), 347 RTW89_DECL_RFK_WM(0x5a74, MASKDWORD, 0x00000000), 348 RTW89_DECL_RFK_WM(0x5a78, MASKDWORD, 0x00000000), 349 RTW89_DECL_RFK_WM(0x5a7c, MASKDWORD, 0x00000000), 350 RTW89_DECL_RFK_WM(0x5a80, MASKDWORD, 0x00000000), 351 RTW89_DECL_RFK_WM(0x5a84, MASKDWORD, 0x00000000), 352 RTW89_DECL_RFK_WM(0x5a88, MASKDWORD, 0x00000000), 353 RTW89_DECL_RFK_WM(0x5a8c, MASKDWORD, 0x00000000), 354 RTW89_DECL_RFK_WM(0x5a90, MASKDWORD, 0x00000000), 355 RTW89_DECL_RFK_WM(0x5a94, MASKDWORD, 0x00000000), 356 RTW89_DECL_RFK_WM(0x5a98, MASKDWORD, 0x00000000), 357 RTW89_DECL_RFK_WM(0x5a9c, MASKDWORD, 0x00000000), 358 RTW89_DECL_RFK_WM(0x5aa0, MASKDWORD, 0x00000000), 359 RTW89_DECL_RFK_WM(0x5aa4, MASKDWORD, 0x00000000), 360 RTW89_DECL_RFK_WM(0x5aa8, MASKDWORD, 0x00000000), 361 RTW89_DECL_RFK_WM(0x5aac, MASKDWORD, 0x00000000), 362 RTW89_DECL_RFK_WM(0x5ab0, MASKDWORD, 0x00000000), 363 RTW89_DECL_RFK_WM(0x5ab4, MASKDWORD, 0x00000000), 364 RTW89_DECL_RFK_WM(0x5ab8, MASKDWORD, 0x00000000), 365 RTW89_DECL_RFK_WM(0x5abc, MASKDWORD, 0x00000000), 366 RTW89_DECL_RFK_WM(0x5ac0, MASKDWORD, 0x00000000), 367 }; 368 369 RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_dac_gain_defs_a); 370 371 static const struct rtw89_reg5_def rtw8851b_tssi_slope_a_defs_2g[] = { 372 RTW89_DECL_RFK_WM(0x5608, 0x07ffffff, 0x0201008), 373 RTW89_DECL_RFK_WM(0x560c, 0x07ffffff, 0x0201008), 374 RTW89_DECL_RFK_WM(0x5610, 0x07ffffff, 0x0200e08), 375 RTW89_DECL_RFK_WM(0x5614, 0x07ffffff, 0x0201008), 376 RTW89_DECL_RFK_WM(0x5618, 0x07ffffff, 0x0201008), 377 RTW89_DECL_RFK_WM(0x561c, 0x000001ff, 0x007), 378 RTW89_DECL_RFK_WM(0x561c, 0xffff0000, 0x0808), 379 RTW89_DECL_RFK_WM(0x5620, 0xffffffff, 0x08080808), 380 RTW89_DECL_RFK_WM(0x5624, 0xffffffff, 0x08080808), 381 RTW89_DECL_RFK_WM(0x5628, 0xffffffff, 0x08080808), 382 RTW89_DECL_RFK_WM(0x562c, 0x0000ffff, 0x0808), 383 RTW89_DECL_RFK_WM(0x581c, 0x00100000, 0x1), 384 }; 385 386 RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_slope_a_defs_2g); 387 388 static const struct rtw89_reg5_def rtw8851b_tssi_slope_a_defs_5g[] = { 389 RTW89_DECL_RFK_WM(0x5608, 0x07ffffff, 0x0201008), 390 RTW89_DECL_RFK_WM(0x560c, 0x07ffffff, 0x0341a08), 391 RTW89_DECL_RFK_WM(0x5610, 0x07ffffff, 0x0201417), 392 RTW89_DECL_RFK_WM(0x5614, 0x07ffffff, 0x0201008), 393 RTW89_DECL_RFK_WM(0x5618, 0x07ffffff, 0x0201008), 394 RTW89_DECL_RFK_WM(0x561c, 0x000001ff, 0x008), 395 RTW89_DECL_RFK_WM(0x561c, 0xffff0000, 0x0808), 396 RTW89_DECL_RFK_WM(0x5620, 0xffffffff, 0x0e0e0808), 397 RTW89_DECL_RFK_WM(0x5624, 0xffffffff, 0x08080d18), 398 RTW89_DECL_RFK_WM(0x5628, 0xffffffff, 0x08080808), 399 RTW89_DECL_RFK_WM(0x562c, 0x0000ffff, 0x0808), 400 RTW89_DECL_RFK_WM(0x581c, 0x00100000, 0x1), 401 }; 402 403 RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_slope_a_defs_5g); 404 405 static const struct rtw89_reg5_def rtw8851b_tssi_align_a_2g_defs[] = { 406 RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1), 407 RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x000000), 408 RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x2d2400), 409 RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x00000000), 410 RTW89_DECL_RFK_WM(0x5634, 0x000003ff, 0x000), 411 RTW89_DECL_RFK_WM(0x5634, 0x000ffc00, 0x000), 412 RTW89_DECL_RFK_WM(0x5634, 0x3ff00000, 0x3fa), 413 RTW89_DECL_RFK_WM(0x5638, 0x000003ff, 0x02e), 414 RTW89_DECL_RFK_WM(0x5638, 0x000ffc00, 0x09c), 415 RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000), 416 RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x3fb00000), 417 RTW89_DECL_RFK_WM(0x5644, 0x000003ff, 0x02f), 418 RTW89_DECL_RFK_WM(0x5644, 0x000ffc00, 0x09c), 419 }; 420 421 RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_align_a_2g_defs); 422 423 static const struct rtw89_reg5_def rtw8851b_tssi_align_a_5g_defs[] = { 424 RTW89_DECL_RFK_WM(0x5604, 0x80000000, 0x1), 425 RTW89_DECL_RFK_WM(0x5600, 0x3fffffff, 0x000000), 426 RTW89_DECL_RFK_WM(0x5604, 0x003fffff, 0x3b2d24), 427 RTW89_DECL_RFK_WM(0x5630, 0x3fffffff, 0x00000000), 428 RTW89_DECL_RFK_WM(0x5634, 0x000003ff, 0x000), 429 RTW89_DECL_RFK_WM(0x5634, 0x000ffc00, 0x3cb), 430 RTW89_DECL_RFK_WM(0x5634, 0x3ff00000, 0x030), 431 RTW89_DECL_RFK_WM(0x5638, 0x000003ff, 0x73), 432 RTW89_DECL_RFK_WM(0x5638, 0x000ffc00, 0xd4), 433 RTW89_DECL_RFK_WM(0x563c, 0x3fffffff, 0x00000000), 434 RTW89_DECL_RFK_WM(0x5640, 0x3fffffff, 0x00000000), 435 RTW89_DECL_RFK_WM(0x5644, 0x000fffff, 0x00000), 436 }; 437 438 RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_align_a_5g_defs); 439 440 static const struct rtw89_reg5_def rtw8851b_tssi_slope_defs_a[] = { 441 RTW89_DECL_RFK_WM(0x5820, 0x80000000, 0x0), 442 RTW89_DECL_RFK_WM(0x5818, 0x10000000, 0x0), 443 RTW89_DECL_RFK_WM(0x5814, 0x00000800, 0x1), 444 RTW89_DECL_RFK_WM(0x581c, 0x20000000, 0x1), 445 RTW89_DECL_RFK_WM(0x5820, 0x0000f000, 0xf), 446 RTW89_DECL_RFK_WM(0x581c, 0x000003ff, 0x280), 447 RTW89_DECL_RFK_WM(0x581c, 0x000ffc00, 0x200), 448 RTW89_DECL_RFK_WM(0x58b8, 0x007f0000, 0x00), 449 RTW89_DECL_RFK_WM(0x58b8, 0x7f000000, 0x00), 450 RTW89_DECL_RFK_WM(0x58b4, 0x7f000000, 0x0a), 451 RTW89_DECL_RFK_WM(0x58b8, 0x0000007f, 0x28), 452 RTW89_DECL_RFK_WM(0x58b8, 0x00007f00, 0x76), 453 RTW89_DECL_RFK_WM(0x5810, 0x20000000, 0x0), 454 RTW89_DECL_RFK_WM(0x580c, 0x10000000, 0x1), 455 RTW89_DECL_RFK_WM(0x580c, 0x40000000, 0x1), 456 RTW89_DECL_RFK_WM(0x5834, 0x0003ffff, 0x115f2), 457 RTW89_DECL_RFK_WM(0x5834, 0x3ffc0000, 0x000), 458 RTW89_DECL_RFK_WM(0x5838, 0x00000fff, 0x121), 459 RTW89_DECL_RFK_WM(0x5838, 0x003ff000, 0x000), 460 RTW89_DECL_RFK_WM(0x5854, 0x0003ffff, 0x115f2), 461 RTW89_DECL_RFK_WM(0x5854, 0x3ffc0000, 0x000), 462 RTW89_DECL_RFK_WM(0x5858, 0x00000fff, 0x121), 463 RTW89_DECL_RFK_WM(0x5858, 0x003ff000, 0x000), 464 RTW89_DECL_RFK_WM(0x5824, 0x0003ffff, 0x115f2), 465 RTW89_DECL_RFK_WM(0x5824, 0x3ffc0000, 0x000), 466 RTW89_DECL_RFK_WM(0x5828, 0x00000fff, 0x121), 467 RTW89_DECL_RFK_WM(0x5828, 0x003ff000, 0x000), 468 RTW89_DECL_RFK_WM(0x582c, 0x0003ffff, 0x115f2), 469 RTW89_DECL_RFK_WM(0x582c, 0x3ffc0000, 0x000), 470 RTW89_DECL_RFK_WM(0x5830, 0x00000fff, 0x121), 471 RTW89_DECL_RFK_WM(0x5830, 0x003ff000, 0x000), 472 RTW89_DECL_RFK_WM(0x583c, 0x0003ffff, 0x115f2), 473 RTW89_DECL_RFK_WM(0x583c, 0x3ffc0000, 0x000), 474 RTW89_DECL_RFK_WM(0x5840, 0x00000fff, 0x121), 475 RTW89_DECL_RFK_WM(0x5840, 0x003ff000, 0x000), 476 RTW89_DECL_RFK_WM(0x5844, 0x0003ffff, 0x115f2), 477 RTW89_DECL_RFK_WM(0x5844, 0x3ffc0000, 0x000), 478 RTW89_DECL_RFK_WM(0x5848, 0x00000fff, 0x121), 479 RTW89_DECL_RFK_WM(0x5848, 0x003ff000, 0x000), 480 RTW89_DECL_RFK_WM(0x584c, 0x0003ffff, 0x115f2), 481 RTW89_DECL_RFK_WM(0x584c, 0x3ffc0000, 0x000), 482 RTW89_DECL_RFK_WM(0x5850, 0x00000fff, 0x121), 483 RTW89_DECL_RFK_WM(0x5850, 0x003ff000, 0x000), 484 RTW89_DECL_RFK_WM(0x585c, 0x0003ffff, 0x115f2), 485 RTW89_DECL_RFK_WM(0x585c, 0x3ffc0000, 0x000), 486 RTW89_DECL_RFK_WM(0x5860, 0x00000fff, 0x121), 487 RTW89_DECL_RFK_WM(0x5860, 0x003ff000, 0x000), 488 }; 489 490 RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_slope_defs_a); 491 492 static const struct rtw89_reg5_def rtw8851b_tssi_track_defs_a[] = { 493 RTW89_DECL_RFK_WM(0x5820, 0x80000000, 0x0), 494 RTW89_DECL_RFK_WM(0x5818, 0x10000000, 0x0), 495 RTW89_DECL_RFK_WM(0x5814, 0x00000800, 0x0), 496 RTW89_DECL_RFK_WM(0x581c, 0x20000000, 0x1), 497 RTW89_DECL_RFK_WM(0x5864, 0x000003ff, 0x1ff), 498 RTW89_DECL_RFK_WM(0x5864, 0x000ffc00, 0x200), 499 RTW89_DECL_RFK_WM(0x5820, 0x00000fff, 0x080), 500 RTW89_DECL_RFK_WM(0x5814, 0x01000000, 0x0), 501 }; 502 503 RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_track_defs_a); 504 505 static const struct rtw89_reg5_def rtw8851b_tssi_mv_avg_defs_a[] = { 506 RTW89_DECL_RFK_WM(0x58e4, 0x00003800, 0x1), 507 RTW89_DECL_RFK_WM(0x58e4, 0x00004000, 0x0), 508 RTW89_DECL_RFK_WM(0x58e4, 0x00008000, 0x1), 509 RTW89_DECL_RFK_WM(0x58e4, 0x000f0000, 0x0), 510 }; 511 512 RTW89_DECLARE_RFK_TBL(rtw8851b_tssi_mv_avg_defs_a); 513 514 static const struct rtw89_reg5_def rtw8851b_nctl_post_defs[] = { 515 RTW89_DECL_RFK_WM(0x5864, 0x18000000, 0x3), 516 RTW89_DECL_RFK_WM(0x7864, 0x18000000, 0x3), 517 RTW89_DECL_RFK_WM(0x030c, 0xff000000, 0x13), 518 RTW89_DECL_RFK_WM(0x032c, 0xffff0000, 0x0041), 519 RTW89_DECL_RFK_WM(0x12b8, 0x10000000, 0x1), 520 RTW89_DECL_RFK_WM(0x2008, 0x01ffffff, 0x00fffff), 521 RTW89_DECL_RFK_WM(0x0c60, 0x00000003, 0x3), 522 RTW89_DECL_RFK_WM(0x0c6c, 0x00000001, 0x1), 523 RTW89_DECL_RFK_WM(0x58ac, 0x08000000, 0x1), 524 RTW89_DECL_RFK_WM(0x78ac, 0x08000000, 0x1), 525 RTW89_DECL_RFK_WM(0x0730, 0x00003800, 0x7), 526 RTW89_DECL_RFK_WM(0x2730, 0x00003800, 0x7), 527 RTW89_DECL_RFK_WM(0x0c7c, 0x00e00000, 0x1), 528 RTW89_DECL_RFK_WM(0x58c0, 0x0001ffff, 0x00000), 529 RTW89_DECL_RFK_WM(0x78c0, 0x0001ffff, 0x00000), 530 RTW89_DECL_RFK_WM(0x58fc, 0x3f000000, 0x00), 531 RTW89_DECL_RFK_WM(0x78fc, 0x3f000000, 0x00), 532 }; 533 534 RTW89_DECLARE_RFK_TBL(rtw8851b_nctl_post_defs); 535