1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_PHY_H__ 6 #define __RTW89_PHY_H__ 7 8 #include "core.h" 9 10 #define RTW89_PHY_ADDR_OFFSET 0x10000 11 #define RTW89_RF_ADDR_ADSEL_MASK BIT(16) 12 13 #define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr) 14 #define PHY_HEADLINE_VALID 0xf 15 #define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr) 16 #define get_phy_compare(rfe, cv) (FIELD_PREP(GENMASK(23, 16), rfe) | \ 17 FIELD_PREP(GENMASK(7, 0), cv)) 18 19 #define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr) 20 #define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr) 21 #define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr) 22 #define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr) 23 #define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; }) 24 #define PHY_COND_BRANCH_IF 0x8 25 #define PHY_COND_BRANCH_ELIF 0x9 26 #define PHY_COND_BRANCH_ELSE 0xa 27 #define PHY_COND_BRANCH_END 0xb 28 #define PHY_COND_CHECK 0x4 29 #define PHY_COND_DONT_CARE 0xff 30 31 #define RA_MASK_CCK_RATES GENMASK_ULL(3, 0) 32 #define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4) 33 #define RA_MASK_SUBCCK_RATES 0x5ULL 34 #define RA_MASK_SUBOFDM_RATES 0x10ULL 35 #define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12) 36 #define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24) 37 #define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36) 38 #define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48) 39 #define RA_MASK_HT_RATES GENMASK_ULL(55, 12) 40 #define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12) 41 #define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24) 42 #define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36) 43 #define RA_MASK_VHT_4SS_RATES GENMASK_ULL(57, 48) 44 #define RA_MASK_VHT_RATES GENMASK_ULL(57, 12) 45 #define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12) 46 #define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24) 47 #define RA_MASK_HE_3SS_RATES GENMASK_ULL(47, 36) 48 #define RA_MASK_HE_4SS_RATES GENMASK_ULL(59, 48) 49 #define RA_MASK_HE_RATES GENMASK_ULL(59, 12) 50 51 #define CFO_TRK_ENABLE_TH (2 << 2) 52 #define CFO_TRK_STOP_TH_4 (30 << 2) 53 #define CFO_TRK_STOP_TH_3 (20 << 2) 54 #define CFO_TRK_STOP_TH_2 (10 << 2) 55 #define CFO_TRK_STOP_TH_1 (00 << 2) 56 #define CFO_TRK_STOP_TH (2 << 2) 57 #define CFO_SW_COMP_FINE_TUNE (2 << 2) 58 #define CFO_PERIOD_CNT 15 59 #define CFO_BOUND 64 60 #define CFO_TP_UPPER 100 61 #define CFO_TP_LOWER 50 62 #define CFO_COMP_PERIOD 250 63 #define CFO_COMP_WEIGHT 8 64 #define MAX_CFO_TOLERANCE 30 65 #define CFO_TF_CNT_TH 300 66 67 #define UL_TB_TF_CNT_L2H_TH 100 68 #define UL_TB_TF_CNT_H2L_TH 70 69 70 #define ANTDIV_TRAINNING_CNT 2 71 #define ANTDIV_TRAINNING_INTVL 30 72 #define ANTDIV_DELAY 110 73 #define ANTDIV_TP_DIFF_TH_HIGH 100 74 #define ANTDIV_TP_DIFF_TH_LOW 5 75 #define ANTDIV_EVM_DIFF_TH 8 76 #define ANTDIV_RSSI_DIFF_TH 3 77 78 #define CCX_MAX_PERIOD 2097 79 #define CCX_MAX_PERIOD_UNIT 32 80 #define MS_TO_4US_RATIO 250 81 #define ENV_MNTR_FAIL_DWORD 0xffffffff 82 #define ENV_MNTR_IFSCLM_HIS_MAX 127 83 #define PERMIL 1000 84 #define PERCENT 100 85 #define IFS_CLM_TH0_UPPER 64 86 #define IFS_CLM_TH_MUL 4 87 #define IFS_CLM_TH_START_IDX 0 88 89 #define TIA0_GAIN_A 12 90 #define TIA0_GAIN_G 16 91 #define LNA0_GAIN (-24) 92 #define U4_MAX_BIT 3 93 #define U8_MAX_BIT 7 94 #define DIG_GAIN_SHIFT 2 95 #define DIG_GAIN 8 96 97 #define LNA_IDX_MAX 6 98 #define LNA_IDX_MIN 0 99 #define TIA_IDX_MAX 1 100 #define TIA_IDX_MIN 0 101 #define RXB_IDX_MAX 31 102 #define RXB_IDX_MIN 0 103 104 #define IGI_RSSI_MAX 110 105 #define PD_TH_MAX_RSSI 70 106 #define PD_TH_MIN_RSSI 8 107 #define CCKPD_TH_MIN_RSSI (-18) 108 #define PD_TH_BW160_CMP_VAL 9 109 #define PD_TH_BW80_CMP_VAL 6 110 #define PD_TH_BW40_CMP_VAL 3 111 #define PD_TH_BW20_CMP_VAL 0 112 #define PD_TH_CMP_VAL 3 113 #define PD_TH_SB_FLTR_CMP_VAL 7 114 115 #define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT) 116 #define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL) 117 #define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA) 118 #define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD) 119 #define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA) 120 121 enum rtw89_phy_c2h_ra_func { 122 RTW89_PHY_C2H_FUNC_STS_RPT, 123 RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT, 124 RTW89_PHY_C2H_FUNC_TXSTS, 125 RTW89_PHY_C2H_FUNC_RA_MAX, 126 }; 127 128 enum rtw89_phy_c2h_dm_func { 129 RTW89_PHY_C2H_DM_FUNC_FW_TEST, 130 RTW89_PHY_C2H_DM_FUNC_FW_TRIG_TX_RPT, 131 RTW89_PHY_C2H_DM_FUNC_SIGB, 132 RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY, 133 RTW89_PHY_C2H_DM_FUNC_MCC_DIG, 134 RTW89_PHY_C2H_DM_FUNC_NUM, 135 }; 136 137 enum rtw89_phy_c2h_class { 138 RTW89_PHY_C2H_CLASS_RUA, 139 RTW89_PHY_C2H_CLASS_RA, 140 RTW89_PHY_C2H_CLASS_DM, 141 RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10, 142 RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17, 143 RTW89_PHY_C2H_CLASS_MAX, 144 }; 145 146 enum rtw89_env_monitor_result_level { 147 RTW89_PHY_ENV_MON_CCX_FAIL = 0, 148 RTW89_PHY_ENV_MON_NHM = BIT(0), 149 RTW89_PHY_ENV_MON_CLM = BIT(1), 150 RTW89_PHY_ENV_MON_FAHM = BIT(2), 151 RTW89_PHY_ENV_MON_IFS_CLM = BIT(3), 152 RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4), 153 }; 154 155 #define CCX_US_BASE_RATIO 4 156 enum rtw89_ccx_unit { 157 RTW89_CCX_4_US = 0, 158 RTW89_CCX_8_US = 1, 159 RTW89_CCX_16_US = 2, 160 RTW89_CCX_32_US = 3 161 }; 162 163 enum rtw89_phy_status_ie_type { 164 RTW89_PHYSTS_IE00_CMN_CCK = 0, 165 RTW89_PHYSTS_IE01_CMN_OFDM = 1, 166 RTW89_PHYSTS_IE02_CMN_EXT_AX = 2, 167 RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3, 168 RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4, 169 RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5, 170 RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6, 171 RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7, 172 RTW89_PHYSTS_IE08_FTR_CH = 8, 173 RTW89_PHYSTS_IE09_FTR_0 = 9, 174 RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10, 175 RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11, 176 RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12, 177 RTW89_PHYSTS_IE13_DL_MU_DEF = 13, 178 RTW89_PHYSTS_IE14_TB_UL_CQI = 14, 179 RTW89_PHYSTS_IE15_TB_UL_DEF = 15, 180 RTW89_PHYSTS_IE16_RSVD16 = 16, 181 RTW89_PHYSTS_IE17_TB_UL_CTRL = 17, 182 RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18, 183 RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19, 184 RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20, 185 RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21, 186 RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22, 187 RTW89_PHYSTS_IE23_RSVD23 = 23, 188 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A = 24, 189 RTW89_PHYSTS_IE25_OFDM_TD_PATH_B = 25, 190 RTW89_PHYSTS_IE26_OFDM_TD_PATH_C = 26, 191 RTW89_PHYSTS_IE27_OFDM_TD_PATH_D = 27, 192 RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28, 193 RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29, 194 RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30, 195 RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31, 196 197 /* keep last */ 198 RTW89_PHYSTS_IE_NUM, 199 RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1 200 }; 201 202 enum rtw89_phy_status_bitmap { 203 RTW89_TD_SEARCH_FAIL = 0, 204 RTW89_BRK_BY_TX_PKT = 1, 205 RTW89_CCA_SPOOF = 2, 206 RTW89_OFDM_BRK = 3, 207 RTW89_CCK_BRK = 4, 208 RTW89_DL_MU_SPOOFING = 5, 209 RTW89_HE_MU = 6, 210 RTW89_VHT_MU = 7, 211 RTW89_UL_TB_SPOOFING = 8, 212 RTW89_RSVD_9 = 9, 213 RTW89_TRIG_BASE_PPDU = 10, 214 RTW89_CCK_PKT = 11, 215 RTW89_LEGACY_OFDM_PKT = 12, 216 RTW89_HT_PKT = 13, 217 RTW89_VHT_PKT = 14, 218 RTW89_HE_PKT = 15, 219 220 RTW89_PHYSTS_BITMAP_NUM 221 }; 222 223 enum rtw89_dig_gain_type { 224 RTW89_DIG_GAIN_LNA_G = 0, 225 RTW89_DIG_GAIN_TIA_G = 1, 226 RTW89_DIG_GAIN_LNA_A = 2, 227 RTW89_DIG_GAIN_TIA_A = 3, 228 RTW89_DIG_GAIN_MAX = 4 229 }; 230 231 enum rtw89_dig_gain_lna_idx { 232 RTW89_DIG_GAIN_LNA_IDX1 = 1, 233 RTW89_DIG_GAIN_LNA_IDX2 = 2, 234 RTW89_DIG_GAIN_LNA_IDX3 = 3, 235 RTW89_DIG_GAIN_LNA_IDX4 = 4, 236 RTW89_DIG_GAIN_LNA_IDX5 = 5, 237 RTW89_DIG_GAIN_LNA_IDX6 = 6 238 }; 239 240 enum rtw89_dig_gain_tia_idx { 241 RTW89_DIG_GAIN_TIA_IDX0 = 0, 242 RTW89_DIG_GAIN_TIA_IDX1 = 1 243 }; 244 245 enum rtw89_tssi_bandedge_cfg { 246 RTW89_TSSI_BANDEDGE_FLAT, 247 RTW89_TSSI_BANDEDGE_LOW, 248 RTW89_TSSI_BANDEDGE_MID, 249 RTW89_TSSI_BANDEDGE_HIGH, 250 251 RTW89_TSSI_CFG_NUM, 252 }; 253 254 enum rtw89_tssi_sbw_idx { 255 RTW89_TSSI_SBW20, 256 RTW89_TSSI_SBW40_0, 257 RTW89_TSSI_SBW40_1, 258 RTW89_TSSI_SBW80_0, 259 RTW89_TSSI_SBW80_1, 260 RTW89_TSSI_SBW80_2, 261 RTW89_TSSI_SBW80_3, 262 RTW89_TSSI_SBW160_0, 263 RTW89_TSSI_SBW160_1, 264 RTW89_TSSI_SBW160_2, 265 RTW89_TSSI_SBW160_3, 266 RTW89_TSSI_SBW160_4, 267 RTW89_TSSI_SBW160_5, 268 RTW89_TSSI_SBW160_6, 269 RTW89_TSSI_SBW160_7, 270 271 RTW89_TSSI_SBW_NUM, 272 }; 273 274 struct rtw89_txpwr_byrate_cfg { 275 enum rtw89_band band; 276 enum rtw89_nss nss; 277 enum rtw89_rate_section rs; 278 u8 shf; 279 u8 len; 280 u32 data; 281 }; 282 283 #define DELTA_SWINGIDX_SIZE 30 284 285 struct rtw89_txpwr_track_cfg { 286 const s8 (*delta_swingidx_6gb_n)[DELTA_SWINGIDX_SIZE]; 287 const s8 (*delta_swingidx_6gb_p)[DELTA_SWINGIDX_SIZE]; 288 const s8 (*delta_swingidx_6ga_n)[DELTA_SWINGIDX_SIZE]; 289 const s8 (*delta_swingidx_6ga_p)[DELTA_SWINGIDX_SIZE]; 290 const s8 (*delta_swingidx_5gb_n)[DELTA_SWINGIDX_SIZE]; 291 const s8 (*delta_swingidx_5gb_p)[DELTA_SWINGIDX_SIZE]; 292 const s8 (*delta_swingidx_5ga_n)[DELTA_SWINGIDX_SIZE]; 293 const s8 (*delta_swingidx_5ga_p)[DELTA_SWINGIDX_SIZE]; 294 const s8 *delta_swingidx_2gb_n; 295 const s8 *delta_swingidx_2gb_p; 296 const s8 *delta_swingidx_2ga_n; 297 const s8 *delta_swingidx_2ga_p; 298 const s8 *delta_swingidx_2g_cck_b_n; 299 const s8 *delta_swingidx_2g_cck_b_p; 300 const s8 *delta_swingidx_2g_cck_a_n; 301 const s8 *delta_swingidx_2g_cck_a_p; 302 }; 303 304 struct rtw89_phy_dig_gain_cfg { 305 const struct rtw89_reg_def *table; 306 u8 size; 307 }; 308 309 struct rtw89_phy_dig_gain_table { 310 const struct rtw89_phy_dig_gain_cfg *cfg_lna_g; 311 const struct rtw89_phy_dig_gain_cfg *cfg_tia_g; 312 const struct rtw89_phy_dig_gain_cfg *cfg_lna_a; 313 const struct rtw89_phy_dig_gain_cfg *cfg_tia_a; 314 }; 315 316 struct rtw89_phy_tssi_dbw_table { 317 u32 data[RTW89_TSSI_CFG_NUM][RTW89_TSSI_SBW_NUM]; 318 }; 319 320 struct rtw89_phy_reg3_tbl { 321 const struct rtw89_reg3_def *reg3; 322 int size; 323 }; 324 325 #define DECLARE_PHY_REG3_TBL(_name) \ 326 const struct rtw89_phy_reg3_tbl _name ## _tbl = { \ 327 .reg3 = _name, \ 328 .size = ARRAY_SIZE(_name), \ 329 } 330 331 struct rtw89_nbi_reg_def { 332 struct rtw89_reg_def notch1_idx; 333 struct rtw89_reg_def notch1_frac_idx; 334 struct rtw89_reg_def notch1_en; 335 struct rtw89_reg_def notch2_idx; 336 struct rtw89_reg_def notch2_frac_idx; 337 struct rtw89_reg_def notch2_en; 338 }; 339 340 static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev, 341 u32 addr, u8 data) 342 { 343 rtw89_write8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data); 344 } 345 346 static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev, 347 u32 addr, u16 data) 348 { 349 rtw89_write16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data); 350 } 351 352 static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev, 353 u32 addr, u32 data) 354 { 355 rtw89_write32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, data); 356 } 357 358 static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev, 359 u32 addr, u32 bits) 360 { 361 rtw89_write32_set(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits); 362 } 363 364 static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev, 365 u32 addr, u32 bits) 366 { 367 rtw89_write32_clr(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, bits); 368 } 369 370 static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev, 371 u32 addr, u32 mask, u32 data) 372 { 373 rtw89_write32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask, data); 374 } 375 376 static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr) 377 { 378 return rtw89_read8(rtwdev, addr | RTW89_PHY_ADDR_OFFSET); 379 } 380 381 static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr) 382 { 383 return rtw89_read16(rtwdev, addr | RTW89_PHY_ADDR_OFFSET); 384 } 385 386 static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr) 387 { 388 return rtw89_read32(rtwdev, addr | RTW89_PHY_ADDR_OFFSET); 389 } 390 391 static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev, 392 u32 addr, u32 mask) 393 { 394 return rtw89_read32_mask(rtwdev, addr | RTW89_PHY_ADDR_OFFSET, mask); 395 } 396 397 static inline 398 enum rtw89_gain_offset rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband) 399 { 400 switch (subband) { 401 default: 402 case RTW89_CH_2G: 403 return RTW89_GAIN_OFFSET_2G_OFDM; 404 case RTW89_CH_5G_BAND_1: 405 return RTW89_GAIN_OFFSET_5G_LOW; 406 case RTW89_CH_5G_BAND_3: 407 return RTW89_GAIN_OFFSET_5G_MID; 408 case RTW89_CH_5G_BAND_4: 409 return RTW89_GAIN_OFFSET_5G_HIGH; 410 } 411 } 412 413 static inline 414 enum rtw89_phy_bb_gain_band rtw89_subband_to_bb_gain_band(enum rtw89_subband subband) 415 { 416 switch (subband) { 417 default: 418 case RTW89_CH_2G: 419 return RTW89_BB_GAIN_BAND_2G; 420 case RTW89_CH_5G_BAND_1: 421 return RTW89_BB_GAIN_BAND_5G_L; 422 case RTW89_CH_5G_BAND_3: 423 return RTW89_BB_GAIN_BAND_5G_M; 424 case RTW89_CH_5G_BAND_4: 425 return RTW89_BB_GAIN_BAND_5G_H; 426 case RTW89_CH_6G_BAND_IDX0: 427 case RTW89_CH_6G_BAND_IDX1: 428 return RTW89_BB_GAIN_BAND_6G_L; 429 case RTW89_CH_6G_BAND_IDX2: 430 case RTW89_CH_6G_BAND_IDX3: 431 return RTW89_BB_GAIN_BAND_6G_M; 432 case RTW89_CH_6G_BAND_IDX4: 433 case RTW89_CH_6G_BAND_IDX5: 434 return RTW89_BB_GAIN_BAND_6G_H; 435 case RTW89_CH_6G_BAND_IDX6: 436 case RTW89_CH_6G_BAND_IDX7: 437 return RTW89_BB_GAIN_BAND_6G_UH; 438 } 439 } 440 441 enum rtw89_rfk_flag { 442 RTW89_RFK_F_WRF = 0, 443 RTW89_RFK_F_WM = 1, 444 RTW89_RFK_F_WS = 2, 445 RTW89_RFK_F_WC = 3, 446 RTW89_RFK_F_DELAY = 4, 447 RTW89_RFK_F_NUM, 448 }; 449 450 struct rtw89_rfk_tbl { 451 const struct rtw89_reg5_def *defs; 452 u32 size; 453 }; 454 455 #define RTW89_DECLARE_RFK_TBL(_name) \ 456 const struct rtw89_rfk_tbl _name ## _tbl = { \ 457 .defs = _name, \ 458 .size = ARRAY_SIZE(_name), \ 459 } 460 461 #define RTW89_DECL_RFK_WRF(_path, _addr, _mask, _data) \ 462 {.flag = RTW89_RFK_F_WRF, \ 463 .path = _path, \ 464 .addr = _addr, \ 465 .mask = _mask, \ 466 .data = _data,} 467 468 #define RTW89_DECL_RFK_WM(_addr, _mask, _data) \ 469 {.flag = RTW89_RFK_F_WM, \ 470 .addr = _addr, \ 471 .mask = _mask, \ 472 .data = _data,} 473 474 #define RTW89_DECL_RFK_WS(_addr, _mask) \ 475 {.flag = RTW89_RFK_F_WS, \ 476 .addr = _addr, \ 477 .mask = _mask,} 478 479 #define RTW89_DECL_RFK_WC(_addr, _mask) \ 480 {.flag = RTW89_RFK_F_WC, \ 481 .addr = _addr, \ 482 .mask = _mask,} 483 484 #define RTW89_DECL_RFK_DELAY(_data) \ 485 {.flag = RTW89_RFK_F_DELAY, \ 486 .data = _data,} 487 488 void 489 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl); 490 491 #define rtw89_rfk_parser_by_cond(dev, cond, tbl_t, tbl_f) \ 492 do { \ 493 typeof(dev) __dev = (dev); \ 494 if (cond) \ 495 rtw89_rfk_parser(__dev, (tbl_t)); \ 496 else \ 497 rtw89_rfk_parser(__dev, (tbl_f)); \ 498 } while (0) 499 500 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 501 const struct rtw89_phy_reg3_tbl *tbl); 502 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 503 const struct rtw89_chan *chan, 504 enum rtw89_bandwidth dbw); 505 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 506 u32 addr, u32 mask); 507 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 508 u32 addr, u32 mask); 509 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 510 u32 addr, u32 mask, u32 data); 511 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 512 u32 addr, u32 mask, u32 data); 513 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev); 514 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio); 515 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 516 const struct rtw89_reg2_def *reg, 517 enum rtw89_rf_path rf_path, 518 void *extra_data); 519 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev); 520 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 521 u32 data, enum rtw89_phy_idx phy_idx); 522 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 523 enum rtw89_phy_idx phy_idx); 524 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 525 const struct rtw89_txpwr_table *tbl); 526 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 527 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch); 528 void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev, 529 const struct rtw89_chan *chan, 530 enum rtw89_phy_idx phy_idx); 531 void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev, 532 const struct rtw89_chan *chan, 533 enum rtw89_phy_idx phy_idx); 534 void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev, 535 const struct rtw89_chan *chan, 536 enum rtw89_phy_idx phy_idx); 537 void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, 538 const struct rtw89_chan *chan, 539 enum rtw89_phy_idx phy_idx); 540 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta); 541 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev); 542 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 543 u32 changed); 544 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 545 struct ieee80211_vif *vif, 546 const struct cfg80211_bitrate_mask *mask); 547 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 548 u32 len, u8 class, u8 func); 549 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev); 550 void rtw89_phy_cfo_track_work(struct work_struct *work); 551 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 552 struct rtw89_rx_phy_ppdu *phy_ppdu); 553 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev); 554 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev); 555 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 556 u32 val); 557 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev); 558 void rtw89_phy_dig(struct rtw89_dev *rtwdev); 559 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev); 560 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev, 561 struct rtw89_rx_phy_ppdu *phy_ppdu); 562 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev); 563 void rtw89_phy_antdiv_work(struct work_struct *work); 564 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 565 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 566 enum rtw89_mac_idx mac_idx, 567 enum rtw89_tssi_bandedge_cfg bandedge_cfg); 568 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 569 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev); 570 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band); 571 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx, 572 u8 *ch, enum nl80211_band *band); 573 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan); 574 575 #endif 576