1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "debug.h" 6 #include "fw.h" 7 #include "mac.h" 8 #include "phy.h" 9 #include "ps.h" 10 #include "reg.h" 11 #include "sar.h" 12 #include "coex.h" 13 14 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev, 15 const struct rtw89_ra_report *report) 16 { 17 u32 bit_rate = report->bit_rate; 18 19 /* lower than ofdm, do not aggregate */ 20 if (bit_rate < 550) 21 return 1; 22 23 /* avoid AMSDU for legacy rate */ 24 if (report->might_fallback_legacy) 25 return 1; 26 27 /* lower than 20M vht 2ss mcs8, make it small */ 28 if (bit_rate < 1800) 29 return 1200; 30 31 /* lower than 40M vht 2ss mcs9, make it medium */ 32 if (bit_rate < 4000) 33 return 2600; 34 35 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ 36 if (bit_rate < 7000) 37 return 3500; 38 39 return rtwdev->chip->max_amsdu_limit; 40 } 41 42 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap) 43 { 44 u64 ra_mask = 0; 45 u8 mcs_cap; 46 int i, nss; 47 48 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) { 49 mcs_cap = mcs_map & 0x3; 50 switch (mcs_cap) { 51 case 2: 52 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss; 53 break; 54 case 1: 55 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; 56 break; 57 case 0: 58 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; 59 break; 60 default: 61 break; 62 } 63 } 64 65 return ra_mask; 66 } 67 68 static u64 get_he_ra_mask(struct ieee80211_sta *sta) 69 { 70 struct ieee80211_sta_he_cap cap = sta->deflink.he_cap; 71 u16 mcs_map; 72 73 switch (sta->deflink.bandwidth) { 74 case IEEE80211_STA_RX_BW_160: 75 if (cap.he_cap_elem.phy_cap_info[0] & 76 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) 77 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80); 78 else 79 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160); 80 break; 81 default: 82 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80); 83 } 84 85 /* MCS11, MCS9, MCS7 */ 86 return get_mcs_ra_mask(mcs_map, 11, 2); 87 } 88 89 #define RA_FLOOR_TABLE_SIZE 7 90 #define RA_FLOOR_UP_GAP 3 91 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi, 92 u8 ratr_state) 93 { 94 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; 95 u8 rssi_lv = 0; 96 u8 i; 97 98 rssi >>= 1; 99 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 100 if (i >= ratr_state) 101 rssi_lv_t[i] += RA_FLOOR_UP_GAP; 102 if (rssi < rssi_lv_t[i]) { 103 rssi_lv = i; 104 break; 105 } 106 } 107 if (rssi_lv == 0) 108 return 0xffffffffffffffffULL; 109 else if (rssi_lv == 1) 110 return 0xfffffffffffffff0ULL; 111 else if (rssi_lv == 2) 112 return 0xffffffffffffefe0ULL; 113 else if (rssi_lv == 3) 114 return 0xffffffffffffcfc0ULL; 115 else if (rssi_lv == 4) 116 return 0xffffffffffff8f80ULL; 117 else if (rssi_lv >= 5) 118 return 0xffffffffffff0f00ULL; 119 120 return 0xffffffffffffffffULL; 121 } 122 123 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak) 124 { 125 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 126 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 127 128 if (ra_mask == 0) 129 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 130 131 return ra_mask; 132 } 133 134 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 135 { 136 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 137 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 138 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 139 enum nl80211_band band; 140 u64 cfg_mask; 141 142 if (!rtwsta->use_cfg_mask) 143 return -1; 144 145 switch (chan->band_type) { 146 case RTW89_BAND_2G: 147 band = NL80211_BAND_2GHZ; 148 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, 149 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES); 150 break; 151 case RTW89_BAND_5G: 152 band = NL80211_BAND_5GHZ; 153 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, 154 RA_MASK_OFDM_RATES); 155 break; 156 case RTW89_BAND_6G: 157 band = NL80211_BAND_6GHZ; 158 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy, 159 RA_MASK_OFDM_RATES); 160 break; 161 default: 162 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type); 163 return -1; 164 } 165 166 if (sta->deflink.he_cap.has_he) { 167 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], 168 RA_MASK_HE_1SS_RATES); 169 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], 170 RA_MASK_HE_2SS_RATES); 171 } else if (sta->deflink.vht_cap.vht_supported) { 172 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 173 RA_MASK_VHT_1SS_RATES); 174 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 175 RA_MASK_VHT_2SS_RATES); 176 } else if (sta->deflink.ht_cap.ht_supported) { 177 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 178 RA_MASK_HT_1SS_RATES); 179 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 180 RA_MASK_HT_2SS_RATES); 181 } 182 183 return cfg_mask; 184 } 185 186 static const u64 187 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES, 188 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES}; 189 static const u64 190 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, 191 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES}; 192 static const u64 193 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, 194 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES}; 195 196 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, 197 struct ieee80211_sta *sta, bool csi) 198 { 199 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 200 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 201 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 202 struct rtw89_ra_info *ra = &rtwsta->ra; 203 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 204 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; 205 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 206 u64 ra_mask = 0; 207 u64 ra_mask_bak; 208 u8 mode = 0; 209 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY; 210 u8 bw_mode = 0; 211 u8 stbc_en = 0; 212 u8 ldpc_en = 0; 213 u8 i; 214 bool sgi = false; 215 216 memset(ra, 0, sizeof(*ra)); 217 /* Set the ra mask from sta's capability */ 218 if (sta->deflink.he_cap.has_he) { 219 mode |= RTW89_RA_MODE_HE; 220 csi_mode = RTW89_RA_RPT_MODE_HE; 221 ra_mask |= get_he_ra_mask(sta); 222 high_rate_masks = rtw89_ra_mask_he_rates; 223 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[2] & 224 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ) 225 stbc_en = 1; 226 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[1] & 227 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) 228 ldpc_en = 1; 229 } else if (sta->deflink.vht_cap.vht_supported) { 230 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 231 232 mode |= RTW89_RA_MODE_VHT; 233 csi_mode = RTW89_RA_RPT_MODE_VHT; 234 /* MCS9, MCS8, MCS7 */ 235 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1); 236 high_rate_masks = rtw89_ra_mask_vht_rates; 237 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 238 stbc_en = 1; 239 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 240 ldpc_en = 1; 241 } else if (sta->deflink.ht_cap.ht_supported) { 242 mode |= RTW89_RA_MODE_HT; 243 csi_mode = RTW89_RA_RPT_MODE_HT; 244 ra_mask |= ((u64)sta->deflink.ht_cap.mcs.rx_mask[3] << 48) | 245 ((u64)sta->deflink.ht_cap.mcs.rx_mask[2] << 36) | 246 (sta->deflink.ht_cap.mcs.rx_mask[1] << 24) | 247 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 248 high_rate_masks = rtw89_ra_mask_ht_rates; 249 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 250 stbc_en = 1; 251 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 252 ldpc_en = 1; 253 } 254 255 switch (chan->band_type) { 256 case RTW89_BAND_2G: 257 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 258 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] <= 0xf) 259 mode |= RTW89_RA_MODE_CCK; 260 else 261 mode |= RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM; 262 break; 263 case RTW89_BAND_5G: 264 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 265 mode |= RTW89_RA_MODE_OFDM; 266 break; 267 case RTW89_BAND_6G: 268 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_6GHZ] << 4; 269 mode |= RTW89_RA_MODE_OFDM; 270 break; 271 default: 272 rtw89_err(rtwdev, "Unknown band type\n"); 273 break; 274 } 275 276 ra_mask_bak = ra_mask; 277 278 if (mode >= RTW89_RA_MODE_HT) { 279 u64 mask = 0; 280 for (i = 0; i < rtwdev->hal.tx_nss; i++) 281 mask |= high_rate_masks[i]; 282 if (mode & RTW89_RA_MODE_OFDM) 283 mask |= RA_MASK_SUBOFDM_RATES; 284 if (mode & RTW89_RA_MODE_CCK) 285 mask |= RA_MASK_SUBCCK_RATES; 286 ra_mask &= mask; 287 } else if (mode & RTW89_RA_MODE_OFDM) { 288 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES); 289 } 290 291 if (mode != RTW89_RA_MODE_CCK) 292 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); 293 294 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak); 295 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 296 297 switch (sta->deflink.bandwidth) { 298 case IEEE80211_STA_RX_BW_160: 299 bw_mode = RTW89_CHANNEL_WIDTH_160; 300 sgi = sta->deflink.vht_cap.vht_supported && 301 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160); 302 break; 303 case IEEE80211_STA_RX_BW_80: 304 bw_mode = RTW89_CHANNEL_WIDTH_80; 305 sgi = sta->deflink.vht_cap.vht_supported && 306 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 307 break; 308 case IEEE80211_STA_RX_BW_40: 309 bw_mode = RTW89_CHANNEL_WIDTH_40; 310 sgi = sta->deflink.ht_cap.ht_supported && 311 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 312 break; 313 default: 314 bw_mode = RTW89_CHANNEL_WIDTH_20; 315 sgi = sta->deflink.ht_cap.ht_supported && 316 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 317 break; 318 } 319 320 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 321 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM) 322 ra->dcm_cap = 1; 323 324 if (rate_pattern->enable) { 325 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta); 326 ra_mask &= rate_pattern->ra_mask; 327 mode = rate_pattern->ra_mode; 328 } 329 330 ra->bw_cap = bw_mode; 331 ra->mode_ctrl = mode; 332 ra->macid = rtwsta->mac_id; 333 ra->stbc_cap = stbc_en; 334 ra->ldpc_cap = ldpc_en; 335 ra->ss_num = min(sta->deflink.rx_nss, rtwdev->hal.tx_nss) - 1; 336 ra->en_sgi = sgi; 337 ra->ra_mask = ra_mask; 338 339 if (!csi) 340 return; 341 342 ra->fixed_csi_rate_en = false; 343 ra->ra_csi_rate_en = true; 344 ra->cr_tbl_sel = false; 345 ra->band_num = rtwvif->phy_idx; 346 ra->csi_bw = bw_mode; 347 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32; 348 ra->csi_mcs_ss_idx = 5; 349 ra->csi_mode = csi_mode; 350 } 351 352 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 353 u32 changed) 354 { 355 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 356 struct rtw89_ra_info *ra = &rtwsta->ra; 357 358 rtw89_phy_ra_sta_update(rtwdev, sta, false); 359 360 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) 361 ra->upd_mask = 1; 362 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED)) 363 ra->upd_bw_nss_mask = 1; 364 365 rtw89_debug(rtwdev, RTW89_DBG_RA, 366 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d", 367 ra->macid, 368 ra->bw_cap, 369 ra->ss_num, 370 ra->en_sgi, 371 ra->giltf); 372 373 rtw89_fw_h2c_ra(rtwdev, ra, false); 374 } 375 376 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next, 377 u16 rate_base, u64 ra_mask, u8 ra_mode, 378 u32 rate_ctrl, u32 ctrl_skip, bool force) 379 { 380 u8 n, c; 381 382 if (rate_ctrl == ctrl_skip) 383 return true; 384 385 n = hweight32(rate_ctrl); 386 if (n == 0) 387 return true; 388 389 if (force && n != 1) 390 return false; 391 392 if (next->enable) 393 return false; 394 395 c = __fls(rate_ctrl); 396 next->rate = rate_base + c; 397 next->ra_mode = ra_mode; 398 next->ra_mask = ra_mask; 399 next->enable = true; 400 401 return true; 402 } 403 404 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 405 struct ieee80211_vif *vif, 406 const struct cfg80211_bitrate_mask *mask) 407 { 408 struct ieee80211_supported_band *sband; 409 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 410 struct rtw89_phy_rate_pattern next_pattern = {0}; 411 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 412 static const u16 hw_rate_he[] = {RTW89_HW_RATE_HE_NSS1_MCS0, 413 RTW89_HW_RATE_HE_NSS2_MCS0, 414 RTW89_HW_RATE_HE_NSS3_MCS0, 415 RTW89_HW_RATE_HE_NSS4_MCS0}; 416 static const u16 hw_rate_vht[] = {RTW89_HW_RATE_VHT_NSS1_MCS0, 417 RTW89_HW_RATE_VHT_NSS2_MCS0, 418 RTW89_HW_RATE_VHT_NSS3_MCS0, 419 RTW89_HW_RATE_VHT_NSS4_MCS0}; 420 static const u16 hw_rate_ht[] = {RTW89_HW_RATE_MCS0, 421 RTW89_HW_RATE_MCS8, 422 RTW89_HW_RATE_MCS16, 423 RTW89_HW_RATE_MCS24}; 424 u8 band = chan->band_type; 425 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 426 u8 tx_nss = rtwdev->hal.tx_nss; 427 u8 i; 428 429 for (i = 0; i < tx_nss; i++) 430 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i], 431 RA_MASK_HE_RATES, RTW89_RA_MODE_HE, 432 mask->control[nl_band].he_mcs[i], 433 0, true)) 434 goto out; 435 436 for (i = 0; i < tx_nss; i++) 437 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i], 438 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT, 439 mask->control[nl_band].vht_mcs[i], 440 0, true)) 441 goto out; 442 443 for (i = 0; i < tx_nss; i++) 444 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i], 445 RA_MASK_HT_RATES, RTW89_RA_MODE_HT, 446 mask->control[nl_band].ht_mcs[i], 447 0, true)) 448 goto out; 449 450 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and 451 * require at least one basic rate for ieee80211_set_bitrate_mask, 452 * so the decision just depends on if all bitrates are set or not. 453 */ 454 sband = rtwdev->hw->wiphy->bands[nl_band]; 455 if (band == RTW89_BAND_2G) { 456 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1, 457 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES, 458 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM, 459 mask->control[nl_band].legacy, 460 BIT(sband->n_bitrates) - 1, false)) 461 goto out; 462 } else { 463 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6, 464 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM, 465 mask->control[nl_band].legacy, 466 BIT(sband->n_bitrates) - 1, false)) 467 goto out; 468 } 469 470 if (!next_pattern.enable) 471 goto out; 472 473 rtwvif->rate_pattern = next_pattern; 474 rtw89_debug(rtwdev, RTW89_DBG_RA, 475 #if defined(__linux__) 476 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n", 477 #elif defined(__FreeBSD__) 478 "configure pattern: rate 0x%x, mask 0x%jx, mode 0x%x\n", 479 #endif 480 next_pattern.rate, 481 #if defined(__FreeBSD__) 482 (uintmax_t) 483 #endif 484 next_pattern.ra_mask, 485 next_pattern.ra_mode); 486 return; 487 488 out: 489 rtwvif->rate_pattern.enable = false; 490 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n"); 491 } 492 493 static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta) 494 { 495 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; 496 497 rtw89_phy_ra_updata_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED); 498 } 499 500 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev) 501 { 502 ieee80211_iterate_stations_atomic(rtwdev->hw, 503 rtw89_phy_ra_updata_sta_iter, 504 rtwdev); 505 } 506 507 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) 508 { 509 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 510 struct rtw89_ra_info *ra = &rtwsta->ra; 511 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR; 512 bool csi = rtw89_sta_has_beamformer_cap(sta); 513 514 rtw89_phy_ra_sta_update(rtwdev, sta, csi); 515 516 if (rssi > 40) 517 ra->init_rate_lv = 1; 518 else if (rssi > 20) 519 ra->init_rate_lv = 2; 520 else if (rssi > 1) 521 ra->init_rate_lv = 3; 522 else 523 ra->init_rate_lv = 0; 524 ra->upd_all = 1; 525 rtw89_debug(rtwdev, RTW89_DBG_RA, 526 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d", 527 ra->macid, 528 ra->mode_ctrl, 529 ra->bw_cap, 530 ra->ss_num, 531 ra->init_rate_lv); 532 rtw89_debug(rtwdev, RTW89_DBG_RA, 533 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d", 534 ra->dcm_cap, 535 ra->er_cap, 536 ra->ldpc_cap, 537 ra->stbc_cap, 538 ra->en_sgi, 539 ra->giltf); 540 541 rtw89_fw_h2c_ra(rtwdev, ra, csi); 542 } 543 544 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 545 const struct rtw89_chan *chan, 546 enum rtw89_bandwidth dbw) 547 { 548 enum rtw89_bandwidth cbw = chan->band_width; 549 u8 pri_ch = chan->primary_channel; 550 u8 central_ch = chan->channel; 551 u8 txsc_idx = 0; 552 u8 tmp = 0; 553 554 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 555 return txsc_idx; 556 557 switch (cbw) { 558 case RTW89_CHANNEL_WIDTH_40: 559 txsc_idx = pri_ch > central_ch ? 1 : 2; 560 break; 561 case RTW89_CHANNEL_WIDTH_80: 562 if (dbw == RTW89_CHANNEL_WIDTH_20) { 563 if (pri_ch > central_ch) 564 txsc_idx = (pri_ch - central_ch) >> 1; 565 else 566 txsc_idx = ((central_ch - pri_ch) >> 1) + 1; 567 } else { 568 txsc_idx = pri_ch > central_ch ? 9 : 10; 569 } 570 break; 571 case RTW89_CHANNEL_WIDTH_160: 572 if (pri_ch > central_ch) 573 tmp = (pri_ch - central_ch) >> 1; 574 else 575 tmp = ((central_ch - pri_ch) >> 1) + 1; 576 577 if (dbw == RTW89_CHANNEL_WIDTH_20) { 578 txsc_idx = tmp; 579 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 580 if (tmp == 1 || tmp == 3) 581 txsc_idx = 9; 582 else if (tmp == 5 || tmp == 7) 583 txsc_idx = 11; 584 else if (tmp == 2 || tmp == 4) 585 txsc_idx = 10; 586 else if (tmp == 6 || tmp == 8) 587 txsc_idx = 12; 588 else 589 return 0xff; 590 } else { 591 txsc_idx = pri_ch > central_ch ? 13 : 14; 592 } 593 break; 594 case RTW89_CHANNEL_WIDTH_80_80: 595 if (dbw == RTW89_CHANNEL_WIDTH_20) { 596 if (pri_ch > central_ch) 597 txsc_idx = (10 - (pri_ch - central_ch)) >> 1; 598 else 599 txsc_idx = ((central_ch - pri_ch) >> 1) + 5; 600 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 601 txsc_idx = pri_ch > central_ch ? 10 : 12; 602 } else { 603 txsc_idx = 14; 604 } 605 break; 606 default: 607 break; 608 } 609 610 return txsc_idx; 611 } 612 EXPORT_SYMBOL(rtw89_phy_get_txsc); 613 614 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev) 615 { 616 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) || 617 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1); 618 } 619 620 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 621 u32 addr, u32 mask) 622 { 623 const struct rtw89_chip_info *chip = rtwdev->chip; 624 const u32 *base_addr = chip->rf_base_addr; 625 u32 val, direct_addr; 626 627 if (rf_path >= rtwdev->chip->rf_path_num) { 628 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 629 return INV_RF_DATA; 630 } 631 632 addr &= 0xff; 633 direct_addr = base_addr[rf_path] + (addr << 2); 634 mask &= RFREG_MASK; 635 636 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask); 637 638 return val; 639 } 640 EXPORT_SYMBOL(rtw89_phy_read_rf); 641 642 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev, 643 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 644 { 645 bool busy; 646 bool done; 647 u32 val; 648 int ret; 649 650 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 651 1, 30, false, rtwdev); 652 if (ret) { 653 rtw89_err(rtwdev, "read rf busy swsi\n"); 654 return INV_RF_DATA; 655 } 656 657 mask &= RFREG_MASK; 658 659 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) | 660 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr); 661 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val); 662 udelay(2); 663 664 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1, 665 30, false, rtwdev, R_SWSI_V1, 666 B_SWSI_R_DATA_DONE_V1); 667 if (ret) { 668 rtw89_err(rtwdev, "read swsi busy\n"); 669 return INV_RF_DATA; 670 } 671 672 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask); 673 } 674 675 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 676 u32 addr, u32 mask) 677 { 678 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 679 680 if (rf_path >= rtwdev->chip->rf_path_num) { 681 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 682 return INV_RF_DATA; 683 } 684 685 if (ad_sel) 686 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 687 else 688 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask); 689 } 690 EXPORT_SYMBOL(rtw89_phy_read_rf_v1); 691 692 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 693 u32 addr, u32 mask, u32 data) 694 { 695 const struct rtw89_chip_info *chip = rtwdev->chip; 696 const u32 *base_addr = chip->rf_base_addr; 697 u32 direct_addr; 698 699 if (rf_path >= rtwdev->chip->rf_path_num) { 700 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 701 return false; 702 } 703 704 addr &= 0xff; 705 direct_addr = base_addr[rf_path] + (addr << 2); 706 mask &= RFREG_MASK; 707 708 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data); 709 710 /* delay to ensure writing properly */ 711 udelay(1); 712 713 return true; 714 } 715 EXPORT_SYMBOL(rtw89_phy_write_rf); 716 717 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev, 718 enum rtw89_rf_path rf_path, u32 addr, u32 mask, 719 u32 data) 720 { 721 u8 bit_shift; 722 u32 val; 723 bool busy, b_msk_en = false; 724 int ret; 725 726 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 727 1, 30, false, rtwdev); 728 if (ret) { 729 rtw89_err(rtwdev, "write rf busy swsi\n"); 730 return false; 731 } 732 733 data &= RFREG_MASK; 734 mask &= RFREG_MASK; 735 736 if (mask != RFREG_MASK) { 737 b_msk_en = true; 738 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK, 739 mask); 740 bit_shift = __ffs(mask); 741 data = (data << bit_shift) & RFREG_MASK; 742 } 743 744 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) | 745 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) | 746 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) | 747 FIELD_PREP(B_SWSI_DATA_VAL_V1, data); 748 749 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val); 750 751 return true; 752 } 753 754 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 755 u32 addr, u32 mask, u32 data) 756 { 757 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 758 759 if (rf_path >= rtwdev->chip->rf_path_num) { 760 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 761 return false; 762 } 763 764 if (ad_sel) 765 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 766 else 767 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data); 768 } 769 EXPORT_SYMBOL(rtw89_phy_write_rf_v1); 770 771 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev, 772 enum rtw89_phy_idx phy_idx) 773 { 774 const struct rtw89_chip_info *chip = rtwdev->chip; 775 776 chip->ops->bb_reset(rtwdev, phy_idx); 777 } 778 779 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev, 780 const struct rtw89_reg2_def *reg, 781 enum rtw89_rf_path rf_path, 782 void *extra_data) 783 { 784 if (reg->addr == 0xfe) 785 mdelay(50); 786 else if (reg->addr == 0xfd) 787 mdelay(5); 788 else if (reg->addr == 0xfc) 789 mdelay(1); 790 else if (reg->addr == 0xfb) 791 udelay(50); 792 else if (reg->addr == 0xfa) 793 udelay(5); 794 else if (reg->addr == 0xf9) 795 udelay(1); 796 else 797 rtw89_phy_write32(rtwdev, reg->addr, reg->data); 798 } 799 800 union rtw89_phy_bb_gain_arg { 801 u32 addr; 802 struct { 803 union { 804 u8 type; 805 struct { 806 u8 rxsc_start:4; 807 u8 bw:4; 808 }; 809 }; 810 u8 path; 811 u8 gain_band; 812 u8 cfg_type; 813 }; 814 } __packed; 815 816 static void 817 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev, 818 union rtw89_phy_bb_gain_arg arg, u32 data) 819 { 820 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 821 u8 type = arg.type; 822 u8 path = arg.path; 823 u8 gband = arg.gain_band; 824 int i; 825 826 switch (type) { 827 case 0: 828 for (i = 0; i < 4; i++, data >>= 8) 829 gain->lna_gain[gband][path][i] = data & 0xff; 830 break; 831 case 1: 832 for (i = 4; i < 7; i++, data >>= 8) 833 gain->lna_gain[gband][path][i] = data & 0xff; 834 break; 835 case 2: 836 for (i = 0; i < 2; i++, data >>= 8) 837 gain->tia_gain[gband][path][i] = data & 0xff; 838 break; 839 default: 840 rtw89_warn(rtwdev, 841 "bb gain error {0x%x:0x%x} with unknown type: %d\n", 842 arg.addr, data, type); 843 break; 844 } 845 } 846 847 enum rtw89_phy_bb_rxsc_start_idx { 848 RTW89_BB_RXSC_START_IDX_FULL = 0, 849 RTW89_BB_RXSC_START_IDX_20 = 1, 850 RTW89_BB_RXSC_START_IDX_20_1 = 5, 851 RTW89_BB_RXSC_START_IDX_40 = 9, 852 RTW89_BB_RXSC_START_IDX_80 = 13, 853 }; 854 855 static void 856 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev, 857 union rtw89_phy_bb_gain_arg arg, u32 data) 858 { 859 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 860 u8 rxsc_start = arg.rxsc_start; 861 u8 bw = arg.bw; 862 u8 path = arg.path; 863 u8 gband = arg.gain_band; 864 u8 rxsc; 865 s8 ofst; 866 int i; 867 868 switch (bw) { 869 case RTW89_CHANNEL_WIDTH_20: 870 gain->rpl_ofst_20[gband][path] = (s8)data; 871 break; 872 case RTW89_CHANNEL_WIDTH_40: 873 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 874 gain->rpl_ofst_40[gband][path][0] = (s8)data; 875 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 876 for (i = 0; i < 2; i++, data >>= 8) { 877 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 878 ofst = (s8)(data & 0xff); 879 gain->rpl_ofst_40[gband][path][rxsc] = ofst; 880 } 881 } 882 break; 883 case RTW89_CHANNEL_WIDTH_80: 884 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 885 gain->rpl_ofst_80[gband][path][0] = (s8)data; 886 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 887 for (i = 0; i < 4; i++, data >>= 8) { 888 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 889 ofst = (s8)(data & 0xff); 890 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 891 } 892 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 893 for (i = 0; i < 2; i++, data >>= 8) { 894 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 895 ofst = (s8)(data & 0xff); 896 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 897 } 898 } 899 break; 900 case RTW89_CHANNEL_WIDTH_160: 901 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 902 gain->rpl_ofst_160[gband][path][0] = (s8)data; 903 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 904 for (i = 0; i < 4; i++, data >>= 8) { 905 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 906 ofst = (s8)(data & 0xff); 907 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 908 } 909 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) { 910 for (i = 0; i < 4; i++, data >>= 8) { 911 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i; 912 ofst = (s8)(data & 0xff); 913 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 914 } 915 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 916 for (i = 0; i < 4; i++, data >>= 8) { 917 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 918 ofst = (s8)(data & 0xff); 919 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 920 } 921 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) { 922 for (i = 0; i < 2; i++, data >>= 8) { 923 rxsc = RTW89_BB_RXSC_START_IDX_80 + i; 924 ofst = (s8)(data & 0xff); 925 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 926 } 927 } 928 break; 929 default: 930 rtw89_warn(rtwdev, 931 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n", 932 arg.addr, data, bw); 933 break; 934 } 935 } 936 937 static void 938 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev, 939 union rtw89_phy_bb_gain_arg arg, u32 data) 940 { 941 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 942 u8 type = arg.type; 943 u8 path = arg.path; 944 u8 gband = arg.gain_band; 945 int i; 946 947 switch (type) { 948 case 0: 949 for (i = 0; i < 4; i++, data >>= 8) 950 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 951 break; 952 case 1: 953 for (i = 4; i < 7; i++, data >>= 8) 954 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 955 break; 956 default: 957 rtw89_warn(rtwdev, 958 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n", 959 arg.addr, data, type); 960 break; 961 } 962 } 963 964 static void 965 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev, 966 union rtw89_phy_bb_gain_arg arg, u32 data) 967 { 968 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain; 969 u8 type = arg.type; 970 u8 path = arg.path; 971 u8 gband = arg.gain_band; 972 int i; 973 974 switch (type) { 975 case 0: 976 for (i = 0; i < 4; i++, data >>= 8) 977 gain->lna_op1db[gband][path][i] = data & 0xff; 978 break; 979 case 1: 980 for (i = 4; i < 7; i++, data >>= 8) 981 gain->lna_op1db[gband][path][i] = data & 0xff; 982 break; 983 case 2: 984 for (i = 0; i < 4; i++, data >>= 8) 985 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 986 break; 987 case 3: 988 for (i = 4; i < 8; i++, data >>= 8) 989 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 990 break; 991 default: 992 rtw89_warn(rtwdev, 993 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n", 994 arg.addr, data, type); 995 break; 996 } 997 } 998 999 static void rtw89_phy_config_bb_gain(struct rtw89_dev *rtwdev, 1000 const struct rtw89_reg2_def *reg, 1001 enum rtw89_rf_path rf_path, 1002 void *extra_data) 1003 { 1004 const struct rtw89_chip_info *chip = rtwdev->chip; 1005 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr }; 1006 1007 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR) 1008 return; 1009 1010 if (arg.path >= chip->rf_path_num) 1011 return; 1012 1013 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) { 1014 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n"); 1015 return; 1016 } 1017 1018 switch (arg.cfg_type) { 1019 case 0: 1020 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data); 1021 break; 1022 case 1: 1023 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data); 1024 break; 1025 case 2: 1026 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data); 1027 break; 1028 case 3: 1029 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data); 1030 break; 1031 default: 1032 rtw89_warn(rtwdev, 1033 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n", 1034 arg.addr, reg->data, arg.cfg_type); 1035 break; 1036 } 1037 } 1038 1039 static void 1040 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, 1041 const struct rtw89_reg2_def *reg, 1042 enum rtw89_rf_path rf_path, 1043 struct rtw89_fw_h2c_rf_reg_info *info) 1044 { 1045 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; 1046 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; 1047 1048 if (page >= RTW89_H2C_RF_PAGE_NUM) { 1049 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d", 1050 rf_path, info->curr_idx); 1051 return; 1052 } 1053 1054 info->rtw89_phy_config_rf_h2c[page][idx] = 1055 cpu_to_le32((reg->addr << 20) | reg->data); 1056 info->curr_idx++; 1057 } 1058 1059 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, 1060 struct rtw89_fw_h2c_rf_reg_info *info) 1061 { 1062 u16 remain = info->curr_idx; 1063 u16 len = 0; 1064 u8 i; 1065 int ret = 0; 1066 1067 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) { 1068 rtw89_warn(rtwdev, 1069 "rf reg h2c total len %d larger than %d\n", 1070 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE); 1071 ret = -EINVAL; 1072 goto out; 1073 } 1074 1075 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) { 1076 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain; 1077 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i); 1078 if (ret) 1079 goto out; 1080 } 1081 out: 1082 info->curr_idx = 0; 1083 1084 return ret; 1085 } 1086 1087 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, 1088 const struct rtw89_reg2_def *reg, 1089 enum rtw89_rf_path rf_path, 1090 void *extra_data) 1091 { 1092 if (reg->addr == 0xfe) { 1093 mdelay(50); 1094 } else if (reg->addr == 0xfd) { 1095 mdelay(5); 1096 } else if (reg->addr == 0xfc) { 1097 mdelay(1); 1098 } else if (reg->addr == 0xfb) { 1099 udelay(50); 1100 } else if (reg->addr == 0xfa) { 1101 udelay(5); 1102 } else if (reg->addr == 0xf9) { 1103 udelay(1); 1104 } else { 1105 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data); 1106 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1107 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1108 } 1109 } 1110 1111 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 1112 const struct rtw89_reg2_def *reg, 1113 enum rtw89_rf_path rf_path, 1114 void *extra_data) 1115 { 1116 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data); 1117 1118 if (reg->addr < 0x100) 1119 return; 1120 1121 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1122 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1123 } 1124 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1); 1125 1126 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev, 1127 const struct rtw89_phy_table *table, 1128 u32 *headline_size, u32 *headline_idx, 1129 u8 rfe, u8 cv) 1130 { 1131 const struct rtw89_reg2_def *reg; 1132 u32 headline; 1133 u32 compare, target; 1134 u8 rfe_para, cv_para; 1135 u8 cv_max = 0; 1136 bool case_matched = false; 1137 u32 i; 1138 1139 for (i = 0; i < table->n_regs; i++) { 1140 reg = &table->regs[i]; 1141 headline = get_phy_headline(reg->addr); 1142 if (headline != PHY_HEADLINE_VALID) 1143 break; 1144 } 1145 *headline_size = i; 1146 if (*headline_size == 0) 1147 return 0; 1148 1149 /* case 1: RFE match, CV match */ 1150 compare = get_phy_compare(rfe, cv); 1151 for (i = 0; i < *headline_size; i++) { 1152 reg = &table->regs[i]; 1153 target = get_phy_target(reg->addr); 1154 if (target == compare) { 1155 *headline_idx = i; 1156 return 0; 1157 } 1158 } 1159 1160 /* case 2: RFE match, CV don't care */ 1161 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE); 1162 for (i = 0; i < *headline_size; i++) { 1163 reg = &table->regs[i]; 1164 target = get_phy_target(reg->addr); 1165 if (target == compare) { 1166 *headline_idx = i; 1167 return 0; 1168 } 1169 } 1170 1171 /* case 3: RFE match, CV max in table */ 1172 for (i = 0; i < *headline_size; i++) { 1173 reg = &table->regs[i]; 1174 rfe_para = get_phy_cond_rfe(reg->addr); 1175 cv_para = get_phy_cond_cv(reg->addr); 1176 if (rfe_para == rfe) { 1177 if (cv_para >= cv_max) { 1178 cv_max = cv_para; 1179 *headline_idx = i; 1180 case_matched = true; 1181 } 1182 } 1183 } 1184 1185 if (case_matched) 1186 return 0; 1187 1188 /* case 4: RFE don't care, CV max in table */ 1189 for (i = 0; i < *headline_size; i++) { 1190 reg = &table->regs[i]; 1191 rfe_para = get_phy_cond_rfe(reg->addr); 1192 cv_para = get_phy_cond_cv(reg->addr); 1193 if (rfe_para == PHY_COND_DONT_CARE) { 1194 if (cv_para >= cv_max) { 1195 cv_max = cv_para; 1196 *headline_idx = i; 1197 case_matched = true; 1198 } 1199 } 1200 } 1201 1202 if (case_matched) 1203 return 0; 1204 1205 return -EINVAL; 1206 } 1207 1208 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev, 1209 const struct rtw89_phy_table *table, 1210 void (*config)(struct rtw89_dev *rtwdev, 1211 const struct rtw89_reg2_def *reg, 1212 enum rtw89_rf_path rf_path, 1213 void *data), 1214 void *extra_data) 1215 { 1216 const struct rtw89_reg2_def *reg; 1217 enum rtw89_rf_path rf_path = table->rf_path; 1218 u8 rfe = rtwdev->efuse.rfe_type; 1219 u8 cv = rtwdev->hal.cv; 1220 u32 i; 1221 u32 headline_size = 0, headline_idx = 0; 1222 u32 target = 0, cfg_target; 1223 u8 cond; 1224 bool is_matched = true; 1225 bool target_found = false; 1226 int ret; 1227 1228 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size, 1229 &headline_idx, rfe, cv); 1230 if (ret) { 1231 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv); 1232 return; 1233 } 1234 1235 cfg_target = get_phy_target(table->regs[headline_idx].addr); 1236 for (i = headline_size; i < table->n_regs; i++) { 1237 reg = &table->regs[i]; 1238 cond = get_phy_cond(reg->addr); 1239 switch (cond) { 1240 case PHY_COND_BRANCH_IF: 1241 case PHY_COND_BRANCH_ELIF: 1242 target = get_phy_target(reg->addr); 1243 break; 1244 case PHY_COND_BRANCH_ELSE: 1245 is_matched = false; 1246 if (!target_found) { 1247 rtw89_warn(rtwdev, "failed to load CR %x/%x\n", 1248 reg->addr, reg->data); 1249 return; 1250 } 1251 break; 1252 case PHY_COND_BRANCH_END: 1253 is_matched = true; 1254 target_found = false; 1255 break; 1256 case PHY_COND_CHECK: 1257 if (target_found) { 1258 is_matched = false; 1259 break; 1260 } 1261 1262 if (target == cfg_target) { 1263 is_matched = true; 1264 target_found = true; 1265 } else { 1266 is_matched = false; 1267 target_found = false; 1268 } 1269 break; 1270 default: 1271 if (is_matched) 1272 config(rtwdev, reg, rf_path, extra_data); 1273 break; 1274 } 1275 } 1276 } 1277 1278 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev) 1279 { 1280 const struct rtw89_chip_info *chip = rtwdev->chip; 1281 const struct rtw89_phy_table *bb_table = chip->bb_table; 1282 const struct rtw89_phy_table *bb_gain_table = chip->bb_gain_table; 1283 1284 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL); 1285 rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 1286 if (bb_gain_table) 1287 rtw89_phy_init_reg(rtwdev, bb_gain_table, 1288 rtw89_phy_config_bb_gain, NULL); 1289 rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0); 1290 } 1291 1292 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) 1293 { 1294 rtw89_phy_write32(rtwdev, 0x8080, 0x4); 1295 udelay(1); 1296 return rtw89_phy_read32(rtwdev, 0x8080); 1297 } 1298 1299 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev) 1300 { 1301 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 1302 enum rtw89_rf_path rf_path, void *data); 1303 const struct rtw89_chip_info *chip = rtwdev->chip; 1304 const struct rtw89_phy_table *rf_table; 1305 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info; 1306 u8 path; 1307 1308 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL); 1309 if (!rf_reg_info) 1310 return; 1311 1312 for (path = RF_PATH_A; path < chip->rf_path_num; path++) { 1313 rf_table = chip->rf_table[path]; 1314 rf_reg_info->rf_path = rf_table->rf_path; 1315 config = rf_table->config ? rf_table->config : rtw89_phy_config_rf_reg; 1316 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info); 1317 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info)) 1318 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n", 1319 rf_reg_info->rf_path); 1320 } 1321 kfree(rf_reg_info); 1322 } 1323 1324 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev) 1325 { 1326 const struct rtw89_chip_info *chip = rtwdev->chip; 1327 const struct rtw89_phy_table *nctl_table; 1328 u32 val; 1329 int ret; 1330 1331 /* IQK/DPK clock & reset */ 1332 rtw89_phy_write32_set(rtwdev, 0x0c60, 0x3); 1333 rtw89_phy_write32_set(rtwdev, 0x0c6c, 0x1); 1334 rtw89_phy_write32_set(rtwdev, 0x58ac, 0x8000000); 1335 rtw89_phy_write32_set(rtwdev, 0x78ac, 0x8000000); 1336 1337 /* check 0x8080 */ 1338 rtw89_phy_write32(rtwdev, 0x8000, 0x8); 1339 1340 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, 1341 1000, false, rtwdev); 1342 if (ret) 1343 rtw89_err(rtwdev, "failed to poll nctl block\n"); 1344 1345 nctl_table = chip->nctl_table; 1346 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL); 1347 } 1348 1349 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) 1350 { 1351 u32 phy_page = addr >> 8; 1352 u32 ofst = 0; 1353 1354 switch (phy_page) { 1355 case 0x6: 1356 case 0x7: 1357 case 0x8: 1358 case 0x9: 1359 case 0xa: 1360 case 0xb: 1361 case 0xc: 1362 case 0xd: 1363 case 0x19: 1364 case 0x1a: 1365 case 0x1b: 1366 ofst = 0x2000; 1367 break; 1368 default: 1369 /* warning case */ 1370 ofst = 0; 1371 break; 1372 } 1373 1374 if (phy_page >= 0x40 && phy_page <= 0x4f) 1375 ofst = 0x2000; 1376 1377 return ofst; 1378 } 1379 1380 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1381 u32 data, enum rtw89_phy_idx phy_idx) 1382 { 1383 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1384 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1385 rtw89_phy_write32_mask(rtwdev, addr, mask, data); 1386 } 1387 EXPORT_SYMBOL(rtw89_phy_write32_idx); 1388 1389 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1390 u32 val) 1391 { 1392 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); 1393 1394 if (!rtwdev->dbcc_en) 1395 return; 1396 1397 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); 1398 } 1399 1400 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 1401 const struct rtw89_phy_reg3_tbl *tbl) 1402 { 1403 const struct rtw89_reg3_def *reg3; 1404 int i; 1405 1406 for (i = 0; i < tbl->size; i++) { 1407 reg3 = &tbl->reg3[i]; 1408 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data); 1409 } 1410 } 1411 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl); 1412 1413 const u8 rtw89_rs_idx_max[] = { 1414 [RTW89_RS_CCK] = RTW89_RATE_CCK_MAX, 1415 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_MAX, 1416 [RTW89_RS_MCS] = RTW89_RATE_MCS_MAX, 1417 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_MAX, 1418 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_MAX, 1419 }; 1420 EXPORT_SYMBOL(rtw89_rs_idx_max); 1421 1422 const u8 rtw89_rs_nss_max[] = { 1423 [RTW89_RS_CCK] = 1, 1424 [RTW89_RS_OFDM] = 1, 1425 [RTW89_RS_MCS] = RTW89_NSS_MAX, 1426 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_MAX, 1427 [RTW89_RS_OFFSET] = 1, 1428 }; 1429 EXPORT_SYMBOL(rtw89_rs_nss_max); 1430 1431 static const u8 _byr_of_rs[] = { 1432 [RTW89_RS_CCK] = offsetof(struct rtw89_txpwr_byrate, cck), 1433 [RTW89_RS_OFDM] = offsetof(struct rtw89_txpwr_byrate, ofdm), 1434 [RTW89_RS_MCS] = offsetof(struct rtw89_txpwr_byrate, mcs), 1435 [RTW89_RS_HEDCM] = offsetof(struct rtw89_txpwr_byrate, hedcm), 1436 [RTW89_RS_OFFSET] = offsetof(struct rtw89_txpwr_byrate, offset), 1437 }; 1438 1439 #define _byr_seek(rs, raw) ((s8 *)(raw) + _byr_of_rs[rs]) 1440 #define _byr_idx(rs, nss, idx) ((nss) * rtw89_rs_idx_max[rs] + (idx)) 1441 #define _byr_chk(rs, nss, idx) \ 1442 ((nss) < rtw89_rs_nss_max[rs] && (idx) < rtw89_rs_idx_max[rs]) 1443 1444 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 1445 const struct rtw89_txpwr_table *tbl) 1446 { 1447 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data; 1448 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size; 1449 s8 *byr; 1450 u32 data; 1451 u8 i, idx; 1452 1453 for (; cfg < end; cfg++) { 1454 byr = _byr_seek(cfg->rs, &rtwdev->byr[cfg->band]); 1455 data = cfg->data; 1456 1457 for (i = 0; i < cfg->len; i++, data >>= 8) { 1458 idx = _byr_idx(cfg->rs, cfg->nss, (cfg->shf + i)); 1459 byr[idx] = (s8)(data & 0xff); 1460 } 1461 } 1462 } 1463 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate); 1464 1465 #define _phy_txpwr_rf_to_mac(rtwdev, txpwr_rf) \ 1466 ({ \ 1467 const struct rtw89_chip_info *__c = (rtwdev)->chip; \ 1468 (txpwr_rf) >> (__c->txpwr_factor_rf - __c->txpwr_factor_mac); \ 1469 }) 1470 1471 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, 1472 const struct rtw89_rate_desc *rate_desc) 1473 { 1474 s8 *byr; 1475 u8 idx; 1476 1477 if (rate_desc->rs == RTW89_RS_CCK) 1478 band = RTW89_BAND_2G; 1479 1480 if (!_byr_chk(rate_desc->rs, rate_desc->nss, rate_desc->idx)) { 1481 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 1482 "[TXPWR] unknown byrate desc rs=%d nss=%d idx=%d\n", 1483 rate_desc->rs, rate_desc->nss, rate_desc->idx); 1484 1485 return 0; 1486 } 1487 1488 byr = _byr_seek(rate_desc->rs, &rtwdev->byr[band]); 1489 idx = _byr_idx(rate_desc->rs, rate_desc->nss, rate_desc->idx); 1490 1491 return _phy_txpwr_rf_to_mac(rtwdev, byr[idx]); 1492 } 1493 EXPORT_SYMBOL(rtw89_phy_read_txpwr_byrate); 1494 1495 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g) 1496 { 1497 switch (channel_6g) { 1498 case 1 ... 29: 1499 return (channel_6g - 1) / 2; 1500 case 33 ... 61: 1501 return (channel_6g - 3) / 2; 1502 case 65 ... 93: 1503 return (channel_6g - 5) / 2; 1504 case 97 ... 125: 1505 return (channel_6g - 7) / 2; 1506 case 129 ... 157: 1507 return (channel_6g - 9) / 2; 1508 case 161 ... 189: 1509 return (channel_6g - 11) / 2; 1510 case 193 ... 221: 1511 return (channel_6g - 13) / 2; 1512 case 225 ... 253: 1513 return (channel_6g - 15) / 2; 1514 default: 1515 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g); 1516 return 0; 1517 } 1518 } 1519 1520 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel) 1521 { 1522 if (band == RTW89_BAND_6G) 1523 return rtw89_channel_6g_to_idx(rtwdev, channel); 1524 1525 switch (channel) { 1526 case 1 ... 14: 1527 return channel - 1; 1528 case 36 ... 64: 1529 return (channel - 36) / 2; 1530 case 100 ... 144: 1531 return ((channel - 100) / 2) + 15; 1532 case 149 ... 177: 1533 return ((channel - 149) / 2) + 38; 1534 default: 1535 rtw89_warn(rtwdev, "unknown channel: %d\n", channel); 1536 return 0; 1537 } 1538 } 1539 1540 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 1541 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) 1542 { 1543 const struct rtw89_chip_info *chip = rtwdev->chip; 1544 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1545 u8 regd = rtw89_regd_get(rtwdev, band); 1546 s8 lmt = 0, sar; 1547 1548 switch (band) { 1549 case RTW89_BAND_2G: 1550 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf][regd][ch_idx]; 1551 if (!lmt) 1552 lmt = (*chip->txpwr_lmt_2g)[bw][ntx][rs][bf] 1553 [RTW89_WW][ch_idx]; 1554 break; 1555 case RTW89_BAND_5G: 1556 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf][regd][ch_idx]; 1557 if (!lmt) 1558 lmt = (*chip->txpwr_lmt_5g)[bw][ntx][rs][bf] 1559 [RTW89_WW][ch_idx]; 1560 break; 1561 case RTW89_BAND_6G: 1562 lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf][regd][ch_idx]; 1563 if (!lmt) 1564 lmt = (*chip->txpwr_lmt_6g)[bw][ntx][rs][bf] 1565 [RTW89_WW][ch_idx]; 1566 break; 1567 default: 1568 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1569 return 0; 1570 } 1571 1572 lmt = _phy_txpwr_rf_to_mac(rtwdev, lmt); 1573 sar = rtw89_query_sar(rtwdev); 1574 1575 return min(lmt, sar); 1576 } 1577 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit); 1578 1579 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \ 1580 do { \ 1581 u8 __i; \ 1582 for (__i = 0; __i < RTW89_BF_NUM; __i++) \ 1583 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \ 1584 band, \ 1585 bw, ntx, \ 1586 rs, __i, \ 1587 (ch)); \ 1588 } while (0) 1589 1590 static void rtw89_phy_fill_txpwr_limit_20m(struct rtw89_dev *rtwdev, 1591 struct rtw89_txpwr_limit *lmt, 1592 u8 band, u8 ntx, u8 ch) 1593 { 1594 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 1595 ntx, RTW89_RS_CCK, ch); 1596 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 1597 ntx, RTW89_RS_CCK, ch); 1598 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1599 ntx, RTW89_RS_OFDM, ch); 1600 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1601 RTW89_CHANNEL_WIDTH_20, 1602 ntx, RTW89_RS_MCS, ch); 1603 } 1604 1605 static void rtw89_phy_fill_txpwr_limit_40m(struct rtw89_dev *rtwdev, 1606 struct rtw89_txpwr_limit *lmt, 1607 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1608 { 1609 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 1610 ntx, RTW89_RS_CCK, ch - 2); 1611 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 1612 ntx, RTW89_RS_CCK, ch); 1613 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1614 ntx, RTW89_RS_OFDM, pri_ch); 1615 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1616 RTW89_CHANNEL_WIDTH_20, 1617 ntx, RTW89_RS_MCS, ch - 2); 1618 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1619 RTW89_CHANNEL_WIDTH_20, 1620 ntx, RTW89_RS_MCS, ch + 2); 1621 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1622 RTW89_CHANNEL_WIDTH_40, 1623 ntx, RTW89_RS_MCS, ch); 1624 } 1625 1626 static void rtw89_phy_fill_txpwr_limit_80m(struct rtw89_dev *rtwdev, 1627 struct rtw89_txpwr_limit *lmt, 1628 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1629 { 1630 s8 val_0p5_n[RTW89_BF_NUM]; 1631 s8 val_0p5_p[RTW89_BF_NUM]; 1632 u8 i; 1633 1634 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1635 ntx, RTW89_RS_OFDM, pri_ch); 1636 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1637 RTW89_CHANNEL_WIDTH_20, 1638 ntx, RTW89_RS_MCS, ch - 6); 1639 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1640 RTW89_CHANNEL_WIDTH_20, 1641 ntx, RTW89_RS_MCS, ch - 2); 1642 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 1643 RTW89_CHANNEL_WIDTH_20, 1644 ntx, RTW89_RS_MCS, ch + 2); 1645 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 1646 RTW89_CHANNEL_WIDTH_20, 1647 ntx, RTW89_RS_MCS, ch + 6); 1648 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1649 RTW89_CHANNEL_WIDTH_40, 1650 ntx, RTW89_RS_MCS, ch - 4); 1651 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 1652 RTW89_CHANNEL_WIDTH_40, 1653 ntx, RTW89_RS_MCS, ch + 4); 1654 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 1655 RTW89_CHANNEL_WIDTH_80, 1656 ntx, RTW89_RS_MCS, ch); 1657 1658 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 1659 ntx, RTW89_RS_MCS, ch - 4); 1660 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 1661 ntx, RTW89_RS_MCS, ch + 4); 1662 1663 for (i = 0; i < RTW89_BF_NUM; i++) 1664 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1665 } 1666 1667 static void rtw89_phy_fill_txpwr_limit_160m(struct rtw89_dev *rtwdev, 1668 struct rtw89_txpwr_limit *lmt, 1669 u8 band, u8 ntx, u8 ch, u8 pri_ch) 1670 { 1671 s8 val_0p5_n[RTW89_BF_NUM]; 1672 s8 val_0p5_p[RTW89_BF_NUM]; 1673 s8 val_2p5_n[RTW89_BF_NUM]; 1674 s8 val_2p5_p[RTW89_BF_NUM]; 1675 u8 i; 1676 1677 /* fill ofdm section */ 1678 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 1679 ntx, RTW89_RS_OFDM, pri_ch); 1680 1681 /* fill mcs 20m section */ 1682 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 1683 RTW89_CHANNEL_WIDTH_20, 1684 ntx, RTW89_RS_MCS, ch - 14); 1685 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 1686 RTW89_CHANNEL_WIDTH_20, 1687 ntx, RTW89_RS_MCS, ch - 10); 1688 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 1689 RTW89_CHANNEL_WIDTH_20, 1690 ntx, RTW89_RS_MCS, ch - 6); 1691 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 1692 RTW89_CHANNEL_WIDTH_20, 1693 ntx, RTW89_RS_MCS, ch - 2); 1694 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band, 1695 RTW89_CHANNEL_WIDTH_20, 1696 ntx, RTW89_RS_MCS, ch + 2); 1697 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band, 1698 RTW89_CHANNEL_WIDTH_20, 1699 ntx, RTW89_RS_MCS, ch + 6); 1700 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band, 1701 RTW89_CHANNEL_WIDTH_20, 1702 ntx, RTW89_RS_MCS, ch + 10); 1703 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band, 1704 RTW89_CHANNEL_WIDTH_20, 1705 ntx, RTW89_RS_MCS, ch + 14); 1706 1707 /* fill mcs 40m section */ 1708 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 1709 RTW89_CHANNEL_WIDTH_40, 1710 ntx, RTW89_RS_MCS, ch - 12); 1711 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 1712 RTW89_CHANNEL_WIDTH_40, 1713 ntx, RTW89_RS_MCS, ch - 4); 1714 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band, 1715 RTW89_CHANNEL_WIDTH_40, 1716 ntx, RTW89_RS_MCS, ch + 4); 1717 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band, 1718 RTW89_CHANNEL_WIDTH_40, 1719 ntx, RTW89_RS_MCS, ch + 12); 1720 1721 /* fill mcs 80m section */ 1722 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 1723 RTW89_CHANNEL_WIDTH_80, 1724 ntx, RTW89_RS_MCS, ch - 8); 1725 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band, 1726 RTW89_CHANNEL_WIDTH_80, 1727 ntx, RTW89_RS_MCS, ch + 8); 1728 1729 /* fill mcs 160m section */ 1730 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band, 1731 RTW89_CHANNEL_WIDTH_160, 1732 ntx, RTW89_RS_MCS, ch); 1733 1734 /* fill mcs 40m 0p5 section */ 1735 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 1736 ntx, RTW89_RS_MCS, ch - 4); 1737 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 1738 ntx, RTW89_RS_MCS, ch + 4); 1739 1740 for (i = 0; i < RTW89_BF_NUM; i++) 1741 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 1742 1743 /* fill mcs 40m 2p5 section */ 1744 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40, 1745 ntx, RTW89_RS_MCS, ch - 8); 1746 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40, 1747 ntx, RTW89_RS_MCS, ch + 8); 1748 1749 for (i = 0; i < RTW89_BF_NUM; i++) 1750 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]); 1751 } 1752 1753 void rtw89_phy_fill_txpwr_limit(struct rtw89_dev *rtwdev, 1754 const struct rtw89_chan *chan, 1755 struct rtw89_txpwr_limit *lmt, 1756 u8 ntx) 1757 { 1758 u8 band = chan->band_type; 1759 u8 pri_ch = chan->primary_channel; 1760 u8 ch = chan->channel; 1761 u8 bw = chan->band_width; 1762 1763 memset(lmt, 0, sizeof(*lmt)); 1764 1765 switch (bw) { 1766 case RTW89_CHANNEL_WIDTH_20: 1767 rtw89_phy_fill_txpwr_limit_20m(rtwdev, lmt, band, ntx, ch); 1768 break; 1769 case RTW89_CHANNEL_WIDTH_40: 1770 rtw89_phy_fill_txpwr_limit_40m(rtwdev, lmt, band, ntx, ch, 1771 pri_ch); 1772 break; 1773 case RTW89_CHANNEL_WIDTH_80: 1774 rtw89_phy_fill_txpwr_limit_80m(rtwdev, lmt, band, ntx, ch, 1775 pri_ch); 1776 break; 1777 case RTW89_CHANNEL_WIDTH_160: 1778 rtw89_phy_fill_txpwr_limit_160m(rtwdev, lmt, band, ntx, ch, 1779 pri_ch); 1780 break; 1781 } 1782 } 1783 EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit); 1784 1785 static s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, 1786 u8 ru, u8 ntx, u8 ch) 1787 { 1788 const struct rtw89_chip_info *chip = rtwdev->chip; 1789 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1790 u8 regd = rtw89_regd_get(rtwdev, band); 1791 s8 lmt_ru = 0, sar; 1792 1793 switch (band) { 1794 case RTW89_BAND_2G: 1795 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx][regd][ch_idx]; 1796 if (!lmt_ru) 1797 lmt_ru = (*chip->txpwr_lmt_ru_2g)[ru][ntx] 1798 [RTW89_WW][ch_idx]; 1799 break; 1800 case RTW89_BAND_5G: 1801 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx][regd][ch_idx]; 1802 if (!lmt_ru) 1803 lmt_ru = (*chip->txpwr_lmt_ru_5g)[ru][ntx] 1804 [RTW89_WW][ch_idx]; 1805 break; 1806 case RTW89_BAND_6G: 1807 lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx][regd][ch_idx]; 1808 if (!lmt_ru) 1809 lmt_ru = (*chip->txpwr_lmt_ru_6g)[ru][ntx] 1810 [RTW89_WW][ch_idx]; 1811 break; 1812 default: 1813 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1814 return 0; 1815 } 1816 1817 lmt_ru = _phy_txpwr_rf_to_mac(rtwdev, lmt_ru); 1818 sar = rtw89_query_sar(rtwdev); 1819 1820 return min(lmt_ru, sar); 1821 } 1822 1823 static void 1824 rtw89_phy_fill_txpwr_limit_ru_20m(struct rtw89_dev *rtwdev, 1825 struct rtw89_txpwr_limit_ru *lmt_ru, 1826 u8 band, u8 ntx, u8 ch) 1827 { 1828 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1829 RTW89_RU26, 1830 ntx, ch); 1831 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1832 RTW89_RU52, 1833 ntx, ch); 1834 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1835 RTW89_RU106, 1836 ntx, ch); 1837 } 1838 1839 static void 1840 rtw89_phy_fill_txpwr_limit_ru_40m(struct rtw89_dev *rtwdev, 1841 struct rtw89_txpwr_limit_ru *lmt_ru, 1842 u8 band, u8 ntx, u8 ch) 1843 { 1844 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1845 RTW89_RU26, 1846 ntx, ch - 2); 1847 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1848 RTW89_RU26, 1849 ntx, ch + 2); 1850 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1851 RTW89_RU52, 1852 ntx, ch - 2); 1853 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1854 RTW89_RU52, 1855 ntx, ch + 2); 1856 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1857 RTW89_RU106, 1858 ntx, ch - 2); 1859 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1860 RTW89_RU106, 1861 ntx, ch + 2); 1862 } 1863 1864 static void 1865 rtw89_phy_fill_txpwr_limit_ru_80m(struct rtw89_dev *rtwdev, 1866 struct rtw89_txpwr_limit_ru *lmt_ru, 1867 u8 band, u8 ntx, u8 ch) 1868 { 1869 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1870 RTW89_RU26, 1871 ntx, ch - 6); 1872 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1873 RTW89_RU26, 1874 ntx, ch - 2); 1875 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1876 RTW89_RU26, 1877 ntx, ch + 2); 1878 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1879 RTW89_RU26, 1880 ntx, ch + 6); 1881 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1882 RTW89_RU52, 1883 ntx, ch - 6); 1884 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1885 RTW89_RU52, 1886 ntx, ch - 2); 1887 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1888 RTW89_RU52, 1889 ntx, ch + 2); 1890 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1891 RTW89_RU52, 1892 ntx, ch + 6); 1893 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1894 RTW89_RU106, 1895 ntx, ch - 6); 1896 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1897 RTW89_RU106, 1898 ntx, ch - 2); 1899 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1900 RTW89_RU106, 1901 ntx, ch + 2); 1902 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1903 RTW89_RU106, 1904 ntx, ch + 6); 1905 } 1906 1907 static void 1908 rtw89_phy_fill_txpwr_limit_ru_160m(struct rtw89_dev *rtwdev, 1909 struct rtw89_txpwr_limit_ru *lmt_ru, 1910 u8 band, u8 ntx, u8 ch) 1911 { 1912 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 }; 1913 int i; 1914 1915 #if defined(__linux__) 1916 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM); 1917 #elif defined(__FreeBSD__) 1918 rtw89_static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM); 1919 #endif 1920 for (i = 0; i < RTW89_RU_SEC_NUM; i++) { 1921 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1922 RTW89_RU26, 1923 ntx, 1924 ch + ofst[i]); 1925 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1926 RTW89_RU52, 1927 ntx, 1928 ch + ofst[i]); 1929 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 1930 RTW89_RU106, 1931 ntx, 1932 ch + ofst[i]); 1933 } 1934 } 1935 1936 void rtw89_phy_fill_txpwr_limit_ru(struct rtw89_dev *rtwdev, 1937 const struct rtw89_chan *chan, 1938 struct rtw89_txpwr_limit_ru *lmt_ru, 1939 u8 ntx) 1940 { 1941 u8 band = chan->band_type; 1942 u8 ch = chan->channel; 1943 u8 bw = chan->band_width; 1944 1945 memset(lmt_ru, 0, sizeof(*lmt_ru)); 1946 1947 switch (bw) { 1948 case RTW89_CHANNEL_WIDTH_20: 1949 rtw89_phy_fill_txpwr_limit_ru_20m(rtwdev, lmt_ru, band, ntx, 1950 ch); 1951 break; 1952 case RTW89_CHANNEL_WIDTH_40: 1953 rtw89_phy_fill_txpwr_limit_ru_40m(rtwdev, lmt_ru, band, ntx, 1954 ch); 1955 break; 1956 case RTW89_CHANNEL_WIDTH_80: 1957 rtw89_phy_fill_txpwr_limit_ru_80m(rtwdev, lmt_ru, band, ntx, 1958 ch); 1959 break; 1960 case RTW89_CHANNEL_WIDTH_160: 1961 rtw89_phy_fill_txpwr_limit_ru_160m(rtwdev, lmt_ru, band, ntx, 1962 ch); 1963 break; 1964 } 1965 } 1966 EXPORT_SYMBOL(rtw89_phy_fill_txpwr_limit_ru); 1967 1968 struct rtw89_phy_iter_ra_data { 1969 struct rtw89_dev *rtwdev; 1970 struct sk_buff *c2h; 1971 }; 1972 1973 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta) 1974 { 1975 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data; 1976 struct rtw89_dev *rtwdev = ra_data->rtwdev; 1977 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1978 struct rtw89_ra_report *ra_report = &rtwsta->ra_report; 1979 struct sk_buff *c2h = ra_data->c2h; 1980 u8 mode, rate, bw, giltf, mac_id; 1981 u16 legacy_bitrate; 1982 bool valid; 1983 u8 mcs = 0; 1984 1985 mac_id = RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h->data); 1986 if (mac_id != rtwsta->mac_id) 1987 return; 1988 1989 rate = RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h->data); 1990 bw = RTW89_GET_PHY_C2H_RA_RPT_BW(c2h->data); 1991 giltf = RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h->data); 1992 mode = RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h->data); 1993 1994 if (mode == RTW89_RA_RPT_MODE_LEGACY) { 1995 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate); 1996 if (!valid) 1997 return; 1998 } 1999 2000 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate)); 2001 2002 switch (mode) { 2003 case RTW89_RA_RPT_MODE_LEGACY: 2004 ra_report->txrate.legacy = legacy_bitrate; 2005 break; 2006 case RTW89_RA_RPT_MODE_HT: 2007 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS; 2008 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw)) 2009 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate), 2010 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate)); 2011 else 2012 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate); 2013 ra_report->txrate.mcs = rate; 2014 if (giltf) 2015 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2016 mcs = ra_report->txrate.mcs & 0x07; 2017 break; 2018 case RTW89_RA_RPT_MODE_VHT: 2019 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS; 2020 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 2021 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 2022 if (giltf) 2023 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2024 mcs = ra_report->txrate.mcs; 2025 break; 2026 case RTW89_RA_RPT_MODE_HE: 2027 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS; 2028 ra_report->txrate.mcs = FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate); 2029 ra_report->txrate.nss = FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate) + 1; 2030 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 2031 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8; 2032 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 2033 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6; 2034 else 2035 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2; 2036 mcs = ra_report->txrate.mcs; 2037 break; 2038 } 2039 2040 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw); 2041 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate); 2042 ra_report->hw_rate = FIELD_PREP(RTW89_HW_RATE_MASK_MOD, mode) | 2043 FIELD_PREP(RTW89_HW_RATE_MASK_VAL, rate); 2044 ra_report->might_fallback_legacy = mcs <= 2; 2045 sta->max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report); 2046 rtwsta->max_agg_wait = sta->max_rc_amsdu_len / 1500 - 1; 2047 } 2048 2049 static void 2050 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2051 { 2052 struct rtw89_phy_iter_ra_data ra_data; 2053 2054 ra_data.rtwdev = rtwdev; 2055 ra_data.c2h = c2h; 2056 ieee80211_iterate_stations_atomic(rtwdev->hw, 2057 rtw89_phy_c2h_ra_rpt_iter, 2058 &ra_data); 2059 } 2060 2061 static 2062 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, 2063 struct sk_buff *c2h, u32 len) = { 2064 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, 2065 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, 2066 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, 2067 }; 2068 2069 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 2070 u32 len, u8 class, u8 func) 2071 { 2072 void (*handler)(struct rtw89_dev *rtwdev, 2073 struct sk_buff *c2h, u32 len) = NULL; 2074 2075 switch (class) { 2076 case RTW89_PHY_C2H_CLASS_RA: 2077 if (func < RTW89_PHY_C2H_FUNC_RA_MAX) 2078 handler = rtw89_phy_c2h_ra_handler[func]; 2079 break; 2080 default: 2081 rtw89_info(rtwdev, "c2h class %d not support\n", class); 2082 return; 2083 } 2084 if (!handler) { 2085 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 2086 func); 2087 return; 2088 } 2089 handler(rtwdev, skb, len); 2090 } 2091 2092 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo) 2093 { 2094 u32 reg_mask; 2095 2096 if (sc_xo) 2097 reg_mask = B_AX_XTAL_SC_XO_MASK; 2098 else 2099 reg_mask = B_AX_XTAL_SC_XI_MASK; 2100 2101 return (u8)rtw89_read32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask); 2102 } 2103 2104 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo, 2105 u8 val) 2106 { 2107 u32 reg_mask; 2108 2109 if (sc_xo) 2110 reg_mask = B_AX_XTAL_SC_XO_MASK; 2111 else 2112 reg_mask = B_AX_XTAL_SC_XI_MASK; 2113 2114 rtw89_write32_mask(rtwdev, R_AX_XTAL_ON_CTRL0, reg_mask, val); 2115 } 2116 2117 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev, 2118 u8 crystal_cap, bool force) 2119 { 2120 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2121 const struct rtw89_chip_info *chip = rtwdev->chip; 2122 u8 sc_xi_val, sc_xo_val; 2123 2124 if (!force && cfo->crystal_cap == crystal_cap) 2125 return; 2126 crystal_cap = clamp_t(u8, crystal_cap, 0, 127); 2127 if (chip->chip_id == RTL8852A) { 2128 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap); 2129 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap); 2130 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true); 2131 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false); 2132 } else { 2133 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, 2134 crystal_cap, XTAL_SC_XO_MASK); 2135 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, 2136 crystal_cap, XTAL_SC_XI_MASK); 2137 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val); 2138 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val); 2139 } 2140 cfo->crystal_cap = sc_xi_val; 2141 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap); 2142 2143 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val); 2144 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val); 2145 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n", 2146 cfo->x_cap_ofst); 2147 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n"); 2148 } 2149 2150 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev) 2151 { 2152 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2153 u8 cap; 2154 2155 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK; 2156 cfo->is_adjust = false; 2157 if (cfo->crystal_cap == cfo->def_x_cap) 2158 return; 2159 cap = cfo->crystal_cap; 2160 cap += (cap > cfo->def_x_cap ? -1 : 1); 2161 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false); 2162 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2163 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap, 2164 cfo->def_x_cap); 2165 } 2166 2167 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo) 2168 { 2169 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp; 2170 bool is_linked = rtwdev->total_sta_assoc > 0; 2171 s32 cfo_avg_312; 2172 s32 dcfo_comp_val; 2173 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft; 2174 int sign; 2175 2176 if (!is_linked) { 2177 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n", 2178 is_linked); 2179 return; 2180 } 2181 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo); 2182 if (curr_cfo == 0) 2183 return; 2184 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO); 2185 sign = curr_cfo > 0 ? 1 : -1; 2186 cfo_avg_312 = (curr_cfo << dcfo_comp_sft) / 5 + sign * dcfo_comp_val; 2187 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: avg_cfo=%d\n", cfo_avg_312); 2188 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) 2189 cfo_avg_312 = -cfo_avg_312; 2190 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask, 2191 cfo_avg_312); 2192 } 2193 2194 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev) 2195 { 2196 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_OPT, B_DCFO_OPT_EN, 1); 2197 rtw89_phy_set_phy_regs(rtwdev, R_DCFO_WEIGHT, B_DCFO_WEIGHT_MSK, 8); 2198 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, B_AX_PWR_UL_CFO_MASK); 2199 } 2200 2201 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev) 2202 { 2203 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2204 struct rtw89_efuse *efuse = &rtwdev->efuse; 2205 2206 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK; 2207 cfo->crystal_cap = cfo->crystal_cap_default; 2208 cfo->def_x_cap = cfo->crystal_cap; 2209 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f); 2210 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1); 2211 cfo->is_adjust = false; 2212 cfo->divergence_lock_en = false; 2213 cfo->x_cap_ofst = 0; 2214 cfo->lock_cnt = 0; 2215 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE; 2216 cfo->apply_compensation = false; 2217 cfo->residual_cfo_acc = 0; 2218 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n", 2219 cfo->crystal_cap_default); 2220 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true); 2221 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1); 2222 rtw89_dcfo_comp_init(rtwdev); 2223 cfo->cfo_timer_ms = 2000; 2224 cfo->cfo_trig_by_timer_en = false; 2225 cfo->phy_cfo_trk_cnt = 0; 2226 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2227 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE; 2228 } 2229 2230 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev, 2231 s32 curr_cfo) 2232 { 2233 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2234 s8 crystal_cap = cfo->crystal_cap; 2235 s32 cfo_abs = abs(curr_cfo); 2236 int sign; 2237 2238 if (!cfo->is_adjust) { 2239 if (cfo_abs > CFO_TRK_ENABLE_TH) 2240 cfo->is_adjust = true; 2241 } else { 2242 if (cfo_abs < CFO_TRK_STOP_TH) 2243 cfo->is_adjust = false; 2244 } 2245 if (!cfo->is_adjust) { 2246 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n"); 2247 return; 2248 } 2249 sign = curr_cfo > 0 ? 1 : -1; 2250 if (cfo_abs > CFO_TRK_STOP_TH_4) 2251 crystal_cap += 7 * sign; 2252 else if (cfo_abs > CFO_TRK_STOP_TH_3) 2253 crystal_cap += 5 * sign; 2254 else if (cfo_abs > CFO_TRK_STOP_TH_2) 2255 crystal_cap += 3 * sign; 2256 else if (cfo_abs > CFO_TRK_STOP_TH_1) 2257 crystal_cap += 1 * sign; 2258 else 2259 return; 2260 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false); 2261 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2262 "X_cap{Curr,Default}={0x%x,0x%x}\n", 2263 cfo->crystal_cap, cfo->def_x_cap); 2264 } 2265 2266 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev) 2267 { 2268 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2269 s32 cfo_khz_all = 0; 2270 s32 cfo_cnt_all = 0; 2271 s32 cfo_all_avg = 0; 2272 u8 i; 2273 2274 if (rtwdev->total_sta_assoc != 1) 2275 return 0; 2276 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n"); 2277 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2278 if (cfo->cfo_cnt[i] == 0) 2279 continue; 2280 cfo_khz_all += cfo->cfo_tail[i]; 2281 cfo_cnt_all += cfo->cfo_cnt[i]; 2282 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all); 2283 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2284 } 2285 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2286 "CFO track for macid = %d\n", i); 2287 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2288 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n", 2289 cfo_khz_all, cfo_cnt_all, cfo_all_avg); 2290 return cfo_all_avg; 2291 } 2292 2293 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) 2294 { 2295 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2296 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2297 s32 target_cfo = 0; 2298 s32 cfo_khz_all = 0; 2299 s32 cfo_khz_all_tp_wgt = 0; 2300 s32 cfo_avg = 0; 2301 s32 max_cfo_lb = BIT(31); 2302 s32 min_cfo_ub = GENMASK(30, 0); 2303 u16 cfo_cnt_all = 0; 2304 u8 active_entry_cnt = 0; 2305 u8 sta_cnt = 0; 2306 u32 tp_all = 0; 2307 u8 i; 2308 u8 cfo_tol = 0; 2309 2310 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n"); 2311 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) { 2312 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n"); 2313 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2314 if (cfo->cfo_cnt[i] == 0) 2315 continue; 2316 cfo_khz_all += cfo->cfo_tail[i]; 2317 cfo_cnt_all += cfo->cfo_cnt[i]; 2318 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all); 2319 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2320 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n", 2321 cfo_khz_all, cfo_cnt_all, cfo_avg); 2322 target_cfo = cfo_avg; 2323 } 2324 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) { 2325 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n"); 2326 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2327 if (cfo->cfo_cnt[i] == 0) 2328 continue; 2329 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2330 (s32)cfo->cfo_cnt[i]); 2331 cfo_khz_all += cfo->cfo_avg[i]; 2332 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2333 "Macid=%d, cfo_avg=%d\n", i, 2334 cfo->cfo_avg[i]); 2335 } 2336 sta_cnt = rtwdev->total_sta_assoc; 2337 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt); 2338 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2339 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n", 2340 cfo_khz_all, sta_cnt, cfo_avg); 2341 target_cfo = cfo_avg; 2342 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) { 2343 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n"); 2344 cfo_tol = cfo->sta_cfo_tolerance; 2345 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 2346 sta_cnt++; 2347 if (cfo->cfo_cnt[i] != 0) { 2348 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 2349 (s32)cfo->cfo_cnt[i]); 2350 active_entry_cnt++; 2351 } else { 2352 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i]; 2353 } 2354 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb); 2355 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub); 2356 cfo_khz_all += cfo->cfo_avg[i]; 2357 /* need tp for each entry */ 2358 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2359 "[%d] cfo_avg=%d, tp=tbd\n", 2360 i, cfo->cfo_avg[i]); 2361 if (sta_cnt >= rtwdev->total_sta_assoc) 2362 break; 2363 } 2364 tp_all = stats->rx_throughput; /* need tp for each entry */ 2365 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all); 2366 2367 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n", 2368 sta_cnt); 2369 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n", 2370 active_entry_cnt); 2371 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2372 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n", 2373 cfo_khz_all_tp_wgt, cfo_avg); 2374 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n", 2375 max_cfo_lb, min_cfo_ub); 2376 if (max_cfo_lb <= min_cfo_ub) { 2377 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2378 "cfo win_size=%d\n", 2379 min_cfo_ub - max_cfo_lb); 2380 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); 2381 } else { 2382 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2383 "No intersection of cfo tolerance windows\n"); 2384 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); 2385 } 2386 for (i = 0; i < CFO_TRACK_MAX_USER; i++) 2387 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 2388 } 2389 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo); 2390 return target_cfo; 2391 } 2392 2393 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev) 2394 { 2395 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2396 2397 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail)); 2398 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt)); 2399 cfo->packet_count = 0; 2400 cfo->packet_count_pre = 0; 2401 cfo->cfo_avg_pre = 0; 2402 } 2403 2404 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) 2405 { 2406 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2407 s32 new_cfo = 0; 2408 bool x_cap_update = false; 2409 u8 pre_x_cap = cfo->crystal_cap; 2410 2411 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n", 2412 rtwdev->total_sta_assoc); 2413 if (rtwdev->total_sta_assoc == 0) { 2414 rtw89_phy_cfo_reset(rtwdev); 2415 return; 2416 } 2417 if (cfo->packet_count == 0) { 2418 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n"); 2419 return; 2420 } 2421 if (cfo->packet_count == cfo->packet_count_pre) { 2422 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n"); 2423 return; 2424 } 2425 if (rtwdev->total_sta_assoc == 1) 2426 new_cfo = rtw89_phy_average_cfo_calc(rtwdev); 2427 else 2428 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev); 2429 if (new_cfo == 0) { 2430 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n"); 2431 return; 2432 } 2433 if (cfo->divergence_lock_en) { 2434 cfo->lock_cnt++; 2435 if (cfo->lock_cnt > CFO_PERIOD_CNT) { 2436 cfo->divergence_lock_en = false; 2437 cfo->lock_cnt = 0; 2438 } else { 2439 rtw89_phy_cfo_reset(rtwdev); 2440 } 2441 return; 2442 } 2443 if (cfo->crystal_cap >= cfo->x_cap_ub || 2444 cfo->crystal_cap <= cfo->x_cap_lb) { 2445 cfo->divergence_lock_en = true; 2446 rtw89_phy_cfo_reset(rtwdev); 2447 return; 2448 } 2449 2450 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); 2451 cfo->cfo_avg_pre = new_cfo; 2452 x_cap_update = cfo->crystal_cap != pre_x_cap; 2453 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); 2454 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", 2455 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, 2456 cfo->x_cap_ofst); 2457 if (x_cap_update) { 2458 if (new_cfo > 0) 2459 new_cfo -= CFO_SW_COMP_FINE_TUNE; 2460 else 2461 new_cfo += CFO_SW_COMP_FINE_TUNE; 2462 } 2463 rtw89_dcfo_comp(rtwdev, new_cfo); 2464 rtw89_phy_cfo_statistics_reset(rtwdev); 2465 } 2466 2467 void rtw89_phy_cfo_track_work(struct work_struct *work) 2468 { 2469 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2470 cfo_track_work.work); 2471 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2472 2473 mutex_lock(&rtwdev->mutex); 2474 if (!cfo->cfo_trig_by_timer_en) 2475 goto out; 2476 rtw89_leave_ps_mode(rtwdev); 2477 rtw89_phy_cfo_dm(rtwdev); 2478 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2479 msecs_to_jiffies(cfo->cfo_timer_ms)); 2480 out: 2481 mutex_unlock(&rtwdev->mutex); 2482 } 2483 2484 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev) 2485 { 2486 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2487 2488 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 2489 msecs_to_jiffies(cfo->cfo_timer_ms)); 2490 } 2491 2492 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev) 2493 { 2494 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2495 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2496 bool is_ul_ofdma = false, ofdma_acc_en = false; 2497 2498 if (stats->rx_tf_periodic > CFO_TF_CNT_TH) 2499 is_ul_ofdma = true; 2500 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE && 2501 is_ul_ofdma) 2502 ofdma_acc_en = true; 2503 2504 switch (cfo->phy_cfo_status) { 2505 case RTW89_PHY_DCFO_STATE_NORMAL: 2506 if (stats->tx_throughput >= CFO_TP_UPPER) { 2507 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE; 2508 cfo->cfo_trig_by_timer_en = true; 2509 cfo->cfo_timer_ms = CFO_COMP_PERIOD; 2510 rtw89_phy_cfo_start_work(rtwdev); 2511 } 2512 break; 2513 case RTW89_PHY_DCFO_STATE_ENHANCE: 2514 if (stats->tx_throughput <= CFO_TP_LOWER) 2515 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2516 else if (ofdma_acc_en && 2517 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) 2518 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD; 2519 else 2520 cfo->phy_cfo_trk_cnt++; 2521 2522 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) { 2523 cfo->phy_cfo_trk_cnt = 0; 2524 cfo->cfo_trig_by_timer_en = false; 2525 } 2526 break; 2527 case RTW89_PHY_DCFO_STATE_HOLD: 2528 if (stats->tx_throughput <= CFO_TP_LOWER) { 2529 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2530 cfo->phy_cfo_trk_cnt = 0; 2531 cfo->cfo_trig_by_timer_en = false; 2532 } else { 2533 cfo->phy_cfo_trk_cnt++; 2534 } 2535 break; 2536 default: 2537 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 2538 cfo->phy_cfo_trk_cnt = 0; 2539 break; 2540 } 2541 rtw89_debug(rtwdev, RTW89_DBG_CFO, 2542 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n", 2543 stats->tx_throughput, cfo->phy_cfo_status, 2544 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt, 2545 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0])); 2546 if (cfo->cfo_trig_by_timer_en) 2547 return; 2548 rtw89_phy_cfo_dm(rtwdev); 2549 } 2550 2551 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 2552 struct rtw89_rx_phy_ppdu *phy_ppdu) 2553 { 2554 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 2555 u8 macid = phy_ppdu->mac_id; 2556 2557 if (macid >= CFO_TRACK_MAX_USER) { 2558 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid); 2559 return; 2560 } 2561 2562 cfo->cfo_tail[macid] += cfo_val; 2563 cfo->cfo_cnt[macid]++; 2564 cfo->packet_count++; 2565 } 2566 2567 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev) 2568 { 2569 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2570 int i; 2571 u8 th; 2572 2573 for (i = 0; i < rtwdev->chip->rf_path_num; i++) { 2574 th = rtw89_chip_get_thermal(rtwdev, i); 2575 if (th) 2576 ewma_thermal_add(&phystat->avg_thermal[i], th); 2577 2578 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 2579 "path(%d) thermal cur=%u avg=%ld", i, th, 2580 ewma_thermal_read(&phystat->avg_thermal[i])); 2581 } 2582 } 2583 2584 struct rtw89_phy_iter_rssi_data { 2585 struct rtw89_dev *rtwdev; 2586 struct rtw89_phy_ch_info *ch_info; 2587 bool rssi_changed; 2588 }; 2589 2590 static void rtw89_phy_stat_rssi_update_iter(void *data, 2591 struct ieee80211_sta *sta) 2592 { 2593 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2594 struct rtw89_phy_iter_rssi_data *rssi_data = 2595 (struct rtw89_phy_iter_rssi_data *)data; 2596 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info; 2597 unsigned long rssi_curr; 2598 2599 rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi); 2600 2601 if (rssi_curr < ch_info->rssi_min) { 2602 ch_info->rssi_min = rssi_curr; 2603 ch_info->rssi_min_macid = rtwsta->mac_id; 2604 } 2605 2606 if (rtwsta->prev_rssi == 0) { 2607 rtwsta->prev_rssi = rssi_curr; 2608 } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) { 2609 rtwsta->prev_rssi = rssi_curr; 2610 rssi_data->rssi_changed = true; 2611 } 2612 } 2613 2614 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev) 2615 { 2616 struct rtw89_phy_iter_rssi_data rssi_data = {0}; 2617 2618 rssi_data.rtwdev = rtwdev; 2619 rssi_data.ch_info = &rtwdev->ch_info; 2620 rssi_data.ch_info->rssi_min = U8_MAX; 2621 ieee80211_iterate_stations_atomic(rtwdev->hw, 2622 rtw89_phy_stat_rssi_update_iter, 2623 &rssi_data); 2624 if (rssi_data.rssi_changed) 2625 rtw89_btc_ntfy_wl_sta(rtwdev); 2626 } 2627 2628 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev) 2629 { 2630 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2631 int i; 2632 2633 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 2634 ewma_thermal_init(&phystat->avg_thermal[i]); 2635 2636 rtw89_phy_stat_thermal_update(rtwdev); 2637 2638 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 2639 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat)); 2640 } 2641 2642 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev) 2643 { 2644 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 2645 2646 rtw89_phy_stat_thermal_update(rtwdev); 2647 rtw89_phy_stat_rssi_update(rtwdev); 2648 2649 phystat->last_pkt_stat = phystat->cur_pkt_stat; 2650 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 2651 } 2652 2653 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us) 2654 { 2655 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2656 2657 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 2658 } 2659 2660 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx) 2661 { 2662 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2663 2664 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 2665 } 2666 2667 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev) 2668 { 2669 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2670 2671 env->ccx_manual_ctrl = false; 2672 env->ccx_ongoing = false; 2673 env->ccx_rac_lv = RTW89_RAC_RELEASE; 2674 env->ccx_rpt_stamp = 0; 2675 env->ccx_period = 0; 2676 env->ccx_unit_idx = RTW89_CCX_32_US; 2677 env->ccx_trigger_time = 0; 2678 env->ccx_edcca_opt_bw_idx = RTW89_CCX_EDCCA_BW20_0; 2679 2680 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EN_MSK, 1); 2681 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_TRIG_OPT_MSK, 1); 2682 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 2683 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_CCX_EDCCA_OPT_MSK, 2684 RTW89_CCX_EDCCA_BW20_0); 2685 } 2686 2687 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report, 2688 u16 score) 2689 { 2690 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2691 u32 numer = 0; 2692 u16 ret = 0; 2693 2694 numer = report * score + (env->ccx_period >> 1); 2695 if (env->ccx_period) 2696 ret = numer / env->ccx_period; 2697 2698 return ret >= score ? score - 1 : ret; 2699 } 2700 2701 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev, 2702 u16 time_ms, u32 *period, 2703 u32 *unit_idx) 2704 { 2705 u32 idx; 2706 u8 quotient; 2707 2708 if (time_ms >= CCX_MAX_PERIOD) 2709 time_ms = CCX_MAX_PERIOD; 2710 2711 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD; 2712 2713 if (quotient < 4) 2714 idx = RTW89_CCX_4_US; 2715 else if (quotient < 8) 2716 idx = RTW89_CCX_8_US; 2717 else if (quotient < 16) 2718 idx = RTW89_CCX_16_US; 2719 else 2720 idx = RTW89_CCX_32_US; 2721 2722 *unit_idx = idx; 2723 *period = (time_ms * MS_TO_4US_RATIO) >> idx; 2724 2725 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2726 "[Trigger Time] period:%d, unit_idx:%d\n", 2727 *period, *unit_idx); 2728 } 2729 2730 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev) 2731 { 2732 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2733 2734 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2735 "lv:(%d)->(0)\n", env->ccx_rac_lv); 2736 2737 env->ccx_ongoing = false; 2738 env->ccx_rac_lv = RTW89_RAC_RELEASE; 2739 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 2740 } 2741 2742 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev, 2743 struct rtw89_ccx_para_info *para) 2744 { 2745 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2746 bool is_update = env->ifs_clm_app != para->ifs_clm_app; 2747 u8 i = 0; 2748 u16 *ifs_th_l = env->ifs_clm_th_l; 2749 u16 *ifs_th_h = env->ifs_clm_th_h; 2750 u32 ifs_th0_us = 0, ifs_th_times = 0; 2751 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0}; 2752 2753 if (!is_update) 2754 goto ifs_update_finished; 2755 2756 switch (para->ifs_clm_app) { 2757 case RTW89_IFS_CLM_INIT: 2758 case RTW89_IFS_CLM_BACKGROUND: 2759 case RTW89_IFS_CLM_ACS: 2760 case RTW89_IFS_CLM_DBG: 2761 case RTW89_IFS_CLM_DIG: 2762 case RTW89_IFS_CLM_TDMA_DIG: 2763 ifs_th0_us = IFS_CLM_TH0_UPPER; 2764 ifs_th_times = IFS_CLM_TH_MUL; 2765 break; 2766 case RTW89_IFS_CLM_DBG_MANUAL: 2767 ifs_th0_us = para->ifs_clm_manual_th0; 2768 ifs_th_times = para->ifs_clm_manual_th_times; 2769 break; 2770 default: 2771 break; 2772 } 2773 2774 /* Set sampling threshold for 4 different regions, unit in idx_cnt. 2775 * low[i] = high[i-1] + 1 2776 * high[i] = high[i-1] * ifs_th_times 2777 */ 2778 ifs_th_l[IFS_CLM_TH_START_IDX] = 0; 2779 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us; 2780 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, 2781 ifs_th0_us); 2782 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) { 2783 ifs_th_l[i] = ifs_th_h[i - 1] + 1; 2784 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times; 2785 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]); 2786 } 2787 2788 ifs_update_finished: 2789 if (!is_update) 2790 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2791 "No need to update IFS_TH\n"); 2792 2793 return is_update; 2794 } 2795 2796 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev) 2797 { 2798 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2799 u8 i = 0; 2800 2801 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_LOW_MSK, 2802 env->ifs_clm_th_l[0]); 2803 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_LOW_MSK, 2804 env->ifs_clm_th_l[1]); 2805 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_LOW_MSK, 2806 env->ifs_clm_th_l[2]); 2807 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_LOW_MSK, 2808 env->ifs_clm_th_l[3]); 2809 2810 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_TH_HIGH_MSK, 2811 env->ifs_clm_th_h[0]); 2812 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_TH_HIGH_MSK, 2813 env->ifs_clm_th_h[1]); 2814 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_TH_HIGH_MSK, 2815 env->ifs_clm_th_h[2]); 2816 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_TH_HIGH_MSK, 2817 env->ifs_clm_th_h[3]); 2818 2819 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 2820 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2821 "Update IFS_T%d_th{low, high} : {%d, %d}\n", 2822 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); 2823 } 2824 2825 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev) 2826 { 2827 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2828 struct rtw89_ccx_para_info para = {0}; 2829 2830 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 2831 env->ifs_clm_mntr_time = 0; 2832 2833 para.ifs_clm_app = RTW89_IFS_CLM_INIT; 2834 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶)) 2835 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 2836 2837 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COLLECT_EN, 2838 true); 2839 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T1, B_IFS_T1_EN_MSK, true); 2840 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T2, B_IFS_T2_EN_MSK, true); 2841 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T3, B_IFS_T3_EN_MSK, true); 2842 rtw89_phy_set_phy_regs(rtwdev, R_IFS_T4, B_IFS_T4_EN_MSK, true); 2843 } 2844 2845 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, 2846 enum rtw89_env_racing_lv level) 2847 { 2848 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2849 int ret = 0; 2850 2851 if (level >= RTW89_RAC_MAX_NUM) { 2852 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2853 "[WARNING] Wrong LV=%d\n", level); 2854 return -EINVAL; 2855 } 2856 2857 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2858 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing, 2859 env->ccx_rac_lv, level); 2860 2861 if (env->ccx_ongoing) { 2862 if (level <= env->ccx_rac_lv) 2863 ret = -EINVAL; 2864 else 2865 env->ccx_ongoing = false; 2866 } 2867 2868 if (ret == 0) 2869 env->ccx_rac_lv = level; 2870 2871 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n", 2872 !ret); 2873 2874 return ret; 2875 } 2876 2877 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev) 2878 { 2879 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2880 2881 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 0); 2882 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 0); 2883 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, B_IFS_COUNTER_CLR_MSK, 1); 2884 rtw89_phy_set_phy_regs(rtwdev, R_CCX, B_MEASUREMENT_TRIG_MSK, 1); 2885 2886 env->ccx_rpt_stamp++; 2887 env->ccx_ongoing = true; 2888 } 2889 2890 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev) 2891 { 2892 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2893 u8 i = 0; 2894 u32 res = 0; 2895 2896 env->ifs_clm_tx_ratio = 2897 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT); 2898 env->ifs_clm_edcca_excl_cca_ratio = 2899 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca, 2900 PERCENT); 2901 env->ifs_clm_cck_fa_ratio = 2902 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT); 2903 env->ifs_clm_ofdm_fa_ratio = 2904 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT); 2905 env->ifs_clm_cck_cca_excl_fa_ratio = 2906 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa, 2907 PERCENT); 2908 env->ifs_clm_ofdm_cca_excl_fa_ratio = 2909 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa, 2910 PERCENT); 2911 env->ifs_clm_cck_fa_permil = 2912 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL); 2913 env->ifs_clm_ofdm_fa_permil = 2914 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL); 2915 2916 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) { 2917 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) { 2918 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; 2919 } else { 2920 env->ifs_clm_ifs_avg[i] = 2921 rtw89_phy_ccx_idx_to_us(rtwdev, 2922 env->ifs_clm_avg[i]); 2923 } 2924 2925 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]); 2926 res += env->ifs_clm_his[i] >> 1; 2927 if (env->ifs_clm_his[i]) 2928 res /= env->ifs_clm_his[i]; 2929 else 2930 res = 0; 2931 env->ifs_clm_cca_avg[i] = res; 2932 } 2933 2934 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2935 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", 2936 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); 2937 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2938 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", 2939 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); 2940 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2941 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", 2942 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); 2943 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2944 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", 2945 env->ifs_clm_cck_cca_excl_fa_ratio, 2946 env->ifs_clm_ofdm_cca_excl_fa_ratio); 2947 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2948 "Time:[his, ifs_avg(us), cca_avg(us)]\n"); 2949 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 2950 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", 2951 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], 2952 env->ifs_clm_cca_avg[i]); 2953 } 2954 2955 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev) 2956 { 2957 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 2958 u8 i = 0; 2959 2960 if (rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_DONE_MSK) == 0) { 2961 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 2962 "Get IFS_CLM report Fail\n"); 2963 return false; 2964 } 2965 2966 env->ifs_clm_tx = 2967 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 2968 B_IFS_CLM_TX_CNT_MSK); 2969 env->ifs_clm_edcca_excl_cca = 2970 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_TX_CNT, 2971 B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK); 2972 env->ifs_clm_cckcca_excl_fa = 2973 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 2974 B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK); 2975 env->ifs_clm_ofdmcca_excl_fa = 2976 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_CCA, 2977 B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK); 2978 env->ifs_clm_cckfa = 2979 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 2980 B_IFS_CLM_CCK_FA_MSK); 2981 env->ifs_clm_ofdmfa = 2982 rtw89_phy_read32_mask(rtwdev, R_IFS_CLM_FA, 2983 B_IFS_CLM_OFDM_FA_MSK); 2984 2985 env->ifs_clm_his[0] = 2986 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T1_HIS_MSK); 2987 env->ifs_clm_his[1] = 2988 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T2_HIS_MSK); 2989 env->ifs_clm_his[2] = 2990 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T3_HIS_MSK); 2991 env->ifs_clm_his[3] = 2992 rtw89_phy_read32_mask(rtwdev, R_IFS_HIS, B_IFS_T4_HIS_MSK); 2993 2994 env->ifs_clm_avg[0] = 2995 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T1_AVG_MSK); 2996 env->ifs_clm_avg[1] = 2997 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_L, B_IFS_T2_AVG_MSK); 2998 env->ifs_clm_avg[2] = 2999 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T3_AVG_MSK); 3000 env->ifs_clm_avg[3] = 3001 rtw89_phy_read32_mask(rtwdev, R_IFS_AVG_H, B_IFS_T4_AVG_MSK); 3002 3003 env->ifs_clm_cca[0] = 3004 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T1_CCA_MSK); 3005 env->ifs_clm_cca[1] = 3006 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_L, B_IFS_T2_CCA_MSK); 3007 env->ifs_clm_cca[2] = 3008 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T3_CCA_MSK); 3009 env->ifs_clm_cca[3] = 3010 rtw89_phy_read32_mask(rtwdev, R_IFS_CCA_H, B_IFS_T4_CCA_MSK); 3011 3012 env->ifs_clm_total_ifs = 3013 rtw89_phy_read32_mask(rtwdev, R_IFSCNT, B_IFSCNT_TOTAL_CNT_MSK); 3014 3015 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", 3016 env->ifs_clm_total_ifs); 3017 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3018 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n", 3019 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); 3020 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3021 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n", 3022 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); 3023 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3024 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n", 3025 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); 3026 3027 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n"); 3028 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 3029 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3030 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i], 3031 env->ifs_clm_avg[i], env->ifs_clm_cca[i]); 3032 3033 rtw89_phy_ifs_clm_get_utility(rtwdev); 3034 3035 return true; 3036 } 3037 3038 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, 3039 struct rtw89_ccx_para_info *para) 3040 { 3041 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3042 u32 period = 0; 3043 u32 unit_idx = 0; 3044 3045 if (para->mntr_time == 0) { 3046 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3047 "[WARN] MNTR_TIME is 0\n"); 3048 return -EINVAL; 3049 } 3050 3051 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv)) 3052 return -EINVAL; 3053 3054 if (para->mntr_time != env->ifs_clm_mntr_time) { 3055 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, 3056 &period, &unit_idx); 3057 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 3058 B_IFS_CLM_PERIOD_MSK, period); 3059 rtw89_phy_set_phy_regs(rtwdev, R_IFS_COUNTER, 3060 B_IFS_CLM_COUNTER_UNIT_MSK, unit_idx); 3061 3062 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3063 "Update IFS-CLM time ((%d)) -> ((%d))\n", 3064 env->ifs_clm_mntr_time, para->mntr_time); 3065 3066 env->ifs_clm_mntr_time = para->mntr_time; 3067 env->ccx_period = (u16)period; 3068 env->ccx_unit_idx = (u8)unit_idx; 3069 } 3070 3071 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) { 3072 env->ifs_clm_app = para->ifs_clm_app; 3073 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 3074 } 3075 3076 return 0; 3077 } 3078 3079 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) 3080 { 3081 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3082 struct rtw89_ccx_para_info para = {0}; 3083 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL; 3084 3085 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL; 3086 if (env->ccx_manual_ctrl) { 3087 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3088 "CCX in manual ctrl\n"); 3089 return; 3090 } 3091 3092 /* only ifs_clm for now */ 3093 if (rtw89_phy_ifs_clm_get_result(rtwdev)) 3094 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3095 3096 rtw89_phy_ccx_racing_release(rtwdev); 3097 para.mntr_time = 1900; 3098 para.rac_lv = RTW89_RAC_LV_1; 3099 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 3100 3101 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0) 3102 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; 3103 if (chk_result) 3104 rtw89_phy_ccx_trigger(rtwdev); 3105 3106 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 3107 "get_result=0x%x, chk_result:0x%x\n", 3108 env->ccx_watchdog_result, chk_result); 3109 } 3110 3111 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page) 3112 { 3113 if (*ie_page > RTW89_PHYSTS_BITMAP_NUM || 3114 *ie_page == RTW89_RSVD_9) 3115 return false; 3116 else if (*ie_page > RTW89_RSVD_9) 3117 *ie_page -= 1; 3118 3119 return true; 3120 } 3121 3122 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page) 3123 { 3124 static const u8 ie_page_shift = 2; 3125 3126 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift); 3127 } 3128 3129 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, 3130 enum rtw89_phy_status_bitmap ie_page) 3131 { 3132 u32 addr; 3133 3134 if (!rtw89_physts_ie_page_valid(&ie_page)) 3135 return 0; 3136 3137 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3138 3139 return rtw89_phy_read32(rtwdev, addr); 3140 } 3141 3142 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev, 3143 enum rtw89_phy_status_bitmap ie_page, 3144 u32 val) 3145 { 3146 const struct rtw89_chip_info *chip = rtwdev->chip; 3147 u32 addr; 3148 3149 if (!rtw89_physts_ie_page_valid(&ie_page)) 3150 return; 3151 3152 if (chip->chip_id == RTL8852A) 3153 val &= B_PHY_STS_BITMAP_MSK_52A; 3154 3155 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 3156 rtw89_phy_write32(rtwdev, addr, val); 3157 } 3158 3159 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev, 3160 enum rtw89_phy_status_bitmap bitmap, 3161 enum rtw89_phy_status_ie_type ie, 3162 bool enable) 3163 { 3164 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap); 3165 3166 if (enable) 3167 val |= BIT(ie); 3168 else 3169 val &= ~BIT(ie); 3170 3171 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val); 3172 } 3173 3174 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev, 3175 bool enable, 3176 enum rtw89_phy_idx phy_idx) 3177 { 3178 if (enable) { 3179 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 3180 B_STS_DIS_TRIG_BY_FAIL); 3181 rtw89_phy_write32_clr(rtwdev, R_PLCP_HISTOGRAM, 3182 B_STS_DIS_TRIG_BY_BRK); 3183 } else { 3184 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 3185 B_STS_DIS_TRIG_BY_FAIL); 3186 rtw89_phy_write32_set(rtwdev, R_PLCP_HISTOGRAM, 3187 B_STS_DIS_TRIG_BY_BRK); 3188 } 3189 } 3190 3191 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev) 3192 { 3193 u8 i; 3194 3195 rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0); 3196 3197 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) { 3198 if (i >= RTW89_CCK_PKT) 3199 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3200 RTW89_PHYSTS_IE09_FTR_0, 3201 true); 3202 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) || 3203 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT)) 3204 continue; 3205 rtw89_physts_enable_ie_bitmap(rtwdev, i, 3206 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A, 3207 true); 3208 } 3209 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT, 3210 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3211 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT, 3212 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 3213 3214 /* force IE01 for channel index, only channel field is valid */ 3215 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT, 3216 RTW89_PHYSTS_IE01_CMN_OFDM, true); 3217 } 3218 3219 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type) 3220 { 3221 const struct rtw89_chip_info *chip = rtwdev->chip; 3222 struct rtw89_dig_info *dig = &rtwdev->dig; 3223 const struct rtw89_phy_dig_gain_cfg *cfg; 3224 const char *msg; 3225 u8 i; 3226 s8 gain_base; 3227 s8 *gain_arr; 3228 u32 tmp; 3229 3230 switch (type) { 3231 case RTW89_DIG_GAIN_LNA_G: 3232 gain_arr = dig->lna_gain_g; 3233 gain_base = LNA0_GAIN; 3234 cfg = chip->dig_table->cfg_lna_g; 3235 msg = "lna_gain_g"; 3236 break; 3237 case RTW89_DIG_GAIN_TIA_G: 3238 gain_arr = dig->tia_gain_g; 3239 gain_base = TIA0_GAIN_G; 3240 cfg = chip->dig_table->cfg_tia_g; 3241 msg = "tia_gain_g"; 3242 break; 3243 case RTW89_DIG_GAIN_LNA_A: 3244 gain_arr = dig->lna_gain_a; 3245 gain_base = LNA0_GAIN; 3246 cfg = chip->dig_table->cfg_lna_a; 3247 msg = "lna_gain_a"; 3248 break; 3249 case RTW89_DIG_GAIN_TIA_A: 3250 gain_arr = dig->tia_gain_a; 3251 gain_base = TIA0_GAIN_A; 3252 cfg = chip->dig_table->cfg_tia_a; 3253 msg = "tia_gain_a"; 3254 break; 3255 default: 3256 return; 3257 } 3258 3259 for (i = 0; i < cfg->size; i++) { 3260 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr, 3261 cfg->table[i].mask); 3262 tmp >>= DIG_GAIN_SHIFT; 3263 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base; 3264 gain_base += DIG_GAIN; 3265 3266 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n", 3267 msg, i, gain_arr[i]); 3268 } 3269 } 3270 3271 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev) 3272 { 3273 struct rtw89_dig_info *dig = &rtwdev->dig; 3274 u32 tmp; 3275 u8 i; 3276 3277 if (!rtwdev->hal.support_igi) 3278 return; 3279 3280 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW, 3281 B_PATH0_IB_PKPW_MSK); 3282 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT); 3283 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK, 3284 B_PATH0_IB_PBK_MSK); 3285 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n", 3286 dig->ib_pkpwr, dig->ib_pbk); 3287 3288 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++) 3289 rtw89_phy_dig_read_gain_table(rtwdev, i); 3290 } 3291 3292 static const u8 rssi_nolink = 22; 3293 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; 3294 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88}; 3295 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16}; 3296 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528}; 3297 3298 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev) 3299 { 3300 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; 3301 struct rtw89_dig_info *dig = &rtwdev->dig; 3302 bool is_linked = rtwdev->total_sta_assoc > 0; 3303 3304 if (is_linked) { 3305 dig->igi_rssi = ch_info->rssi_min >> 1; 3306 } else { 3307 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n"); 3308 dig->igi_rssi = rssi_nolink; 3309 } 3310 } 3311 3312 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev) 3313 { 3314 struct rtw89_dig_info *dig = &rtwdev->dig; 3315 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3316 bool is_linked = rtwdev->total_sta_assoc > 0; 3317 const u16 *fa_th_src = NULL; 3318 3319 switch (chan->band_type) { 3320 case RTW89_BAND_2G: 3321 dig->lna_gain = dig->lna_gain_g; 3322 dig->tia_gain = dig->tia_gain_g; 3323 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink; 3324 dig->force_gaincode_idx_en = false; 3325 dig->dyn_pd_th_en = true; 3326 break; 3327 case RTW89_BAND_5G: 3328 default: 3329 dig->lna_gain = dig->lna_gain_a; 3330 dig->tia_gain = dig->tia_gain_a; 3331 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink; 3332 dig->force_gaincode_idx_en = true; 3333 dig->dyn_pd_th_en = true; 3334 break; 3335 } 3336 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th)); 3337 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th)); 3338 } 3339 3340 static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20; 3341 static const u8 igi_max_performance_mode = 0x5a; 3342 static const u8 dynamic_pd_threshold_max; 3343 3344 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev) 3345 { 3346 struct rtw89_dig_info *dig = &rtwdev->dig; 3347 3348 dig->cur_gaincode.lna_idx = LNA_IDX_MAX; 3349 dig->cur_gaincode.tia_idx = TIA_IDX_MAX; 3350 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX; 3351 dig->force_gaincode.lna_idx = LNA_IDX_MAX; 3352 dig->force_gaincode.tia_idx = TIA_IDX_MAX; 3353 dig->force_gaincode.rxb_idx = RXB_IDX_MAX; 3354 3355 dig->dyn_igi_max = igi_max_performance_mode; 3356 dig->dyn_igi_min = dynamic_igi_min; 3357 dig->dyn_pd_th_max = dynamic_pd_threshold_max; 3358 dig->pd_low_th_ofst = pd_low_th_offset; 3359 dig->is_linked_pre = false; 3360 } 3361 3362 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev) 3363 { 3364 rtw89_phy_dig_update_gain_para(rtwdev); 3365 rtw89_phy_dig_reset(rtwdev); 3366 } 3367 3368 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3369 { 3370 struct rtw89_dig_info *dig = &rtwdev->dig; 3371 u8 lna_idx; 3372 3373 if (rssi < dig->igi_rssi_th[0]) 3374 lna_idx = RTW89_DIG_GAIN_LNA_IDX6; 3375 else if (rssi < dig->igi_rssi_th[1]) 3376 lna_idx = RTW89_DIG_GAIN_LNA_IDX5; 3377 else if (rssi < dig->igi_rssi_th[2]) 3378 lna_idx = RTW89_DIG_GAIN_LNA_IDX4; 3379 else if (rssi < dig->igi_rssi_th[3]) 3380 lna_idx = RTW89_DIG_GAIN_LNA_IDX3; 3381 else if (rssi < dig->igi_rssi_th[4]) 3382 lna_idx = RTW89_DIG_GAIN_LNA_IDX2; 3383 else 3384 lna_idx = RTW89_DIG_GAIN_LNA_IDX1; 3385 3386 return lna_idx; 3387 } 3388 3389 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 3390 { 3391 struct rtw89_dig_info *dig = &rtwdev->dig; 3392 u8 tia_idx; 3393 3394 if (rssi < dig->igi_rssi_th[0]) 3395 tia_idx = RTW89_DIG_GAIN_TIA_IDX1; 3396 else 3397 tia_idx = RTW89_DIG_GAIN_TIA_IDX0; 3398 3399 return tia_idx; 3400 } 3401 3402 #define IB_PBK_BASE 110 3403 #define WB_RSSI_BASE 10 3404 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3405 struct rtw89_agc_gaincode_set *set) 3406 { 3407 struct rtw89_dig_info *dig = &rtwdev->dig; 3408 s8 lna_gain = dig->lna_gain[set->lna_idx]; 3409 s8 tia_gain = dig->tia_gain[set->tia_idx]; 3410 s32 wb_rssi = rssi + lna_gain + tia_gain; 3411 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE; 3412 u8 rxb_idx; 3413 3414 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi; 3415 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX); 3416 3417 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", 3418 wb_rssi, rxb_idx_tmp); 3419 3420 return rxb_idx; 3421 } 3422 3423 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 3424 struct rtw89_agc_gaincode_set *set) 3425 { 3426 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi); 3427 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi); 3428 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set); 3429 3430 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3431 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", 3432 rssi, set->lna_idx, set->tia_idx, set->rxb_idx); 3433 } 3434 3435 #define IGI_OFFSET_MAX 25 3436 #define IGI_OFFSET_MUL 2 3437 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev) 3438 { 3439 struct rtw89_dig_info *dig = &rtwdev->dig; 3440 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 3441 enum rtw89_dig_noisy_level noisy_lv; 3442 u8 igi_offset = dig->fa_rssi_ofst; 3443 u16 fa_ratio = 0; 3444 3445 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil; 3446 3447 if (fa_ratio < dig->fa_th[0]) 3448 noisy_lv = RTW89_DIG_NOISY_LEVEL0; 3449 else if (fa_ratio < dig->fa_th[1]) 3450 noisy_lv = RTW89_DIG_NOISY_LEVEL1; 3451 else if (fa_ratio < dig->fa_th[2]) 3452 noisy_lv = RTW89_DIG_NOISY_LEVEL2; 3453 else if (fa_ratio < dig->fa_th[3]) 3454 noisy_lv = RTW89_DIG_NOISY_LEVEL3; 3455 else 3456 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX; 3457 3458 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2) 3459 igi_offset = 0; 3460 else 3461 igi_offset += noisy_lv * IGI_OFFSET_MUL; 3462 3463 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX); 3464 dig->fa_rssi_ofst = igi_offset; 3465 3466 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3467 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", 3468 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]); 3469 3470 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3471 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n", 3472 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil, 3473 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil, 3474 noisy_lv, igi_offset); 3475 } 3476 3477 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx) 3478 { 3479 rtw89_phy_write32_mask(rtwdev, R_PATH0_LNA_INIT, 3480 B_PATH0_LNA_INIT_IDX_MSK, lna_idx); 3481 rtw89_phy_write32_mask(rtwdev, R_PATH1_LNA_INIT, 3482 B_PATH1_LNA_INIT_IDX_MSK, lna_idx); 3483 } 3484 3485 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx) 3486 { 3487 rtw89_phy_write32_mask(rtwdev, R_PATH0_TIA_INIT, 3488 B_PATH0_TIA_INIT_IDX_MSK, tia_idx); 3489 rtw89_phy_write32_mask(rtwdev, R_PATH1_TIA_INIT, 3490 B_PATH1_TIA_INIT_IDX_MSK, tia_idx); 3491 } 3492 3493 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx) 3494 { 3495 rtw89_phy_write32_mask(rtwdev, R_PATH0_RXB_INIT, 3496 B_PATH0_RXB_INIT_IDX_MSK, rxb_idx); 3497 rtw89_phy_write32_mask(rtwdev, R_PATH1_RXB_INIT, 3498 B_PATH1_RXB_INIT_IDX_MSK, rxb_idx); 3499 } 3500 3501 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev, 3502 const struct rtw89_agc_gaincode_set set) 3503 { 3504 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx); 3505 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx); 3506 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx); 3507 3508 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", 3509 set.lna_idx, set.tia_idx, set.rxb_idx); 3510 } 3511 3512 static const struct rtw89_reg_def sdagc_config[4] = { 3513 {R_PATH0_P20_FOLLOW_BY_PAGCUGC, B_PATH0_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 3514 {R_PATH0_S20_FOLLOW_BY_PAGCUGC, B_PATH0_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 3515 {R_PATH1_P20_FOLLOW_BY_PAGCUGC, B_PATH1_P20_FOLLOW_BY_PAGCUGC_EN_MSK}, 3516 {R_PATH1_S20_FOLLOW_BY_PAGCUGC, B_PATH1_S20_FOLLOW_BY_PAGCUGC_EN_MSK}, 3517 }; 3518 3519 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, 3520 bool enable) 3521 { 3522 u8 i = 0; 3523 3524 for (i = 0; i < ARRAY_SIZE(sdagc_config); i++) 3525 rtw89_phy_write32_mask(rtwdev, sdagc_config[i].addr, 3526 sdagc_config[i].mask, enable); 3527 3528 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable); 3529 } 3530 3531 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev) 3532 { 3533 struct rtw89_dig_info *dig = &rtwdev->dig; 3534 3535 if (!rtwdev->hal.support_igi) 3536 return; 3537 3538 if (dig->force_gaincode_idx_en) { 3539 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 3540 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3541 "Force gaincode index enabled.\n"); 3542 } else { 3543 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi, 3544 &dig->cur_gaincode); 3545 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode); 3546 } 3547 } 3548 3549 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi, 3550 bool enable) 3551 { 3552 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3553 enum rtw89_bandwidth cbw = chan->band_width; 3554 struct rtw89_dig_info *dig = &rtwdev->dig; 3555 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst; 3556 u8 ofdm_cca_th; 3557 s8 cck_cca_th; 3558 u32 pd_val = 0; 3559 3560 under_region += PD_TH_SB_FLTR_CMP_VAL; 3561 3562 switch (cbw) { 3563 case RTW89_CHANNEL_WIDTH_40: 3564 under_region += PD_TH_BW40_CMP_VAL; 3565 break; 3566 case RTW89_CHANNEL_WIDTH_80: 3567 under_region += PD_TH_BW80_CMP_VAL; 3568 break; 3569 case RTW89_CHANNEL_WIDTH_160: 3570 under_region += PD_TH_BW160_CMP_VAL; 3571 break; 3572 case RTW89_CHANNEL_WIDTH_20: 3573 fallthrough; 3574 default: 3575 under_region += PD_TH_BW20_CMP_VAL; 3576 break; 3577 } 3578 3579 dig->dyn_pd_th_max = dig->igi_rssi; 3580 3581 final_rssi = min_t(u8, rssi, dig->igi_rssi); 3582 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region, 3583 PD_TH_MAX_RSSI + under_region); 3584 3585 if (enable) { 3586 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1; 3587 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3588 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n", 3589 final_rssi, ofdm_cca_th, under_region, pd_val); 3590 } else { 3591 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3592 "Dynamic PD th disabled, Set PD_low_bd=0\n"); 3593 } 3594 3595 rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD, B_SEG0R_PD_LOWER_BOUND_MSK, 3596 pd_val); 3597 rtw89_phy_write32_mask(rtwdev, R_SEG0R_PD, 3598 B_SEG0R_PD_SPATIAL_REUSE_EN_MSK, enable); 3599 3600 if (!rtwdev->hal.support_cckpd) 3601 return; 3602 3603 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI); 3604 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX); 3605 3606 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3607 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n", 3608 final_rssi, cck_cca_th, under_region, pd_val); 3609 3610 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_EN_V1, 3611 B_BMODE_PDTH_LIMIT_EN_MSK_V1, enable); 3612 rtw89_phy_write32_mask(rtwdev, R_BMODE_PDTH_V1, 3613 B_BMODE_PDTH_LOWER_BOUND_MSK_V1, pd_val); 3614 } 3615 3616 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev) 3617 { 3618 struct rtw89_dig_info *dig = &rtwdev->dig; 3619 3620 dig->bypass_dig = false; 3621 rtw89_phy_dig_para_reset(rtwdev); 3622 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 3623 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false); 3624 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 3625 rtw89_phy_dig_update_para(rtwdev); 3626 } 3627 3628 #define IGI_RSSI_MIN 10 3629 void rtw89_phy_dig(struct rtw89_dev *rtwdev) 3630 { 3631 struct rtw89_dig_info *dig = &rtwdev->dig; 3632 bool is_linked = rtwdev->total_sta_assoc > 0; 3633 3634 if (unlikely(dig->bypass_dig)) { 3635 dig->bypass_dig = false; 3636 return; 3637 } 3638 3639 if (!dig->is_linked_pre && is_linked) { 3640 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n"); 3641 rtw89_phy_dig_update_para(rtwdev); 3642 } else if (dig->is_linked_pre && !is_linked) { 3643 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n"); 3644 rtw89_phy_dig_update_para(rtwdev); 3645 } 3646 dig->is_linked_pre = is_linked; 3647 3648 rtw89_phy_dig_igi_offset_by_env(rtwdev); 3649 rtw89_phy_dig_update_rssi_info(rtwdev); 3650 3651 dig->dyn_igi_min = (dig->igi_rssi > IGI_RSSI_MIN) ? 3652 dig->igi_rssi - IGI_RSSI_MIN : 0; 3653 dig->dyn_igi_max = dig->dyn_igi_min + IGI_OFFSET_MAX; 3654 dig->igi_fa_rssi = dig->dyn_igi_min + dig->fa_rssi_ofst; 3655 3656 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min, 3657 dig->dyn_igi_max); 3658 3659 rtw89_debug(rtwdev, RTW89_DBG_DIG, 3660 "rssi=%03d, dyn(max,min)=(%d,%d), final_rssi=%d\n", 3661 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min, 3662 dig->igi_fa_rssi); 3663 3664 rtw89_phy_dig_config_igi(rtwdev); 3665 3666 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en); 3667 3668 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max) 3669 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true); 3670 else 3671 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 3672 } 3673 3674 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev) 3675 { 3676 rtw89_phy_ccx_top_setting_init(rtwdev); 3677 rtw89_phy_ifs_clm_setting_init(rtwdev); 3678 } 3679 3680 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) 3681 { 3682 const struct rtw89_chip_info *chip = rtwdev->chip; 3683 3684 rtw89_phy_stat_init(rtwdev); 3685 3686 rtw89_chip_bb_sethw(rtwdev); 3687 3688 rtw89_phy_env_monitor_init(rtwdev); 3689 rtw89_physts_parsing_init(rtwdev); 3690 rtw89_phy_dig_init(rtwdev); 3691 rtw89_phy_cfo_init(rtwdev); 3692 3693 rtw89_phy_init_rf_nctl(rtwdev); 3694 rtw89_chip_rfk_init(rtwdev); 3695 rtw89_load_txpwr_table(rtwdev, chip->byr_table); 3696 rtw89_chip_set_txpwr_ctrl(rtwdev); 3697 rtw89_chip_power_trim(rtwdev); 3698 rtw89_chip_cfg_txrx_path(rtwdev); 3699 } 3700 3701 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 3702 { 3703 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 3704 u8 bss_color; 3705 3706 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 3707 return; 3708 3709 bss_color = vif->bss_conf.he_bss_color.color; 3710 3711 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_VLD0, 0x1, 3712 phy_idx); 3713 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_TGT, bss_color, 3714 phy_idx); 3715 rtw89_phy_write32_idx(rtwdev, R_BSS_CLR_MAP, B_BSS_CLR_MAP_STAID, 3716 vif->cfg.aid, phy_idx); 3717 } 3718 3719 static void 3720 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3721 { 3722 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data); 3723 } 3724 3725 static void 3726 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3727 { 3728 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 3729 } 3730 3731 static void 3732 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3733 { 3734 rtw89_phy_write32_set(rtwdev, def->addr, def->mask); 3735 } 3736 3737 static void 3738 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3739 { 3740 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask); 3741 } 3742 3743 static void 3744 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 3745 { 3746 udelay(def->data); 3747 } 3748 3749 static void 3750 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = { 3751 [RTW89_RFK_F_WRF] = _rfk_write_rf, 3752 [RTW89_RFK_F_WM] = _rfk_write32_mask, 3753 [RTW89_RFK_F_WS] = _rfk_write32_set, 3754 [RTW89_RFK_F_WC] = _rfk_write32_clr, 3755 [RTW89_RFK_F_DELAY] = _rfk_delay, 3756 }; 3757 3758 #if defined(__linux__) 3759 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); 3760 #elif defined(__FreeBSD__) 3761 rtw89_static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); 3762 #endif 3763 3764 void 3765 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl) 3766 { 3767 const struct rtw89_reg5_def *p = tbl->defs; 3768 const struct rtw89_reg5_def *end = tbl->defs + tbl->size; 3769 3770 for (; p < end; p++) 3771 _rfk_handler[p->flag](rtwdev, p); 3772 } 3773 EXPORT_SYMBOL(rtw89_rfk_parser); 3774 3775 #define RTW89_TSSI_FAST_MODE_NUM 4 3776 3777 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = { 3778 {0xD934, 0xff0000}, 3779 {0xD934, 0xff000000}, 3780 {0xD938, 0xff}, 3781 {0xD934, 0xff00}, 3782 }; 3783 3784 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = { 3785 {0xD930, 0xff0000}, 3786 {0xD930, 0xff000000}, 3787 {0xD934, 0xff}, 3788 {0xD930, 0xff00}, 3789 }; 3790 3791 static 3792 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev, 3793 enum rtw89_mac_idx mac_idx, 3794 enum rtw89_tssi_bandedge_cfg bandedge_cfg, 3795 u32 val) 3796 { 3797 const struct rtw89_reg_def *regs; 3798 u32 reg; 3799 int i; 3800 3801 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 3802 regs = rtw89_tssi_fastmode_regs_flat; 3803 else 3804 regs = rtw89_tssi_fastmode_regs_level; 3805 3806 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) { 3807 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); 3808 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val); 3809 } 3810 } 3811 3812 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = { 3813 {0xD91C, 0xff000000}, 3814 {0xD920, 0xff}, 3815 {0xD920, 0xff00}, 3816 {0xD920, 0xff0000}, 3817 {0xD920, 0xff000000}, 3818 {0xD924, 0xff}, 3819 {0xD924, 0xff00}, 3820 {0xD914, 0xff000000}, 3821 {0xD918, 0xff}, 3822 {0xD918, 0xff00}, 3823 {0xD918, 0xff0000}, 3824 {0xD918, 0xff000000}, 3825 {0xD91C, 0xff}, 3826 {0xD91C, 0xff00}, 3827 {0xD91C, 0xff0000}, 3828 }; 3829 3830 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = { 3831 {0xD910, 0xff}, 3832 {0xD910, 0xff00}, 3833 {0xD910, 0xff0000}, 3834 {0xD910, 0xff000000}, 3835 {0xD914, 0xff}, 3836 {0xD914, 0xff00}, 3837 {0xD914, 0xff0000}, 3838 {0xD908, 0xff}, 3839 {0xD908, 0xff00}, 3840 {0xD908, 0xff0000}, 3841 {0xD908, 0xff000000}, 3842 {0xD90C, 0xff}, 3843 {0xD90C, 0xff00}, 3844 {0xD90C, 0xff0000}, 3845 {0xD90C, 0xff000000}, 3846 }; 3847 3848 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 3849 enum rtw89_mac_idx mac_idx, 3850 enum rtw89_tssi_bandedge_cfg bandedge_cfg) 3851 { 3852 const struct rtw89_chip_info *chip = rtwdev->chip; 3853 const struct rtw89_reg_def *regs; 3854 const u32 *data; 3855 u32 reg; 3856 int i; 3857 3858 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM) 3859 return; 3860 3861 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 3862 regs = rtw89_tssi_bandedge_regs_flat; 3863 else 3864 regs = rtw89_tssi_bandedge_regs_level; 3865 3866 data = chip->tssi_dbw_table->data[bandedge_cfg]; 3867 3868 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) { 3869 reg = rtw89_mac_reg_by_idx(regs[i].addr, mac_idx); 3870 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]); 3871 } 3872 3873 reg = rtw89_mac_reg_by_idx(R_AX_BANDEDGE_CFG, mac_idx); 3874 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg); 3875 3876 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg, 3877 data[RTW89_TSSI_SBW20]); 3878 } 3879 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg); 3880