1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "chan.h" 6 #include "coex.h" 7 #include "debug.h" 8 #include "fw.h" 9 #include "mac.h" 10 #include "phy.h" 11 #include "ps.h" 12 #include "reg.h" 13 #include "sar.h" 14 #include "txrx.h" 15 #include "util.h" 16 17 static u32 rtw89_phy0_phy1_offset(struct rtw89_dev *rtwdev, u32 addr) 18 { 19 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 20 21 return phy->phy0_phy1_offset(rtwdev, addr); 22 } 23 24 static u16 get_max_amsdu_len(struct rtw89_dev *rtwdev, 25 const struct rtw89_ra_report *report) 26 { 27 u32 bit_rate = report->bit_rate; 28 29 /* lower than ofdm, do not aggregate */ 30 if (bit_rate < 550) 31 return 1; 32 33 /* avoid AMSDU for legacy rate */ 34 if (report->might_fallback_legacy) 35 return 1; 36 37 /* lower than 20M vht 2ss mcs8, make it small */ 38 if (bit_rate < 1800) 39 return 1200; 40 41 /* lower than 40M vht 2ss mcs9, make it medium */ 42 if (bit_rate < 4000) 43 return 2600; 44 45 /* not yet 80M vht 2ss mcs8/9, make it twice regular packet size */ 46 if (bit_rate < 7000) 47 return 3500; 48 49 return rtwdev->chip->max_amsdu_limit; 50 } 51 52 static u64 get_mcs_ra_mask(u16 mcs_map, u8 highest_mcs, u8 gap) 53 { 54 u64 ra_mask = 0; 55 u8 mcs_cap; 56 int i, nss; 57 58 for (i = 0, nss = 12; i < 4; i++, mcs_map >>= 2, nss += 12) { 59 mcs_cap = mcs_map & 0x3; 60 switch (mcs_cap) { 61 case 2: 62 ra_mask |= GENMASK_ULL(highest_mcs, 0) << nss; 63 break; 64 case 1: 65 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; 66 break; 67 case 0: 68 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; 69 break; 70 default: 71 break; 72 } 73 } 74 75 return ra_mask; 76 } 77 78 static u64 get_he_ra_mask(struct ieee80211_sta *sta) 79 { 80 struct ieee80211_sta_he_cap cap = sta->deflink.he_cap; 81 u16 mcs_map; 82 83 switch (sta->deflink.bandwidth) { 84 case IEEE80211_STA_RX_BW_160: 85 if (cap.he_cap_elem.phy_cap_info[0] & 86 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_80PLUS80_MHZ_IN_5G) 87 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80p80); 88 else 89 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_160); 90 break; 91 default: 92 mcs_map = le16_to_cpu(cap.he_mcs_nss_supp.rx_mcs_80); 93 } 94 95 /* MCS11, MCS9, MCS7 */ 96 return get_mcs_ra_mask(mcs_map, 11, 2); 97 } 98 99 static u64 get_eht_mcs_ra_mask(u8 *max_nss, u8 start_mcs, u8 n_nss) 100 { 101 u64 nss_mcs_shift; 102 u64 nss_mcs_val; 103 u64 mask = 0; 104 int i, j; 105 u8 nss; 106 107 for (i = 0; i < n_nss; i++) { 108 nss = u8_get_bits(max_nss[i], IEEE80211_EHT_MCS_NSS_RX); 109 if (!nss) 110 continue; 111 112 nss_mcs_val = GENMASK_ULL(start_mcs + i * 2, 0); 113 114 for (j = 0, nss_mcs_shift = 12; j < nss; j++, nss_mcs_shift += 16) 115 mask |= nss_mcs_val << nss_mcs_shift; 116 } 117 118 return mask; 119 } 120 121 static u64 get_eht_ra_mask(struct ieee80211_sta *sta) 122 { 123 struct ieee80211_sta_eht_cap *eht_cap = &sta->deflink.eht_cap; 124 struct ieee80211_eht_mcs_nss_supp_20mhz_only *mcs_nss_20mhz; 125 struct ieee80211_eht_mcs_nss_supp_bw *mcs_nss; 126 u8 *he_phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 127 128 switch (sta->deflink.bandwidth) { 129 case IEEE80211_STA_RX_BW_320: 130 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._320; 131 /* MCS 9, 11, 13 */ 132 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3); 133 case IEEE80211_STA_RX_BW_160: 134 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._160; 135 /* MCS 9, 11, 13 */ 136 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3); 137 case IEEE80211_STA_RX_BW_20: 138 if (!(he_phy_cap[0] & 139 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_MASK_ALL)) { 140 mcs_nss_20mhz = &eht_cap->eht_mcs_nss_supp.only_20mhz; 141 /* MCS 7, 9, 11, 13 */ 142 return get_eht_mcs_ra_mask(mcs_nss_20mhz->rx_tx_max_nss, 7, 4); 143 } 144 fallthrough; 145 case IEEE80211_STA_RX_BW_80: 146 default: 147 mcs_nss = &eht_cap->eht_mcs_nss_supp.bw._80; 148 /* MCS 9, 11, 13 */ 149 return get_eht_mcs_ra_mask(mcs_nss->rx_tx_max_nss, 9, 3); 150 } 151 } 152 153 #define RA_FLOOR_TABLE_SIZE 7 154 #define RA_FLOOR_UP_GAP 3 155 static u64 rtw89_phy_ra_mask_rssi(struct rtw89_dev *rtwdev, u8 rssi, 156 u8 ratr_state) 157 { 158 u8 rssi_lv_t[RA_FLOOR_TABLE_SIZE] = {30, 44, 48, 52, 56, 60, 100}; 159 u8 rssi_lv = 0; 160 u8 i; 161 162 rssi >>= 1; 163 for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) { 164 if (i >= ratr_state) 165 rssi_lv_t[i] += RA_FLOOR_UP_GAP; 166 if (rssi < rssi_lv_t[i]) { 167 rssi_lv = i; 168 break; 169 } 170 } 171 if (rssi_lv == 0) 172 return 0xffffffffffffffffULL; 173 else if (rssi_lv == 1) 174 return 0xfffffffffffffff0ULL; 175 else if (rssi_lv == 2) 176 return 0xffffffffffffefe0ULL; 177 else if (rssi_lv == 3) 178 return 0xffffffffffffcfc0ULL; 179 else if (rssi_lv == 4) 180 return 0xffffffffffff8f80ULL; 181 else if (rssi_lv >= 5) 182 return 0xffffffffffff0f00ULL; 183 184 return 0xffffffffffffffffULL; 185 } 186 187 static u64 rtw89_phy_ra_mask_recover(u64 ra_mask, u64 ra_mask_bak) 188 { 189 if ((ra_mask & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)) == 0) 190 ra_mask |= (ra_mask_bak & ~(RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 191 192 if (ra_mask == 0) 193 ra_mask |= (ra_mask_bak & (RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES)); 194 195 return ra_mask; 196 } 197 198 static u64 rtw89_phy_ra_mask_cfg(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 199 const struct rtw89_chan *chan) 200 { 201 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 202 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 203 enum nl80211_band band; 204 u64 cfg_mask; 205 206 if (!rtwsta->use_cfg_mask) 207 return -1; 208 209 switch (chan->band_type) { 210 case RTW89_BAND_2G: 211 band = NL80211_BAND_2GHZ; 212 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_2GHZ].legacy, 213 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES); 214 break; 215 case RTW89_BAND_5G: 216 band = NL80211_BAND_5GHZ; 217 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_5GHZ].legacy, 218 RA_MASK_OFDM_RATES); 219 break; 220 case RTW89_BAND_6G: 221 band = NL80211_BAND_6GHZ; 222 cfg_mask = u64_encode_bits(mask->control[NL80211_BAND_6GHZ].legacy, 223 RA_MASK_OFDM_RATES); 224 break; 225 default: 226 rtw89_warn(rtwdev, "unhandled band type %d\n", chan->band_type); 227 return -1; 228 } 229 230 if (sta->deflink.he_cap.has_he) { 231 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[0], 232 RA_MASK_HE_1SS_RATES); 233 cfg_mask |= u64_encode_bits(mask->control[band].he_mcs[1], 234 RA_MASK_HE_2SS_RATES); 235 } else if (sta->deflink.vht_cap.vht_supported) { 236 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[0], 237 RA_MASK_VHT_1SS_RATES); 238 cfg_mask |= u64_encode_bits(mask->control[band].vht_mcs[1], 239 RA_MASK_VHT_2SS_RATES); 240 } else if (sta->deflink.ht_cap.ht_supported) { 241 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[0], 242 RA_MASK_HT_1SS_RATES); 243 cfg_mask |= u64_encode_bits(mask->control[band].ht_mcs[1], 244 RA_MASK_HT_2SS_RATES); 245 } 246 247 return cfg_mask; 248 } 249 250 static const u64 251 rtw89_ra_mask_ht_rates[4] = {RA_MASK_HT_1SS_RATES, RA_MASK_HT_2SS_RATES, 252 RA_MASK_HT_3SS_RATES, RA_MASK_HT_4SS_RATES}; 253 static const u64 254 rtw89_ra_mask_vht_rates[4] = {RA_MASK_VHT_1SS_RATES, RA_MASK_VHT_2SS_RATES, 255 RA_MASK_VHT_3SS_RATES, RA_MASK_VHT_4SS_RATES}; 256 static const u64 257 rtw89_ra_mask_he_rates[4] = {RA_MASK_HE_1SS_RATES, RA_MASK_HE_2SS_RATES, 258 RA_MASK_HE_3SS_RATES, RA_MASK_HE_4SS_RATES}; 259 static const u64 260 rtw89_ra_mask_eht_rates[4] = {RA_MASK_EHT_1SS_RATES, RA_MASK_EHT_2SS_RATES, 261 RA_MASK_EHT_3SS_RATES, RA_MASK_EHT_4SS_RATES}; 262 263 static void rtw89_phy_ra_gi_ltf(struct rtw89_dev *rtwdev, 264 struct rtw89_sta *rtwsta, 265 const struct rtw89_chan *chan, 266 bool *fix_giltf_en, u8 *fix_giltf) 267 { 268 struct cfg80211_bitrate_mask *mask = &rtwsta->mask; 269 u8 band = chan->band_type; 270 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 271 u8 he_gi = mask->control[nl_band].he_gi; 272 u8 he_ltf = mask->control[nl_band].he_ltf; 273 274 if (!rtwsta->use_cfg_mask) 275 return; 276 277 if (he_ltf == 2 && he_gi == 2) { 278 *fix_giltf = RTW89_GILTF_LGI_4XHE32; 279 } else if (he_ltf == 2 && he_gi == 0) { 280 *fix_giltf = RTW89_GILTF_SGI_4XHE08; 281 } else if (he_ltf == 1 && he_gi == 1) { 282 *fix_giltf = RTW89_GILTF_2XHE16; 283 } else if (he_ltf == 1 && he_gi == 0) { 284 *fix_giltf = RTW89_GILTF_2XHE08; 285 } else if (he_ltf == 0 && he_gi == 1) { 286 *fix_giltf = RTW89_GILTF_1XHE16; 287 } else if (he_ltf == 0 && he_gi == 0) { 288 *fix_giltf = RTW89_GILTF_1XHE08; 289 } else { 290 *fix_giltf_en = false; 291 return; 292 } 293 294 *fix_giltf_en = true; 295 } 296 297 static void rtw89_phy_ra_sta_update(struct rtw89_dev *rtwdev, 298 struct ieee80211_sta *sta, bool csi) 299 { 300 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 301 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 302 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 303 struct rtw89_ra_info *ra = &rtwsta->ra; 304 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 305 rtwvif->sub_entity_idx); 306 struct ieee80211_vif *vif = rtwvif_to_vif(rtwsta->rtwvif); 307 const u64 *high_rate_masks = rtw89_ra_mask_ht_rates; 308 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 309 u64 ra_mask = 0; 310 u64 ra_mask_bak; 311 u8 mode = 0; 312 u8 csi_mode = RTW89_RA_RPT_MODE_LEGACY; 313 u8 bw_mode = 0; 314 u8 stbc_en = 0; 315 u8 ldpc_en = 0; 316 u8 fix_giltf = 0; 317 u8 i; 318 bool sgi = false; 319 bool fix_giltf_en = false; 320 321 memset(ra, 0, sizeof(*ra)); 322 /* Set the ra mask from sta's capability */ 323 if (sta->deflink.eht_cap.has_eht) { 324 mode |= RTW89_RA_MODE_EHT; 325 ra_mask |= get_eht_ra_mask(sta); 326 high_rate_masks = rtw89_ra_mask_eht_rates; 327 } else if (sta->deflink.he_cap.has_he) { 328 mode |= RTW89_RA_MODE_HE; 329 csi_mode = RTW89_RA_RPT_MODE_HE; 330 ra_mask |= get_he_ra_mask(sta); 331 high_rate_masks = rtw89_ra_mask_he_rates; 332 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[2] & 333 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ) 334 stbc_en = 1; 335 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[1] & 336 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD) 337 ldpc_en = 1; 338 rtw89_phy_ra_gi_ltf(rtwdev, rtwsta, chan, &fix_giltf_en, &fix_giltf); 339 } else if (sta->deflink.vht_cap.vht_supported) { 340 u16 mcs_map = le16_to_cpu(sta->deflink.vht_cap.vht_mcs.rx_mcs_map); 341 342 mode |= RTW89_RA_MODE_VHT; 343 csi_mode = RTW89_RA_RPT_MODE_VHT; 344 /* MCS9, MCS8, MCS7 */ 345 ra_mask |= get_mcs_ra_mask(mcs_map, 9, 1); 346 high_rate_masks = rtw89_ra_mask_vht_rates; 347 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK) 348 stbc_en = 1; 349 if (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC) 350 ldpc_en = 1; 351 } else if (sta->deflink.ht_cap.ht_supported) { 352 mode |= RTW89_RA_MODE_HT; 353 csi_mode = RTW89_RA_RPT_MODE_HT; 354 ra_mask |= ((u64)sta->deflink.ht_cap.mcs.rx_mask[3] << 48) | 355 ((u64)sta->deflink.ht_cap.mcs.rx_mask[2] << 36) | 356 (sta->deflink.ht_cap.mcs.rx_mask[1] << 24) | 357 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12); 358 high_rate_masks = rtw89_ra_mask_ht_rates; 359 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_RX_STBC) 360 stbc_en = 1; 361 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_LDPC_CODING) 362 ldpc_en = 1; 363 } 364 365 switch (chan->band_type) { 366 case RTW89_BAND_2G: 367 ra_mask |= sta->deflink.supp_rates[NL80211_BAND_2GHZ]; 368 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xf) 369 mode |= RTW89_RA_MODE_CCK; 370 if (sta->deflink.supp_rates[NL80211_BAND_2GHZ] & 0xff0) 371 mode |= RTW89_RA_MODE_OFDM; 372 break; 373 case RTW89_BAND_5G: 374 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_5GHZ] << 4; 375 mode |= RTW89_RA_MODE_OFDM; 376 break; 377 case RTW89_BAND_6G: 378 ra_mask |= (u64)sta->deflink.supp_rates[NL80211_BAND_6GHZ] << 4; 379 mode |= RTW89_RA_MODE_OFDM; 380 break; 381 default: 382 rtw89_err(rtwdev, "Unknown band type\n"); 383 break; 384 } 385 386 ra_mask_bak = ra_mask; 387 388 if (mode >= RTW89_RA_MODE_HT) { 389 u64 mask = 0; 390 for (i = 0; i < rtwdev->hal.tx_nss; i++) 391 mask |= high_rate_masks[i]; 392 if (mode & RTW89_RA_MODE_OFDM) 393 mask |= RA_MASK_SUBOFDM_RATES; 394 if (mode & RTW89_RA_MODE_CCK) 395 mask |= RA_MASK_SUBCCK_RATES; 396 ra_mask &= mask; 397 } else if (mode & RTW89_RA_MODE_OFDM) { 398 ra_mask &= (RA_MASK_OFDM_RATES | RA_MASK_SUBCCK_RATES); 399 } 400 401 if (mode != RTW89_RA_MODE_CCK) 402 ra_mask &= rtw89_phy_ra_mask_rssi(rtwdev, rssi, 0); 403 404 ra_mask = rtw89_phy_ra_mask_recover(ra_mask, ra_mask_bak); 405 ra_mask &= rtw89_phy_ra_mask_cfg(rtwdev, rtwsta, chan); 406 407 switch (sta->deflink.bandwidth) { 408 case IEEE80211_STA_RX_BW_160: 409 bw_mode = RTW89_CHANNEL_WIDTH_160; 410 sgi = sta->deflink.vht_cap.vht_supported && 411 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_160); 412 break; 413 case IEEE80211_STA_RX_BW_80: 414 bw_mode = RTW89_CHANNEL_WIDTH_80; 415 sgi = sta->deflink.vht_cap.vht_supported && 416 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SHORT_GI_80); 417 break; 418 case IEEE80211_STA_RX_BW_40: 419 bw_mode = RTW89_CHANNEL_WIDTH_40; 420 sgi = sta->deflink.ht_cap.ht_supported && 421 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40); 422 break; 423 default: 424 bw_mode = RTW89_CHANNEL_WIDTH_20; 425 sgi = sta->deflink.ht_cap.ht_supported && 426 (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20); 427 break; 428 } 429 430 if (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 431 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM) 432 ra->dcm_cap = 1; 433 434 if (rate_pattern->enable && !vif->p2p) { 435 ra_mask = rtw89_phy_ra_mask_cfg(rtwdev, rtwsta, chan); 436 ra_mask &= rate_pattern->ra_mask; 437 mode = rate_pattern->ra_mode; 438 } 439 440 ra->bw_cap = bw_mode; 441 ra->er_cap = rtwsta->er_cap; 442 ra->mode_ctrl = mode; 443 ra->macid = rtwsta->mac_id; 444 ra->stbc_cap = stbc_en; 445 ra->ldpc_cap = ldpc_en; 446 ra->ss_num = min(sta->deflink.rx_nss, rtwdev->hal.tx_nss) - 1; 447 ra->en_sgi = sgi; 448 ra->ra_mask = ra_mask; 449 ra->fix_giltf_en = fix_giltf_en; 450 ra->fix_giltf = fix_giltf; 451 452 if (!csi) 453 return; 454 455 ra->fixed_csi_rate_en = false; 456 ra->ra_csi_rate_en = true; 457 ra->cr_tbl_sel = false; 458 ra->band_num = rtwvif->phy_idx; 459 ra->csi_bw = bw_mode; 460 ra->csi_gi_ltf = RTW89_GILTF_LGI_4XHE32; 461 ra->csi_mcs_ss_idx = 5; 462 ra->csi_mode = csi_mode; 463 } 464 465 void rtw89_phy_ra_updata_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, 466 u32 changed) 467 { 468 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 469 struct rtw89_ra_info *ra = &rtwsta->ra; 470 471 rtw89_phy_ra_sta_update(rtwdev, sta, false); 472 473 if (changed & IEEE80211_RC_SUPP_RATES_CHANGED) 474 ra->upd_mask = 1; 475 if (changed & (IEEE80211_RC_BW_CHANGED | IEEE80211_RC_NSS_CHANGED)) 476 ra->upd_bw_nss_mask = 1; 477 478 rtw89_debug(rtwdev, RTW89_DBG_RA, 479 "ra updat: macid = %d, bw = %d, nss = %d, gi = %d %d", 480 ra->macid, 481 ra->bw_cap, 482 ra->ss_num, 483 ra->en_sgi, 484 ra->giltf); 485 486 rtw89_fw_h2c_ra(rtwdev, ra, false); 487 } 488 489 static bool __check_rate_pattern(struct rtw89_phy_rate_pattern *next, 490 u16 rate_base, u64 ra_mask, u8 ra_mode, 491 u32 rate_ctrl, u32 ctrl_skip, bool force) 492 { 493 u8 n, c; 494 495 if (rate_ctrl == ctrl_skip) 496 return true; 497 498 n = hweight32(rate_ctrl); 499 if (n == 0) 500 return true; 501 502 if (force && n != 1) 503 return false; 504 505 if (next->enable) 506 return false; 507 508 c = __fls(rate_ctrl); 509 next->rate = rate_base + c; 510 next->ra_mode = ra_mode; 511 next->ra_mask = ra_mask; 512 next->enable = true; 513 514 return true; 515 } 516 517 #define RTW89_HW_RATE_BY_CHIP_GEN(rate) \ 518 { \ 519 [RTW89_CHIP_AX] = RTW89_HW_RATE_ ## rate, \ 520 [RTW89_CHIP_BE] = RTW89_HW_RATE_V1_ ## rate, \ 521 } 522 523 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, 524 struct ieee80211_vif *vif, 525 const struct cfg80211_bitrate_mask *mask) 526 { 527 struct ieee80211_supported_band *sband; 528 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 529 struct rtw89_phy_rate_pattern next_pattern = {0}; 530 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 531 rtwvif->sub_entity_idx); 532 static const u16 hw_rate_he[][RTW89_CHIP_GEN_NUM] = { 533 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS1_MCS0), 534 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS2_MCS0), 535 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS3_MCS0), 536 RTW89_HW_RATE_BY_CHIP_GEN(HE_NSS4_MCS0), 537 }; 538 static const u16 hw_rate_vht[][RTW89_CHIP_GEN_NUM] = { 539 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS1_MCS0), 540 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS2_MCS0), 541 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS3_MCS0), 542 RTW89_HW_RATE_BY_CHIP_GEN(VHT_NSS4_MCS0), 543 }; 544 static const u16 hw_rate_ht[][RTW89_CHIP_GEN_NUM] = { 545 RTW89_HW_RATE_BY_CHIP_GEN(MCS0), 546 RTW89_HW_RATE_BY_CHIP_GEN(MCS8), 547 RTW89_HW_RATE_BY_CHIP_GEN(MCS16), 548 RTW89_HW_RATE_BY_CHIP_GEN(MCS24), 549 }; 550 u8 band = chan->band_type; 551 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 552 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 553 u8 tx_nss = rtwdev->hal.tx_nss; 554 u8 i; 555 556 for (i = 0; i < tx_nss; i++) 557 if (!__check_rate_pattern(&next_pattern, hw_rate_he[i][chip_gen], 558 RA_MASK_HE_RATES, RTW89_RA_MODE_HE, 559 mask->control[nl_band].he_mcs[i], 560 0, true)) 561 goto out; 562 563 for (i = 0; i < tx_nss; i++) 564 if (!__check_rate_pattern(&next_pattern, hw_rate_vht[i][chip_gen], 565 RA_MASK_VHT_RATES, RTW89_RA_MODE_VHT, 566 mask->control[nl_band].vht_mcs[i], 567 0, true)) 568 goto out; 569 570 for (i = 0; i < tx_nss; i++) 571 if (!__check_rate_pattern(&next_pattern, hw_rate_ht[i][chip_gen], 572 RA_MASK_HT_RATES, RTW89_RA_MODE_HT, 573 mask->control[nl_band].ht_mcs[i], 574 0, true)) 575 goto out; 576 577 /* lagacy cannot be empty for nl80211_parse_tx_bitrate_mask, and 578 * require at least one basic rate for ieee80211_set_bitrate_mask, 579 * so the decision just depends on if all bitrates are set or not. 580 */ 581 sband = rtwdev->hw->wiphy->bands[nl_band]; 582 if (band == RTW89_BAND_2G) { 583 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_CCK1, 584 RA_MASK_CCK_RATES | RA_MASK_OFDM_RATES, 585 RTW89_RA_MODE_CCK | RTW89_RA_MODE_OFDM, 586 mask->control[nl_band].legacy, 587 BIT(sband->n_bitrates) - 1, false)) 588 goto out; 589 } else { 590 if (!__check_rate_pattern(&next_pattern, RTW89_HW_RATE_OFDM6, 591 RA_MASK_OFDM_RATES, RTW89_RA_MODE_OFDM, 592 mask->control[nl_band].legacy, 593 BIT(sband->n_bitrates) - 1, false)) 594 goto out; 595 } 596 597 if (!next_pattern.enable) 598 goto out; 599 600 rtwvif->rate_pattern = next_pattern; 601 rtw89_debug(rtwdev, RTW89_DBG_RA, 602 #if defined(__linux__) 603 "configure pattern: rate 0x%x, mask 0x%llx, mode 0x%x\n", 604 #elif defined(__FreeBSD__) 605 "configure pattern: rate 0x%x, mask 0x%jx, mode 0x%x\n", 606 #endif 607 next_pattern.rate, 608 #if defined(__FreeBSD__) 609 (uintmax_t) 610 #endif 611 next_pattern.ra_mask, 612 next_pattern.ra_mode); 613 return; 614 615 out: 616 rtwvif->rate_pattern.enable = false; 617 rtw89_debug(rtwdev, RTW89_DBG_RA, "unset rate pattern\n"); 618 } 619 620 static void rtw89_phy_ra_updata_sta_iter(void *data, struct ieee80211_sta *sta) 621 { 622 struct rtw89_dev *rtwdev = (struct rtw89_dev *)data; 623 624 rtw89_phy_ra_updata_sta(rtwdev, sta, IEEE80211_RC_SUPP_RATES_CHANGED); 625 } 626 627 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev) 628 { 629 ieee80211_iterate_stations_atomic(rtwdev->hw, 630 rtw89_phy_ra_updata_sta_iter, 631 rtwdev); 632 } 633 634 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta) 635 { 636 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 637 struct rtw89_ra_info *ra = &rtwsta->ra; 638 u8 rssi = ewma_rssi_read(&rtwsta->avg_rssi) >> RSSI_FACTOR; 639 bool csi = rtw89_sta_has_beamformer_cap(sta); 640 641 rtw89_phy_ra_sta_update(rtwdev, sta, csi); 642 643 if (rssi > 40) 644 ra->init_rate_lv = 1; 645 else if (rssi > 20) 646 ra->init_rate_lv = 2; 647 else if (rssi > 1) 648 ra->init_rate_lv = 3; 649 else 650 ra->init_rate_lv = 0; 651 ra->upd_all = 1; 652 rtw89_debug(rtwdev, RTW89_DBG_RA, 653 "ra assoc: macid = %d, mode = %d, bw = %d, nss = %d, lv = %d", 654 ra->macid, 655 ra->mode_ctrl, 656 ra->bw_cap, 657 ra->ss_num, 658 ra->init_rate_lv); 659 rtw89_debug(rtwdev, RTW89_DBG_RA, 660 "ra assoc: dcm = %d, er = %d, ldpc = %d, stbc = %d, gi = %d %d", 661 ra->dcm_cap, 662 ra->er_cap, 663 ra->ldpc_cap, 664 ra->stbc_cap, 665 ra->en_sgi, 666 ra->giltf); 667 668 rtw89_fw_h2c_ra(rtwdev, ra, csi); 669 } 670 671 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, 672 const struct rtw89_chan *chan, 673 enum rtw89_bandwidth dbw) 674 { 675 enum rtw89_bandwidth cbw = chan->band_width; 676 u8 pri_ch = chan->primary_channel; 677 u8 central_ch = chan->channel; 678 u8 txsc_idx = 0; 679 u8 tmp = 0; 680 681 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 682 return txsc_idx; 683 684 switch (cbw) { 685 case RTW89_CHANNEL_WIDTH_40: 686 txsc_idx = pri_ch > central_ch ? 1 : 2; 687 break; 688 case RTW89_CHANNEL_WIDTH_80: 689 if (dbw == RTW89_CHANNEL_WIDTH_20) { 690 if (pri_ch > central_ch) 691 txsc_idx = (pri_ch - central_ch) >> 1; 692 else 693 txsc_idx = ((central_ch - pri_ch) >> 1) + 1; 694 } else { 695 txsc_idx = pri_ch > central_ch ? 9 : 10; 696 } 697 break; 698 case RTW89_CHANNEL_WIDTH_160: 699 if (pri_ch > central_ch) 700 tmp = (pri_ch - central_ch) >> 1; 701 else 702 tmp = ((central_ch - pri_ch) >> 1) + 1; 703 704 if (dbw == RTW89_CHANNEL_WIDTH_20) { 705 txsc_idx = tmp; 706 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 707 if (tmp == 1 || tmp == 3) 708 txsc_idx = 9; 709 else if (tmp == 5 || tmp == 7) 710 txsc_idx = 11; 711 else if (tmp == 2 || tmp == 4) 712 txsc_idx = 10; 713 else if (tmp == 6 || tmp == 8) 714 txsc_idx = 12; 715 else 716 return 0xff; 717 } else { 718 txsc_idx = pri_ch > central_ch ? 13 : 14; 719 } 720 break; 721 case RTW89_CHANNEL_WIDTH_80_80: 722 if (dbw == RTW89_CHANNEL_WIDTH_20) { 723 if (pri_ch > central_ch) 724 txsc_idx = (10 - (pri_ch - central_ch)) >> 1; 725 else 726 txsc_idx = ((central_ch - pri_ch) >> 1) + 5; 727 } else if (dbw == RTW89_CHANNEL_WIDTH_40) { 728 txsc_idx = pri_ch > central_ch ? 10 : 12; 729 } else { 730 txsc_idx = 14; 731 } 732 break; 733 default: 734 break; 735 } 736 737 return txsc_idx; 738 } 739 EXPORT_SYMBOL(rtw89_phy_get_txsc); 740 741 u8 rtw89_phy_get_txsb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 742 enum rtw89_bandwidth dbw) 743 { 744 enum rtw89_bandwidth cbw = chan->band_width; 745 u8 pri_ch = chan->primary_channel; 746 u8 central_ch = chan->channel; 747 u8 txsb_idx = 0; 748 749 if (cbw == dbw || cbw == RTW89_CHANNEL_WIDTH_20) 750 return txsb_idx; 751 752 switch (cbw) { 753 case RTW89_CHANNEL_WIDTH_40: 754 txsb_idx = pri_ch > central_ch ? 1 : 0; 755 break; 756 case RTW89_CHANNEL_WIDTH_80: 757 if (dbw == RTW89_CHANNEL_WIDTH_20) 758 txsb_idx = (pri_ch - central_ch + 6) / 4; 759 else 760 txsb_idx = pri_ch > central_ch ? 1 : 0; 761 break; 762 case RTW89_CHANNEL_WIDTH_160: 763 if (dbw == RTW89_CHANNEL_WIDTH_20) 764 txsb_idx = (pri_ch - central_ch + 14) / 4; 765 else if (dbw == RTW89_CHANNEL_WIDTH_40) 766 txsb_idx = (pri_ch - central_ch + 12) / 8; 767 else 768 txsb_idx = pri_ch > central_ch ? 1 : 0; 769 break; 770 case RTW89_CHANNEL_WIDTH_320: 771 if (dbw == RTW89_CHANNEL_WIDTH_20) 772 txsb_idx = (pri_ch - central_ch + 30) / 4; 773 else if (dbw == RTW89_CHANNEL_WIDTH_40) 774 txsb_idx = (pri_ch - central_ch + 28) / 8; 775 else if (dbw == RTW89_CHANNEL_WIDTH_80) 776 txsb_idx = (pri_ch - central_ch + 24) / 16; 777 else 778 txsb_idx = pri_ch > central_ch ? 1 : 0; 779 break; 780 default: 781 break; 782 } 783 784 return txsb_idx; 785 } 786 EXPORT_SYMBOL(rtw89_phy_get_txsb); 787 788 static bool rtw89_phy_check_swsi_busy(struct rtw89_dev *rtwdev) 789 { 790 return !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_W_BUSY_V1) || 791 !!rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, B_SWSI_R_BUSY_V1); 792 } 793 794 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 795 u32 addr, u32 mask) 796 { 797 const struct rtw89_chip_info *chip = rtwdev->chip; 798 const u32 *base_addr = chip->rf_base_addr; 799 u32 val, direct_addr; 800 801 if (rf_path >= rtwdev->chip->rf_path_num) { 802 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 803 return INV_RF_DATA; 804 } 805 806 addr &= 0xff; 807 direct_addr = base_addr[rf_path] + (addr << 2); 808 mask &= RFREG_MASK; 809 810 val = rtw89_phy_read32_mask(rtwdev, direct_addr, mask); 811 812 return val; 813 } 814 EXPORT_SYMBOL(rtw89_phy_read_rf); 815 816 static u32 rtw89_phy_read_rf_a(struct rtw89_dev *rtwdev, 817 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 818 { 819 bool busy; 820 bool done; 821 u32 val; 822 int ret; 823 824 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 825 1, 30, false, rtwdev); 826 if (ret) { 827 rtw89_err(rtwdev, "read rf busy swsi\n"); 828 return INV_RF_DATA; 829 } 830 831 mask &= RFREG_MASK; 832 833 val = FIELD_PREP(B_SWSI_READ_ADDR_PATH_V1, rf_path) | 834 FIELD_PREP(B_SWSI_READ_ADDR_ADDR_V1, addr); 835 rtw89_phy_write32_mask(rtwdev, R_SWSI_READ_ADDR_V1, B_SWSI_READ_ADDR_V1, val); 836 udelay(2); 837 838 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 1, 839 30, false, rtwdev, R_SWSI_V1, 840 B_SWSI_R_DATA_DONE_V1); 841 if (ret) { 842 rtw89_err(rtwdev, "read swsi busy\n"); 843 return INV_RF_DATA; 844 } 845 846 return rtw89_phy_read32_mask(rtwdev, R_SWSI_V1, mask); 847 } 848 849 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 850 u32 addr, u32 mask) 851 { 852 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 853 854 if (rf_path >= rtwdev->chip->rf_path_num) { 855 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 856 return INV_RF_DATA; 857 } 858 859 if (ad_sel) 860 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 861 else 862 return rtw89_phy_read_rf_a(rtwdev, rf_path, addr, mask); 863 } 864 EXPORT_SYMBOL(rtw89_phy_read_rf_v1); 865 866 static u32 rtw89_phy_read_full_rf_v2_a(struct rtw89_dev *rtwdev, 867 enum rtw89_rf_path rf_path, u32 addr) 868 { 869 static const u16 r_addr_ofst[2] = {0x2C24, 0x2D24}; 870 static const u16 addr_ofst[2] = {0x2ADC, 0x2BDC}; 871 bool busy, done; 872 int ret; 873 u32 val; 874 875 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_CTL_MASK, 0x1); 876 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy, 877 1, 3800, false, 878 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_BUSY); 879 if (ret) { 880 rtw89_warn(rtwdev, "poll HWSI is busy\n"); 881 return INV_RF_DATA; 882 } 883 884 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_MASK, addr); 885 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_RD, 0x1); 886 udelay(2); 887 888 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, done, done, 889 1, 3800, false, 890 rtwdev, r_addr_ofst[rf_path], B_HWSI_VAL_RDONE); 891 if (ret) { 892 rtw89_warn(rtwdev, "read HWSI is busy\n"); 893 val = INV_RF_DATA; 894 goto out; 895 } 896 897 val = rtw89_phy_read32_mask(rtwdev, r_addr_ofst[rf_path], RFREG_MASK); 898 out: 899 rtw89_phy_write32_mask(rtwdev, addr_ofst[rf_path], B_HWSI_ADD_POLL_MASK, 0); 900 901 return val; 902 } 903 904 static u32 rtw89_phy_read_rf_v2_a(struct rtw89_dev *rtwdev, 905 enum rtw89_rf_path rf_path, u32 addr, u32 mask) 906 { 907 u32 val; 908 909 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr); 910 911 return (val & mask) >> __ffs(mask); 912 } 913 914 u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 915 u32 addr, u32 mask) 916 { 917 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK); 918 919 if (rf_path >= rtwdev->chip->rf_path_num) { 920 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 921 return INV_RF_DATA; 922 } 923 924 if (ad_sel) 925 return rtw89_phy_read_rf(rtwdev, rf_path, addr, mask); 926 else 927 return rtw89_phy_read_rf_v2_a(rtwdev, rf_path, addr, mask); 928 } 929 EXPORT_SYMBOL(rtw89_phy_read_rf_v2); 930 931 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 932 u32 addr, u32 mask, u32 data) 933 { 934 const struct rtw89_chip_info *chip = rtwdev->chip; 935 const u32 *base_addr = chip->rf_base_addr; 936 u32 direct_addr; 937 938 if (rf_path >= rtwdev->chip->rf_path_num) { 939 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 940 return false; 941 } 942 943 addr &= 0xff; 944 direct_addr = base_addr[rf_path] + (addr << 2); 945 mask &= RFREG_MASK; 946 947 rtw89_phy_write32_mask(rtwdev, direct_addr, mask, data); 948 949 /* delay to ensure writing properly */ 950 udelay(1); 951 952 return true; 953 } 954 EXPORT_SYMBOL(rtw89_phy_write_rf); 955 956 static bool rtw89_phy_write_rf_a(struct rtw89_dev *rtwdev, 957 enum rtw89_rf_path rf_path, u32 addr, u32 mask, 958 u32 data) 959 { 960 u8 bit_shift; 961 u32 val; 962 bool busy, b_msk_en = false; 963 int ret; 964 965 ret = read_poll_timeout_atomic(rtw89_phy_check_swsi_busy, busy, !busy, 966 1, 30, false, rtwdev); 967 if (ret) { 968 rtw89_err(rtwdev, "write rf busy swsi\n"); 969 return false; 970 } 971 972 data &= RFREG_MASK; 973 mask &= RFREG_MASK; 974 975 if (mask != RFREG_MASK) { 976 b_msk_en = true; 977 rtw89_phy_write32_mask(rtwdev, R_SWSI_BIT_MASK_V1, RFREG_MASK, 978 mask); 979 bit_shift = __ffs(mask); 980 data = (data << bit_shift) & RFREG_MASK; 981 } 982 983 val = FIELD_PREP(B_SWSI_DATA_BIT_MASK_EN_V1, b_msk_en) | 984 FIELD_PREP(B_SWSI_DATA_PATH_V1, rf_path) | 985 FIELD_PREP(B_SWSI_DATA_ADDR_V1, addr) | 986 FIELD_PREP(B_SWSI_DATA_VAL_V1, data); 987 988 rtw89_phy_write32_mask(rtwdev, R_SWSI_DATA_V1, MASKDWORD, val); 989 990 return true; 991 } 992 993 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 994 u32 addr, u32 mask, u32 data) 995 { 996 bool ad_sel = FIELD_GET(RTW89_RF_ADDR_ADSEL_MASK, addr); 997 998 if (rf_path >= rtwdev->chip->rf_path_num) { 999 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 1000 return false; 1001 } 1002 1003 if (ad_sel) 1004 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 1005 else 1006 return rtw89_phy_write_rf_a(rtwdev, rf_path, addr, mask, data); 1007 } 1008 EXPORT_SYMBOL(rtw89_phy_write_rf_v1); 1009 1010 static 1011 bool rtw89_phy_write_full_rf_v2_a(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 1012 u32 addr, u32 data) 1013 { 1014 static const u32 addr_is_idle[2] = {0x2C24, 0x2D24}; 1015 static const u32 addr_ofst[2] = {0x2AE0, 0x2BE0}; 1016 bool busy; 1017 u32 val; 1018 int ret; 1019 1020 ret = read_poll_timeout_atomic(rtw89_phy_read32_mask, busy, !busy, 1021 1, 3800, false, 1022 rtwdev, addr_is_idle[rf_path], BIT(29)); 1023 if (ret) { 1024 rtw89_warn(rtwdev, "[%s] HWSI is busy\n", __func__); 1025 return false; 1026 } 1027 1028 val = u32_encode_bits(addr, B_HWSI_DATA_ADDR) | 1029 u32_encode_bits(data, B_HWSI_DATA_VAL); 1030 1031 rtw89_phy_write32(rtwdev, addr_ofst[rf_path], val); 1032 1033 return true; 1034 } 1035 1036 static 1037 bool rtw89_phy_write_rf_a_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 1038 u32 addr, u32 mask, u32 data) 1039 { 1040 u32 val; 1041 1042 if (mask == RFREG_MASK) { 1043 val = data; 1044 } else { 1045 val = rtw89_phy_read_full_rf_v2_a(rtwdev, rf_path, addr); 1046 val &= ~mask; 1047 val |= (data << __ffs(mask)) & mask; 1048 } 1049 1050 return rtw89_phy_write_full_rf_v2_a(rtwdev, rf_path, addr, val); 1051 } 1052 1053 bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 1054 u32 addr, u32 mask, u32 data) 1055 { 1056 bool ad_sel = u32_get_bits(addr, RTW89_RF_ADDR_ADSEL_MASK); 1057 1058 if (rf_path >= rtwdev->chip->rf_path_num) { 1059 rtw89_err(rtwdev, "unsupported rf path (%d)\n", rf_path); 1060 return INV_RF_DATA; 1061 } 1062 1063 if (ad_sel) 1064 return rtw89_phy_write_rf(rtwdev, rf_path, addr, mask, data); 1065 else 1066 return rtw89_phy_write_rf_a_v2(rtwdev, rf_path, addr, mask, data); 1067 } 1068 EXPORT_SYMBOL(rtw89_phy_write_rf_v2); 1069 1070 static bool rtw89_chip_rf_v1(struct rtw89_dev *rtwdev) 1071 { 1072 return rtwdev->chip->ops->write_rf == rtw89_phy_write_rf_v1; 1073 } 1074 1075 static void rtw89_phy_bb_reset(struct rtw89_dev *rtwdev, 1076 enum rtw89_phy_idx phy_idx) 1077 { 1078 const struct rtw89_chip_info *chip = rtwdev->chip; 1079 1080 chip->ops->bb_reset(rtwdev, phy_idx); 1081 } 1082 1083 static void rtw89_phy_config_bb_reg(struct rtw89_dev *rtwdev, 1084 const struct rtw89_reg2_def *reg, 1085 enum rtw89_rf_path rf_path, 1086 void *extra_data) 1087 { 1088 u32 addr; 1089 1090 if (reg->addr == 0xfe) { 1091 mdelay(50); 1092 } else if (reg->addr == 0xfd) { 1093 mdelay(5); 1094 } else if (reg->addr == 0xfc) { 1095 mdelay(1); 1096 } else if (reg->addr == 0xfb) { 1097 udelay(50); 1098 } else if (reg->addr == 0xfa) { 1099 udelay(5); 1100 } else if (reg->addr == 0xf9) { 1101 udelay(1); 1102 } else if (reg->data == BYPASS_CR_DATA) { 1103 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Bypass CR 0x%x\n", reg->addr); 1104 } else { 1105 addr = reg->addr; 1106 1107 if ((uintptr_t)extra_data == RTW89_PHY_1) 1108 addr += rtw89_phy0_phy1_offset(rtwdev, reg->addr); 1109 1110 rtw89_phy_write32(rtwdev, addr, reg->data); 1111 } 1112 } 1113 1114 union rtw89_phy_bb_gain_arg { 1115 u32 addr; 1116 struct { 1117 union { 1118 u8 type; 1119 struct { 1120 u8 rxsc_start:4; 1121 u8 bw:4; 1122 }; 1123 }; 1124 u8 path; 1125 u8 gain_band; 1126 u8 cfg_type; 1127 }; 1128 } __packed; 1129 1130 static void 1131 rtw89_phy_cfg_bb_gain_error(struct rtw89_dev *rtwdev, 1132 union rtw89_phy_bb_gain_arg arg, u32 data) 1133 { 1134 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1135 u8 type = arg.type; 1136 u8 path = arg.path; 1137 u8 gband = arg.gain_band; 1138 int i; 1139 1140 switch (type) { 1141 case 0: 1142 for (i = 0; i < 4; i++, data >>= 8) 1143 gain->lna_gain[gband][path][i] = data & 0xff; 1144 break; 1145 case 1: 1146 for (i = 4; i < 7; i++, data >>= 8) 1147 gain->lna_gain[gband][path][i] = data & 0xff; 1148 break; 1149 case 2: 1150 for (i = 0; i < 2; i++, data >>= 8) 1151 gain->tia_gain[gband][path][i] = data & 0xff; 1152 break; 1153 default: 1154 rtw89_warn(rtwdev, 1155 "bb gain error {0x%x:0x%x} with unknown type: %d\n", 1156 arg.addr, data, type); 1157 break; 1158 } 1159 } 1160 1161 enum rtw89_phy_bb_rxsc_start_idx { 1162 RTW89_BB_RXSC_START_IDX_FULL = 0, 1163 RTW89_BB_RXSC_START_IDX_20 = 1, 1164 RTW89_BB_RXSC_START_IDX_20_1 = 5, 1165 RTW89_BB_RXSC_START_IDX_40 = 9, 1166 RTW89_BB_RXSC_START_IDX_80 = 13, 1167 }; 1168 1169 static void 1170 rtw89_phy_cfg_bb_rpl_ofst(struct rtw89_dev *rtwdev, 1171 union rtw89_phy_bb_gain_arg arg, u32 data) 1172 { 1173 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1174 u8 rxsc_start = arg.rxsc_start; 1175 u8 bw = arg.bw; 1176 u8 path = arg.path; 1177 u8 gband = arg.gain_band; 1178 u8 rxsc; 1179 s8 ofst; 1180 int i; 1181 1182 switch (bw) { 1183 case RTW89_CHANNEL_WIDTH_20: 1184 gain->rpl_ofst_20[gband][path] = (s8)data; 1185 break; 1186 case RTW89_CHANNEL_WIDTH_40: 1187 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 1188 gain->rpl_ofst_40[gband][path][0] = (s8)data; 1189 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 1190 for (i = 0; i < 2; i++, data >>= 8) { 1191 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 1192 ofst = (s8)(data & 0xff); 1193 gain->rpl_ofst_40[gband][path][rxsc] = ofst; 1194 } 1195 } 1196 break; 1197 case RTW89_CHANNEL_WIDTH_80: 1198 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 1199 gain->rpl_ofst_80[gband][path][0] = (s8)data; 1200 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 1201 for (i = 0; i < 4; i++, data >>= 8) { 1202 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 1203 ofst = (s8)(data & 0xff); 1204 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 1205 } 1206 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 1207 for (i = 0; i < 2; i++, data >>= 8) { 1208 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 1209 ofst = (s8)(data & 0xff); 1210 gain->rpl_ofst_80[gband][path][rxsc] = ofst; 1211 } 1212 } 1213 break; 1214 case RTW89_CHANNEL_WIDTH_160: 1215 if (rxsc_start == RTW89_BB_RXSC_START_IDX_FULL) { 1216 gain->rpl_ofst_160[gband][path][0] = (s8)data; 1217 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20) { 1218 for (i = 0; i < 4; i++, data >>= 8) { 1219 rxsc = RTW89_BB_RXSC_START_IDX_20 + i; 1220 ofst = (s8)(data & 0xff); 1221 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1222 } 1223 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_20_1) { 1224 for (i = 0; i < 4; i++, data >>= 8) { 1225 rxsc = RTW89_BB_RXSC_START_IDX_20_1 + i; 1226 ofst = (s8)(data & 0xff); 1227 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1228 } 1229 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_40) { 1230 for (i = 0; i < 4; i++, data >>= 8) { 1231 rxsc = RTW89_BB_RXSC_START_IDX_40 + i; 1232 ofst = (s8)(data & 0xff); 1233 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1234 } 1235 } else if (rxsc_start == RTW89_BB_RXSC_START_IDX_80) { 1236 for (i = 0; i < 2; i++, data >>= 8) { 1237 rxsc = RTW89_BB_RXSC_START_IDX_80 + i; 1238 ofst = (s8)(data & 0xff); 1239 gain->rpl_ofst_160[gband][path][rxsc] = ofst; 1240 } 1241 } 1242 break; 1243 default: 1244 rtw89_warn(rtwdev, 1245 "bb rpl ofst {0x%x:0x%x} with unknown bw: %d\n", 1246 arg.addr, data, bw); 1247 break; 1248 } 1249 } 1250 1251 static void 1252 rtw89_phy_cfg_bb_gain_bypass(struct rtw89_dev *rtwdev, 1253 union rtw89_phy_bb_gain_arg arg, u32 data) 1254 { 1255 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1256 u8 type = arg.type; 1257 u8 path = arg.path; 1258 u8 gband = arg.gain_band; 1259 int i; 1260 1261 switch (type) { 1262 case 0: 1263 for (i = 0; i < 4; i++, data >>= 8) 1264 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 1265 break; 1266 case 1: 1267 for (i = 4; i < 7; i++, data >>= 8) 1268 gain->lna_gain_bypass[gband][path][i] = data & 0xff; 1269 break; 1270 default: 1271 rtw89_warn(rtwdev, 1272 "bb gain bypass {0x%x:0x%x} with unknown type: %d\n", 1273 arg.addr, data, type); 1274 break; 1275 } 1276 } 1277 1278 static void 1279 rtw89_phy_cfg_bb_gain_op1db(struct rtw89_dev *rtwdev, 1280 union rtw89_phy_bb_gain_arg arg, u32 data) 1281 { 1282 struct rtw89_phy_bb_gain_info *gain = &rtwdev->bb_gain.ax; 1283 u8 type = arg.type; 1284 u8 path = arg.path; 1285 u8 gband = arg.gain_band; 1286 int i; 1287 1288 switch (type) { 1289 case 0: 1290 for (i = 0; i < 4; i++, data >>= 8) 1291 gain->lna_op1db[gband][path][i] = data & 0xff; 1292 break; 1293 case 1: 1294 for (i = 4; i < 7; i++, data >>= 8) 1295 gain->lna_op1db[gband][path][i] = data & 0xff; 1296 break; 1297 case 2: 1298 for (i = 0; i < 4; i++, data >>= 8) 1299 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1300 break; 1301 case 3: 1302 for (i = 4; i < 8; i++, data >>= 8) 1303 gain->tia_lna_op1db[gband][path][i] = data & 0xff; 1304 break; 1305 default: 1306 rtw89_warn(rtwdev, 1307 "bb gain op1db {0x%x:0x%x} with unknown type: %d\n", 1308 arg.addr, data, type); 1309 break; 1310 } 1311 } 1312 1313 static void rtw89_phy_config_bb_gain_ax(struct rtw89_dev *rtwdev, 1314 const struct rtw89_reg2_def *reg, 1315 enum rtw89_rf_path rf_path, 1316 void *extra_data) 1317 { 1318 const struct rtw89_chip_info *chip = rtwdev->chip; 1319 union rtw89_phy_bb_gain_arg arg = { .addr = reg->addr }; 1320 struct rtw89_efuse *efuse = &rtwdev->efuse; 1321 1322 if (arg.gain_band >= RTW89_BB_GAIN_BAND_NR) 1323 return; 1324 1325 if (arg.path >= chip->rf_path_num) 1326 return; 1327 1328 if (arg.addr >= 0xf9 && arg.addr <= 0xfe) { 1329 rtw89_warn(rtwdev, "bb gain table with flow ctrl\n"); 1330 return; 1331 } 1332 1333 switch (arg.cfg_type) { 1334 case 0: 1335 rtw89_phy_cfg_bb_gain_error(rtwdev, arg, reg->data); 1336 break; 1337 case 1: 1338 rtw89_phy_cfg_bb_rpl_ofst(rtwdev, arg, reg->data); 1339 break; 1340 case 2: 1341 rtw89_phy_cfg_bb_gain_bypass(rtwdev, arg, reg->data); 1342 break; 1343 case 3: 1344 rtw89_phy_cfg_bb_gain_op1db(rtwdev, arg, reg->data); 1345 break; 1346 case 4: 1347 /* This cfg_type is only used by rfe_type >= 50 with eFEM */ 1348 if (efuse->rfe_type < 50) 1349 break; 1350 fallthrough; 1351 default: 1352 rtw89_warn(rtwdev, 1353 "bb gain {0x%x:0x%x} with unknown cfg type: %d\n", 1354 arg.addr, reg->data, arg.cfg_type); 1355 break; 1356 } 1357 } 1358 1359 static void 1360 rtw89_phy_cofig_rf_reg_store(struct rtw89_dev *rtwdev, 1361 const struct rtw89_reg2_def *reg, 1362 enum rtw89_rf_path rf_path, 1363 struct rtw89_fw_h2c_rf_reg_info *info) 1364 { 1365 u16 idx = info->curr_idx % RTW89_H2C_RF_PAGE_SIZE; 1366 u8 page = info->curr_idx / RTW89_H2C_RF_PAGE_SIZE; 1367 1368 if (page >= RTW89_H2C_RF_PAGE_NUM) { 1369 rtw89_warn(rtwdev, "RF parameters exceed size. path=%d, idx=%d", 1370 rf_path, info->curr_idx); 1371 return; 1372 } 1373 1374 info->rtw89_phy_config_rf_h2c[page][idx] = 1375 cpu_to_le32((reg->addr << 20) | reg->data); 1376 info->curr_idx++; 1377 } 1378 1379 static int rtw89_phy_config_rf_reg_fw(struct rtw89_dev *rtwdev, 1380 struct rtw89_fw_h2c_rf_reg_info *info) 1381 { 1382 u16 remain = info->curr_idx; 1383 u16 len = 0; 1384 u8 i; 1385 int ret = 0; 1386 1387 if (remain > RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE) { 1388 rtw89_warn(rtwdev, 1389 "rf reg h2c total len %d larger than %d\n", 1390 remain, RTW89_H2C_RF_PAGE_NUM * RTW89_H2C_RF_PAGE_SIZE); 1391 ret = -EINVAL; 1392 goto out; 1393 } 1394 1395 for (i = 0; i < RTW89_H2C_RF_PAGE_NUM && remain; i++, remain -= len) { 1396 len = remain > RTW89_H2C_RF_PAGE_SIZE ? RTW89_H2C_RF_PAGE_SIZE : remain; 1397 ret = rtw89_fw_h2c_rf_reg(rtwdev, info, len * 4, i); 1398 if (ret) 1399 goto out; 1400 } 1401 out: 1402 info->curr_idx = 0; 1403 1404 return ret; 1405 } 1406 1407 static void rtw89_phy_config_rf_reg_noio(struct rtw89_dev *rtwdev, 1408 const struct rtw89_reg2_def *reg, 1409 enum rtw89_rf_path rf_path, 1410 void *extra_data) 1411 { 1412 u32 addr = reg->addr; 1413 1414 if (addr == 0xfe || addr == 0xfd || addr == 0xfc || addr == 0xfb || 1415 addr == 0xfa || addr == 0xf9) 1416 return; 1417 1418 if (rtw89_chip_rf_v1(rtwdev) && addr < 0x100) 1419 return; 1420 1421 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1422 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1423 } 1424 1425 static void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev, 1426 const struct rtw89_reg2_def *reg, 1427 enum rtw89_rf_path rf_path, 1428 void *extra_data) 1429 { 1430 if (reg->addr == 0xfe) { 1431 mdelay(50); 1432 } else if (reg->addr == 0xfd) { 1433 mdelay(5); 1434 } else if (reg->addr == 0xfc) { 1435 mdelay(1); 1436 } else if (reg->addr == 0xfb) { 1437 udelay(50); 1438 } else if (reg->addr == 0xfa) { 1439 udelay(5); 1440 } else if (reg->addr == 0xf9) { 1441 udelay(1); 1442 } else { 1443 rtw89_write_rf(rtwdev, rf_path, reg->addr, 0xfffff, reg->data); 1444 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1445 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1446 } 1447 } 1448 1449 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, 1450 const struct rtw89_reg2_def *reg, 1451 enum rtw89_rf_path rf_path, 1452 void *extra_data) 1453 { 1454 rtw89_write_rf(rtwdev, rf_path, reg->addr, RFREG_MASK, reg->data); 1455 1456 if (reg->addr < 0x100) 1457 return; 1458 1459 rtw89_phy_cofig_rf_reg_store(rtwdev, reg, rf_path, 1460 (struct rtw89_fw_h2c_rf_reg_info *)extra_data); 1461 } 1462 EXPORT_SYMBOL(rtw89_phy_config_rf_reg_v1); 1463 1464 static int rtw89_phy_sel_headline(struct rtw89_dev *rtwdev, 1465 const struct rtw89_phy_table *table, 1466 u32 *headline_size, u32 *headline_idx, 1467 u8 rfe, u8 cv) 1468 { 1469 const struct rtw89_reg2_def *reg; 1470 u32 headline; 1471 u32 compare, target; 1472 u8 rfe_para, cv_para; 1473 u8 cv_max = 0; 1474 bool case_matched = false; 1475 u32 i; 1476 1477 for (i = 0; i < table->n_regs; i++) { 1478 reg = &table->regs[i]; 1479 headline = get_phy_headline(reg->addr); 1480 if (headline != PHY_HEADLINE_VALID) 1481 break; 1482 } 1483 *headline_size = i; 1484 if (*headline_size == 0) 1485 return 0; 1486 1487 /* case 1: RFE match, CV match */ 1488 compare = get_phy_compare(rfe, cv); 1489 for (i = 0; i < *headline_size; i++) { 1490 reg = &table->regs[i]; 1491 target = get_phy_target(reg->addr); 1492 if (target == compare) { 1493 *headline_idx = i; 1494 return 0; 1495 } 1496 } 1497 1498 /* case 2: RFE match, CV don't care */ 1499 compare = get_phy_compare(rfe, PHY_COND_DONT_CARE); 1500 for (i = 0; i < *headline_size; i++) { 1501 reg = &table->regs[i]; 1502 target = get_phy_target(reg->addr); 1503 if (target == compare) { 1504 *headline_idx = i; 1505 return 0; 1506 } 1507 } 1508 1509 /* case 3: RFE match, CV max in table */ 1510 for (i = 0; i < *headline_size; i++) { 1511 reg = &table->regs[i]; 1512 rfe_para = get_phy_cond_rfe(reg->addr); 1513 cv_para = get_phy_cond_cv(reg->addr); 1514 if (rfe_para == rfe) { 1515 if (cv_para >= cv_max) { 1516 cv_max = cv_para; 1517 *headline_idx = i; 1518 case_matched = true; 1519 } 1520 } 1521 } 1522 1523 if (case_matched) 1524 return 0; 1525 1526 /* case 4: RFE don't care, CV max in table */ 1527 for (i = 0; i < *headline_size; i++) { 1528 reg = &table->regs[i]; 1529 rfe_para = get_phy_cond_rfe(reg->addr); 1530 cv_para = get_phy_cond_cv(reg->addr); 1531 if (rfe_para == PHY_COND_DONT_CARE) { 1532 if (cv_para >= cv_max) { 1533 cv_max = cv_para; 1534 *headline_idx = i; 1535 case_matched = true; 1536 } 1537 } 1538 } 1539 1540 if (case_matched) 1541 return 0; 1542 1543 return -EINVAL; 1544 } 1545 1546 static void rtw89_phy_init_reg(struct rtw89_dev *rtwdev, 1547 const struct rtw89_phy_table *table, 1548 void (*config)(struct rtw89_dev *rtwdev, 1549 const struct rtw89_reg2_def *reg, 1550 enum rtw89_rf_path rf_path, 1551 void *data), 1552 void *extra_data) 1553 { 1554 const struct rtw89_reg2_def *reg; 1555 enum rtw89_rf_path rf_path = table->rf_path; 1556 u8 rfe = rtwdev->efuse.rfe_type; 1557 u8 cv = rtwdev->hal.cv; 1558 u32 i; 1559 u32 headline_size = 0, headline_idx = 0; 1560 u32 target = 0, cfg_target; 1561 u8 cond; 1562 bool is_matched = true; 1563 bool target_found = false; 1564 int ret; 1565 1566 ret = rtw89_phy_sel_headline(rtwdev, table, &headline_size, 1567 &headline_idx, rfe, cv); 1568 if (ret) { 1569 rtw89_err(rtwdev, "invalid PHY package: %d/%d\n", rfe, cv); 1570 return; 1571 } 1572 1573 cfg_target = get_phy_target(table->regs[headline_idx].addr); 1574 for (i = headline_size; i < table->n_regs; i++) { 1575 reg = &table->regs[i]; 1576 cond = get_phy_cond(reg->addr); 1577 switch (cond) { 1578 case PHY_COND_BRANCH_IF: 1579 case PHY_COND_BRANCH_ELIF: 1580 target = get_phy_target(reg->addr); 1581 break; 1582 case PHY_COND_BRANCH_ELSE: 1583 is_matched = false; 1584 if (!target_found) { 1585 rtw89_warn(rtwdev, "failed to load CR %x/%x\n", 1586 reg->addr, reg->data); 1587 return; 1588 } 1589 break; 1590 case PHY_COND_BRANCH_END: 1591 is_matched = true; 1592 target_found = false; 1593 break; 1594 case PHY_COND_CHECK: 1595 if (target_found) { 1596 is_matched = false; 1597 break; 1598 } 1599 1600 if (target == cfg_target) { 1601 is_matched = true; 1602 target_found = true; 1603 } else { 1604 is_matched = false; 1605 target_found = false; 1606 } 1607 break; 1608 default: 1609 if (is_matched) 1610 config(rtwdev, reg, rf_path, extra_data); 1611 break; 1612 } 1613 } 1614 } 1615 1616 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev) 1617 { 1618 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1619 const struct rtw89_chip_info *chip = rtwdev->chip; 1620 const struct rtw89_phy_table *bb_table; 1621 const struct rtw89_phy_table *bb_gain_table; 1622 1623 bb_table = elm_info->bb_tbl ? elm_info->bb_tbl : chip->bb_table; 1624 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, NULL); 1625 if (rtwdev->dbcc_en) 1626 rtw89_phy_init_reg(rtwdev, bb_table, rtw89_phy_config_bb_reg, 1627 (void *)RTW89_PHY_1); 1628 rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 1629 1630 bb_gain_table = elm_info->bb_gain ? elm_info->bb_gain : chip->bb_gain_table; 1631 if (bb_gain_table) 1632 rtw89_phy_init_reg(rtwdev, bb_gain_table, 1633 chip->phy_def->config_bb_gain, NULL); 1634 rtw89_phy_bb_reset(rtwdev, RTW89_PHY_0); 1635 } 1636 1637 static u32 rtw89_phy_nctl_poll(struct rtw89_dev *rtwdev) 1638 { 1639 rtw89_phy_write32(rtwdev, 0x8080, 0x4); 1640 udelay(1); 1641 return rtw89_phy_read32(rtwdev, 0x8080); 1642 } 1643 1644 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio) 1645 { 1646 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 1647 enum rtw89_rf_path rf_path, void *data); 1648 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1649 const struct rtw89_chip_info *chip = rtwdev->chip; 1650 const struct rtw89_phy_table *rf_table; 1651 struct rtw89_fw_h2c_rf_reg_info *rf_reg_info; 1652 u8 path; 1653 1654 rf_reg_info = kzalloc(sizeof(*rf_reg_info), GFP_KERNEL); 1655 if (!rf_reg_info) 1656 return; 1657 1658 for (path = RF_PATH_A; path < chip->rf_path_num; path++) { 1659 rf_table = elm_info->rf_radio[path] ? 1660 elm_info->rf_radio[path] : chip->rf_table[path]; 1661 rf_reg_info->rf_path = rf_table->rf_path; 1662 if (noio) 1663 config = rtw89_phy_config_rf_reg_noio; 1664 else 1665 config = rf_table->config ? rf_table->config : 1666 rtw89_phy_config_rf_reg; 1667 rtw89_phy_init_reg(rtwdev, rf_table, config, (void *)rf_reg_info); 1668 if (rtw89_phy_config_rf_reg_fw(rtwdev, rf_reg_info)) 1669 rtw89_warn(rtwdev, "rf path %d reg h2c config failed\n", 1670 rf_reg_info->rf_path); 1671 } 1672 kfree(rf_reg_info); 1673 } 1674 1675 static void rtw89_phy_preinit_rf_nctl_ax(struct rtw89_dev *rtwdev) 1676 { 1677 const struct rtw89_chip_info *chip = rtwdev->chip; 1678 u32 val; 1679 int ret; 1680 1681 /* IQK/DPK clock & reset */ 1682 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x3); 1683 rtw89_phy_write32_set(rtwdev, R_GNT_BT_WGT_EN, 0x1); 1684 rtw89_phy_write32_set(rtwdev, R_P0_PATH_RST, 0x8000000); 1685 if (chip->chip_id != RTL8851B) 1686 rtw89_phy_write32_set(rtwdev, R_P1_PATH_RST, 0x8000000); 1687 if (chip->chip_id == RTL8852B || chip->chip_id == RTL8852BT) 1688 rtw89_phy_write32_set(rtwdev, R_IOQ_IQK_DPK, 0x2); 1689 1690 /* check 0x8080 */ 1691 rtw89_phy_write32(rtwdev, R_NCTL_CFG, 0x8); 1692 1693 ret = read_poll_timeout(rtw89_phy_nctl_poll, val, val == 0x4, 10, 1694 1000, false, rtwdev); 1695 if (ret) 1696 #if defined(__linux__) 1697 rtw89_err(rtwdev, "failed to poll nctl block\n"); 1698 #elif defined(__FreeBSD__) 1699 rtw89_err(rtwdev, "failed to poll nctl block: ret %d val %#06x\n", ret, val); 1700 #endif 1701 } 1702 1703 static void rtw89_phy_init_rf_nctl(struct rtw89_dev *rtwdev) 1704 { 1705 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 1706 const struct rtw89_chip_info *chip = rtwdev->chip; 1707 const struct rtw89_phy_table *nctl_table; 1708 1709 rtw89_phy_preinit_rf_nctl(rtwdev); 1710 1711 nctl_table = elm_info->rf_nctl ? elm_info->rf_nctl : chip->nctl_table; 1712 rtw89_phy_init_reg(rtwdev, nctl_table, rtw89_phy_config_bb_reg, NULL); 1713 1714 if (chip->nctl_post_table) 1715 rtw89_rfk_parser(rtwdev, chip->nctl_post_table); 1716 } 1717 1718 static u32 rtw89_phy0_phy1_offset_ax(struct rtw89_dev *rtwdev, u32 addr) 1719 { 1720 u32 phy_page = addr >> 8; 1721 u32 ofst = 0; 1722 1723 switch (phy_page) { 1724 case 0x6: 1725 case 0x7: 1726 case 0x8: 1727 case 0x9: 1728 case 0xa: 1729 case 0xb: 1730 case 0xc: 1731 case 0xd: 1732 case 0x19: 1733 case 0x1a: 1734 case 0x1b: 1735 ofst = 0x2000; 1736 break; 1737 default: 1738 /* warning case */ 1739 ofst = 0; 1740 break; 1741 } 1742 1743 if (phy_page >= 0x40 && phy_page <= 0x4f) 1744 ofst = 0x2000; 1745 1746 return ofst; 1747 } 1748 1749 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1750 u32 data, enum rtw89_phy_idx phy_idx) 1751 { 1752 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1753 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1754 rtw89_phy_write32_mask(rtwdev, addr, mask, data); 1755 } 1756 EXPORT_SYMBOL(rtw89_phy_write32_idx); 1757 1758 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1759 enum rtw89_phy_idx phy_idx) 1760 { 1761 if (rtwdev->dbcc_en && phy_idx == RTW89_PHY_1) 1762 addr += rtw89_phy0_phy1_offset(rtwdev, addr); 1763 return rtw89_phy_read32_mask(rtwdev, addr, mask); 1764 } 1765 EXPORT_SYMBOL(rtw89_phy_read32_idx); 1766 1767 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, 1768 u32 val) 1769 { 1770 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_0); 1771 1772 if (!rtwdev->dbcc_en) 1773 return; 1774 1775 rtw89_phy_write32_idx(rtwdev, addr, mask, val, RTW89_PHY_1); 1776 } 1777 EXPORT_SYMBOL(rtw89_phy_set_phy_regs); 1778 1779 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, 1780 const struct rtw89_phy_reg3_tbl *tbl) 1781 { 1782 const struct rtw89_reg3_def *reg3; 1783 int i; 1784 1785 for (i = 0; i < tbl->size; i++) { 1786 reg3 = &tbl->reg3[i]; 1787 rtw89_phy_write32_mask(rtwdev, reg3->addr, reg3->mask, reg3->data); 1788 } 1789 } 1790 EXPORT_SYMBOL(rtw89_phy_write_reg3_tbl); 1791 1792 static const u8 rtw89_rs_idx_num_ax[] = { 1793 [RTW89_RS_CCK] = RTW89_RATE_CCK_NUM, 1794 [RTW89_RS_OFDM] = RTW89_RATE_OFDM_NUM, 1795 [RTW89_RS_MCS] = RTW89_RATE_MCS_NUM_AX, 1796 [RTW89_RS_HEDCM] = RTW89_RATE_HEDCM_NUM, 1797 [RTW89_RS_OFFSET] = RTW89_RATE_OFFSET_NUM_AX, 1798 }; 1799 1800 static const u8 rtw89_rs_nss_num_ax[] = { 1801 [RTW89_RS_CCK] = 1, 1802 [RTW89_RS_OFDM] = 1, 1803 [RTW89_RS_MCS] = RTW89_NSS_NUM, 1804 [RTW89_RS_HEDCM] = RTW89_NSS_HEDCM_NUM, 1805 [RTW89_RS_OFFSET] = 1, 1806 }; 1807 1808 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev, 1809 struct rtw89_txpwr_byrate *head, 1810 const struct rtw89_rate_desc *desc) 1811 { 1812 switch (desc->rs) { 1813 case RTW89_RS_CCK: 1814 return &head->cck[desc->idx]; 1815 case RTW89_RS_OFDM: 1816 return &head->ofdm[desc->idx]; 1817 case RTW89_RS_MCS: 1818 return &head->mcs[desc->ofdma][desc->nss][desc->idx]; 1819 case RTW89_RS_HEDCM: 1820 return &head->hedcm[desc->ofdma][desc->nss][desc->idx]; 1821 case RTW89_RS_OFFSET: 1822 return &head->offset[desc->idx]; 1823 default: 1824 rtw89_warn(rtwdev, "unrecognized byr rs: %d\n", desc->rs); 1825 return &head->trap; 1826 } 1827 } 1828 1829 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, 1830 const struct rtw89_txpwr_table *tbl) 1831 { 1832 const struct rtw89_txpwr_byrate_cfg *cfg = tbl->data; 1833 const struct rtw89_txpwr_byrate_cfg *end = cfg + tbl->size; 1834 struct rtw89_txpwr_byrate *byr_head; 1835 struct rtw89_rate_desc desc = {}; 1836 s8 *byr; 1837 u32 data; 1838 u8 i; 1839 1840 for (; cfg < end; cfg++) { 1841 byr_head = &rtwdev->byr[cfg->band][0]; 1842 desc.rs = cfg->rs; 1843 desc.nss = cfg->nss; 1844 data = cfg->data; 1845 1846 for (i = 0; i < cfg->len; i++, data >>= 8) { 1847 desc.idx = cfg->shf + i; 1848 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, &desc); 1849 *byr = data & 0xff; 1850 } 1851 } 1852 } 1853 EXPORT_SYMBOL(rtw89_phy_load_txpwr_byrate); 1854 1855 static s8 rtw89_phy_txpwr_rf_to_mac(struct rtw89_dev *rtwdev, s8 txpwr_rf) 1856 { 1857 const struct rtw89_chip_info *chip = rtwdev->chip; 1858 1859 return txpwr_rf >> (chip->txpwr_factor_rf - chip->txpwr_factor_mac); 1860 } 1861 1862 static s8 rtw89_phy_txpwr_dbm_to_mac(struct rtw89_dev *rtwdev, s8 dbm) 1863 { 1864 const struct rtw89_chip_info *chip = rtwdev->chip; 1865 1866 return clamp_t(s16, dbm << chip->txpwr_factor_mac, -64, 63); 1867 } 1868 1869 static s8 rtw89_phy_txpwr_dbm_without_tolerance(s8 dbm) 1870 { 1871 const u8 tssi_deviation_point = 0; 1872 const u8 tssi_max_deviation = 2; 1873 1874 if (dbm <= tssi_deviation_point) 1875 dbm -= tssi_max_deviation; 1876 1877 return dbm; 1878 } 1879 1880 static s8 rtw89_phy_get_tpe_constraint(struct rtw89_dev *rtwdev, u8 band) 1881 { 1882 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 1883 const struct rtw89_reg_6ghz_tpe *tpe = ®ulatory->reg_6ghz_tpe; 1884 s8 cstr = S8_MAX; 1885 1886 if (band == RTW89_BAND_6G && tpe->valid) 1887 cstr = rtw89_phy_txpwr_dbm_without_tolerance(tpe->constraint); 1888 1889 return rtw89_phy_txpwr_dbm_to_mac(rtwdev, cstr); 1890 } 1891 1892 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw, 1893 const struct rtw89_rate_desc *rate_desc) 1894 { 1895 struct rtw89_txpwr_byrate *byr_head; 1896 s8 *byr; 1897 1898 if (rate_desc->rs == RTW89_RS_CCK) 1899 band = RTW89_BAND_2G; 1900 1901 byr_head = &rtwdev->byr[band][bw]; 1902 byr = rtw89_phy_raw_byr_seek(rtwdev, byr_head, rate_desc); 1903 1904 return rtw89_phy_txpwr_rf_to_mac(rtwdev, *byr); 1905 } 1906 1907 static u8 rtw89_channel_6g_to_idx(struct rtw89_dev *rtwdev, u8 channel_6g) 1908 { 1909 switch (channel_6g) { 1910 case 1 ... 29: 1911 return (channel_6g - 1) / 2; 1912 case 33 ... 61: 1913 return (channel_6g - 3) / 2; 1914 case 65 ... 93: 1915 return (channel_6g - 5) / 2; 1916 case 97 ... 125: 1917 return (channel_6g - 7) / 2; 1918 case 129 ... 157: 1919 return (channel_6g - 9) / 2; 1920 case 161 ... 189: 1921 return (channel_6g - 11) / 2; 1922 case 193 ... 221: 1923 return (channel_6g - 13) / 2; 1924 case 225 ... 253: 1925 return (channel_6g - 15) / 2; 1926 default: 1927 rtw89_warn(rtwdev, "unknown 6g channel: %d\n", channel_6g); 1928 return 0; 1929 } 1930 } 1931 1932 static u8 rtw89_channel_to_idx(struct rtw89_dev *rtwdev, u8 band, u8 channel) 1933 { 1934 if (band == RTW89_BAND_6G) 1935 return rtw89_channel_6g_to_idx(rtwdev, channel); 1936 1937 switch (channel) { 1938 case 1 ... 14: 1939 return channel - 1; 1940 case 36 ... 64: 1941 return (channel - 36) / 2; 1942 case 100 ... 144: 1943 return ((channel - 100) / 2) + 15; 1944 case 149 ... 177: 1945 return ((channel - 149) / 2) + 38; 1946 default: 1947 rtw89_warn(rtwdev, "unknown channel: %d\n", channel); 1948 return 0; 1949 } 1950 } 1951 1952 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, 1953 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch) 1954 { 1955 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 1956 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz; 1957 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz; 1958 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz; 1959 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 1960 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 1961 u32 freq = ieee80211_channel_to_frequency(ch, nl_band); 1962 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 1963 u8 regd = rtw89_regd_get(rtwdev, band); 1964 u8 reg6 = regulatory->reg_6ghz_power; 1965 s8 lmt = 0, sar; 1966 s8 cstr; 1967 1968 switch (band) { 1969 case RTW89_BAND_2G: 1970 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 1971 if (lmt) 1972 break; 1973 1974 lmt = (*rule_2ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx]; 1975 break; 1976 case RTW89_BAND_5G: 1977 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][regd][ch_idx]; 1978 if (lmt) 1979 break; 1980 1981 lmt = (*rule_5ghz->lmt)[bw][ntx][rs][bf][RTW89_WW][ch_idx]; 1982 break; 1983 case RTW89_BAND_6G: 1984 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][regd][reg6][ch_idx]; 1985 if (lmt) 1986 break; 1987 1988 lmt = (*rule_6ghz->lmt)[bw][ntx][rs][bf][RTW89_WW] 1989 [RTW89_REG_6GHZ_POWER_DFLT] 1990 [ch_idx]; 1991 break; 1992 default: 1993 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 1994 return 0; 1995 } 1996 1997 lmt = rtw89_phy_txpwr_rf_to_mac(rtwdev, lmt); 1998 sar = rtw89_query_sar(rtwdev, freq); 1999 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band); 2000 2001 return min3(lmt, sar, cstr); 2002 } 2003 EXPORT_SYMBOL(rtw89_phy_read_txpwr_limit); 2004 2005 #define __fill_txpwr_limit_nonbf_bf(ptr, band, bw, ntx, rs, ch) \ 2006 do { \ 2007 u8 __i; \ 2008 for (__i = 0; __i < RTW89_BF_NUM; __i++) \ 2009 ptr[__i] = rtw89_phy_read_txpwr_limit(rtwdev, \ 2010 band, \ 2011 bw, ntx, \ 2012 rs, __i, \ 2013 (ch)); \ 2014 } while (0) 2015 2016 static void rtw89_phy_fill_txpwr_limit_20m_ax(struct rtw89_dev *rtwdev, 2017 struct rtw89_txpwr_limit_ax *lmt, 2018 u8 band, u8 ntx, u8 ch) 2019 { 2020 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 2021 ntx, RTW89_RS_CCK, ch); 2022 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 2023 ntx, RTW89_RS_CCK, ch); 2024 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 2025 ntx, RTW89_RS_OFDM, ch); 2026 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 2027 RTW89_CHANNEL_WIDTH_20, 2028 ntx, RTW89_RS_MCS, ch); 2029 } 2030 2031 static void rtw89_phy_fill_txpwr_limit_40m_ax(struct rtw89_dev *rtwdev, 2032 struct rtw89_txpwr_limit_ax *lmt, 2033 u8 band, u8 ntx, u8 ch, u8 pri_ch) 2034 { 2035 __fill_txpwr_limit_nonbf_bf(lmt->cck_20m, band, RTW89_CHANNEL_WIDTH_20, 2036 ntx, RTW89_RS_CCK, ch - 2); 2037 __fill_txpwr_limit_nonbf_bf(lmt->cck_40m, band, RTW89_CHANNEL_WIDTH_40, 2038 ntx, RTW89_RS_CCK, ch); 2039 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 2040 ntx, RTW89_RS_OFDM, pri_ch); 2041 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 2042 RTW89_CHANNEL_WIDTH_20, 2043 ntx, RTW89_RS_MCS, ch - 2); 2044 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 2045 RTW89_CHANNEL_WIDTH_20, 2046 ntx, RTW89_RS_MCS, ch + 2); 2047 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 2048 RTW89_CHANNEL_WIDTH_40, 2049 ntx, RTW89_RS_MCS, ch); 2050 } 2051 2052 static void rtw89_phy_fill_txpwr_limit_80m_ax(struct rtw89_dev *rtwdev, 2053 struct rtw89_txpwr_limit_ax *lmt, 2054 u8 band, u8 ntx, u8 ch, u8 pri_ch) 2055 { 2056 s8 val_0p5_n[RTW89_BF_NUM]; 2057 s8 val_0p5_p[RTW89_BF_NUM]; 2058 u8 i; 2059 2060 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 2061 ntx, RTW89_RS_OFDM, pri_ch); 2062 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 2063 RTW89_CHANNEL_WIDTH_20, 2064 ntx, RTW89_RS_MCS, ch - 6); 2065 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 2066 RTW89_CHANNEL_WIDTH_20, 2067 ntx, RTW89_RS_MCS, ch - 2); 2068 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 2069 RTW89_CHANNEL_WIDTH_20, 2070 ntx, RTW89_RS_MCS, ch + 2); 2071 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 2072 RTW89_CHANNEL_WIDTH_20, 2073 ntx, RTW89_RS_MCS, ch + 6); 2074 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 2075 RTW89_CHANNEL_WIDTH_40, 2076 ntx, RTW89_RS_MCS, ch - 4); 2077 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 2078 RTW89_CHANNEL_WIDTH_40, 2079 ntx, RTW89_RS_MCS, ch + 4); 2080 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 2081 RTW89_CHANNEL_WIDTH_80, 2082 ntx, RTW89_RS_MCS, ch); 2083 2084 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 2085 ntx, RTW89_RS_MCS, ch - 4); 2086 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 2087 ntx, RTW89_RS_MCS, ch + 4); 2088 2089 for (i = 0; i < RTW89_BF_NUM; i++) 2090 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 2091 } 2092 2093 static void rtw89_phy_fill_txpwr_limit_160m_ax(struct rtw89_dev *rtwdev, 2094 struct rtw89_txpwr_limit_ax *lmt, 2095 u8 band, u8 ntx, u8 ch, u8 pri_ch) 2096 { 2097 s8 val_0p5_n[RTW89_BF_NUM]; 2098 s8 val_0p5_p[RTW89_BF_NUM]; 2099 s8 val_2p5_n[RTW89_BF_NUM]; 2100 s8 val_2p5_p[RTW89_BF_NUM]; 2101 u8 i; 2102 2103 /* fill ofdm section */ 2104 __fill_txpwr_limit_nonbf_bf(lmt->ofdm, band, RTW89_CHANNEL_WIDTH_20, 2105 ntx, RTW89_RS_OFDM, pri_ch); 2106 2107 /* fill mcs 20m section */ 2108 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[0], band, 2109 RTW89_CHANNEL_WIDTH_20, 2110 ntx, RTW89_RS_MCS, ch - 14); 2111 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[1], band, 2112 RTW89_CHANNEL_WIDTH_20, 2113 ntx, RTW89_RS_MCS, ch - 10); 2114 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[2], band, 2115 RTW89_CHANNEL_WIDTH_20, 2116 ntx, RTW89_RS_MCS, ch - 6); 2117 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[3], band, 2118 RTW89_CHANNEL_WIDTH_20, 2119 ntx, RTW89_RS_MCS, ch - 2); 2120 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[4], band, 2121 RTW89_CHANNEL_WIDTH_20, 2122 ntx, RTW89_RS_MCS, ch + 2); 2123 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[5], band, 2124 RTW89_CHANNEL_WIDTH_20, 2125 ntx, RTW89_RS_MCS, ch + 6); 2126 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[6], band, 2127 RTW89_CHANNEL_WIDTH_20, 2128 ntx, RTW89_RS_MCS, ch + 10); 2129 __fill_txpwr_limit_nonbf_bf(lmt->mcs_20m[7], band, 2130 RTW89_CHANNEL_WIDTH_20, 2131 ntx, RTW89_RS_MCS, ch + 14); 2132 2133 /* fill mcs 40m section */ 2134 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[0], band, 2135 RTW89_CHANNEL_WIDTH_40, 2136 ntx, RTW89_RS_MCS, ch - 12); 2137 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[1], band, 2138 RTW89_CHANNEL_WIDTH_40, 2139 ntx, RTW89_RS_MCS, ch - 4); 2140 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[2], band, 2141 RTW89_CHANNEL_WIDTH_40, 2142 ntx, RTW89_RS_MCS, ch + 4); 2143 __fill_txpwr_limit_nonbf_bf(lmt->mcs_40m[3], band, 2144 RTW89_CHANNEL_WIDTH_40, 2145 ntx, RTW89_RS_MCS, ch + 12); 2146 2147 /* fill mcs 80m section */ 2148 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[0], band, 2149 RTW89_CHANNEL_WIDTH_80, 2150 ntx, RTW89_RS_MCS, ch - 8); 2151 __fill_txpwr_limit_nonbf_bf(lmt->mcs_80m[1], band, 2152 RTW89_CHANNEL_WIDTH_80, 2153 ntx, RTW89_RS_MCS, ch + 8); 2154 2155 /* fill mcs 160m section */ 2156 __fill_txpwr_limit_nonbf_bf(lmt->mcs_160m, band, 2157 RTW89_CHANNEL_WIDTH_160, 2158 ntx, RTW89_RS_MCS, ch); 2159 2160 /* fill mcs 40m 0p5 section */ 2161 __fill_txpwr_limit_nonbf_bf(val_0p5_n, band, RTW89_CHANNEL_WIDTH_40, 2162 ntx, RTW89_RS_MCS, ch - 4); 2163 __fill_txpwr_limit_nonbf_bf(val_0p5_p, band, RTW89_CHANNEL_WIDTH_40, 2164 ntx, RTW89_RS_MCS, ch + 4); 2165 2166 for (i = 0; i < RTW89_BF_NUM; i++) 2167 lmt->mcs_40m_0p5[i] = min_t(s8, val_0p5_n[i], val_0p5_p[i]); 2168 2169 /* fill mcs 40m 2p5 section */ 2170 __fill_txpwr_limit_nonbf_bf(val_2p5_n, band, RTW89_CHANNEL_WIDTH_40, 2171 ntx, RTW89_RS_MCS, ch - 8); 2172 __fill_txpwr_limit_nonbf_bf(val_2p5_p, band, RTW89_CHANNEL_WIDTH_40, 2173 ntx, RTW89_RS_MCS, ch + 8); 2174 2175 for (i = 0; i < RTW89_BF_NUM; i++) 2176 lmt->mcs_40m_2p5[i] = min_t(s8, val_2p5_n[i], val_2p5_p[i]); 2177 } 2178 2179 static 2180 void rtw89_phy_fill_txpwr_limit_ax(struct rtw89_dev *rtwdev, 2181 const struct rtw89_chan *chan, 2182 struct rtw89_txpwr_limit_ax *lmt, 2183 u8 ntx) 2184 { 2185 u8 band = chan->band_type; 2186 u8 pri_ch = chan->primary_channel; 2187 u8 ch = chan->channel; 2188 u8 bw = chan->band_width; 2189 2190 memset(lmt, 0, sizeof(*lmt)); 2191 2192 switch (bw) { 2193 case RTW89_CHANNEL_WIDTH_20: 2194 rtw89_phy_fill_txpwr_limit_20m_ax(rtwdev, lmt, band, ntx, ch); 2195 break; 2196 case RTW89_CHANNEL_WIDTH_40: 2197 rtw89_phy_fill_txpwr_limit_40m_ax(rtwdev, lmt, band, ntx, ch, 2198 pri_ch); 2199 break; 2200 case RTW89_CHANNEL_WIDTH_80: 2201 rtw89_phy_fill_txpwr_limit_80m_ax(rtwdev, lmt, band, ntx, ch, 2202 pri_ch); 2203 break; 2204 case RTW89_CHANNEL_WIDTH_160: 2205 rtw89_phy_fill_txpwr_limit_160m_ax(rtwdev, lmt, band, ntx, ch, 2206 pri_ch); 2207 break; 2208 } 2209 } 2210 2211 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, 2212 u8 ru, u8 ntx, u8 ch) 2213 { 2214 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 2215 const struct rtw89_txpwr_rule_2ghz *rule_2ghz = &rfe_parms->rule_2ghz; 2216 const struct rtw89_txpwr_rule_5ghz *rule_5ghz = &rfe_parms->rule_5ghz; 2217 const struct rtw89_txpwr_rule_6ghz *rule_6ghz = &rfe_parms->rule_6ghz; 2218 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 2219 enum nl80211_band nl_band = rtw89_hw_to_nl80211_band(band); 2220 u32 freq = ieee80211_channel_to_frequency(ch, nl_band); 2221 u8 ch_idx = rtw89_channel_to_idx(rtwdev, band, ch); 2222 u8 regd = rtw89_regd_get(rtwdev, band); 2223 u8 reg6 = regulatory->reg_6ghz_power; 2224 s8 lmt_ru = 0, sar; 2225 s8 cstr; 2226 2227 switch (band) { 2228 case RTW89_BAND_2G: 2229 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 2230 if (lmt_ru) 2231 break; 2232 2233 lmt_ru = (*rule_2ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx]; 2234 break; 2235 case RTW89_BAND_5G: 2236 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][regd][ch_idx]; 2237 if (lmt_ru) 2238 break; 2239 2240 lmt_ru = (*rule_5ghz->lmt_ru)[ru][ntx][RTW89_WW][ch_idx]; 2241 break; 2242 case RTW89_BAND_6G: 2243 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][regd][reg6][ch_idx]; 2244 if (lmt_ru) 2245 break; 2246 2247 lmt_ru = (*rule_6ghz->lmt_ru)[ru][ntx][RTW89_WW] 2248 [RTW89_REG_6GHZ_POWER_DFLT] 2249 [ch_idx]; 2250 break; 2251 default: 2252 rtw89_warn(rtwdev, "unknown band type: %d\n", band); 2253 return 0; 2254 } 2255 2256 lmt_ru = rtw89_phy_txpwr_rf_to_mac(rtwdev, lmt_ru); 2257 sar = rtw89_query_sar(rtwdev, freq); 2258 cstr = rtw89_phy_get_tpe_constraint(rtwdev, band); 2259 2260 return min3(lmt_ru, sar, cstr); 2261 } 2262 2263 static void 2264 rtw89_phy_fill_txpwr_limit_ru_20m_ax(struct rtw89_dev *rtwdev, 2265 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2266 u8 band, u8 ntx, u8 ch) 2267 { 2268 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2269 RTW89_RU26, 2270 ntx, ch); 2271 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2272 RTW89_RU52, 2273 ntx, ch); 2274 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2275 RTW89_RU106, 2276 ntx, ch); 2277 } 2278 2279 static void 2280 rtw89_phy_fill_txpwr_limit_ru_40m_ax(struct rtw89_dev *rtwdev, 2281 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2282 u8 band, u8 ntx, u8 ch) 2283 { 2284 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2285 RTW89_RU26, 2286 ntx, ch - 2); 2287 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2288 RTW89_RU26, 2289 ntx, ch + 2); 2290 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2291 RTW89_RU52, 2292 ntx, ch - 2); 2293 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2294 RTW89_RU52, 2295 ntx, ch + 2); 2296 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2297 RTW89_RU106, 2298 ntx, ch - 2); 2299 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2300 RTW89_RU106, 2301 ntx, ch + 2); 2302 } 2303 2304 static void 2305 rtw89_phy_fill_txpwr_limit_ru_80m_ax(struct rtw89_dev *rtwdev, 2306 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2307 u8 band, u8 ntx, u8 ch) 2308 { 2309 lmt_ru->ru26[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2310 RTW89_RU26, 2311 ntx, ch - 6); 2312 lmt_ru->ru26[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2313 RTW89_RU26, 2314 ntx, ch - 2); 2315 lmt_ru->ru26[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2316 RTW89_RU26, 2317 ntx, ch + 2); 2318 lmt_ru->ru26[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2319 RTW89_RU26, 2320 ntx, ch + 6); 2321 lmt_ru->ru52[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2322 RTW89_RU52, 2323 ntx, ch - 6); 2324 lmt_ru->ru52[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2325 RTW89_RU52, 2326 ntx, ch - 2); 2327 lmt_ru->ru52[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2328 RTW89_RU52, 2329 ntx, ch + 2); 2330 lmt_ru->ru52[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2331 RTW89_RU52, 2332 ntx, ch + 6); 2333 lmt_ru->ru106[0] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2334 RTW89_RU106, 2335 ntx, ch - 6); 2336 lmt_ru->ru106[1] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2337 RTW89_RU106, 2338 ntx, ch - 2); 2339 lmt_ru->ru106[2] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2340 RTW89_RU106, 2341 ntx, ch + 2); 2342 lmt_ru->ru106[3] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2343 RTW89_RU106, 2344 ntx, ch + 6); 2345 } 2346 2347 static void 2348 rtw89_phy_fill_txpwr_limit_ru_160m_ax(struct rtw89_dev *rtwdev, 2349 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2350 u8 band, u8 ntx, u8 ch) 2351 { 2352 static const int ofst[] = { -14, -10, -6, -2, 2, 6, 10, 14 }; 2353 int i; 2354 2355 #if defined(__linux__) 2356 static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM_AX); 2357 #elif defined(__FreeBSD__) 2358 rtw89_static_assert(ARRAY_SIZE(ofst) == RTW89_RU_SEC_NUM_AX); 2359 #endif 2360 for (i = 0; i < RTW89_RU_SEC_NUM_AX; i++) { 2361 lmt_ru->ru26[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2362 RTW89_RU26, 2363 ntx, 2364 ch + ofst[i]); 2365 lmt_ru->ru52[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2366 RTW89_RU52, 2367 ntx, 2368 ch + ofst[i]); 2369 lmt_ru->ru106[i] = rtw89_phy_read_txpwr_limit_ru(rtwdev, band, 2370 RTW89_RU106, 2371 ntx, 2372 ch + ofst[i]); 2373 } 2374 } 2375 2376 static 2377 void rtw89_phy_fill_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev, 2378 const struct rtw89_chan *chan, 2379 struct rtw89_txpwr_limit_ru_ax *lmt_ru, 2380 u8 ntx) 2381 { 2382 u8 band = chan->band_type; 2383 u8 ch = chan->channel; 2384 u8 bw = chan->band_width; 2385 2386 memset(lmt_ru, 0, sizeof(*lmt_ru)); 2387 2388 switch (bw) { 2389 case RTW89_CHANNEL_WIDTH_20: 2390 rtw89_phy_fill_txpwr_limit_ru_20m_ax(rtwdev, lmt_ru, band, ntx, 2391 ch); 2392 break; 2393 case RTW89_CHANNEL_WIDTH_40: 2394 rtw89_phy_fill_txpwr_limit_ru_40m_ax(rtwdev, lmt_ru, band, ntx, 2395 ch); 2396 break; 2397 case RTW89_CHANNEL_WIDTH_80: 2398 rtw89_phy_fill_txpwr_limit_ru_80m_ax(rtwdev, lmt_ru, band, ntx, 2399 ch); 2400 break; 2401 case RTW89_CHANNEL_WIDTH_160: 2402 rtw89_phy_fill_txpwr_limit_ru_160m_ax(rtwdev, lmt_ru, band, ntx, 2403 ch); 2404 break; 2405 } 2406 } 2407 2408 static void rtw89_phy_set_txpwr_byrate_ax(struct rtw89_dev *rtwdev, 2409 const struct rtw89_chan *chan, 2410 enum rtw89_phy_idx phy_idx) 2411 { 2412 u8 max_nss_num = rtwdev->chip->rf_path_num; 2413 static const u8 rs[] = { 2414 RTW89_RS_CCK, 2415 RTW89_RS_OFDM, 2416 RTW89_RS_MCS, 2417 RTW89_RS_HEDCM, 2418 }; 2419 struct rtw89_rate_desc cur = {}; 2420 u8 band = chan->band_type; 2421 u8 ch = chan->channel; 2422 u32 addr, val; 2423 s8 v[4] = {}; 2424 u8 i; 2425 2426 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2427 "[TXPWR] set txpwr byrate with ch=%d\n", ch); 2428 2429 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_CCK] % 4); 2430 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_OFDM] % 4); 2431 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_MCS] % 4); 2432 BUILD_BUG_ON(rtw89_rs_idx_num_ax[RTW89_RS_HEDCM] % 4); 2433 2434 addr = R_AX_PWR_BY_RATE; 2435 for (cur.nss = 0; cur.nss < max_nss_num; cur.nss++) { 2436 for (i = 0; i < ARRAY_SIZE(rs); i++) { 2437 if (cur.nss >= rtw89_rs_nss_num_ax[rs[i]]) 2438 continue; 2439 2440 cur.rs = rs[i]; 2441 for (cur.idx = 0; cur.idx < rtw89_rs_idx_num_ax[rs[i]]; 2442 cur.idx++) { 2443 v[cur.idx % 4] = 2444 rtw89_phy_read_txpwr_byrate(rtwdev, 2445 band, 0, 2446 &cur); 2447 2448 if ((cur.idx + 1) % 4) 2449 continue; 2450 2451 val = FIELD_PREP(GENMASK(7, 0), v[0]) | 2452 FIELD_PREP(GENMASK(15, 8), v[1]) | 2453 FIELD_PREP(GENMASK(23, 16), v[2]) | 2454 FIELD_PREP(GENMASK(31, 24), v[3]); 2455 2456 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, 2457 val); 2458 addr += 4; 2459 } 2460 } 2461 } 2462 } 2463 2464 static 2465 void rtw89_phy_set_txpwr_offset_ax(struct rtw89_dev *rtwdev, 2466 const struct rtw89_chan *chan, 2467 enum rtw89_phy_idx phy_idx) 2468 { 2469 struct rtw89_rate_desc desc = { 2470 .nss = RTW89_NSS_1, 2471 .rs = RTW89_RS_OFFSET, 2472 }; 2473 u8 band = chan->band_type; 2474 s8 v[RTW89_RATE_OFFSET_NUM_AX] = {}; 2475 u32 val; 2476 2477 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, "[TXPWR] set txpwr offset\n"); 2478 2479 for (desc.idx = 0; desc.idx < RTW89_RATE_OFFSET_NUM_AX; desc.idx++) 2480 v[desc.idx] = rtw89_phy_read_txpwr_byrate(rtwdev, band, 0, &desc); 2481 2482 BUILD_BUG_ON(RTW89_RATE_OFFSET_NUM_AX != 5); 2483 val = FIELD_PREP(GENMASK(3, 0), v[0]) | 2484 FIELD_PREP(GENMASK(7, 4), v[1]) | 2485 FIELD_PREP(GENMASK(11, 8), v[2]) | 2486 FIELD_PREP(GENMASK(15, 12), v[3]) | 2487 FIELD_PREP(GENMASK(19, 16), v[4]); 2488 2489 rtw89_mac_txpwr_write32_mask(rtwdev, phy_idx, R_AX_PWR_RATE_OFST_CTRL, 2490 GENMASK(19, 0), val); 2491 } 2492 2493 static void rtw89_phy_set_txpwr_limit_ax(struct rtw89_dev *rtwdev, 2494 const struct rtw89_chan *chan, 2495 enum rtw89_phy_idx phy_idx) 2496 { 2497 u8 max_ntx_num = rtwdev->chip->rf_path_num; 2498 struct rtw89_txpwr_limit_ax lmt; 2499 u8 ch = chan->channel; 2500 u8 bw = chan->band_width; 2501 const s8 *ptr; 2502 u32 addr, val; 2503 u8 i, j; 2504 2505 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2506 "[TXPWR] set txpwr limit with ch=%d bw=%d\n", ch, bw); 2507 2508 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ax) != 2509 RTW89_TXPWR_LMT_PAGE_SIZE_AX); 2510 2511 addr = R_AX_PWR_LMT; 2512 for (i = 0; i < max_ntx_num; i++) { 2513 rtw89_phy_fill_txpwr_limit_ax(rtwdev, chan, &lmt, i); 2514 2515 ptr = (s8 *)&lmt; 2516 for (j = 0; j < RTW89_TXPWR_LMT_PAGE_SIZE_AX; 2517 j += 4, addr += 4, ptr += 4) { 2518 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2519 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2520 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2521 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2522 2523 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2524 } 2525 } 2526 } 2527 2528 static void rtw89_phy_set_txpwr_limit_ru_ax(struct rtw89_dev *rtwdev, 2529 const struct rtw89_chan *chan, 2530 enum rtw89_phy_idx phy_idx) 2531 { 2532 u8 max_ntx_num = rtwdev->chip->rf_path_num; 2533 struct rtw89_txpwr_limit_ru_ax lmt_ru; 2534 u8 ch = chan->channel; 2535 u8 bw = chan->band_width; 2536 const s8 *ptr; 2537 u32 addr, val; 2538 u8 i, j; 2539 2540 rtw89_debug(rtwdev, RTW89_DBG_TXPWR, 2541 "[TXPWR] set txpwr limit ru with ch=%d bw=%d\n", ch, bw); 2542 2543 BUILD_BUG_ON(sizeof(struct rtw89_txpwr_limit_ru_ax) != 2544 RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX); 2545 2546 addr = R_AX_PWR_RU_LMT; 2547 for (i = 0; i < max_ntx_num; i++) { 2548 rtw89_phy_fill_txpwr_limit_ru_ax(rtwdev, chan, &lmt_ru, i); 2549 2550 ptr = (s8 *)&lmt_ru; 2551 for (j = 0; j < RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX; 2552 j += 4, addr += 4, ptr += 4) { 2553 val = FIELD_PREP(GENMASK(7, 0), ptr[0]) | 2554 FIELD_PREP(GENMASK(15, 8), ptr[1]) | 2555 FIELD_PREP(GENMASK(23, 16), ptr[2]) | 2556 FIELD_PREP(GENMASK(31, 24), ptr[3]); 2557 2558 rtw89_mac_txpwr_write32(rtwdev, phy_idx, addr, val); 2559 } 2560 } 2561 } 2562 2563 struct rtw89_phy_iter_ra_data { 2564 struct rtw89_dev *rtwdev; 2565 struct sk_buff *c2h; 2566 }; 2567 2568 static void rtw89_phy_c2h_ra_rpt_iter(void *data, struct ieee80211_sta *sta) 2569 { 2570 struct rtw89_phy_iter_ra_data *ra_data = (struct rtw89_phy_iter_ra_data *)data; 2571 struct rtw89_dev *rtwdev = ra_data->rtwdev; 2572 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2573 const struct rtw89_c2h_ra_rpt *c2h = 2574 (const struct rtw89_c2h_ra_rpt *)ra_data->c2h->data; 2575 struct rtw89_ra_report *ra_report = &rtwsta->ra_report; 2576 const struct rtw89_chip_info *chip = rtwdev->chip; 2577 bool format_v1 = chip->chip_gen == RTW89_CHIP_BE; 2578 u8 mode, rate, bw, giltf, mac_id; 2579 u16 legacy_bitrate; 2580 bool valid; 2581 u8 mcs = 0; 2582 u8 t; 2583 2584 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MACID); 2585 if (mac_id != rtwsta->mac_id) 2586 return; 2587 2588 rate = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MCSNSS); 2589 bw = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW); 2590 giltf = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_GILTF); 2591 mode = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL); 2592 2593 if (format_v1) { 2594 t = le32_get_bits(c2h->w2, RTW89_C2H_RA_RPT_W2_MCSNSS_B7); 2595 rate |= u8_encode_bits(t, BIT(7)); 2596 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_BW_B2); 2597 bw |= u8_encode_bits(t, BIT(2)); 2598 t = le32_get_bits(c2h->w3, RTW89_C2H_RA_RPT_W3_MD_SEL_B2); 2599 mode |= u8_encode_bits(t, BIT(2)); 2600 } 2601 2602 if (mode == RTW89_RA_RPT_MODE_LEGACY) { 2603 valid = rtw89_ra_report_to_bitrate(rtwdev, rate, &legacy_bitrate); 2604 if (!valid) 2605 return; 2606 } 2607 2608 memset(&ra_report->txrate, 0, sizeof(ra_report->txrate)); 2609 2610 switch (mode) { 2611 case RTW89_RA_RPT_MODE_LEGACY: 2612 ra_report->txrate.legacy = legacy_bitrate; 2613 break; 2614 case RTW89_RA_RPT_MODE_HT: 2615 ra_report->txrate.flags |= RATE_INFO_FLAGS_MCS; 2616 if (RTW89_CHK_FW_FEATURE(OLD_HT_RA_FORMAT, &rtwdev->fw)) 2617 rate = RTW89_MK_HT_RATE(FIELD_GET(RTW89_RA_RATE_MASK_NSS, rate), 2618 FIELD_GET(RTW89_RA_RATE_MASK_MCS, rate)); 2619 else 2620 rate = FIELD_GET(RTW89_RA_RATE_MASK_HT_MCS, rate); 2621 ra_report->txrate.mcs = rate; 2622 if (giltf) 2623 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2624 mcs = ra_report->txrate.mcs & 0x07; 2625 break; 2626 case RTW89_RA_RPT_MODE_VHT: 2627 ra_report->txrate.flags |= RATE_INFO_FLAGS_VHT_MCS; 2628 ra_report->txrate.mcs = format_v1 ? 2629 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) : 2630 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS); 2631 ra_report->txrate.nss = format_v1 ? 2632 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 : 2633 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1; 2634 if (giltf) 2635 ra_report->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 2636 mcs = ra_report->txrate.mcs; 2637 break; 2638 case RTW89_RA_RPT_MODE_HE: 2639 ra_report->txrate.flags |= RATE_INFO_FLAGS_HE_MCS; 2640 ra_report->txrate.mcs = format_v1 ? 2641 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1) : 2642 u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS); 2643 ra_report->txrate.nss = format_v1 ? 2644 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1 : 2645 u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS) + 1; 2646 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 2647 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_0_8; 2648 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 2649 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_1_6; 2650 else 2651 ra_report->txrate.he_gi = NL80211_RATE_INFO_HE_GI_3_2; 2652 mcs = ra_report->txrate.mcs; 2653 break; 2654 case RTW89_RA_RPT_MODE_EHT: 2655 ra_report->txrate.flags |= RATE_INFO_FLAGS_EHT_MCS; 2656 ra_report->txrate.mcs = u8_get_bits(rate, RTW89_RA_RATE_MASK_MCS_V1); 2657 ra_report->txrate.nss = u8_get_bits(rate, RTW89_RA_RATE_MASK_NSS_V1) + 1; 2658 if (giltf == RTW89_GILTF_2XHE08 || giltf == RTW89_GILTF_1XHE08) 2659 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_0_8; 2660 else if (giltf == RTW89_GILTF_2XHE16 || giltf == RTW89_GILTF_1XHE16) 2661 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_1_6; 2662 else 2663 ra_report->txrate.eht_gi = NL80211_RATE_INFO_EHT_GI_3_2; 2664 mcs = ra_report->txrate.mcs; 2665 break; 2666 } 2667 2668 ra_report->txrate.bw = rtw89_hw_to_rate_info_bw(bw); 2669 ra_report->bit_rate = cfg80211_calculate_bitrate(&ra_report->txrate); 2670 ra_report->hw_rate = format_v1 ? 2671 u16_encode_bits(mode, RTW89_HW_RATE_V1_MASK_MOD) | 2672 u16_encode_bits(rate, RTW89_HW_RATE_V1_MASK_VAL) : 2673 u16_encode_bits(mode, RTW89_HW_RATE_MASK_MOD) | 2674 u16_encode_bits(rate, RTW89_HW_RATE_MASK_VAL); 2675 ra_report->might_fallback_legacy = mcs <= 2; 2676 sta->deflink.agg.max_rc_amsdu_len = get_max_amsdu_len(rtwdev, ra_report); 2677 rtwsta->max_agg_wait = sta->deflink.agg.max_rc_amsdu_len / 1500 - 1; 2678 } 2679 2680 static void 2681 rtw89_phy_c2h_ra_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2682 { 2683 struct rtw89_phy_iter_ra_data ra_data; 2684 2685 ra_data.rtwdev = rtwdev; 2686 ra_data.c2h = c2h; 2687 ieee80211_iterate_stations_atomic(rtwdev->hw, 2688 rtw89_phy_c2h_ra_rpt_iter, 2689 &ra_data); 2690 } 2691 2692 static 2693 void (* const rtw89_phy_c2h_ra_handler[])(struct rtw89_dev *rtwdev, 2694 struct sk_buff *c2h, u32 len) = { 2695 [RTW89_PHY_C2H_FUNC_STS_RPT] = rtw89_phy_c2h_ra_rpt, 2696 [RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT] = NULL, 2697 [RTW89_PHY_C2H_FUNC_TXSTS] = NULL, 2698 }; 2699 2700 static void rtw89_phy_c2h_rfk_rpt_log(struct rtw89_dev *rtwdev, 2701 enum rtw89_phy_c2h_rfk_log_func func, 2702 void *content, u16 len) 2703 { 2704 struct rtw89_c2h_rf_txgapk_rpt_log *txgapk; 2705 struct rtw89_c2h_rf_rxdck_rpt_log *rxdck; 2706 struct rtw89_c2h_rf_dack_rpt_log *dack; 2707 struct rtw89_c2h_rf_dpk_rpt_log *dpk; 2708 2709 switch (func) { 2710 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK: 2711 if (len != sizeof(*dpk)) 2712 goto out; 2713 2714 dpk = content; 2715 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2716 "DPK ver:%d idx:%2ph band:%2ph bw:%2ph ch:%2ph path:%2ph\n", 2717 dpk->ver, dpk->idx, dpk->band, dpk->bw, dpk->ch, dpk->path_ok); 2718 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2719 "DPK txagc:%2ph ther:%2ph gs:%2ph dc_i:%4ph dc_q:%4ph\n", 2720 dpk->txagc, dpk->ther, dpk->gs, dpk->dc_i, dpk->dc_q); 2721 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2722 "DPK corr_v:%2ph corr_i:%2ph to:%2ph ov:%2ph\n", 2723 dpk->corr_val, dpk->corr_idx, dpk->is_timeout, dpk->rxbb_ov); 2724 return; 2725 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK: 2726 if (len != sizeof(*dack)) 2727 goto out; 2728 2729 dack = content; 2730 2731 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]ver=0x%x 0x%x\n", 2732 dack->fwdack_ver, dack->fwdack_rpt_ver); 2733 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK ic = [0x%x, 0x%x]\n", 2734 dack->cdack_d[0][0][0], dack->cdack_d[0][0][1]); 2735 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 CDACK qc = [0x%x, 0x%x]\n", 2736 dack->cdack_d[0][1][0], dack->cdack_d[0][1][1]); 2737 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK ic = [0x%x, 0x%x]\n", 2738 dack->cdack_d[1][0][0], dack->cdack_d[1][0][1]); 2739 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 CDACK qc = [0x%x, 0x%x]\n", 2740 dack->cdack_d[1][1][0], dack->cdack_d[1][1][1]); 2741 2742 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK ic = [0x%x, 0x%x]\n", 2743 dack->addck2_d[0][0][0], dack->addck2_d[0][0][1]); 2744 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_DCK qc = [0x%x, 0x%x]\n", 2745 dack->addck2_d[0][1][0], dack->addck2_d[0][1][1]); 2746 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK ic = [0x%x, 0x%x]\n", 2747 dack->addck2_d[1][0][0], dack->addck2_d[1][0][1]); 2748 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_DCK qc = [0x%x, 0x%x]\n", 2749 dack->addck2_d[1][1][0], dack->addck2_d[1][1][1]); 2750 2751 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 ADC_GAINK ic = 0x%x, qc = 0x%x\n", 2752 dack->adgaink_d[0][0], dack->adgaink_d[0][1]); 2753 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 ADC_GAINK ic = 0x%x, qc = 0x%x\n", 2754 dack->adgaink_d[1][0], dack->adgaink_d[1][1]); 2755 2756 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 DAC_DCK ic = 0x%x, qc = 0x%x\n", 2757 dack->dadck_d[0][0], dack->dadck_d[0][1]); 2758 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 DAC_DCK ic = 0x%x, qc = 0x%x\n", 2759 dack->dadck_d[1][0], dack->dadck_d[1][1]); 2760 2761 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 biask iqc = 0x%x\n", 2762 dack->biask_d[0][0]); 2763 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 biask iqc = 0x%x\n", 2764 dack->biask_d[1][0]); 2765 2766 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK ic: %*ph\n", 2767 (int)sizeof(dack->msbk_d[0][0]), dack->msbk_d[0][0]); 2768 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S0 MSBK qc: %*ph\n", 2769 (int)sizeof(dack->msbk_d[0][1]), dack->msbk_d[0][1]); 2770 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK ic: %*ph\n", 2771 (int)sizeof(dack->msbk_d[1][0]), dack->msbk_d[1][0]); 2772 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]S1 MSBK qc: %*ph\n", 2773 (int)sizeof(dack->msbk_d[1][1]), dack->msbk_d[1][1]); 2774 return; 2775 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK: 2776 if (len != sizeof(*rxdck)) 2777 goto out; 2778 2779 rxdck = content; 2780 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2781 "RXDCK ver:%d band:%2ph bw:%2ph ch:%2ph to:%2ph\n", 2782 rxdck->ver, rxdck->band, rxdck->bw, rxdck->ch, 2783 rxdck->timeout); 2784 return; 2785 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK: 2786 if (len != sizeof(*txgapk)) 2787 goto out; 2788 2789 txgapk = content; 2790 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2791 "[TXGAPK]rpt r0x8010[0]=0x%x, r0x8010[1]=0x%x\n", 2792 le32_to_cpu(txgapk->r0x8010[0]), 2793 le32_to_cpu(txgapk->r0x8010[1])); 2794 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_id = %d\n", 2795 txgapk->chk_id); 2796 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt chk_cnt = %d\n", 2797 le32_to_cpu(txgapk->chk_cnt)); 2798 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt ver = 0x%x\n", 2799 txgapk->ver); 2800 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt rsv1 = %d\n", 2801 txgapk->rsv1); 2802 2803 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[0] = %*ph\n", 2804 (int)sizeof(txgapk->track_d[0]), txgapk->track_d[0]); 2805 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[0] = %*ph\n", 2806 (int)sizeof(txgapk->power_d[0]), txgapk->power_d[0]); 2807 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt track_d[1] = %*ph\n", 2808 (int)sizeof(txgapk->track_d[1]), txgapk->track_d[1]); 2809 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[TXGAPK]rpt power_d[1] = %*ph\n", 2810 (int)sizeof(txgapk->power_d[1]), txgapk->power_d[1]); 2811 return; 2812 default: 2813 break; 2814 } 2815 2816 out: 2817 rtw89_debug(rtwdev, RTW89_DBG_RFK, 2818 "unexpected RFK func %d report log with length %d\n", func, len); 2819 } 2820 2821 static bool rtw89_phy_c2h_rfk_run_log(struct rtw89_dev *rtwdev, 2822 enum rtw89_phy_c2h_rfk_log_func func, 2823 void *content, u16 len) 2824 { 2825 struct rtw89_fw_elm_info *elm_info = &rtwdev->fw.elm_info; 2826 const struct rtw89_c2h_rf_run_log *log = content; 2827 const struct rtw89_fw_element_hdr *elm; 2828 u32 fmt_idx; 2829 u16 offset; 2830 2831 if (sizeof(*log) != len) 2832 return false; 2833 2834 if (!elm_info->rfk_log_fmt) 2835 return false; 2836 2837 elm = elm_info->rfk_log_fmt->elm[func]; 2838 fmt_idx = le32_to_cpu(log->fmt_idx); 2839 if (!elm || fmt_idx >= elm->u.rfk_log_fmt.nr) 2840 return false; 2841 2842 offset = le16_to_cpu(elm->u.rfk_log_fmt.offset[fmt_idx]); 2843 if (offset == 0) 2844 return false; 2845 2846 rtw89_debug(rtwdev, RTW89_DBG_RFK, &elm->u.common.contents[offset], 2847 le32_to_cpu(log->arg[0]), le32_to_cpu(log->arg[1]), 2848 le32_to_cpu(log->arg[2]), le32_to_cpu(log->arg[3])); 2849 2850 return true; 2851 } 2852 2853 static void rtw89_phy_c2h_rfk_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 2854 u32 len, enum rtw89_phy_c2h_rfk_log_func func, 2855 const char *rfk_name) 2856 { 2857 struct rtw89_c2h_hdr *c2h_hdr = (struct rtw89_c2h_hdr *)c2h->data; 2858 struct rtw89_c2h_rf_log_hdr *log_hdr; 2859 #if defined(__linux__) 2860 void *log_ptr = c2h_hdr; 2861 #elif defined(__FreeBSD__) 2862 u8 *log_ptr = (void *)c2h_hdr; 2863 #endif 2864 u16 content_len; 2865 u16 chunk_len; 2866 bool handled; 2867 2868 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_RFK)) 2869 return; 2870 2871 log_ptr += sizeof(*c2h_hdr); 2872 len -= sizeof(*c2h_hdr); 2873 2874 while (len > sizeof(*log_hdr)) { 2875 #if defined(__linux__) 2876 log_hdr = log_ptr; 2877 #elif defined(__FreeBSD__) 2878 log_hdr = (void *)log_ptr; 2879 #endif 2880 content_len = le16_to_cpu(log_hdr->len); 2881 chunk_len = content_len + sizeof(*log_hdr); 2882 2883 if (chunk_len > len) 2884 break; 2885 2886 switch (log_hdr->type) { 2887 case RTW89_RF_RUN_LOG: 2888 handled = rtw89_phy_c2h_rfk_run_log(rtwdev, func, 2889 log_hdr->content, content_len); 2890 if (handled) 2891 break; 2892 2893 rtw89_debug(rtwdev, RTW89_DBG_RFK, "%s run: %*ph\n", 2894 rfk_name, content_len, log_hdr->content); 2895 break; 2896 case RTW89_RF_RPT_LOG: 2897 rtw89_phy_c2h_rfk_rpt_log(rtwdev, func, 2898 log_hdr->content, content_len); 2899 break; 2900 default: 2901 return; 2902 } 2903 2904 log_ptr += chunk_len; 2905 len -= chunk_len; 2906 } 2907 } 2908 2909 static void 2910 rtw89_phy_c2h_rfk_log_iqk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2911 { 2912 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2913 RTW89_PHY_C2H_RFK_LOG_FUNC_IQK, "IQK"); 2914 } 2915 2916 static void 2917 rtw89_phy_c2h_rfk_log_dpk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2918 { 2919 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2920 RTW89_PHY_C2H_RFK_LOG_FUNC_DPK, "DPK"); 2921 } 2922 2923 static void 2924 rtw89_phy_c2h_rfk_log_dack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2925 { 2926 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2927 RTW89_PHY_C2H_RFK_LOG_FUNC_DACK, "DACK"); 2928 } 2929 2930 static void 2931 rtw89_phy_c2h_rfk_log_rxdck(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2932 { 2933 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2934 RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK, "RX_DCK"); 2935 } 2936 2937 static void 2938 rtw89_phy_c2h_rfk_log_tssi(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2939 { 2940 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2941 RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI, "TSSI"); 2942 } 2943 2944 static void 2945 rtw89_phy_c2h_rfk_log_txgapk(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 2946 { 2947 rtw89_phy_c2h_rfk_log(rtwdev, c2h, len, 2948 RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK, "TXGAPK"); 2949 } 2950 2951 static 2952 void (* const rtw89_phy_c2h_rfk_log_handler[])(struct rtw89_dev *rtwdev, 2953 struct sk_buff *c2h, u32 len) = { 2954 [RTW89_PHY_C2H_RFK_LOG_FUNC_IQK] = rtw89_phy_c2h_rfk_log_iqk, 2955 [RTW89_PHY_C2H_RFK_LOG_FUNC_DPK] = rtw89_phy_c2h_rfk_log_dpk, 2956 [RTW89_PHY_C2H_RFK_LOG_FUNC_DACK] = rtw89_phy_c2h_rfk_log_dack, 2957 [RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK] = rtw89_phy_c2h_rfk_log_rxdck, 2958 [RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI] = rtw89_phy_c2h_rfk_log_tssi, 2959 [RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK] = rtw89_phy_c2h_rfk_log_txgapk, 2960 }; 2961 2962 static 2963 void rtw89_phy_rfk_report_prep(struct rtw89_dev *rtwdev) 2964 { 2965 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait; 2966 2967 wait->state = RTW89_RFK_STATE_START; 2968 wait->start_time = ktime_get(); 2969 reinit_completion(&wait->completion); 2970 } 2971 2972 static 2973 int rtw89_phy_rfk_report_wait(struct rtw89_dev *rtwdev, const char *rfk_name, 2974 unsigned int ms) 2975 { 2976 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait; 2977 unsigned long time_left; 2978 2979 /* Since we can't receive C2H event during SER, use a fixed delay. */ 2980 if (test_bit(RTW89_FLAG_SER_HANDLING, rtwdev->flags)) { 2981 fsleep(1000 * ms / 2); 2982 goto out; 2983 } 2984 2985 time_left = wait_for_completion_timeout(&wait->completion, 2986 msecs_to_jiffies(ms)); 2987 if (time_left == 0) { 2988 rtw89_warn(rtwdev, "failed to wait RF %s\n", rfk_name); 2989 return -ETIMEDOUT; 2990 } else if (wait->state != RTW89_RFK_STATE_OK) { 2991 rtw89_warn(rtwdev, "failed to do RF %s result from state %d\n", 2992 rfk_name, wait->state); 2993 return -EFAULT; 2994 } 2995 2996 out: 2997 #if defined(__linux__) 2998 rtw89_debug(rtwdev, RTW89_DBG_RFK, "RF %s takes %lld ms to complete\n", 2999 rfk_name, ktime_ms_delta(ktime_get(), wait->start_time)); 3000 #elif defined(__FreeBSD__) 3001 rtw89_debug(rtwdev, RTW89_DBG_RFK, "RF %s takes %jd ms to complete\n", 3002 rfk_name, ktime_ms_delta(ktime_get(), (intmax_t)wait->start_time)); 3003 #endif 3004 3005 return 0; 3006 } 3007 3008 static void 3009 rtw89_phy_c2h_rfk_report_state(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 3010 { 3011 const struct rtw89_c2h_rfk_report *report = 3012 (const struct rtw89_c2h_rfk_report *)c2h->data; 3013 struct rtw89_rfk_wait_info *wait = &rtwdev->rfk_wait; 3014 3015 wait->state = report->state; 3016 wait->version = report->version; 3017 3018 complete(&wait->completion); 3019 3020 rtw89_debug(rtwdev, RTW89_DBG_RFK, 3021 "RFK report state %d with version %d (%*ph)\n", 3022 wait->state, wait->version, 3023 (int)(len - sizeof(report->hdr)), &report->state); 3024 } 3025 3026 static 3027 void (* const rtw89_phy_c2h_rfk_report_handler[])(struct rtw89_dev *rtwdev, 3028 struct sk_buff *c2h, u32 len) = { 3029 [RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE] = rtw89_phy_c2h_rfk_report_state, 3030 }; 3031 3032 bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func) 3033 { 3034 switch (class) { 3035 case RTW89_PHY_C2H_RFK_LOG: 3036 switch (func) { 3037 case RTW89_PHY_C2H_RFK_LOG_FUNC_IQK: 3038 case RTW89_PHY_C2H_RFK_LOG_FUNC_DPK: 3039 case RTW89_PHY_C2H_RFK_LOG_FUNC_DACK: 3040 case RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK: 3041 case RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI: 3042 case RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK: 3043 return true; 3044 default: 3045 return false; 3046 } 3047 case RTW89_PHY_C2H_RFK_REPORT: 3048 switch (func) { 3049 case RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE: 3050 return true; 3051 default: 3052 return false; 3053 } 3054 default: 3055 return false; 3056 } 3057 } 3058 3059 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 3060 u32 len, u8 class, u8 func) 3061 { 3062 void (*handler)(struct rtw89_dev *rtwdev, 3063 struct sk_buff *c2h, u32 len) = NULL; 3064 3065 switch (class) { 3066 case RTW89_PHY_C2H_CLASS_RA: 3067 if (func < RTW89_PHY_C2H_FUNC_RA_MAX) 3068 handler = rtw89_phy_c2h_ra_handler[func]; 3069 break; 3070 case RTW89_PHY_C2H_RFK_LOG: 3071 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_log_handler)) 3072 handler = rtw89_phy_c2h_rfk_log_handler[func]; 3073 break; 3074 case RTW89_PHY_C2H_RFK_REPORT: 3075 if (func < ARRAY_SIZE(rtw89_phy_c2h_rfk_report_handler)) 3076 handler = rtw89_phy_c2h_rfk_report_handler[func]; 3077 break; 3078 case RTW89_PHY_C2H_CLASS_DM: 3079 if (func == RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY) 3080 return; 3081 fallthrough; 3082 default: 3083 rtw89_info(rtwdev, "c2h class %d not support\n", class); 3084 return; 3085 } 3086 if (!handler) { 3087 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 3088 func); 3089 return; 3090 } 3091 handler(rtwdev, skb, len); 3092 } 3093 3094 int rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev *rtwdev, 3095 enum rtw89_phy_idx phy_idx, 3096 unsigned int ms) 3097 { 3098 int ret; 3099 3100 rtw89_phy_rfk_report_prep(rtwdev); 3101 3102 ret = rtw89_fw_h2c_rf_pre_ntfy(rtwdev, phy_idx); 3103 if (ret) 3104 return ret; 3105 3106 return rtw89_phy_rfk_report_wait(rtwdev, "PRE_NTFY", ms); 3107 } 3108 EXPORT_SYMBOL(rtw89_phy_rfk_pre_ntfy_and_wait); 3109 3110 int rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev *rtwdev, 3111 enum rtw89_phy_idx phy_idx, 3112 enum rtw89_tssi_mode tssi_mode, 3113 unsigned int ms) 3114 { 3115 int ret; 3116 3117 rtw89_phy_rfk_report_prep(rtwdev); 3118 3119 ret = rtw89_fw_h2c_rf_tssi(rtwdev, phy_idx, tssi_mode); 3120 if (ret) 3121 return ret; 3122 3123 return rtw89_phy_rfk_report_wait(rtwdev, "TSSI", ms); 3124 } 3125 EXPORT_SYMBOL(rtw89_phy_rfk_tssi_and_wait); 3126 3127 int rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev *rtwdev, 3128 enum rtw89_phy_idx phy_idx, 3129 unsigned int ms) 3130 { 3131 int ret; 3132 3133 rtw89_phy_rfk_report_prep(rtwdev); 3134 3135 ret = rtw89_fw_h2c_rf_iqk(rtwdev, phy_idx); 3136 if (ret) 3137 return ret; 3138 3139 return rtw89_phy_rfk_report_wait(rtwdev, "IQK", ms); 3140 } 3141 EXPORT_SYMBOL(rtw89_phy_rfk_iqk_and_wait); 3142 3143 int rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev *rtwdev, 3144 enum rtw89_phy_idx phy_idx, 3145 unsigned int ms) 3146 { 3147 int ret; 3148 3149 rtw89_phy_rfk_report_prep(rtwdev); 3150 3151 ret = rtw89_fw_h2c_rf_dpk(rtwdev, phy_idx); 3152 if (ret) 3153 return ret; 3154 3155 return rtw89_phy_rfk_report_wait(rtwdev, "DPK", ms); 3156 } 3157 EXPORT_SYMBOL(rtw89_phy_rfk_dpk_and_wait); 3158 3159 int rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev *rtwdev, 3160 enum rtw89_phy_idx phy_idx, 3161 unsigned int ms) 3162 { 3163 int ret; 3164 3165 rtw89_phy_rfk_report_prep(rtwdev); 3166 3167 ret = rtw89_fw_h2c_rf_txgapk(rtwdev, phy_idx); 3168 if (ret) 3169 return ret; 3170 3171 return rtw89_phy_rfk_report_wait(rtwdev, "TXGAPK", ms); 3172 } 3173 EXPORT_SYMBOL(rtw89_phy_rfk_txgapk_and_wait); 3174 3175 int rtw89_phy_rfk_dack_and_wait(struct rtw89_dev *rtwdev, 3176 enum rtw89_phy_idx phy_idx, 3177 unsigned int ms) 3178 { 3179 int ret; 3180 3181 rtw89_phy_rfk_report_prep(rtwdev); 3182 3183 ret = rtw89_fw_h2c_rf_dack(rtwdev, phy_idx); 3184 if (ret) 3185 return ret; 3186 3187 return rtw89_phy_rfk_report_wait(rtwdev, "DACK", ms); 3188 } 3189 EXPORT_SYMBOL(rtw89_phy_rfk_dack_and_wait); 3190 3191 int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev, 3192 enum rtw89_phy_idx phy_idx, 3193 unsigned int ms) 3194 { 3195 int ret; 3196 3197 rtw89_phy_rfk_report_prep(rtwdev); 3198 3199 ret = rtw89_fw_h2c_rf_rxdck(rtwdev, phy_idx); 3200 if (ret) 3201 return ret; 3202 3203 return rtw89_phy_rfk_report_wait(rtwdev, "RX_DCK", ms); 3204 } 3205 EXPORT_SYMBOL(rtw89_phy_rfk_rxdck_and_wait); 3206 3207 static u32 phy_tssi_get_cck_group(u8 ch) 3208 { 3209 switch (ch) { 3210 case 1 ... 2: 3211 return 0; 3212 case 3 ... 5: 3213 return 1; 3214 case 6 ... 8: 3215 return 2; 3216 case 9 ... 11: 3217 return 3; 3218 case 12 ... 13: 3219 return 4; 3220 case 14: 3221 return 5; 3222 } 3223 3224 return 0; 3225 } 3226 3227 #define PHY_TSSI_EXTRA_GROUP_BIT BIT(31) 3228 #define PHY_TSSI_EXTRA_GROUP(idx) (PHY_TSSI_EXTRA_GROUP_BIT | (idx)) 3229 #define PHY_IS_TSSI_EXTRA_GROUP(group) ((group) & PHY_TSSI_EXTRA_GROUP_BIT) 3230 #define PHY_TSSI_EXTRA_GET_GROUP_IDX1(group) \ 3231 ((group) & ~PHY_TSSI_EXTRA_GROUP_BIT) 3232 #define PHY_TSSI_EXTRA_GET_GROUP_IDX2(group) \ 3233 (PHY_TSSI_EXTRA_GET_GROUP_IDX1(group) + 1) 3234 3235 static u32 phy_tssi_get_ofdm_group(u8 ch) 3236 { 3237 switch (ch) { 3238 case 1 ... 2: 3239 return 0; 3240 case 3 ... 5: 3241 return 1; 3242 case 6 ... 8: 3243 return 2; 3244 case 9 ... 11: 3245 return 3; 3246 case 12 ... 14: 3247 return 4; 3248 case 36 ... 40: 3249 return 5; 3250 case 41 ... 43: 3251 return PHY_TSSI_EXTRA_GROUP(5); 3252 case 44 ... 48: 3253 return 6; 3254 case 49 ... 51: 3255 return PHY_TSSI_EXTRA_GROUP(6); 3256 case 52 ... 56: 3257 return 7; 3258 case 57 ... 59: 3259 return PHY_TSSI_EXTRA_GROUP(7); 3260 case 60 ... 64: 3261 return 8; 3262 case 100 ... 104: 3263 return 9; 3264 case 105 ... 107: 3265 return PHY_TSSI_EXTRA_GROUP(9); 3266 case 108 ... 112: 3267 return 10; 3268 case 113 ... 115: 3269 return PHY_TSSI_EXTRA_GROUP(10); 3270 case 116 ... 120: 3271 return 11; 3272 case 121 ... 123: 3273 return PHY_TSSI_EXTRA_GROUP(11); 3274 case 124 ... 128: 3275 return 12; 3276 case 129 ... 131: 3277 return PHY_TSSI_EXTRA_GROUP(12); 3278 case 132 ... 136: 3279 return 13; 3280 case 137 ... 139: 3281 return PHY_TSSI_EXTRA_GROUP(13); 3282 case 140 ... 144: 3283 return 14; 3284 case 149 ... 153: 3285 return 15; 3286 case 154 ... 156: 3287 return PHY_TSSI_EXTRA_GROUP(15); 3288 case 157 ... 161: 3289 return 16; 3290 case 162 ... 164: 3291 return PHY_TSSI_EXTRA_GROUP(16); 3292 case 165 ... 169: 3293 return 17; 3294 case 170 ... 172: 3295 return PHY_TSSI_EXTRA_GROUP(17); 3296 case 173 ... 177: 3297 return 18; 3298 } 3299 3300 return 0; 3301 } 3302 3303 static u32 phy_tssi_get_6g_ofdm_group(u8 ch) 3304 { 3305 switch (ch) { 3306 case 1 ... 5: 3307 return 0; 3308 case 6 ... 8: 3309 return PHY_TSSI_EXTRA_GROUP(0); 3310 case 9 ... 13: 3311 return 1; 3312 case 14 ... 16: 3313 return PHY_TSSI_EXTRA_GROUP(1); 3314 case 17 ... 21: 3315 return 2; 3316 case 22 ... 24: 3317 return PHY_TSSI_EXTRA_GROUP(2); 3318 case 25 ... 29: 3319 return 3; 3320 case 33 ... 37: 3321 return 4; 3322 case 38 ... 40: 3323 return PHY_TSSI_EXTRA_GROUP(4); 3324 case 41 ... 45: 3325 return 5; 3326 case 46 ... 48: 3327 return PHY_TSSI_EXTRA_GROUP(5); 3328 case 49 ... 53: 3329 return 6; 3330 case 54 ... 56: 3331 return PHY_TSSI_EXTRA_GROUP(6); 3332 case 57 ... 61: 3333 return 7; 3334 case 65 ... 69: 3335 return 8; 3336 case 70 ... 72: 3337 return PHY_TSSI_EXTRA_GROUP(8); 3338 case 73 ... 77: 3339 return 9; 3340 case 78 ... 80: 3341 return PHY_TSSI_EXTRA_GROUP(9); 3342 case 81 ... 85: 3343 return 10; 3344 case 86 ... 88: 3345 return PHY_TSSI_EXTRA_GROUP(10); 3346 case 89 ... 93: 3347 return 11; 3348 case 97 ... 101: 3349 return 12; 3350 case 102 ... 104: 3351 return PHY_TSSI_EXTRA_GROUP(12); 3352 case 105 ... 109: 3353 return 13; 3354 case 110 ... 112: 3355 return PHY_TSSI_EXTRA_GROUP(13); 3356 case 113 ... 117: 3357 return 14; 3358 case 118 ... 120: 3359 return PHY_TSSI_EXTRA_GROUP(14); 3360 case 121 ... 125: 3361 return 15; 3362 case 129 ... 133: 3363 return 16; 3364 case 134 ... 136: 3365 return PHY_TSSI_EXTRA_GROUP(16); 3366 case 137 ... 141: 3367 return 17; 3368 case 142 ... 144: 3369 return PHY_TSSI_EXTRA_GROUP(17); 3370 case 145 ... 149: 3371 return 18; 3372 case 150 ... 152: 3373 return PHY_TSSI_EXTRA_GROUP(18); 3374 case 153 ... 157: 3375 return 19; 3376 case 161 ... 165: 3377 return 20; 3378 case 166 ... 168: 3379 return PHY_TSSI_EXTRA_GROUP(20); 3380 case 169 ... 173: 3381 return 21; 3382 case 174 ... 176: 3383 return PHY_TSSI_EXTRA_GROUP(21); 3384 case 177 ... 181: 3385 return 22; 3386 case 182 ... 184: 3387 return PHY_TSSI_EXTRA_GROUP(22); 3388 case 185 ... 189: 3389 return 23; 3390 case 193 ... 197: 3391 return 24; 3392 case 198 ... 200: 3393 return PHY_TSSI_EXTRA_GROUP(24); 3394 case 201 ... 205: 3395 return 25; 3396 case 206 ... 208: 3397 return PHY_TSSI_EXTRA_GROUP(25); 3398 case 209 ... 213: 3399 return 26; 3400 case 214 ... 216: 3401 return PHY_TSSI_EXTRA_GROUP(26); 3402 case 217 ... 221: 3403 return 27; 3404 case 225 ... 229: 3405 return 28; 3406 case 230 ... 232: 3407 return PHY_TSSI_EXTRA_GROUP(28); 3408 case 233 ... 237: 3409 return 29; 3410 case 238 ... 240: 3411 return PHY_TSSI_EXTRA_GROUP(29); 3412 case 241 ... 245: 3413 return 30; 3414 case 246 ... 248: 3415 return PHY_TSSI_EXTRA_GROUP(30); 3416 case 249 ... 253: 3417 return 31; 3418 } 3419 3420 return 0; 3421 } 3422 3423 static u32 phy_tssi_get_trim_group(u8 ch) 3424 { 3425 switch (ch) { 3426 case 1 ... 8: 3427 return 0; 3428 case 9 ... 14: 3429 return 1; 3430 case 36 ... 48: 3431 return 2; 3432 case 49 ... 51: 3433 return PHY_TSSI_EXTRA_GROUP(2); 3434 case 52 ... 64: 3435 return 3; 3436 case 100 ... 112: 3437 return 4; 3438 case 113 ... 115: 3439 return PHY_TSSI_EXTRA_GROUP(4); 3440 case 116 ... 128: 3441 return 5; 3442 case 132 ... 144: 3443 return 6; 3444 case 149 ... 177: 3445 return 7; 3446 } 3447 3448 return 0; 3449 } 3450 3451 static u32 phy_tssi_get_6g_trim_group(u8 ch) 3452 { 3453 switch (ch) { 3454 case 1 ... 13: 3455 return 0; 3456 case 14 ... 16: 3457 return PHY_TSSI_EXTRA_GROUP(0); 3458 case 17 ... 29: 3459 return 1; 3460 case 33 ... 45: 3461 return 2; 3462 case 46 ... 48: 3463 return PHY_TSSI_EXTRA_GROUP(2); 3464 case 49 ... 61: 3465 return 3; 3466 case 65 ... 77: 3467 return 4; 3468 case 78 ... 80: 3469 return PHY_TSSI_EXTRA_GROUP(4); 3470 case 81 ... 93: 3471 return 5; 3472 case 97 ... 109: 3473 return 6; 3474 case 110 ... 112: 3475 return PHY_TSSI_EXTRA_GROUP(6); 3476 case 113 ... 125: 3477 return 7; 3478 case 129 ... 141: 3479 return 8; 3480 case 142 ... 144: 3481 return PHY_TSSI_EXTRA_GROUP(8); 3482 case 145 ... 157: 3483 return 9; 3484 case 161 ... 173: 3485 return 10; 3486 case 174 ... 176: 3487 return PHY_TSSI_EXTRA_GROUP(10); 3488 case 177 ... 189: 3489 return 11; 3490 case 193 ... 205: 3491 return 12; 3492 case 206 ... 208: 3493 return PHY_TSSI_EXTRA_GROUP(12); 3494 case 209 ... 221: 3495 return 13; 3496 case 225 ... 237: 3497 return 14; 3498 case 238 ... 240: 3499 return PHY_TSSI_EXTRA_GROUP(14); 3500 case 241 ... 253: 3501 return 15; 3502 } 3503 3504 return 0; 3505 } 3506 3507 static s8 phy_tssi_get_ofdm_de(struct rtw89_dev *rtwdev, 3508 enum rtw89_phy_idx phy, 3509 const struct rtw89_chan *chan, 3510 enum rtw89_rf_path path) 3511 { 3512 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 3513 enum rtw89_band band = chan->band_type; 3514 u8 ch = chan->channel; 3515 u32 gidx_1st; 3516 u32 gidx_2nd; 3517 s8 de_1st; 3518 s8 de_2nd; 3519 u32 gidx; 3520 s8 val; 3521 3522 if (band == RTW89_BAND_6G) 3523 goto calc_6g; 3524 3525 gidx = phy_tssi_get_ofdm_group(ch); 3526 3527 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3528 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", 3529 path, gidx); 3530 3531 if (PHY_IS_TSSI_EXTRA_GROUP(gidx)) { 3532 gidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(gidx); 3533 gidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(gidx); 3534 de_1st = tssi_info->tssi_mcs[path][gidx_1st]; 3535 de_2nd = tssi_info->tssi_mcs[path][gidx_2nd]; 3536 val = (de_1st + de_2nd) / 2; 3537 3538 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3539 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n", 3540 path, val, de_1st, de_2nd); 3541 } else { 3542 val = tssi_info->tssi_mcs[path][gidx]; 3543 3544 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3545 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val); 3546 } 3547 3548 return val; 3549 3550 calc_6g: 3551 gidx = phy_tssi_get_6g_ofdm_group(ch); 3552 3553 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3554 "[TSSI][TRIM]: path=%d mcs group_idx=0x%x\n", 3555 path, gidx); 3556 3557 if (PHY_IS_TSSI_EXTRA_GROUP(gidx)) { 3558 gidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(gidx); 3559 gidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(gidx); 3560 de_1st = tssi_info->tssi_6g_mcs[path][gidx_1st]; 3561 de_2nd = tssi_info->tssi_6g_mcs[path][gidx_2nd]; 3562 val = (de_1st + de_2nd) / 2; 3563 3564 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3565 "[TSSI][TRIM]: path=%d mcs de=%d 1st=%d 2nd=%d\n", 3566 path, val, de_1st, de_2nd); 3567 } else { 3568 val = tssi_info->tssi_6g_mcs[path][gidx]; 3569 3570 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3571 "[TSSI][TRIM]: path=%d mcs de=%d\n", path, val); 3572 } 3573 3574 return val; 3575 } 3576 3577 static s8 phy_tssi_get_ofdm_trim_de(struct rtw89_dev *rtwdev, 3578 enum rtw89_phy_idx phy, 3579 const struct rtw89_chan *chan, 3580 enum rtw89_rf_path path) 3581 { 3582 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 3583 enum rtw89_band band = chan->band_type; 3584 u8 ch = chan->channel; 3585 u32 tgidx_1st; 3586 u32 tgidx_2nd; 3587 s8 tde_1st; 3588 s8 tde_2nd; 3589 u32 tgidx; 3590 s8 val; 3591 3592 if (band == RTW89_BAND_6G) 3593 goto calc_6g; 3594 3595 tgidx = phy_tssi_get_trim_group(ch); 3596 3597 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3598 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n", 3599 path, tgidx); 3600 3601 if (PHY_IS_TSSI_EXTRA_GROUP(tgidx)) { 3602 tgidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(tgidx); 3603 tgidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(tgidx); 3604 tde_1st = tssi_info->tssi_trim[path][tgidx_1st]; 3605 tde_2nd = tssi_info->tssi_trim[path][tgidx_2nd]; 3606 val = (tde_1st + tde_2nd) / 2; 3607 3608 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3609 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n", 3610 path, val, tde_1st, tde_2nd); 3611 } else { 3612 val = tssi_info->tssi_trim[path][tgidx]; 3613 3614 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3615 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n", 3616 path, val); 3617 } 3618 3619 return val; 3620 3621 calc_6g: 3622 tgidx = phy_tssi_get_6g_trim_group(ch); 3623 3624 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3625 "[TSSI][TRIM]: path=%d mcs trim_group_idx=0x%x\n", 3626 path, tgidx); 3627 3628 if (PHY_IS_TSSI_EXTRA_GROUP(tgidx)) { 3629 tgidx_1st = PHY_TSSI_EXTRA_GET_GROUP_IDX1(tgidx); 3630 tgidx_2nd = PHY_TSSI_EXTRA_GET_GROUP_IDX2(tgidx); 3631 tde_1st = tssi_info->tssi_trim_6g[path][tgidx_1st]; 3632 tde_2nd = tssi_info->tssi_trim_6g[path][tgidx_2nd]; 3633 val = (tde_1st + tde_2nd) / 2; 3634 3635 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3636 "[TSSI][TRIM]: path=%d mcs trim_de=%d 1st=%d 2nd=%d\n", 3637 path, val, tde_1st, tde_2nd); 3638 } else { 3639 val = tssi_info->tssi_trim_6g[path][tgidx]; 3640 3641 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3642 "[TSSI][TRIM]: path=%d mcs trim_de=%d\n", 3643 path, val); 3644 } 3645 3646 return val; 3647 } 3648 3649 void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev, 3650 enum rtw89_phy_idx phy, 3651 const struct rtw89_chan *chan, 3652 struct rtw89_h2c_rf_tssi *h2c) 3653 { 3654 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 3655 u8 ch = chan->channel; 3656 s8 trim_de; 3657 s8 ofdm_de; 3658 s8 cck_de; 3659 u8 gidx; 3660 s8 val; 3661 int i; 3662 3663 rtw89_debug(rtwdev, RTW89_DBG_TSSI, "[TSSI][TRIM]: phy=%d ch=%d\n", 3664 phy, ch); 3665 3666 for (i = RF_PATH_A; i <= RF_PATH_B; i++) { 3667 trim_de = phy_tssi_get_ofdm_trim_de(rtwdev, phy, chan, i); 3668 h2c->curr_tssi_trim_de[i] = trim_de; 3669 3670 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3671 "[TSSI][TRIM]: path=%d trim_de=0x%x\n", i, trim_de); 3672 3673 gidx = phy_tssi_get_cck_group(ch); 3674 cck_de = tssi_info->tssi_cck[i][gidx]; 3675 val = u32_get_bits(cck_de + trim_de, 0xff); 3676 3677 h2c->curr_tssi_cck_de[i] = 0x0; 3678 h2c->curr_tssi_cck_de_20m[i] = val; 3679 h2c->curr_tssi_cck_de_40m[i] = val; 3680 h2c->curr_tssi_efuse_cck_de[i] = cck_de; 3681 3682 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3683 "[TSSI][TRIM]: path=%d cck_de=0x%x\n", i, cck_de); 3684 3685 ofdm_de = phy_tssi_get_ofdm_de(rtwdev, phy, chan, i); 3686 val = u32_get_bits(ofdm_de + trim_de, 0xff); 3687 3688 h2c->curr_tssi_ofdm_de[i] = 0x0; 3689 h2c->curr_tssi_ofdm_de_20m[i] = val; 3690 h2c->curr_tssi_ofdm_de_40m[i] = val; 3691 h2c->curr_tssi_ofdm_de_80m[i] = val; 3692 h2c->curr_tssi_ofdm_de_160m[i] = val; 3693 h2c->curr_tssi_ofdm_de_320m[i] = val; 3694 h2c->curr_tssi_efuse_ofdm_de[i] = ofdm_de; 3695 3696 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3697 "[TSSI][TRIM]: path=%d ofdm_de=0x%x\n", i, ofdm_de); 3698 } 3699 } 3700 3701 void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev, 3702 enum rtw89_phy_idx phy, 3703 const struct rtw89_chan *chan, 3704 struct rtw89_h2c_rf_tssi *h2c) 3705 { 3706 struct rtw89_fw_txpwr_track_cfg *trk = rtwdev->fw.elm_info.txpwr_trk; 3707 struct rtw89_tssi_info *tssi_info = &rtwdev->tssi; 3708 const s8 *thm_up[RF_PATH_B + 1] = {}; 3709 const s8 *thm_down[RF_PATH_B + 1] = {}; 3710 u8 subband = chan->subband_type; 3711 s8 thm_ofst[128] = {0}; 3712 u8 thermal; 3713 u8 path; 3714 u8 i, j; 3715 3716 switch (subband) { 3717 default: 3718 case RTW89_CH_2G: 3719 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_P][0]; 3720 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GA_N][0]; 3721 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_P][0]; 3722 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_2GB_N][0]; 3723 break; 3724 case RTW89_CH_5G_BAND_1: 3725 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][0]; 3726 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][0]; 3727 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][0]; 3728 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][0]; 3729 break; 3730 case RTW89_CH_5G_BAND_3: 3731 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][1]; 3732 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][1]; 3733 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][1]; 3734 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][1]; 3735 break; 3736 case RTW89_CH_5G_BAND_4: 3737 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_P][2]; 3738 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GA_N][2]; 3739 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_P][2]; 3740 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_5GB_N][2]; 3741 break; 3742 case RTW89_CH_6G_BAND_IDX0: 3743 case RTW89_CH_6G_BAND_IDX1: 3744 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][0]; 3745 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][0]; 3746 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][0]; 3747 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][0]; 3748 break; 3749 case RTW89_CH_6G_BAND_IDX2: 3750 case RTW89_CH_6G_BAND_IDX3: 3751 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][1]; 3752 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][1]; 3753 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][1]; 3754 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][1]; 3755 break; 3756 case RTW89_CH_6G_BAND_IDX4: 3757 case RTW89_CH_6G_BAND_IDX5: 3758 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][2]; 3759 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][2]; 3760 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][2]; 3761 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][2]; 3762 break; 3763 case RTW89_CH_6G_BAND_IDX6: 3764 case RTW89_CH_6G_BAND_IDX7: 3765 thm_up[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_P][3]; 3766 thm_down[RF_PATH_A] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GA_N][3]; 3767 thm_up[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_P][3]; 3768 thm_down[RF_PATH_B] = trk->delta[RTW89_FW_TXPWR_TRK_TYPE_6GB_N][3]; 3769 break; 3770 } 3771 3772 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3773 "[TSSI] tmeter tbl on subband: %u\n", subband); 3774 3775 for (path = RF_PATH_A; path <= RF_PATH_B; path++) { 3776 thermal = tssi_info->thermal[path]; 3777 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3778 "path: %u, pg thermal: 0x%x\n", path, thermal); 3779 3780 if (thermal == 0xff) { 3781 h2c->pg_thermal[path] = 0x38; 3782 memset(h2c->ftable[path], 0, sizeof(h2c->ftable[path])); 3783 continue; 3784 } 3785 3786 h2c->pg_thermal[path] = thermal; 3787 3788 i = 0; 3789 for (j = 0; j < 64; j++) 3790 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? 3791 thm_up[path][i++] : 3792 thm_up[path][DELTA_SWINGIDX_SIZE - 1]; 3793 3794 i = 1; 3795 for (j = 127; j >= 64; j--) 3796 thm_ofst[j] = i < DELTA_SWINGIDX_SIZE ? 3797 -thm_down[path][i++] : 3798 -thm_down[path][DELTA_SWINGIDX_SIZE - 1]; 3799 3800 for (i = 0; i < 128; i += 4) { 3801 h2c->ftable[path][i + 0] = thm_ofst[i + 3]; 3802 h2c->ftable[path][i + 1] = thm_ofst[i + 2]; 3803 h2c->ftable[path][i + 2] = thm_ofst[i + 1]; 3804 h2c->ftable[path][i + 3] = thm_ofst[i + 0]; 3805 3806 rtw89_debug(rtwdev, RTW89_DBG_TSSI, 3807 "thm ofst [%x]: %02x %02x %02x %02x\n", 3808 i, thm_ofst[i], thm_ofst[i + 1], 3809 thm_ofst[i + 2], thm_ofst[i + 3]); 3810 } 3811 } 3812 } 3813 3814 static u8 rtw89_phy_cfo_get_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo) 3815 { 3816 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info; 3817 u32 reg_mask; 3818 3819 if (sc_xo) 3820 reg_mask = xtal->sc_xo_mask; 3821 else 3822 reg_mask = xtal->sc_xi_mask; 3823 3824 return (u8)rtw89_read32_mask(rtwdev, xtal->xcap_reg, reg_mask); 3825 } 3826 3827 static void rtw89_phy_cfo_set_xcap_reg(struct rtw89_dev *rtwdev, bool sc_xo, 3828 u8 val) 3829 { 3830 const struct rtw89_xtal_info *xtal = rtwdev->chip->xtal_info; 3831 u32 reg_mask; 3832 3833 if (sc_xo) 3834 reg_mask = xtal->sc_xo_mask; 3835 else 3836 reg_mask = xtal->sc_xi_mask; 3837 3838 rtw89_write32_mask(rtwdev, xtal->xcap_reg, reg_mask, val); 3839 } 3840 3841 static void rtw89_phy_cfo_set_crystal_cap(struct rtw89_dev *rtwdev, 3842 u8 crystal_cap, bool force) 3843 { 3844 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 3845 const struct rtw89_chip_info *chip = rtwdev->chip; 3846 u8 sc_xi_val, sc_xo_val; 3847 3848 if (!force && cfo->crystal_cap == crystal_cap) 3849 return; 3850 crystal_cap = clamp_t(u8, crystal_cap, 0, 127); 3851 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8851B) { 3852 rtw89_phy_cfo_set_xcap_reg(rtwdev, true, crystal_cap); 3853 rtw89_phy_cfo_set_xcap_reg(rtwdev, false, crystal_cap); 3854 sc_xo_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, true); 3855 sc_xi_val = rtw89_phy_cfo_get_xcap_reg(rtwdev, false); 3856 } else { 3857 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, 3858 crystal_cap, XTAL_SC_XO_MASK); 3859 rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, 3860 crystal_cap, XTAL_SC_XI_MASK); 3861 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XO, &sc_xo_val); 3862 rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_XTAL_SC_XI, &sc_xi_val); 3863 } 3864 cfo->crystal_cap = sc_xi_val; 3865 cfo->x_cap_ofst = (s8)((int)cfo->crystal_cap - cfo->def_x_cap); 3866 3867 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xi=0x%x\n", sc_xi_val); 3868 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set sc_xo=0x%x\n", sc_xo_val); 3869 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Get xcap_ofst=%d\n", 3870 cfo->x_cap_ofst); 3871 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Set xcap OK\n"); 3872 } 3873 3874 static void rtw89_phy_cfo_reset(struct rtw89_dev *rtwdev) 3875 { 3876 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 3877 u8 cap; 3878 3879 cfo->def_x_cap = cfo->crystal_cap_default & B_AX_XTAL_SC_MASK; 3880 cfo->is_adjust = false; 3881 if (cfo->crystal_cap == cfo->def_x_cap) 3882 return; 3883 cap = cfo->crystal_cap; 3884 cap += (cap > cfo->def_x_cap ? -1 : 1); 3885 rtw89_phy_cfo_set_crystal_cap(rtwdev, cap, false); 3886 rtw89_debug(rtwdev, RTW89_DBG_CFO, 3887 "(0x%x) approach to dflt_val=(0x%x)\n", cfo->crystal_cap, 3888 cfo->def_x_cap); 3889 } 3890 3891 static void rtw89_dcfo_comp(struct rtw89_dev *rtwdev, s32 curr_cfo) 3892 { 3893 const struct rtw89_reg_def *dcfo_comp = rtwdev->chip->dcfo_comp; 3894 bool is_linked = rtwdev->total_sta_assoc > 0; 3895 s32 cfo_avg_312; 3896 s32 dcfo_comp_val; 3897 int sign; 3898 3899 if (rtwdev->chip->chip_id == RTL8922A) 3900 return; 3901 3902 if (!is_linked) { 3903 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: is_linked=%d\n", 3904 is_linked); 3905 return; 3906 } 3907 rtw89_debug(rtwdev, RTW89_DBG_CFO, "DCFO: curr_cfo=%d\n", curr_cfo); 3908 if (curr_cfo == 0) 3909 return; 3910 dcfo_comp_val = rtw89_phy_read32_mask(rtwdev, R_DCFO, B_DCFO); 3911 sign = curr_cfo > 0 ? 1 : -1; 3912 cfo_avg_312 = curr_cfo / 625 + sign * dcfo_comp_val; 3913 rtw89_debug(rtwdev, RTW89_DBG_CFO, "avg_cfo_312=%d step\n", cfo_avg_312); 3914 if (rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) 3915 cfo_avg_312 = -cfo_avg_312; 3916 rtw89_phy_set_phy_regs(rtwdev, dcfo_comp->addr, dcfo_comp->mask, 3917 cfo_avg_312); 3918 } 3919 3920 static void rtw89_dcfo_comp_init(struct rtw89_dev *rtwdev) 3921 { 3922 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 3923 const struct rtw89_chip_info *chip = rtwdev->chip; 3924 const struct rtw89_cfo_regs *cfo = phy->cfo; 3925 3926 rtw89_phy_set_phy_regs(rtwdev, cfo->comp_seg0, cfo->valid_0_mask, 1); 3927 rtw89_phy_set_phy_regs(rtwdev, cfo->comp, cfo->weighting_mask, 8); 3928 3929 if (chip->chip_gen == RTW89_CHIP_AX) { 3930 if (chip->cfo_hw_comp) { 3931 rtw89_write32_mask(rtwdev, R_AX_PWR_UL_CTRL2, 3932 B_AX_PWR_UL_CFO_MASK, 0x6); 3933 } else { 3934 rtw89_phy_set_phy_regs(rtwdev, R_DCFO, B_DCFO, 1); 3935 rtw89_write32_clr(rtwdev, R_AX_PWR_UL_CTRL2, 3936 B_AX_PWR_UL_CFO_MASK); 3937 } 3938 } 3939 } 3940 3941 static void rtw89_phy_cfo_init(struct rtw89_dev *rtwdev) 3942 { 3943 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 3944 struct rtw89_efuse *efuse = &rtwdev->efuse; 3945 3946 cfo->crystal_cap_default = efuse->xtal_cap & B_AX_XTAL_SC_MASK; 3947 cfo->crystal_cap = cfo->crystal_cap_default; 3948 cfo->def_x_cap = cfo->crystal_cap; 3949 cfo->x_cap_ub = min_t(int, cfo->def_x_cap + CFO_BOUND, 0x7f); 3950 cfo->x_cap_lb = max_t(int, cfo->def_x_cap - CFO_BOUND, 0x1); 3951 cfo->is_adjust = false; 3952 cfo->divergence_lock_en = false; 3953 cfo->x_cap_ofst = 0; 3954 cfo->lock_cnt = 0; 3955 cfo->rtw89_multi_cfo_mode = RTW89_TP_BASED_AVG_MODE; 3956 cfo->apply_compensation = false; 3957 cfo->residual_cfo_acc = 0; 3958 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Default xcap=%0x\n", 3959 cfo->crystal_cap_default); 3960 rtw89_phy_cfo_set_crystal_cap(rtwdev, cfo->crystal_cap_default, true); 3961 rtw89_dcfo_comp_init(rtwdev); 3962 cfo->cfo_timer_ms = 2000; 3963 cfo->cfo_trig_by_timer_en = false; 3964 cfo->phy_cfo_trk_cnt = 0; 3965 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 3966 cfo->cfo_ul_ofdma_acc_mode = RTW89_CFO_UL_OFDMA_ACC_ENABLE; 3967 } 3968 3969 static void rtw89_phy_cfo_crystal_cap_adjust(struct rtw89_dev *rtwdev, 3970 s32 curr_cfo) 3971 { 3972 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 3973 s8 crystal_cap = cfo->crystal_cap; 3974 s32 cfo_abs = abs(curr_cfo); 3975 int sign; 3976 3977 if (curr_cfo == 0) { 3978 rtw89_debug(rtwdev, RTW89_DBG_CFO, "curr_cfo=0\n"); 3979 return; 3980 } 3981 if (!cfo->is_adjust) { 3982 if (cfo_abs > CFO_TRK_ENABLE_TH) 3983 cfo->is_adjust = true; 3984 } else { 3985 if (cfo_abs <= CFO_TRK_STOP_TH) 3986 cfo->is_adjust = false; 3987 } 3988 if (!cfo->is_adjust) { 3989 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Stop CFO tracking\n"); 3990 return; 3991 } 3992 sign = curr_cfo > 0 ? 1 : -1; 3993 if (cfo_abs > CFO_TRK_STOP_TH_4) 3994 crystal_cap += 7 * sign; 3995 else if (cfo_abs > CFO_TRK_STOP_TH_3) 3996 crystal_cap += 5 * sign; 3997 else if (cfo_abs > CFO_TRK_STOP_TH_2) 3998 crystal_cap += 3 * sign; 3999 else if (cfo_abs > CFO_TRK_STOP_TH_1) 4000 crystal_cap += 1 * sign; 4001 else 4002 return; 4003 rtw89_phy_cfo_set_crystal_cap(rtwdev, (u8)crystal_cap, false); 4004 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4005 "X_cap{Curr,Default}={0x%x,0x%x}\n", 4006 cfo->crystal_cap, cfo->def_x_cap); 4007 } 4008 4009 static s32 rtw89_phy_average_cfo_calc(struct rtw89_dev *rtwdev) 4010 { 4011 const struct rtw89_chip_info *chip = rtwdev->chip; 4012 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4013 s32 cfo_khz_all = 0; 4014 s32 cfo_cnt_all = 0; 4015 s32 cfo_all_avg = 0; 4016 u8 i; 4017 4018 if (rtwdev->total_sta_assoc != 1) 4019 return 0; 4020 rtw89_debug(rtwdev, RTW89_DBG_CFO, "one_entry_only\n"); 4021 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 4022 if (cfo->cfo_cnt[i] == 0) 4023 continue; 4024 cfo_khz_all += cfo->cfo_tail[i]; 4025 cfo_cnt_all += cfo->cfo_cnt[i]; 4026 cfo_all_avg = phy_div(cfo_khz_all, cfo_cnt_all); 4027 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 4028 cfo->dcfo_avg = phy_div(cfo_khz_all << chip->dcfo_comp_sft, 4029 cfo_cnt_all); 4030 } 4031 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4032 "CFO track for macid = %d\n", i); 4033 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4034 "Total cfo=%dK, pkt_cnt=%d, avg_cfo=%dK\n", 4035 cfo_khz_all, cfo_cnt_all, cfo_all_avg); 4036 return cfo_all_avg; 4037 } 4038 4039 static s32 rtw89_phy_multi_sta_cfo_calc(struct rtw89_dev *rtwdev) 4040 { 4041 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4042 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4043 s32 target_cfo = 0; 4044 s32 cfo_khz_all = 0; 4045 s32 cfo_khz_all_tp_wgt = 0; 4046 s32 cfo_avg = 0; 4047 s32 max_cfo_lb = BIT(31); 4048 s32 min_cfo_ub = GENMASK(30, 0); 4049 u16 cfo_cnt_all = 0; 4050 u8 active_entry_cnt = 0; 4051 u8 sta_cnt = 0; 4052 u32 tp_all = 0; 4053 u8 i; 4054 u8 cfo_tol = 0; 4055 4056 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Multi entry cfo_trk\n"); 4057 if (cfo->rtw89_multi_cfo_mode == RTW89_PKT_BASED_AVG_MODE) { 4058 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt based avg mode\n"); 4059 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 4060 if (cfo->cfo_cnt[i] == 0) 4061 continue; 4062 cfo_khz_all += cfo->cfo_tail[i]; 4063 cfo_cnt_all += cfo->cfo_cnt[i]; 4064 cfo_avg = phy_div(cfo_khz_all, (s32)cfo_cnt_all); 4065 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4066 "Msta cfo=%d, pkt_cnt=%d, avg_cfo=%d\n", 4067 cfo_khz_all, cfo_cnt_all, cfo_avg); 4068 target_cfo = cfo_avg; 4069 } 4070 } else if (cfo->rtw89_multi_cfo_mode == RTW89_ENTRY_BASED_AVG_MODE) { 4071 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Entry based avg mode\n"); 4072 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 4073 if (cfo->cfo_cnt[i] == 0) 4074 continue; 4075 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 4076 (s32)cfo->cfo_cnt[i]); 4077 cfo_khz_all += cfo->cfo_avg[i]; 4078 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4079 "Macid=%d, cfo_avg=%d\n", i, 4080 cfo->cfo_avg[i]); 4081 } 4082 sta_cnt = rtwdev->total_sta_assoc; 4083 cfo_avg = phy_div(cfo_khz_all, (s32)sta_cnt); 4084 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4085 "Msta cfo_acc=%d, ent_cnt=%d, avg_cfo=%d\n", 4086 cfo_khz_all, sta_cnt, cfo_avg); 4087 target_cfo = cfo_avg; 4088 } else if (cfo->rtw89_multi_cfo_mode == RTW89_TP_BASED_AVG_MODE) { 4089 rtw89_debug(rtwdev, RTW89_DBG_CFO, "TP based avg mode\n"); 4090 cfo_tol = cfo->sta_cfo_tolerance; 4091 for (i = 0; i < CFO_TRACK_MAX_USER; i++) { 4092 sta_cnt++; 4093 if (cfo->cfo_cnt[i] != 0) { 4094 cfo->cfo_avg[i] = phy_div(cfo->cfo_tail[i], 4095 (s32)cfo->cfo_cnt[i]); 4096 active_entry_cnt++; 4097 } else { 4098 cfo->cfo_avg[i] = cfo->pre_cfo_avg[i]; 4099 } 4100 max_cfo_lb = max(cfo->cfo_avg[i] - cfo_tol, max_cfo_lb); 4101 min_cfo_ub = min(cfo->cfo_avg[i] + cfo_tol, min_cfo_ub); 4102 cfo_khz_all += cfo->cfo_avg[i]; 4103 /* need tp for each entry */ 4104 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4105 "[%d] cfo_avg=%d, tp=tbd\n", 4106 i, cfo->cfo_avg[i]); 4107 if (sta_cnt >= rtwdev->total_sta_assoc) 4108 break; 4109 } 4110 tp_all = stats->rx_throughput; /* need tp for each entry */ 4111 cfo_avg = phy_div(cfo_khz_all_tp_wgt, (s32)tp_all); 4112 4113 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Assoc sta cnt=%d\n", 4114 sta_cnt); 4115 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Active sta cnt=%d\n", 4116 active_entry_cnt); 4117 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4118 "Msta cfo with tp_wgt=%d, avg_cfo=%d\n", 4119 cfo_khz_all_tp_wgt, cfo_avg); 4120 rtw89_debug(rtwdev, RTW89_DBG_CFO, "cfo_lb=%d,cfo_ub=%d\n", 4121 max_cfo_lb, min_cfo_ub); 4122 if (max_cfo_lb <= min_cfo_ub) { 4123 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4124 "cfo win_size=%d\n", 4125 min_cfo_ub - max_cfo_lb); 4126 target_cfo = clamp(cfo_avg, max_cfo_lb, min_cfo_ub); 4127 } else { 4128 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4129 "No intersection of cfo tolerance windows\n"); 4130 target_cfo = phy_div(cfo_khz_all, (s32)sta_cnt); 4131 } 4132 for (i = 0; i < CFO_TRACK_MAX_USER; i++) 4133 cfo->pre_cfo_avg[i] = cfo->cfo_avg[i]; 4134 } 4135 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Target cfo=%d\n", target_cfo); 4136 return target_cfo; 4137 } 4138 4139 static void rtw89_phy_cfo_statistics_reset(struct rtw89_dev *rtwdev) 4140 { 4141 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4142 4143 memset(&cfo->cfo_tail, 0, sizeof(cfo->cfo_tail)); 4144 memset(&cfo->cfo_cnt, 0, sizeof(cfo->cfo_cnt)); 4145 cfo->packet_count = 0; 4146 cfo->packet_count_pre = 0; 4147 cfo->cfo_avg_pre = 0; 4148 } 4149 4150 static void rtw89_phy_cfo_dm(struct rtw89_dev *rtwdev) 4151 { 4152 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4153 s32 new_cfo = 0; 4154 bool x_cap_update = false; 4155 u8 pre_x_cap = cfo->crystal_cap; 4156 u8 dcfo_comp_sft = rtwdev->chip->dcfo_comp_sft; 4157 4158 cfo->dcfo_avg = 0; 4159 rtw89_debug(rtwdev, RTW89_DBG_CFO, "CFO:total_sta_assoc=%d\n", 4160 rtwdev->total_sta_assoc); 4161 if (rtwdev->total_sta_assoc == 0) { 4162 rtw89_phy_cfo_reset(rtwdev); 4163 return; 4164 } 4165 if (cfo->packet_count == 0) { 4166 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt = 0\n"); 4167 return; 4168 } 4169 if (cfo->packet_count == cfo->packet_count_pre) { 4170 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Pkt cnt doesn't change\n"); 4171 return; 4172 } 4173 if (rtwdev->total_sta_assoc == 1) 4174 new_cfo = rtw89_phy_average_cfo_calc(rtwdev); 4175 else 4176 new_cfo = rtw89_phy_multi_sta_cfo_calc(rtwdev); 4177 if (cfo->divergence_lock_en) { 4178 cfo->lock_cnt++; 4179 if (cfo->lock_cnt > CFO_PERIOD_CNT) { 4180 cfo->divergence_lock_en = false; 4181 cfo->lock_cnt = 0; 4182 } else { 4183 rtw89_phy_cfo_reset(rtwdev); 4184 } 4185 return; 4186 } 4187 if (cfo->crystal_cap >= cfo->x_cap_ub || 4188 cfo->crystal_cap <= cfo->x_cap_lb) { 4189 cfo->divergence_lock_en = true; 4190 rtw89_phy_cfo_reset(rtwdev); 4191 return; 4192 } 4193 4194 rtw89_phy_cfo_crystal_cap_adjust(rtwdev, new_cfo); 4195 cfo->cfo_avg_pre = new_cfo; 4196 cfo->dcfo_avg_pre = cfo->dcfo_avg; 4197 x_cap_update = cfo->crystal_cap != pre_x_cap; 4198 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap_up=%d\n", x_cap_update); 4199 rtw89_debug(rtwdev, RTW89_DBG_CFO, "Xcap: D:%x C:%x->%x, ofst=%d\n", 4200 cfo->def_x_cap, pre_x_cap, cfo->crystal_cap, 4201 cfo->x_cap_ofst); 4202 if (x_cap_update) { 4203 if (cfo->dcfo_avg > 0) 4204 cfo->dcfo_avg -= CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft; 4205 else 4206 cfo->dcfo_avg += CFO_SW_COMP_FINE_TUNE << dcfo_comp_sft; 4207 } 4208 rtw89_dcfo_comp(rtwdev, cfo->dcfo_avg); 4209 rtw89_phy_cfo_statistics_reset(rtwdev); 4210 } 4211 4212 void rtw89_phy_cfo_track_work(struct work_struct *work) 4213 { 4214 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 4215 cfo_track_work.work); 4216 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4217 4218 mutex_lock(&rtwdev->mutex); 4219 if (!cfo->cfo_trig_by_timer_en) 4220 goto out; 4221 rtw89_leave_ps_mode(rtwdev); 4222 rtw89_phy_cfo_dm(rtwdev); 4223 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 4224 msecs_to_jiffies(cfo->cfo_timer_ms)); 4225 out: 4226 mutex_unlock(&rtwdev->mutex); 4227 } 4228 4229 static void rtw89_phy_cfo_start_work(struct rtw89_dev *rtwdev) 4230 { 4231 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4232 4233 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->cfo_track_work, 4234 msecs_to_jiffies(cfo->cfo_timer_ms)); 4235 } 4236 4237 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev) 4238 { 4239 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4240 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4241 bool is_ul_ofdma = false, ofdma_acc_en = false; 4242 4243 if (stats->rx_tf_periodic > CFO_TF_CNT_TH) 4244 is_ul_ofdma = true; 4245 if (cfo->cfo_ul_ofdma_acc_mode == RTW89_CFO_UL_OFDMA_ACC_ENABLE && 4246 is_ul_ofdma) 4247 ofdma_acc_en = true; 4248 4249 switch (cfo->phy_cfo_status) { 4250 case RTW89_PHY_DCFO_STATE_NORMAL: 4251 if (stats->tx_throughput >= CFO_TP_UPPER) { 4252 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_ENHANCE; 4253 cfo->cfo_trig_by_timer_en = true; 4254 cfo->cfo_timer_ms = CFO_COMP_PERIOD; 4255 rtw89_phy_cfo_start_work(rtwdev); 4256 } 4257 break; 4258 case RTW89_PHY_DCFO_STATE_ENHANCE: 4259 if (stats->tx_throughput <= CFO_TP_LOWER) 4260 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 4261 else if (ofdma_acc_en && 4262 cfo->phy_cfo_trk_cnt >= CFO_PERIOD_CNT) 4263 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_HOLD; 4264 else 4265 cfo->phy_cfo_trk_cnt++; 4266 4267 if (cfo->phy_cfo_status == RTW89_PHY_DCFO_STATE_NORMAL) { 4268 cfo->phy_cfo_trk_cnt = 0; 4269 cfo->cfo_trig_by_timer_en = false; 4270 } 4271 break; 4272 case RTW89_PHY_DCFO_STATE_HOLD: 4273 if (stats->tx_throughput <= CFO_TP_LOWER) { 4274 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 4275 cfo->phy_cfo_trk_cnt = 0; 4276 cfo->cfo_trig_by_timer_en = false; 4277 } else { 4278 cfo->phy_cfo_trk_cnt++; 4279 } 4280 break; 4281 default: 4282 cfo->phy_cfo_status = RTW89_PHY_DCFO_STATE_NORMAL; 4283 cfo->phy_cfo_trk_cnt = 0; 4284 break; 4285 } 4286 rtw89_debug(rtwdev, RTW89_DBG_CFO, 4287 "[CFO]WatchDog tp=%d,state=%d,timer_en=%d,trk_cnt=%d,thermal=%ld\n", 4288 stats->tx_throughput, cfo->phy_cfo_status, 4289 cfo->cfo_trig_by_timer_en, cfo->phy_cfo_trk_cnt, 4290 ewma_thermal_read(&rtwdev->phystat.avg_thermal[0])); 4291 if (cfo->cfo_trig_by_timer_en) 4292 return; 4293 rtw89_phy_cfo_dm(rtwdev); 4294 } 4295 4296 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, 4297 struct rtw89_rx_phy_ppdu *phy_ppdu) 4298 { 4299 struct rtw89_cfo_tracking_info *cfo = &rtwdev->cfo_tracking; 4300 u8 macid = phy_ppdu->mac_id; 4301 4302 if (macid >= CFO_TRACK_MAX_USER) { 4303 rtw89_warn(rtwdev, "mac_id %d is out of range\n", macid); 4304 return; 4305 } 4306 4307 cfo->cfo_tail[macid] += cfo_val; 4308 cfo->cfo_cnt[macid]++; 4309 cfo->packet_count++; 4310 } 4311 4312 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4313 { 4314 const struct rtw89_chip_info *chip = rtwdev->chip; 4315 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 4316 rtwvif->sub_entity_idx); 4317 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 4318 4319 if (!chip->ul_tb_waveform_ctrl) 4320 return; 4321 4322 rtwvif->def_tri_idx = 4323 rtw89_phy_read32_mask(rtwdev, R_DCFO_OPT, B_TXSHAPE_TRIANGULAR_CFG); 4324 4325 if (chip->chip_id == RTL8852B && rtwdev->hal.cv > CHIP_CBV) 4326 rtwvif->dyn_tb_bedge_en = false; 4327 else if (chan->band_type >= RTW89_BAND_5G && 4328 chan->band_width >= RTW89_CHANNEL_WIDTH_40) 4329 rtwvif->dyn_tb_bedge_en = true; 4330 else 4331 rtwvif->dyn_tb_bedge_en = false; 4332 4333 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4334 "[ULTB] def_if_bandedge=%d, def_tri_idx=%d\n", 4335 ul_tb_info->def_if_bandedge, rtwvif->def_tri_idx); 4336 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4337 "[ULTB] dyn_tb_begde_en=%d, dyn_tb_tri_en=%d\n", 4338 rtwvif->dyn_tb_bedge_en, ul_tb_info->dyn_tb_tri_en); 4339 } 4340 4341 struct rtw89_phy_ul_tb_check_data { 4342 bool valid; 4343 bool high_tf_client; 4344 bool low_tf_client; 4345 bool dyn_tb_bedge_en; 4346 u8 def_tri_idx; 4347 }; 4348 4349 struct rtw89_phy_power_diff { 4350 u32 q_00; 4351 u32 q_11; 4352 u32 q_matrix_en; 4353 u32 ultb_1t_norm_160; 4354 u32 ultb_2t_norm_160; 4355 u32 com1_norm_1sts; 4356 u32 com2_resp_1sts_path; 4357 }; 4358 4359 static void rtw89_phy_ofdma_power_diff(struct rtw89_dev *rtwdev, 4360 struct rtw89_vif *rtwvif) 4361 { 4362 static const struct rtw89_phy_power_diff table[2] = { 4363 {0x0, 0x0, 0x0, 0x0, 0xf4, 0x3, 0x3}, 4364 {0xb50, 0xb50, 0x1, 0xc, 0x0, 0x1, 0x1}, 4365 }; 4366 const struct rtw89_phy_power_diff *param; 4367 u32 reg; 4368 4369 if (!rtwdev->chip->ul_tb_pwr_diff) 4370 return; 4371 4372 if (rtwvif->pwr_diff_en == rtwvif->pre_pwr_diff_en) { 4373 rtwvif->pwr_diff_en = false; 4374 return; 4375 } 4376 4377 rtwvif->pre_pwr_diff_en = rtwvif->pwr_diff_en; 4378 param = &table[rtwvif->pwr_diff_en]; 4379 4380 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_00, B_Q_MATRIX_00_REAL, 4381 param->q_00); 4382 rtw89_phy_write32_mask(rtwdev, R_Q_MATRIX_11, B_Q_MATRIX_11_REAL, 4383 param->q_11); 4384 rtw89_phy_write32_mask(rtwdev, R_CUSTOMIZE_Q_MATRIX, 4385 B_CUSTOMIZE_Q_MATRIX_EN, param->q_matrix_en); 4386 4387 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_1T, rtwvif->mac_idx); 4388 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_1T_NORM_BW160, 4389 param->ultb_1t_norm_160); 4390 4391 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PWR_UL_TB_2T, rtwvif->mac_idx); 4392 rtw89_write32_mask(rtwdev, reg, B_AX_PWR_UL_TB_2T_NORM_BW160, 4393 param->ultb_2t_norm_160); 4394 4395 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM1, rtwvif->mac_idx); 4396 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM1_NORM_1STS, 4397 param->com1_norm_1sts); 4398 4399 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PATH_COM2, rtwvif->mac_idx); 4400 rtw89_write32_mask(rtwdev, reg, B_AX_PATH_COM2_RESP_1STS_PATH, 4401 param->com2_resp_1sts_path); 4402 } 4403 4404 static 4405 void rtw89_phy_ul_tb_ctrl_check(struct rtw89_dev *rtwdev, 4406 struct rtw89_vif *rtwvif, 4407 struct rtw89_phy_ul_tb_check_data *ul_tb_data) 4408 { 4409 struct rtw89_traffic_stats *stats = &rtwdev->stats; 4410 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4411 4412 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 4413 return; 4414 4415 if (!vif->cfg.assoc) 4416 return; 4417 4418 if (rtwdev->chip->ul_tb_waveform_ctrl) { 4419 if (stats->rx_tf_periodic > UL_TB_TF_CNT_L2H_TH) 4420 ul_tb_data->high_tf_client = true; 4421 else if (stats->rx_tf_periodic < UL_TB_TF_CNT_H2L_TH) 4422 ul_tb_data->low_tf_client = true; 4423 4424 ul_tb_data->valid = true; 4425 ul_tb_data->def_tri_idx = rtwvif->def_tri_idx; 4426 ul_tb_data->dyn_tb_bedge_en = rtwvif->dyn_tb_bedge_en; 4427 } 4428 4429 rtw89_phy_ofdma_power_diff(rtwdev, rtwvif); 4430 } 4431 4432 static void rtw89_phy_ul_tb_waveform_ctrl(struct rtw89_dev *rtwdev, 4433 struct rtw89_phy_ul_tb_check_data *ul_tb_data) 4434 { 4435 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 4436 4437 if (!rtwdev->chip->ul_tb_waveform_ctrl) 4438 return; 4439 4440 if (ul_tb_data->dyn_tb_bedge_en) { 4441 if (ul_tb_data->high_tf_client) { 4442 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 0); 4443 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4444 "[ULTB] Turn off if_bandedge\n"); 4445 } else if (ul_tb_data->low_tf_client) { 4446 rtw89_phy_write32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN, 4447 ul_tb_info->def_if_bandedge); 4448 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4449 "[ULTB] Set to default if_bandedge = %d\n", 4450 ul_tb_info->def_if_bandedge); 4451 } 4452 } 4453 4454 if (ul_tb_info->dyn_tb_tri_en) { 4455 if (ul_tb_data->high_tf_client) { 4456 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 4457 B_TXSHAPE_TRIANGULAR_CFG, 0); 4458 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4459 "[ULTB] Turn off Tx triangle\n"); 4460 } else if (ul_tb_data->low_tf_client) { 4461 rtw89_phy_write32_mask(rtwdev, R_DCFO_OPT, 4462 B_TXSHAPE_TRIANGULAR_CFG, 4463 ul_tb_data->def_tri_idx); 4464 rtw89_debug(rtwdev, RTW89_DBG_UL_TB, 4465 "[ULTB] Set to default tx_shap_idx = %d\n", 4466 ul_tb_data->def_tri_idx); 4467 } 4468 } 4469 } 4470 4471 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev) 4472 { 4473 const struct rtw89_chip_info *chip = rtwdev->chip; 4474 struct rtw89_phy_ul_tb_check_data ul_tb_data = {}; 4475 struct rtw89_vif *rtwvif; 4476 4477 if (!chip->ul_tb_waveform_ctrl && !chip->ul_tb_pwr_diff) 4478 return; 4479 4480 if (rtwdev->total_sta_assoc != 1) 4481 return; 4482 4483 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4484 rtw89_phy_ul_tb_ctrl_check(rtwdev, rtwvif, &ul_tb_data); 4485 4486 if (!ul_tb_data.valid) 4487 return; 4488 4489 rtw89_phy_ul_tb_waveform_ctrl(rtwdev, &ul_tb_data); 4490 } 4491 4492 static void rtw89_phy_ul_tb_info_init(struct rtw89_dev *rtwdev) 4493 { 4494 const struct rtw89_chip_info *chip = rtwdev->chip; 4495 struct rtw89_phy_ul_tb_info *ul_tb_info = &rtwdev->ul_tb_info; 4496 4497 if (!chip->ul_tb_waveform_ctrl) 4498 return; 4499 4500 ul_tb_info->dyn_tb_tri_en = true; 4501 ul_tb_info->def_if_bandedge = 4502 rtw89_phy_read32_mask(rtwdev, R_BANDEDGE, B_BANDEDGE_EN); 4503 } 4504 4505 static 4506 void rtw89_phy_antdiv_sts_instance_reset(struct rtw89_antdiv_stats *antdiv_sts) 4507 { 4508 ewma_rssi_init(&antdiv_sts->cck_rssi_avg); 4509 ewma_rssi_init(&antdiv_sts->ofdm_rssi_avg); 4510 ewma_rssi_init(&antdiv_sts->non_legacy_rssi_avg); 4511 antdiv_sts->pkt_cnt_cck = 0; 4512 antdiv_sts->pkt_cnt_ofdm = 0; 4513 antdiv_sts->pkt_cnt_non_legacy = 0; 4514 antdiv_sts->evm = 0; 4515 } 4516 4517 static void rtw89_phy_antdiv_sts_instance_add(struct rtw89_dev *rtwdev, 4518 struct rtw89_rx_phy_ppdu *phy_ppdu, 4519 struct rtw89_antdiv_stats *stats) 4520 { 4521 if (rtw89_get_data_rate_mode(rtwdev, phy_ppdu->rate) == DATA_RATE_MODE_NON_HT) { 4522 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) { 4523 ewma_rssi_add(&stats->cck_rssi_avg, phy_ppdu->rssi_avg); 4524 stats->pkt_cnt_cck++; 4525 } else { 4526 ewma_rssi_add(&stats->ofdm_rssi_avg, phy_ppdu->rssi_avg); 4527 stats->pkt_cnt_ofdm++; 4528 stats->evm += phy_ppdu->ofdm.evm_min; 4529 } 4530 } else { 4531 ewma_rssi_add(&stats->non_legacy_rssi_avg, phy_ppdu->rssi_avg); 4532 stats->pkt_cnt_non_legacy++; 4533 stats->evm += phy_ppdu->ofdm.evm_min; 4534 } 4535 } 4536 4537 static u8 rtw89_phy_antdiv_sts_instance_get_rssi(struct rtw89_antdiv_stats *stats) 4538 { 4539 if (stats->pkt_cnt_non_legacy >= stats->pkt_cnt_cck && 4540 stats->pkt_cnt_non_legacy >= stats->pkt_cnt_ofdm) 4541 return ewma_rssi_read(&stats->non_legacy_rssi_avg); 4542 else if (stats->pkt_cnt_ofdm >= stats->pkt_cnt_cck && 4543 stats->pkt_cnt_ofdm >= stats->pkt_cnt_non_legacy) 4544 return ewma_rssi_read(&stats->ofdm_rssi_avg); 4545 else 4546 return ewma_rssi_read(&stats->cck_rssi_avg); 4547 } 4548 4549 static u8 rtw89_phy_antdiv_sts_instance_get_evm(struct rtw89_antdiv_stats *stats) 4550 { 4551 return phy_div(stats->evm, stats->pkt_cnt_non_legacy + stats->pkt_cnt_ofdm); 4552 } 4553 4554 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev, 4555 struct rtw89_rx_phy_ppdu *phy_ppdu) 4556 { 4557 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4558 struct rtw89_hal *hal = &rtwdev->hal; 4559 4560 if (!hal->ant_diversity || hal->ant_diversity_fixed) 4561 return; 4562 4563 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->target_stats); 4564 4565 if (!antdiv->get_stats) 4566 return; 4567 4568 if (hal->antenna_rx == RF_A) 4569 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->main_stats); 4570 else if (hal->antenna_rx == RF_B) 4571 rtw89_phy_antdiv_sts_instance_add(rtwdev, phy_ppdu, &antdiv->aux_stats); 4572 } 4573 4574 static void rtw89_phy_antdiv_reg_init(struct rtw89_dev *rtwdev) 4575 { 4576 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_ANT_TRAIN_EN, 4577 0x0, RTW89_PHY_0); 4578 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_TX_ANT_SEL, 4579 0x0, RTW89_PHY_0); 4580 4581 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_TRSW_TX_EXTEND, 4582 0x0, RTW89_PHY_0); 4583 rtw89_phy_write32_idx(rtwdev, R_P0_ANT_SW, B_P0_HW_ANTSW_DIS_BY_GNT_BT, 4584 0x0, RTW89_PHY_0); 4585 4586 rtw89_phy_write32_idx(rtwdev, R_P0_TRSW, B_P0_BT_FORCE_ANTIDX_EN, 4587 0x0, RTW89_PHY_0); 4588 4589 rtw89_phy_write32_idx(rtwdev, R_RFSW_CTRL_ANT0_BASE, B_RFSW_CTRL_ANT_MAPPING, 4590 0x0100, RTW89_PHY_0); 4591 4592 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_BTG_TRX, 4593 0x1, RTW89_PHY_0); 4594 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_HW_CTRL, 4595 0x0, RTW89_PHY_0); 4596 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_2G, 4597 0x0, RTW89_PHY_0); 4598 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_SW_5G, 4599 0x0, RTW89_PHY_0); 4600 } 4601 4602 static void rtw89_phy_antdiv_sts_reset(struct rtw89_dev *rtwdev) 4603 { 4604 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4605 4606 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats); 4607 rtw89_phy_antdiv_sts_instance_reset(&antdiv->main_stats); 4608 rtw89_phy_antdiv_sts_instance_reset(&antdiv->aux_stats); 4609 } 4610 4611 static void rtw89_phy_antdiv_init(struct rtw89_dev *rtwdev) 4612 { 4613 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 4614 struct rtw89_hal *hal = &rtwdev->hal; 4615 4616 if (!hal->ant_diversity) 4617 return; 4618 4619 antdiv->get_stats = false; 4620 antdiv->rssi_pre = 0; 4621 rtw89_phy_antdiv_sts_reset(rtwdev); 4622 rtw89_phy_antdiv_reg_init(rtwdev); 4623 } 4624 4625 static void rtw89_phy_stat_thermal_update(struct rtw89_dev *rtwdev) 4626 { 4627 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 4628 int i; 4629 u8 th; 4630 4631 for (i = 0; i < rtwdev->chip->rf_path_num; i++) { 4632 th = rtw89_chip_get_thermal(rtwdev, i); 4633 if (th) 4634 ewma_thermal_add(&phystat->avg_thermal[i], th); 4635 4636 rtw89_debug(rtwdev, RTW89_DBG_RFK_TRACK, 4637 "path(%d) thermal cur=%u avg=%ld", i, th, 4638 ewma_thermal_read(&phystat->avg_thermal[i])); 4639 } 4640 } 4641 4642 struct rtw89_phy_iter_rssi_data { 4643 struct rtw89_dev *rtwdev; 4644 struct rtw89_phy_ch_info *ch_info; 4645 bool rssi_changed; 4646 }; 4647 4648 static void rtw89_phy_stat_rssi_update_iter(void *data, 4649 struct ieee80211_sta *sta) 4650 { 4651 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 4652 struct rtw89_phy_iter_rssi_data *rssi_data = 4653 (struct rtw89_phy_iter_rssi_data *)data; 4654 struct rtw89_phy_ch_info *ch_info = rssi_data->ch_info; 4655 unsigned long rssi_curr; 4656 4657 rssi_curr = ewma_rssi_read(&rtwsta->avg_rssi); 4658 4659 if (rssi_curr < ch_info->rssi_min) { 4660 ch_info->rssi_min = rssi_curr; 4661 ch_info->rssi_min_macid = rtwsta->mac_id; 4662 } 4663 4664 if (rtwsta->prev_rssi == 0) { 4665 rtwsta->prev_rssi = rssi_curr; 4666 } else if (abs((int)rtwsta->prev_rssi - (int)rssi_curr) > (3 << RSSI_FACTOR)) { 4667 rtwsta->prev_rssi = rssi_curr; 4668 rssi_data->rssi_changed = true; 4669 } 4670 } 4671 4672 static void rtw89_phy_stat_rssi_update(struct rtw89_dev *rtwdev) 4673 { 4674 struct rtw89_phy_iter_rssi_data rssi_data = {0}; 4675 4676 rssi_data.rtwdev = rtwdev; 4677 rssi_data.ch_info = &rtwdev->ch_info; 4678 rssi_data.ch_info->rssi_min = U8_MAX; 4679 ieee80211_iterate_stations_atomic(rtwdev->hw, 4680 rtw89_phy_stat_rssi_update_iter, 4681 &rssi_data); 4682 if (rssi_data.rssi_changed) 4683 rtw89_btc_ntfy_wl_sta(rtwdev); 4684 } 4685 4686 static void rtw89_phy_stat_init(struct rtw89_dev *rtwdev) 4687 { 4688 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 4689 int i; 4690 4691 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 4692 ewma_thermal_init(&phystat->avg_thermal[i]); 4693 4694 rtw89_phy_stat_thermal_update(rtwdev); 4695 4696 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 4697 memset(&phystat->last_pkt_stat, 0, sizeof(phystat->last_pkt_stat)); 4698 } 4699 4700 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev) 4701 { 4702 struct rtw89_phy_stat *phystat = &rtwdev->phystat; 4703 4704 rtw89_phy_stat_thermal_update(rtwdev); 4705 rtw89_phy_stat_rssi_update(rtwdev); 4706 4707 phystat->last_pkt_stat = phystat->cur_pkt_stat; 4708 memset(&phystat->cur_pkt_stat, 0, sizeof(phystat->cur_pkt_stat)); 4709 } 4710 4711 static u16 rtw89_phy_ccx_us_to_idx(struct rtw89_dev *rtwdev, u32 time_us) 4712 { 4713 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4714 4715 return time_us >> (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 4716 } 4717 4718 static u32 rtw89_phy_ccx_idx_to_us(struct rtw89_dev *rtwdev, u16 idx) 4719 { 4720 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4721 4722 return idx << (ilog2(CCX_US_BASE_RATIO) + env->ccx_unit_idx); 4723 } 4724 4725 static void rtw89_phy_ccx_top_setting_init(struct rtw89_dev *rtwdev) 4726 { 4727 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 4728 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4729 const struct rtw89_ccx_regs *ccx = phy->ccx; 4730 4731 env->ccx_manual_ctrl = false; 4732 env->ccx_ongoing = false; 4733 env->ccx_rac_lv = RTW89_RAC_RELEASE; 4734 env->ccx_period = 0; 4735 env->ccx_unit_idx = RTW89_CCX_32_US; 4736 4737 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->en_mask, 1); 4738 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->trig_opt_mask, 1); 4739 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1); 4740 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->edcca_opt_mask, 4741 RTW89_CCX_EDCCA_BW20_0); 4742 } 4743 4744 static u16 rtw89_phy_ccx_get_report(struct rtw89_dev *rtwdev, u16 report, 4745 u16 score) 4746 { 4747 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4748 u32 numer = 0; 4749 u16 ret = 0; 4750 4751 numer = report * score + (env->ccx_period >> 1); 4752 if (env->ccx_period) 4753 ret = numer / env->ccx_period; 4754 4755 return ret >= score ? score - 1 : ret; 4756 } 4757 4758 static void rtw89_phy_ccx_ms_to_period_unit(struct rtw89_dev *rtwdev, 4759 u16 time_ms, u32 *period, 4760 u32 *unit_idx) 4761 { 4762 u32 idx; 4763 u8 quotient; 4764 4765 if (time_ms >= CCX_MAX_PERIOD) 4766 time_ms = CCX_MAX_PERIOD; 4767 4768 quotient = CCX_MAX_PERIOD_UNIT * time_ms / CCX_MAX_PERIOD; 4769 4770 if (quotient < 4) 4771 idx = RTW89_CCX_4_US; 4772 else if (quotient < 8) 4773 idx = RTW89_CCX_8_US; 4774 else if (quotient < 16) 4775 idx = RTW89_CCX_16_US; 4776 else 4777 idx = RTW89_CCX_32_US; 4778 4779 *unit_idx = idx; 4780 *period = (time_ms * MS_TO_4US_RATIO) >> idx; 4781 4782 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4783 "[Trigger Time] period:%d, unit_idx:%d\n", 4784 *period, *unit_idx); 4785 } 4786 4787 static void rtw89_phy_ccx_racing_release(struct rtw89_dev *rtwdev) 4788 { 4789 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4790 4791 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4792 "lv:(%d)->(0)\n", env->ccx_rac_lv); 4793 4794 env->ccx_ongoing = false; 4795 env->ccx_rac_lv = RTW89_RAC_RELEASE; 4796 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 4797 } 4798 4799 static bool rtw89_phy_ifs_clm_th_update_check(struct rtw89_dev *rtwdev, 4800 struct rtw89_ccx_para_info *para) 4801 { 4802 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4803 bool is_update = env->ifs_clm_app != para->ifs_clm_app; 4804 u8 i = 0; 4805 u16 *ifs_th_l = env->ifs_clm_th_l; 4806 u16 *ifs_th_h = env->ifs_clm_th_h; 4807 u32 ifs_th0_us = 0, ifs_th_times = 0; 4808 u32 ifs_th_h_us[RTW89_IFS_CLM_NUM] = {0}; 4809 4810 if (!is_update) 4811 goto ifs_update_finished; 4812 4813 switch (para->ifs_clm_app) { 4814 case RTW89_IFS_CLM_INIT: 4815 case RTW89_IFS_CLM_BACKGROUND: 4816 case RTW89_IFS_CLM_ACS: 4817 case RTW89_IFS_CLM_DBG: 4818 case RTW89_IFS_CLM_DIG: 4819 case RTW89_IFS_CLM_TDMA_DIG: 4820 ifs_th0_us = IFS_CLM_TH0_UPPER; 4821 ifs_th_times = IFS_CLM_TH_MUL; 4822 break; 4823 case RTW89_IFS_CLM_DBG_MANUAL: 4824 ifs_th0_us = para->ifs_clm_manual_th0; 4825 ifs_th_times = para->ifs_clm_manual_th_times; 4826 break; 4827 default: 4828 break; 4829 } 4830 4831 /* Set sampling threshold for 4 different regions, unit in idx_cnt. 4832 * low[i] = high[i-1] + 1 4833 * high[i] = high[i-1] * ifs_th_times 4834 */ 4835 ifs_th_l[IFS_CLM_TH_START_IDX] = 0; 4836 ifs_th_h_us[IFS_CLM_TH_START_IDX] = ifs_th0_us; 4837 ifs_th_h[IFS_CLM_TH_START_IDX] = rtw89_phy_ccx_us_to_idx(rtwdev, 4838 ifs_th0_us); 4839 for (i = 1; i < RTW89_IFS_CLM_NUM; i++) { 4840 ifs_th_l[i] = ifs_th_h[i - 1] + 1; 4841 ifs_th_h_us[i] = ifs_th_h_us[i - 1] * ifs_th_times; 4842 ifs_th_h[i] = rtw89_phy_ccx_us_to_idx(rtwdev, ifs_th_h_us[i]); 4843 } 4844 4845 ifs_update_finished: 4846 if (!is_update) 4847 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4848 "No need to update IFS_TH\n"); 4849 4850 return is_update; 4851 } 4852 4853 static void rtw89_phy_ifs_clm_set_th_reg(struct rtw89_dev *rtwdev) 4854 { 4855 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 4856 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4857 const struct rtw89_ccx_regs *ccx = phy->ccx; 4858 u8 i = 0; 4859 4860 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_l_mask, 4861 env->ifs_clm_th_l[0]); 4862 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_l_mask, 4863 env->ifs_clm_th_l[1]); 4864 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_l_mask, 4865 env->ifs_clm_th_l[2]); 4866 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_l_mask, 4867 env->ifs_clm_th_l[3]); 4868 4869 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_th_h_mask, 4870 env->ifs_clm_th_h[0]); 4871 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_th_h_mask, 4872 env->ifs_clm_th_h[1]); 4873 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_th_h_mask, 4874 env->ifs_clm_th_h[2]); 4875 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_th_h_mask, 4876 env->ifs_clm_th_h[3]); 4877 4878 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 4879 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4880 "Update IFS_T%d_th{low, high} : {%d, %d}\n", 4881 i + 1, env->ifs_clm_th_l[i], env->ifs_clm_th_h[i]); 4882 } 4883 4884 static void rtw89_phy_ifs_clm_setting_init(struct rtw89_dev *rtwdev) 4885 { 4886 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 4887 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4888 const struct rtw89_ccx_regs *ccx = phy->ccx; 4889 struct rtw89_ccx_para_info para = {0}; 4890 4891 env->ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 4892 env->ifs_clm_mntr_time = 0; 4893 4894 para.ifs_clm_app = RTW89_IFS_CLM_INIT; 4895 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, ¶)) 4896 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 4897 4898 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_collect_en_mask, true); 4899 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t1_addr, ccx->ifs_t1_en_mask, true); 4900 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t2_addr, ccx->ifs_t2_en_mask, true); 4901 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t3_addr, ccx->ifs_t3_en_mask, true); 4902 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_t4_addr, ccx->ifs_t4_en_mask, true); 4903 } 4904 4905 static int rtw89_phy_ccx_racing_ctrl(struct rtw89_dev *rtwdev, 4906 enum rtw89_env_racing_lv level) 4907 { 4908 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4909 int ret = 0; 4910 4911 if (level >= RTW89_RAC_MAX_NUM) { 4912 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4913 "[WARNING] Wrong LV=%d\n", level); 4914 return -EINVAL; 4915 } 4916 4917 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4918 "ccx_ongoing=%d, level:(%d)->(%d)\n", env->ccx_ongoing, 4919 env->ccx_rac_lv, level); 4920 4921 if (env->ccx_ongoing) { 4922 if (level <= env->ccx_rac_lv) 4923 ret = -EINVAL; 4924 else 4925 env->ccx_ongoing = false; 4926 } 4927 4928 if (ret == 0) 4929 env->ccx_rac_lv = level; 4930 4931 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "ccx racing success=%d\n", 4932 !ret); 4933 4934 return ret; 4935 } 4936 4937 static void rtw89_phy_ccx_trigger(struct rtw89_dev *rtwdev) 4938 { 4939 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 4940 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4941 const struct rtw89_ccx_regs *ccx = phy->ccx; 4942 4943 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 0); 4944 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 0); 4945 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, ccx->ifs_clm_cnt_clear_mask, 1); 4946 rtw89_phy_set_phy_regs(rtwdev, ccx->setting_addr, ccx->measurement_trig_mask, 1); 4947 4948 env->ccx_ongoing = true; 4949 } 4950 4951 static void rtw89_phy_ifs_clm_get_utility(struct rtw89_dev *rtwdev) 4952 { 4953 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 4954 u8 i = 0; 4955 u32 res = 0; 4956 4957 env->ifs_clm_tx_ratio = 4958 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_tx, PERCENT); 4959 env->ifs_clm_edcca_excl_cca_ratio = 4960 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_edcca_excl_cca, 4961 PERCENT); 4962 env->ifs_clm_cck_fa_ratio = 4963 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERCENT); 4964 env->ifs_clm_ofdm_fa_ratio = 4965 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERCENT); 4966 env->ifs_clm_cck_cca_excl_fa_ratio = 4967 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckcca_excl_fa, 4968 PERCENT); 4969 env->ifs_clm_ofdm_cca_excl_fa_ratio = 4970 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmcca_excl_fa, 4971 PERCENT); 4972 env->ifs_clm_cck_fa_permil = 4973 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_cckfa, PERMIL); 4974 env->ifs_clm_ofdm_fa_permil = 4975 rtw89_phy_ccx_get_report(rtwdev, env->ifs_clm_ofdmfa, PERMIL); 4976 4977 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) { 4978 if (env->ifs_clm_his[i] > ENV_MNTR_IFSCLM_HIS_MAX) { 4979 env->ifs_clm_ifs_avg[i] = ENV_MNTR_FAIL_DWORD; 4980 } else { 4981 env->ifs_clm_ifs_avg[i] = 4982 rtw89_phy_ccx_idx_to_us(rtwdev, 4983 env->ifs_clm_avg[i]); 4984 } 4985 4986 res = rtw89_phy_ccx_idx_to_us(rtwdev, env->ifs_clm_cca[i]); 4987 res += env->ifs_clm_his[i] >> 1; 4988 if (env->ifs_clm_his[i]) 4989 res /= env->ifs_clm_his[i]; 4990 else 4991 res = 0; 4992 env->ifs_clm_cca_avg[i] = res; 4993 } 4994 4995 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4996 "IFS-CLM ratio {Tx, EDCCA_exclu_cca} = {%d, %d}\n", 4997 env->ifs_clm_tx_ratio, env->ifs_clm_edcca_excl_cca_ratio); 4998 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 4999 "IFS-CLM FA ratio {CCK, OFDM} = {%d, %d}\n", 5000 env->ifs_clm_cck_fa_ratio, env->ifs_clm_ofdm_fa_ratio); 5001 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5002 "IFS-CLM FA permil {CCK, OFDM} = {%d, %d}\n", 5003 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil); 5004 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5005 "IFS-CLM CCA_exclu_FA ratio {CCK, OFDM} = {%d, %d}\n", 5006 env->ifs_clm_cck_cca_excl_fa_ratio, 5007 env->ifs_clm_ofdm_cca_excl_fa_ratio); 5008 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5009 "Time:[his, ifs_avg(us), cca_avg(us)]\n"); 5010 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 5011 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "T%d:[%d, %d, %d]\n", 5012 i + 1, env->ifs_clm_his[i], env->ifs_clm_ifs_avg[i], 5013 env->ifs_clm_cca_avg[i]); 5014 } 5015 5016 static bool rtw89_phy_ifs_clm_get_result(struct rtw89_dev *rtwdev) 5017 { 5018 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5019 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 5020 const struct rtw89_ccx_regs *ccx = phy->ccx; 5021 u8 i = 0; 5022 5023 if (rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr, 5024 ccx->ifs_cnt_done_mask) == 0) { 5025 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5026 "Get IFS_CLM report Fail\n"); 5027 return false; 5028 } 5029 5030 env->ifs_clm_tx = 5031 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr, 5032 ccx->ifs_clm_tx_cnt_msk); 5033 env->ifs_clm_edcca_excl_cca = 5034 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_tx_cnt_addr, 5035 ccx->ifs_clm_edcca_excl_cca_fa_mask); 5036 env->ifs_clm_cckcca_excl_fa = 5037 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr, 5038 ccx->ifs_clm_cckcca_excl_fa_mask); 5039 env->ifs_clm_ofdmcca_excl_fa = 5040 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_cca_addr, 5041 ccx->ifs_clm_ofdmcca_excl_fa_mask); 5042 env->ifs_clm_cckfa = 5043 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr, 5044 ccx->ifs_clm_cck_fa_mask); 5045 env->ifs_clm_ofdmfa = 5046 rtw89_phy_read32_mask(rtwdev, ccx->ifs_clm_fa_addr, 5047 ccx->ifs_clm_ofdm_fa_mask); 5048 5049 env->ifs_clm_his[0] = 5050 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, 5051 ccx->ifs_t1_his_mask); 5052 env->ifs_clm_his[1] = 5053 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, 5054 ccx->ifs_t2_his_mask); 5055 env->ifs_clm_his[2] = 5056 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, 5057 ccx->ifs_t3_his_mask); 5058 env->ifs_clm_his[3] = 5059 rtw89_phy_read32_mask(rtwdev, ccx->ifs_his_addr, 5060 ccx->ifs_t4_his_mask); 5061 5062 env->ifs_clm_avg[0] = 5063 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr, 5064 ccx->ifs_t1_avg_mask); 5065 env->ifs_clm_avg[1] = 5066 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_l_addr, 5067 ccx->ifs_t2_avg_mask); 5068 env->ifs_clm_avg[2] = 5069 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr, 5070 ccx->ifs_t3_avg_mask); 5071 env->ifs_clm_avg[3] = 5072 rtw89_phy_read32_mask(rtwdev, ccx->ifs_avg_h_addr, 5073 ccx->ifs_t4_avg_mask); 5074 5075 env->ifs_clm_cca[0] = 5076 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr, 5077 ccx->ifs_t1_cca_mask); 5078 env->ifs_clm_cca[1] = 5079 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_l_addr, 5080 ccx->ifs_t2_cca_mask); 5081 env->ifs_clm_cca[2] = 5082 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr, 5083 ccx->ifs_t3_cca_mask); 5084 env->ifs_clm_cca[3] = 5085 rtw89_phy_read32_mask(rtwdev, ccx->ifs_cca_h_addr, 5086 ccx->ifs_t4_cca_mask); 5087 5088 env->ifs_clm_total_ifs = 5089 rtw89_phy_read32_mask(rtwdev, ccx->ifs_total_addr, 5090 ccx->ifs_total_mask); 5091 5092 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "IFS-CLM total_ifs = %d\n", 5093 env->ifs_clm_total_ifs); 5094 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5095 "{Tx, EDCCA_exclu_cca} = {%d, %d}\n", 5096 env->ifs_clm_tx, env->ifs_clm_edcca_excl_cca); 5097 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5098 "IFS-CLM FA{CCK, OFDM} = {%d, %d}\n", 5099 env->ifs_clm_cckfa, env->ifs_clm_ofdmfa); 5100 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5101 "IFS-CLM CCA_exclu_FA{CCK, OFDM} = {%d, %d}\n", 5102 env->ifs_clm_cckcca_excl_fa, env->ifs_clm_ofdmcca_excl_fa); 5103 5104 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, "Time:[his, avg, cca]\n"); 5105 for (i = 0; i < RTW89_IFS_CLM_NUM; i++) 5106 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5107 "T%d:[%d, %d, %d]\n", i + 1, env->ifs_clm_his[i], 5108 env->ifs_clm_avg[i], env->ifs_clm_cca[i]); 5109 5110 rtw89_phy_ifs_clm_get_utility(rtwdev); 5111 5112 return true; 5113 } 5114 5115 static int rtw89_phy_ifs_clm_set(struct rtw89_dev *rtwdev, 5116 struct rtw89_ccx_para_info *para) 5117 { 5118 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5119 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 5120 const struct rtw89_ccx_regs *ccx = phy->ccx; 5121 u32 period = 0; 5122 u32 unit_idx = 0; 5123 5124 if (para->mntr_time == 0) { 5125 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5126 "[WARN] MNTR_TIME is 0\n"); 5127 return -EINVAL; 5128 } 5129 5130 if (rtw89_phy_ccx_racing_ctrl(rtwdev, para->rac_lv)) 5131 return -EINVAL; 5132 5133 if (para->mntr_time != env->ifs_clm_mntr_time) { 5134 rtw89_phy_ccx_ms_to_period_unit(rtwdev, para->mntr_time, 5135 &period, &unit_idx); 5136 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, 5137 ccx->ifs_clm_period_mask, period); 5138 rtw89_phy_set_phy_regs(rtwdev, ccx->ifs_cnt_addr, 5139 ccx->ifs_clm_cnt_unit_mask, 5140 unit_idx); 5141 5142 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5143 "Update IFS-CLM time ((%d)) -> ((%d))\n", 5144 env->ifs_clm_mntr_time, para->mntr_time); 5145 5146 env->ifs_clm_mntr_time = para->mntr_time; 5147 env->ccx_period = (u16)period; 5148 env->ccx_unit_idx = (u8)unit_idx; 5149 } 5150 5151 if (rtw89_phy_ifs_clm_th_update_check(rtwdev, para)) { 5152 env->ifs_clm_app = para->ifs_clm_app; 5153 rtw89_phy_ifs_clm_set_th_reg(rtwdev); 5154 } 5155 5156 return 0; 5157 } 5158 5159 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev) 5160 { 5161 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 5162 struct rtw89_ccx_para_info para = {0}; 5163 u8 chk_result = RTW89_PHY_ENV_MON_CCX_FAIL; 5164 5165 env->ccx_watchdog_result = RTW89_PHY_ENV_MON_CCX_FAIL; 5166 if (env->ccx_manual_ctrl) { 5167 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5168 "CCX in manual ctrl\n"); 5169 return; 5170 } 5171 5172 /* only ifs_clm for now */ 5173 if (rtw89_phy_ifs_clm_get_result(rtwdev)) 5174 env->ccx_watchdog_result |= RTW89_PHY_ENV_MON_IFS_CLM; 5175 5176 rtw89_phy_ccx_racing_release(rtwdev); 5177 para.mntr_time = 1900; 5178 para.rac_lv = RTW89_RAC_LV_1; 5179 para.ifs_clm_app = RTW89_IFS_CLM_BACKGROUND; 5180 5181 if (rtw89_phy_ifs_clm_set(rtwdev, ¶) == 0) 5182 chk_result |= RTW89_PHY_ENV_MON_IFS_CLM; 5183 if (chk_result) 5184 rtw89_phy_ccx_trigger(rtwdev); 5185 5186 rtw89_debug(rtwdev, RTW89_DBG_PHY_TRACK, 5187 "get_result=0x%x, chk_result:0x%x\n", 5188 env->ccx_watchdog_result, chk_result); 5189 } 5190 5191 static bool rtw89_physts_ie_page_valid(enum rtw89_phy_status_bitmap *ie_page) 5192 { 5193 if (*ie_page >= RTW89_PHYSTS_BITMAP_NUM || 5194 *ie_page == RTW89_RSVD_9) 5195 return false; 5196 else if (*ie_page > RTW89_RSVD_9) 5197 *ie_page -= 1; 5198 5199 return true; 5200 } 5201 5202 static u32 rtw89_phy_get_ie_bitmap_addr(enum rtw89_phy_status_bitmap ie_page) 5203 { 5204 static const u8 ie_page_shift = 2; 5205 5206 return R_PHY_STS_BITMAP_ADDR_START + (ie_page << ie_page_shift); 5207 } 5208 5209 static u32 rtw89_physts_get_ie_bitmap(struct rtw89_dev *rtwdev, 5210 enum rtw89_phy_status_bitmap ie_page) 5211 { 5212 u32 addr; 5213 5214 if (!rtw89_physts_ie_page_valid(&ie_page)) 5215 return 0; 5216 5217 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 5218 5219 return rtw89_phy_read32(rtwdev, addr); 5220 } 5221 5222 static void rtw89_physts_set_ie_bitmap(struct rtw89_dev *rtwdev, 5223 enum rtw89_phy_status_bitmap ie_page, 5224 u32 val) 5225 { 5226 const struct rtw89_chip_info *chip = rtwdev->chip; 5227 u32 addr; 5228 5229 if (!rtw89_physts_ie_page_valid(&ie_page)) 5230 return; 5231 5232 if (chip->chip_id == RTL8852A) 5233 val &= B_PHY_STS_BITMAP_MSK_52A; 5234 5235 addr = rtw89_phy_get_ie_bitmap_addr(ie_page); 5236 rtw89_phy_write32(rtwdev, addr, val); 5237 } 5238 5239 static void rtw89_physts_enable_ie_bitmap(struct rtw89_dev *rtwdev, 5240 enum rtw89_phy_status_bitmap bitmap, 5241 enum rtw89_phy_status_ie_type ie, 5242 bool enable) 5243 { 5244 u32 val = rtw89_physts_get_ie_bitmap(rtwdev, bitmap); 5245 5246 if (enable) 5247 val |= BIT(ie); 5248 else 5249 val &= ~BIT(ie); 5250 5251 rtw89_physts_set_ie_bitmap(rtwdev, bitmap, val); 5252 } 5253 5254 static void rtw89_physts_enable_fail_report(struct rtw89_dev *rtwdev, 5255 bool enable, 5256 enum rtw89_phy_idx phy_idx) 5257 { 5258 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; 5259 const struct rtw89_physts_regs *physts = phy->physts; 5260 5261 if (enable) { 5262 rtw89_phy_write32_clr(rtwdev, physts->setting_addr, 5263 physts->dis_trigger_fail_mask); 5264 rtw89_phy_write32_clr(rtwdev, physts->setting_addr, 5265 physts->dis_trigger_brk_mask); 5266 } else { 5267 rtw89_phy_write32_set(rtwdev, physts->setting_addr, 5268 physts->dis_trigger_fail_mask); 5269 rtw89_phy_write32_set(rtwdev, physts->setting_addr, 5270 physts->dis_trigger_brk_mask); 5271 } 5272 } 5273 5274 static void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev) 5275 { 5276 u8 i; 5277 5278 rtw89_physts_enable_fail_report(rtwdev, false, RTW89_PHY_0); 5279 5280 for (i = 0; i < RTW89_PHYSTS_BITMAP_NUM; i++) { 5281 if (i >= RTW89_CCK_PKT) 5282 rtw89_physts_enable_ie_bitmap(rtwdev, i, 5283 RTW89_PHYSTS_IE09_FTR_0, 5284 true); 5285 if ((i >= RTW89_CCK_BRK && i <= RTW89_VHT_MU) || 5286 (i >= RTW89_RSVD_9 && i <= RTW89_CCK_PKT)) 5287 continue; 5288 rtw89_physts_enable_ie_bitmap(rtwdev, i, 5289 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A, 5290 true); 5291 } 5292 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_VHT_PKT, 5293 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 5294 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_HE_PKT, 5295 RTW89_PHYSTS_IE13_DL_MU_DEF, true); 5296 5297 /* force IE01 for channel index, only channel field is valid */ 5298 rtw89_physts_enable_ie_bitmap(rtwdev, RTW89_CCK_PKT, 5299 RTW89_PHYSTS_IE01_CMN_OFDM, true); 5300 } 5301 5302 static void rtw89_phy_dig_read_gain_table(struct rtw89_dev *rtwdev, int type) 5303 { 5304 const struct rtw89_chip_info *chip = rtwdev->chip; 5305 struct rtw89_dig_info *dig = &rtwdev->dig; 5306 const struct rtw89_phy_dig_gain_cfg *cfg; 5307 const char *msg; 5308 u8 i; 5309 s8 gain_base; 5310 s8 *gain_arr; 5311 u32 tmp; 5312 5313 switch (type) { 5314 case RTW89_DIG_GAIN_LNA_G: 5315 gain_arr = dig->lna_gain_g; 5316 gain_base = LNA0_GAIN; 5317 cfg = chip->dig_table->cfg_lna_g; 5318 msg = "lna_gain_g"; 5319 break; 5320 case RTW89_DIG_GAIN_TIA_G: 5321 gain_arr = dig->tia_gain_g; 5322 gain_base = TIA0_GAIN_G; 5323 cfg = chip->dig_table->cfg_tia_g; 5324 msg = "tia_gain_g"; 5325 break; 5326 case RTW89_DIG_GAIN_LNA_A: 5327 gain_arr = dig->lna_gain_a; 5328 gain_base = LNA0_GAIN; 5329 cfg = chip->dig_table->cfg_lna_a; 5330 msg = "lna_gain_a"; 5331 break; 5332 case RTW89_DIG_GAIN_TIA_A: 5333 gain_arr = dig->tia_gain_a; 5334 gain_base = TIA0_GAIN_A; 5335 cfg = chip->dig_table->cfg_tia_a; 5336 msg = "tia_gain_a"; 5337 break; 5338 default: 5339 return; 5340 } 5341 5342 for (i = 0; i < cfg->size; i++) { 5343 tmp = rtw89_phy_read32_mask(rtwdev, cfg->table[i].addr, 5344 cfg->table[i].mask); 5345 tmp >>= DIG_GAIN_SHIFT; 5346 gain_arr[i] = sign_extend32(tmp, U4_MAX_BIT) + gain_base; 5347 gain_base += DIG_GAIN; 5348 5349 rtw89_debug(rtwdev, RTW89_DBG_DIG, "%s[%d]=%d\n", 5350 msg, i, gain_arr[i]); 5351 } 5352 } 5353 5354 static void rtw89_phy_dig_update_gain_para(struct rtw89_dev *rtwdev) 5355 { 5356 struct rtw89_dig_info *dig = &rtwdev->dig; 5357 u32 tmp; 5358 u8 i; 5359 5360 if (!rtwdev->hal.support_igi) 5361 return; 5362 5363 tmp = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PKPW, 5364 B_PATH0_IB_PKPW_MSK); 5365 dig->ib_pkpwr = sign_extend32(tmp >> DIG_GAIN_SHIFT, U8_MAX_BIT); 5366 dig->ib_pbk = rtw89_phy_read32_mask(rtwdev, R_PATH0_IB_PBK, 5367 B_PATH0_IB_PBK_MSK); 5368 rtw89_debug(rtwdev, RTW89_DBG_DIG, "ib_pkpwr=%d, ib_pbk=%d\n", 5369 dig->ib_pkpwr, dig->ib_pbk); 5370 5371 for (i = RTW89_DIG_GAIN_LNA_G; i < RTW89_DIG_GAIN_MAX; i++) 5372 rtw89_phy_dig_read_gain_table(rtwdev, i); 5373 } 5374 5375 static const u8 rssi_nolink = 22; 5376 static const u8 igi_rssi_th[IGI_RSSI_TH_NUM] = {68, 84, 90, 98, 104}; 5377 static const u16 fa_th_2g[FA_TH_NUM] = {22, 44, 66, 88}; 5378 static const u16 fa_th_5g[FA_TH_NUM] = {4, 8, 12, 16}; 5379 static const u16 fa_th_nolink[FA_TH_NUM] = {196, 352, 440, 528}; 5380 5381 static void rtw89_phy_dig_update_rssi_info(struct rtw89_dev *rtwdev) 5382 { 5383 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; 5384 struct rtw89_dig_info *dig = &rtwdev->dig; 5385 bool is_linked = rtwdev->total_sta_assoc > 0; 5386 5387 if (is_linked) { 5388 dig->igi_rssi = ch_info->rssi_min >> 1; 5389 } else { 5390 rtw89_debug(rtwdev, RTW89_DBG_DIG, "RSSI update : NO Link\n"); 5391 dig->igi_rssi = rssi_nolink; 5392 } 5393 } 5394 5395 static void rtw89_phy_dig_update_para(struct rtw89_dev *rtwdev) 5396 { 5397 struct rtw89_dig_info *dig = &rtwdev->dig; 5398 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 5399 bool is_linked = rtwdev->total_sta_assoc > 0; 5400 const u16 *fa_th_src = NULL; 5401 5402 switch (chan->band_type) { 5403 case RTW89_BAND_2G: 5404 dig->lna_gain = dig->lna_gain_g; 5405 dig->tia_gain = dig->tia_gain_g; 5406 fa_th_src = is_linked ? fa_th_2g : fa_th_nolink; 5407 dig->force_gaincode_idx_en = false; 5408 dig->dyn_pd_th_en = true; 5409 break; 5410 case RTW89_BAND_5G: 5411 default: 5412 dig->lna_gain = dig->lna_gain_a; 5413 dig->tia_gain = dig->tia_gain_a; 5414 fa_th_src = is_linked ? fa_th_5g : fa_th_nolink; 5415 dig->force_gaincode_idx_en = true; 5416 dig->dyn_pd_th_en = true; 5417 break; 5418 } 5419 memcpy(dig->fa_th, fa_th_src, sizeof(dig->fa_th)); 5420 memcpy(dig->igi_rssi_th, igi_rssi_th, sizeof(dig->igi_rssi_th)); 5421 } 5422 5423 static const u8 pd_low_th_offset = 20, dynamic_igi_min = 0x20; 5424 static const u8 igi_max_performance_mode = 0x5a; 5425 static const u8 dynamic_pd_threshold_max; 5426 5427 static void rtw89_phy_dig_para_reset(struct rtw89_dev *rtwdev) 5428 { 5429 struct rtw89_dig_info *dig = &rtwdev->dig; 5430 5431 dig->cur_gaincode.lna_idx = LNA_IDX_MAX; 5432 dig->cur_gaincode.tia_idx = TIA_IDX_MAX; 5433 dig->cur_gaincode.rxb_idx = RXB_IDX_MAX; 5434 dig->force_gaincode.lna_idx = LNA_IDX_MAX; 5435 dig->force_gaincode.tia_idx = TIA_IDX_MAX; 5436 dig->force_gaincode.rxb_idx = RXB_IDX_MAX; 5437 5438 dig->dyn_igi_max = igi_max_performance_mode; 5439 dig->dyn_igi_min = dynamic_igi_min; 5440 dig->dyn_pd_th_max = dynamic_pd_threshold_max; 5441 dig->pd_low_th_ofst = pd_low_th_offset; 5442 dig->is_linked_pre = false; 5443 } 5444 5445 static void rtw89_phy_dig_init(struct rtw89_dev *rtwdev) 5446 { 5447 rtw89_phy_dig_update_gain_para(rtwdev); 5448 rtw89_phy_dig_reset(rtwdev); 5449 } 5450 5451 static u8 rtw89_phy_dig_lna_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 5452 { 5453 struct rtw89_dig_info *dig = &rtwdev->dig; 5454 u8 lna_idx; 5455 5456 if (rssi < dig->igi_rssi_th[0]) 5457 lna_idx = RTW89_DIG_GAIN_LNA_IDX6; 5458 else if (rssi < dig->igi_rssi_th[1]) 5459 lna_idx = RTW89_DIG_GAIN_LNA_IDX5; 5460 else if (rssi < dig->igi_rssi_th[2]) 5461 lna_idx = RTW89_DIG_GAIN_LNA_IDX4; 5462 else if (rssi < dig->igi_rssi_th[3]) 5463 lna_idx = RTW89_DIG_GAIN_LNA_IDX3; 5464 else if (rssi < dig->igi_rssi_th[4]) 5465 lna_idx = RTW89_DIG_GAIN_LNA_IDX2; 5466 else 5467 lna_idx = RTW89_DIG_GAIN_LNA_IDX1; 5468 5469 return lna_idx; 5470 } 5471 5472 static u8 rtw89_phy_dig_tia_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi) 5473 { 5474 struct rtw89_dig_info *dig = &rtwdev->dig; 5475 u8 tia_idx; 5476 5477 if (rssi < dig->igi_rssi_th[0]) 5478 tia_idx = RTW89_DIG_GAIN_TIA_IDX1; 5479 else 5480 tia_idx = RTW89_DIG_GAIN_TIA_IDX0; 5481 5482 return tia_idx; 5483 } 5484 5485 #define IB_PBK_BASE 110 5486 #define WB_RSSI_BASE 10 5487 static u8 rtw89_phy_dig_rxb_idx_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 5488 struct rtw89_agc_gaincode_set *set) 5489 { 5490 struct rtw89_dig_info *dig = &rtwdev->dig; 5491 s8 lna_gain = dig->lna_gain[set->lna_idx]; 5492 s8 tia_gain = dig->tia_gain[set->tia_idx]; 5493 s32 wb_rssi = rssi + lna_gain + tia_gain; 5494 s32 rxb_idx_tmp = IB_PBK_BASE + WB_RSSI_BASE; 5495 u8 rxb_idx; 5496 5497 rxb_idx_tmp += dig->ib_pkpwr - dig->ib_pbk - wb_rssi; 5498 rxb_idx = clamp_t(s32, rxb_idx_tmp, RXB_IDX_MIN, RXB_IDX_MAX); 5499 5500 rtw89_debug(rtwdev, RTW89_DBG_DIG, "wb_rssi=%03d, rxb_idx_tmp=%03d\n", 5501 wb_rssi, rxb_idx_tmp); 5502 5503 return rxb_idx; 5504 } 5505 5506 static void rtw89_phy_dig_gaincode_by_rssi(struct rtw89_dev *rtwdev, u8 rssi, 5507 struct rtw89_agc_gaincode_set *set) 5508 { 5509 set->lna_idx = rtw89_phy_dig_lna_idx_by_rssi(rtwdev, rssi); 5510 set->tia_idx = rtw89_phy_dig_tia_idx_by_rssi(rtwdev, rssi); 5511 set->rxb_idx = rtw89_phy_dig_rxb_idx_by_rssi(rtwdev, rssi, set); 5512 5513 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5514 "final_rssi=%03d, (lna,tia,rab)=(%d,%d,%02d)\n", 5515 rssi, set->lna_idx, set->tia_idx, set->rxb_idx); 5516 } 5517 5518 #define IGI_OFFSET_MAX 25 5519 #define IGI_OFFSET_MUL 2 5520 static void rtw89_phy_dig_igi_offset_by_env(struct rtw89_dev *rtwdev) 5521 { 5522 struct rtw89_dig_info *dig = &rtwdev->dig; 5523 struct rtw89_env_monitor_info *env = &rtwdev->env_monitor; 5524 enum rtw89_dig_noisy_level noisy_lv; 5525 u8 igi_offset = dig->fa_rssi_ofst; 5526 u16 fa_ratio = 0; 5527 5528 fa_ratio = env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil; 5529 5530 if (fa_ratio < dig->fa_th[0]) 5531 noisy_lv = RTW89_DIG_NOISY_LEVEL0; 5532 else if (fa_ratio < dig->fa_th[1]) 5533 noisy_lv = RTW89_DIG_NOISY_LEVEL1; 5534 else if (fa_ratio < dig->fa_th[2]) 5535 noisy_lv = RTW89_DIG_NOISY_LEVEL2; 5536 else if (fa_ratio < dig->fa_th[3]) 5537 noisy_lv = RTW89_DIG_NOISY_LEVEL3; 5538 else 5539 noisy_lv = RTW89_DIG_NOISY_LEVEL_MAX; 5540 5541 if (noisy_lv == RTW89_DIG_NOISY_LEVEL0 && igi_offset < 2) 5542 igi_offset = 0; 5543 else 5544 igi_offset += noisy_lv * IGI_OFFSET_MUL; 5545 5546 igi_offset = min_t(u8, igi_offset, IGI_OFFSET_MAX); 5547 dig->fa_rssi_ofst = igi_offset; 5548 5549 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5550 "fa_th: [+6 (%d) +4 (%d) +2 (%d) 0 (%d) -2 ]\n", 5551 dig->fa_th[3], dig->fa_th[2], dig->fa_th[1], dig->fa_th[0]); 5552 5553 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5554 "fa(CCK,OFDM,ALL)=(%d,%d,%d)%%, noisy_lv=%d, ofst=%d\n", 5555 env->ifs_clm_cck_fa_permil, env->ifs_clm_ofdm_fa_permil, 5556 env->ifs_clm_cck_fa_permil + env->ifs_clm_ofdm_fa_permil, 5557 noisy_lv, igi_offset); 5558 } 5559 5560 static void rtw89_phy_dig_set_lna_idx(struct rtw89_dev *rtwdev, u8 lna_idx) 5561 { 5562 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 5563 5564 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_lna_init.addr, 5565 dig_regs->p0_lna_init.mask, lna_idx); 5566 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_lna_init.addr, 5567 dig_regs->p1_lna_init.mask, lna_idx); 5568 } 5569 5570 static void rtw89_phy_dig_set_tia_idx(struct rtw89_dev *rtwdev, u8 tia_idx) 5571 { 5572 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 5573 5574 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_tia_init.addr, 5575 dig_regs->p0_tia_init.mask, tia_idx); 5576 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_tia_init.addr, 5577 dig_regs->p1_tia_init.mask, tia_idx); 5578 } 5579 5580 static void rtw89_phy_dig_set_rxb_idx(struct rtw89_dev *rtwdev, u8 rxb_idx) 5581 { 5582 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 5583 5584 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_rxb_init.addr, 5585 dig_regs->p0_rxb_init.mask, rxb_idx); 5586 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_rxb_init.addr, 5587 dig_regs->p1_rxb_init.mask, rxb_idx); 5588 } 5589 5590 static void rtw89_phy_dig_set_igi_cr(struct rtw89_dev *rtwdev, 5591 const struct rtw89_agc_gaincode_set set) 5592 { 5593 if (!rtwdev->hal.support_igi) 5594 return; 5595 5596 rtw89_phy_dig_set_lna_idx(rtwdev, set.lna_idx); 5597 rtw89_phy_dig_set_tia_idx(rtwdev, set.tia_idx); 5598 rtw89_phy_dig_set_rxb_idx(rtwdev, set.rxb_idx); 5599 5600 rtw89_debug(rtwdev, RTW89_DBG_DIG, "Set (lna,tia,rxb)=((%d,%d,%02d))\n", 5601 set.lna_idx, set.tia_idx, set.rxb_idx); 5602 } 5603 5604 static void rtw89_phy_dig_sdagc_follow_pagc_config(struct rtw89_dev *rtwdev, 5605 bool enable) 5606 { 5607 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 5608 5609 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_p20_pagcugc_en.addr, 5610 dig_regs->p0_p20_pagcugc_en.mask, enable); 5611 rtw89_phy_write32_mask(rtwdev, dig_regs->p0_s20_pagcugc_en.addr, 5612 dig_regs->p0_s20_pagcugc_en.mask, enable); 5613 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_p20_pagcugc_en.addr, 5614 dig_regs->p1_p20_pagcugc_en.mask, enable); 5615 rtw89_phy_write32_mask(rtwdev, dig_regs->p1_s20_pagcugc_en.addr, 5616 dig_regs->p1_s20_pagcugc_en.mask, enable); 5617 5618 rtw89_debug(rtwdev, RTW89_DBG_DIG, "sdagc_follow_pagc=%d\n", enable); 5619 } 5620 5621 static void rtw89_phy_dig_config_igi(struct rtw89_dev *rtwdev) 5622 { 5623 struct rtw89_dig_info *dig = &rtwdev->dig; 5624 5625 if (!rtwdev->hal.support_igi) 5626 return; 5627 5628 if (dig->force_gaincode_idx_en) { 5629 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 5630 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5631 "Force gaincode index enabled.\n"); 5632 } else { 5633 rtw89_phy_dig_gaincode_by_rssi(rtwdev, dig->igi_fa_rssi, 5634 &dig->cur_gaincode); 5635 rtw89_phy_dig_set_igi_cr(rtwdev, dig->cur_gaincode); 5636 } 5637 } 5638 5639 static void rtw89_phy_dig_dyn_pd_th(struct rtw89_dev *rtwdev, u8 rssi, 5640 bool enable) 5641 { 5642 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 5643 const struct rtw89_dig_regs *dig_regs = rtwdev->chip->dig_regs; 5644 enum rtw89_bandwidth cbw = chan->band_width; 5645 struct rtw89_dig_info *dig = &rtwdev->dig; 5646 u8 final_rssi = 0, under_region = dig->pd_low_th_ofst; 5647 u8 ofdm_cca_th; 5648 s8 cck_cca_th; 5649 u32 pd_val = 0; 5650 5651 if (rtwdev->chip->chip_gen == RTW89_CHIP_AX) 5652 under_region += PD_TH_SB_FLTR_CMP_VAL; 5653 5654 switch (cbw) { 5655 case RTW89_CHANNEL_WIDTH_40: 5656 under_region += PD_TH_BW40_CMP_VAL; 5657 break; 5658 case RTW89_CHANNEL_WIDTH_80: 5659 under_region += PD_TH_BW80_CMP_VAL; 5660 break; 5661 case RTW89_CHANNEL_WIDTH_160: 5662 under_region += PD_TH_BW160_CMP_VAL; 5663 break; 5664 case RTW89_CHANNEL_WIDTH_20: 5665 fallthrough; 5666 default: 5667 under_region += PD_TH_BW20_CMP_VAL; 5668 break; 5669 } 5670 5671 dig->dyn_pd_th_max = dig->igi_rssi; 5672 5673 final_rssi = min_t(u8, rssi, dig->igi_rssi); 5674 ofdm_cca_th = clamp_t(u8, final_rssi, PD_TH_MIN_RSSI + under_region, 5675 PD_TH_MAX_RSSI + under_region); 5676 5677 if (enable) { 5678 pd_val = (ofdm_cca_th - under_region - PD_TH_MIN_RSSI) >> 1; 5679 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5680 "igi=%d, ofdm_ccaTH=%d, backoff=%d, PD_low=%d\n", 5681 final_rssi, ofdm_cca_th, under_region, pd_val); 5682 } else { 5683 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5684 "Dynamic PD th disabled, Set PD_low_bd=0\n"); 5685 } 5686 5687 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 5688 dig_regs->pd_lower_bound_mask, pd_val); 5689 rtw89_phy_write32_mask(rtwdev, dig_regs->seg0_pd_reg, 5690 dig_regs->pd_spatial_reuse_en, enable); 5691 5692 if (!rtwdev->hal.support_cckpd) 5693 return; 5694 5695 cck_cca_th = max_t(s8, final_rssi - under_region, CCKPD_TH_MIN_RSSI); 5696 pd_val = (u32)(cck_cca_th - IGI_RSSI_MAX); 5697 5698 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5699 "igi=%d, cck_ccaTH=%d, backoff=%d, cck_PD_low=((%d))dB\n", 5700 final_rssi, cck_cca_th, under_region, pd_val); 5701 5702 rtw89_phy_write32_mask(rtwdev, dig_regs->bmode_pd_reg, 5703 dig_regs->bmode_cca_rssi_limit_en, enable); 5704 rtw89_phy_write32_mask(rtwdev, dig_regs->bmode_pd_lower_bound_reg, 5705 dig_regs->bmode_rssi_nocca_low_th_mask, pd_val); 5706 } 5707 5708 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev) 5709 { 5710 struct rtw89_dig_info *dig = &rtwdev->dig; 5711 5712 dig->bypass_dig = false; 5713 rtw89_phy_dig_para_reset(rtwdev); 5714 rtw89_phy_dig_set_igi_cr(rtwdev, dig->force_gaincode); 5715 rtw89_phy_dig_dyn_pd_th(rtwdev, rssi_nolink, false); 5716 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 5717 rtw89_phy_dig_update_para(rtwdev); 5718 } 5719 5720 #define IGI_RSSI_MIN 10 5721 void rtw89_phy_dig(struct rtw89_dev *rtwdev) 5722 { 5723 struct rtw89_dig_info *dig = &rtwdev->dig; 5724 bool is_linked = rtwdev->total_sta_assoc > 0; 5725 5726 if (unlikely(dig->bypass_dig)) { 5727 dig->bypass_dig = false; 5728 return; 5729 } 5730 5731 if (!dig->is_linked_pre && is_linked) { 5732 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First connected\n"); 5733 rtw89_phy_dig_update_para(rtwdev); 5734 } else if (dig->is_linked_pre && !is_linked) { 5735 rtw89_debug(rtwdev, RTW89_DBG_DIG, "First disconnected\n"); 5736 rtw89_phy_dig_update_para(rtwdev); 5737 } 5738 dig->is_linked_pre = is_linked; 5739 5740 rtw89_phy_dig_igi_offset_by_env(rtwdev); 5741 rtw89_phy_dig_update_rssi_info(rtwdev); 5742 5743 dig->dyn_igi_min = (dig->igi_rssi > IGI_RSSI_MIN) ? 5744 dig->igi_rssi - IGI_RSSI_MIN : 0; 5745 dig->dyn_igi_max = dig->dyn_igi_min + IGI_OFFSET_MAX; 5746 dig->igi_fa_rssi = dig->dyn_igi_min + dig->fa_rssi_ofst; 5747 5748 dig->igi_fa_rssi = clamp(dig->igi_fa_rssi, dig->dyn_igi_min, 5749 dig->dyn_igi_max); 5750 5751 rtw89_debug(rtwdev, RTW89_DBG_DIG, 5752 "rssi=%03d, dyn(max,min)=(%d,%d), final_rssi=%d\n", 5753 dig->igi_rssi, dig->dyn_igi_max, dig->dyn_igi_min, 5754 dig->igi_fa_rssi); 5755 5756 rtw89_phy_dig_config_igi(rtwdev); 5757 5758 rtw89_phy_dig_dyn_pd_th(rtwdev, dig->igi_fa_rssi, dig->dyn_pd_th_en); 5759 5760 if (dig->dyn_pd_th_en && dig->igi_fa_rssi > dig->dyn_pd_th_max) 5761 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, true); 5762 else 5763 rtw89_phy_dig_sdagc_follow_pagc_config(rtwdev, false); 5764 } 5765 5766 static void rtw89_phy_tx_path_div_sta_iter(void *data, struct ieee80211_sta *sta) 5767 { 5768 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 5769 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 5770 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 5771 struct rtw89_hal *hal = &rtwdev->hal; 5772 bool *done = data; 5773 u8 rssi_a, rssi_b; 5774 u32 candidate; 5775 5776 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || sta->tdls) 5777 return; 5778 5779 if (*done) 5780 return; 5781 5782 *done = true; 5783 5784 rssi_a = ewma_rssi_read(&rtwsta->rssi[RF_PATH_A]); 5785 rssi_b = ewma_rssi_read(&rtwsta->rssi[RF_PATH_B]); 5786 5787 if (rssi_a > rssi_b + RTW89_TX_DIV_RSSI_RAW_TH) 5788 candidate = RF_A; 5789 else if (rssi_b > rssi_a + RTW89_TX_DIV_RSSI_RAW_TH) 5790 candidate = RF_B; 5791 else 5792 return; 5793 5794 if (hal->antenna_tx == candidate) 5795 return; 5796 5797 hal->antenna_tx = candidate; 5798 rtw89_fw_h2c_txpath_cmac_tbl(rtwdev, rtwsta); 5799 5800 if (hal->antenna_tx == RF_A) { 5801 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x12); 5802 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x11); 5803 } else if (hal->antenna_tx == RF_B) { 5804 rtw89_phy_write32_mask(rtwdev, R_P0_RFMODE, B_P0_RFMODE_MUX, 0x11); 5805 rtw89_phy_write32_mask(rtwdev, R_P1_RFMODE, B_P1_RFMODE_MUX, 0x12); 5806 } 5807 } 5808 5809 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev) 5810 { 5811 struct rtw89_hal *hal = &rtwdev->hal; 5812 bool done = false; 5813 5814 if (!hal->tx_path_diversity) 5815 return; 5816 5817 ieee80211_iterate_stations_atomic(rtwdev->hw, 5818 rtw89_phy_tx_path_div_sta_iter, 5819 &done); 5820 } 5821 5822 #define ANTDIV_MAIN 0 5823 #define ANTDIV_AUX 1 5824 5825 static void rtw89_phy_antdiv_set_ant(struct rtw89_dev *rtwdev) 5826 { 5827 struct rtw89_hal *hal = &rtwdev->hal; 5828 u8 default_ant, optional_ant; 5829 5830 if (!hal->ant_diversity || hal->antenna_tx == 0) 5831 return; 5832 5833 if (hal->antenna_tx == RF_B) { 5834 default_ant = ANTDIV_AUX; 5835 optional_ant = ANTDIV_MAIN; 5836 } else { 5837 default_ant = ANTDIV_MAIN; 5838 optional_ant = ANTDIV_AUX; 5839 } 5840 5841 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_CGCS_CTRL, 5842 default_ant, RTW89_PHY_0); 5843 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ORI, 5844 default_ant, RTW89_PHY_0); 5845 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_RX_ALT, 5846 optional_ant, RTW89_PHY_0); 5847 rtw89_phy_write32_idx(rtwdev, R_P0_ANTSEL, B_P0_ANTSEL_TX_ORI, 5848 default_ant, RTW89_PHY_0); 5849 } 5850 5851 static void rtw89_phy_swap_hal_antenna(struct rtw89_dev *rtwdev) 5852 { 5853 struct rtw89_hal *hal = &rtwdev->hal; 5854 5855 hal->antenna_rx = hal->antenna_rx == RF_A ? RF_B : RF_A; 5856 hal->antenna_tx = hal->antenna_rx; 5857 } 5858 5859 static void rtw89_phy_antdiv_decision_state(struct rtw89_dev *rtwdev) 5860 { 5861 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 5862 struct rtw89_hal *hal = &rtwdev->hal; 5863 bool no_change = false; 5864 u8 main_rssi, aux_rssi; 5865 u8 main_evm, aux_evm; 5866 u32 candidate; 5867 5868 antdiv->get_stats = false; 5869 antdiv->training_count = 0; 5870 5871 main_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->main_stats); 5872 main_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->main_stats); 5873 aux_rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->aux_stats); 5874 aux_evm = rtw89_phy_antdiv_sts_instance_get_evm(&antdiv->aux_stats); 5875 5876 if (main_evm > aux_evm + ANTDIV_EVM_DIFF_TH) 5877 candidate = RF_A; 5878 else if (aux_evm > main_evm + ANTDIV_EVM_DIFF_TH) 5879 candidate = RF_B; 5880 else if (main_rssi > aux_rssi + RTW89_TX_DIV_RSSI_RAW_TH) 5881 candidate = RF_A; 5882 else if (aux_rssi > main_rssi + RTW89_TX_DIV_RSSI_RAW_TH) 5883 candidate = RF_B; 5884 else 5885 no_change = true; 5886 5887 if (no_change) { 5888 /* swap back from training antenna to original */ 5889 rtw89_phy_swap_hal_antenna(rtwdev); 5890 return; 5891 } 5892 5893 hal->antenna_tx = candidate; 5894 hal->antenna_rx = candidate; 5895 } 5896 5897 static void rtw89_phy_antdiv_training_state(struct rtw89_dev *rtwdev) 5898 { 5899 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 5900 u64 state_period; 5901 5902 if (antdiv->training_count % 2 == 0) { 5903 if (antdiv->training_count == 0) 5904 rtw89_phy_antdiv_sts_reset(rtwdev); 5905 5906 antdiv->get_stats = true; 5907 state_period = msecs_to_jiffies(ANTDIV_TRAINNING_INTVL); 5908 } else { 5909 antdiv->get_stats = false; 5910 state_period = msecs_to_jiffies(ANTDIV_DELAY); 5911 5912 rtw89_phy_swap_hal_antenna(rtwdev); 5913 rtw89_phy_antdiv_set_ant(rtwdev); 5914 } 5915 5916 antdiv->training_count++; 5917 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work, 5918 state_period); 5919 } 5920 5921 void rtw89_phy_antdiv_work(struct work_struct *work) 5922 { 5923 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 5924 antdiv_work.work); 5925 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 5926 5927 mutex_lock(&rtwdev->mutex); 5928 5929 if (antdiv->training_count <= ANTDIV_TRAINNING_CNT) { 5930 rtw89_phy_antdiv_training_state(rtwdev); 5931 } else { 5932 rtw89_phy_antdiv_decision_state(rtwdev); 5933 rtw89_phy_antdiv_set_ant(rtwdev); 5934 } 5935 5936 mutex_unlock(&rtwdev->mutex); 5937 } 5938 5939 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev) 5940 { 5941 struct rtw89_antdiv_info *antdiv = &rtwdev->antdiv; 5942 struct rtw89_hal *hal = &rtwdev->hal; 5943 u8 rssi, rssi_pre; 5944 5945 if (!hal->ant_diversity || hal->ant_diversity_fixed) 5946 return; 5947 5948 rssi = rtw89_phy_antdiv_sts_instance_get_rssi(&antdiv->target_stats); 5949 rssi_pre = antdiv->rssi_pre; 5950 antdiv->rssi_pre = rssi; 5951 rtw89_phy_antdiv_sts_instance_reset(&antdiv->target_stats); 5952 5953 if (abs((int)rssi - (int)rssi_pre) < ANTDIV_RSSI_DIFF_TH) 5954 return; 5955 5956 antdiv->training_count = 0; 5957 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->antdiv_work, 0); 5958 } 5959 5960 static void rtw89_phy_env_monitor_init(struct rtw89_dev *rtwdev) 5961 { 5962 rtw89_phy_ccx_top_setting_init(rtwdev); 5963 rtw89_phy_ifs_clm_setting_init(rtwdev); 5964 } 5965 5966 static void rtw89_phy_edcca_init(struct rtw89_dev *rtwdev) 5967 { 5968 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 5969 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak; 5970 5971 memset(edcca_bak, 0, sizeof(*edcca_bak)); 5972 5973 if (rtwdev->chip->chip_id == RTL8922A && rtwdev->hal.cv == CHIP_CAV) { 5974 rtw89_phy_set_phy_regs(rtwdev, R_TXGATING, B_TXGATING_EN, 0); 5975 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_VAL, 2); 5976 rtw89_phy_set_phy_regs(rtwdev, R_CTLTOP, B_CTLTOP_ON, 1); 5977 rtw89_phy_set_phy_regs(rtwdev, R_SPOOF_CG, B_SPOOF_CG_EN, 0); 5978 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_CG_EN, 0); 5979 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 0); 5980 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 0); 5981 rtw89_phy_set_phy_regs(rtwdev, R_SEGSND, B_SEGSND_EN, 1); 5982 rtw89_phy_set_phy_regs(rtwdev, R_DFS_FFT_CG, B_DFS_FFT_EN, 1); 5983 } 5984 5985 rtw89_phy_write32_mask(rtwdev, edcca_regs->tx_collision_t2r_st, 5986 edcca_regs->tx_collision_t2r_st_mask, 0x29); 5987 } 5988 5989 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev) 5990 { 5991 rtw89_phy_stat_init(rtwdev); 5992 5993 rtw89_chip_bb_sethw(rtwdev); 5994 5995 rtw89_phy_env_monitor_init(rtwdev); 5996 rtw89_physts_parsing_init(rtwdev); 5997 rtw89_phy_dig_init(rtwdev); 5998 rtw89_phy_cfo_init(rtwdev); 5999 rtw89_phy_bb_wrap_init(rtwdev); 6000 rtw89_phy_edcca_init(rtwdev); 6001 rtw89_phy_ch_info_init(rtwdev); 6002 rtw89_phy_ul_tb_info_init(rtwdev); 6003 rtw89_phy_antdiv_init(rtwdev); 6004 rtw89_chip_rfe_gpio(rtwdev); 6005 rtw89_phy_antdiv_set_ant(rtwdev); 6006 6007 rtw89_chip_rfk_hw_init(rtwdev); 6008 rtw89_phy_init_rf_nctl(rtwdev); 6009 rtw89_chip_rfk_init(rtwdev); 6010 rtw89_chip_set_txpwr_ctrl(rtwdev); 6011 rtw89_chip_power_trim(rtwdev); 6012 rtw89_chip_cfg_txrx_path(rtwdev); 6013 } 6014 6015 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 6016 { 6017 const struct rtw89_chip_info *chip = rtwdev->chip; 6018 const struct rtw89_reg_def *bss_clr_vld = &chip->bss_clr_vld; 6019 enum rtw89_phy_idx phy_idx = RTW89_PHY_0; 6020 u8 bss_color; 6021 6022 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 6023 return; 6024 6025 bss_color = vif->bss_conf.he_bss_color.color; 6026 6027 rtw89_phy_write32_idx(rtwdev, bss_clr_vld->addr, bss_clr_vld->mask, 0x1, 6028 phy_idx); 6029 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_TGT, 6030 bss_color, phy_idx); 6031 rtw89_phy_write32_idx(rtwdev, chip->bss_clr_map_reg, B_BSS_CLR_MAP_STAID, 6032 vif->cfg.aid, phy_idx); 6033 } 6034 6035 static bool rfk_chan_validate_desc(const struct rtw89_rfk_chan_desc *desc) 6036 { 6037 return desc->ch != 0; 6038 } 6039 6040 static bool rfk_chan_is_equivalent(const struct rtw89_rfk_chan_desc *desc, 6041 const struct rtw89_chan *chan) 6042 { 6043 if (!rfk_chan_validate_desc(desc)) 6044 return false; 6045 6046 if (desc->ch != chan->channel) 6047 return false; 6048 6049 if (desc->has_band && desc->band != chan->band_type) 6050 return false; 6051 6052 if (desc->has_bw && desc->bw != chan->band_width) 6053 return false; 6054 6055 return true; 6056 } 6057 6058 struct rfk_chan_iter_data { 6059 const struct rtw89_rfk_chan_desc desc; 6060 unsigned int found; 6061 }; 6062 6063 static int rfk_chan_iter_search(const struct rtw89_chan *chan, void *data) 6064 { 6065 struct rfk_chan_iter_data *iter_data = data; 6066 6067 if (rfk_chan_is_equivalent(&iter_data->desc, chan)) 6068 iter_data->found++; 6069 6070 return 0; 6071 } 6072 6073 u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev, 6074 const struct rtw89_rfk_chan_desc *desc, u8 desc_nr, 6075 const struct rtw89_chan *target_chan) 6076 { 6077 int sel = -1; 6078 u8 i; 6079 6080 for (i = 0; i < desc_nr; i++) { 6081 struct rfk_chan_iter_data iter_data = { 6082 .desc = desc[i], 6083 }; 6084 6085 if (rfk_chan_is_equivalent(&desc[i], target_chan)) 6086 return i; 6087 6088 rtw89_iterate_entity_chan(rtwdev, rfk_chan_iter_search, &iter_data); 6089 if (!iter_data.found && sel == -1) 6090 sel = i; 6091 } 6092 6093 if (sel == -1) { 6094 rtw89_debug(rtwdev, RTW89_DBG_RFK, 6095 "no idle rfk entry; force replace the first\n"); 6096 sel = 0; 6097 } 6098 6099 return sel; 6100 } 6101 EXPORT_SYMBOL(rtw89_rfk_chan_lookup); 6102 6103 static void 6104 _rfk_write_rf(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6105 { 6106 rtw89_write_rf(rtwdev, def->path, def->addr, def->mask, def->data); 6107 } 6108 6109 static void 6110 _rfk_write32_mask(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6111 { 6112 rtw89_phy_write32_mask(rtwdev, def->addr, def->mask, def->data); 6113 } 6114 6115 static void 6116 _rfk_write32_set(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6117 { 6118 rtw89_phy_write32_set(rtwdev, def->addr, def->mask); 6119 } 6120 6121 static void 6122 _rfk_write32_clr(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6123 { 6124 rtw89_phy_write32_clr(rtwdev, def->addr, def->mask); 6125 } 6126 6127 static void 6128 _rfk_delay(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) 6129 { 6130 udelay(def->data); 6131 } 6132 6133 static void 6134 (*_rfk_handler[])(struct rtw89_dev *rtwdev, const struct rtw89_reg5_def *def) = { 6135 [RTW89_RFK_F_WRF] = _rfk_write_rf, 6136 [RTW89_RFK_F_WM] = _rfk_write32_mask, 6137 [RTW89_RFK_F_WS] = _rfk_write32_set, 6138 [RTW89_RFK_F_WC] = _rfk_write32_clr, 6139 [RTW89_RFK_F_DELAY] = _rfk_delay, 6140 }; 6141 6142 #if defined(__linux__) 6143 static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); 6144 #elif defined(__FreeBSD__) 6145 rtw89_static_assert(ARRAY_SIZE(_rfk_handler) == RTW89_RFK_F_NUM); 6146 #endif 6147 6148 void 6149 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl) 6150 { 6151 const struct rtw89_reg5_def *p = tbl->defs; 6152 const struct rtw89_reg5_def *end = tbl->defs + tbl->size; 6153 6154 for (; p < end; p++) 6155 _rfk_handler[p->flag](rtwdev, p); 6156 } 6157 EXPORT_SYMBOL(rtw89_rfk_parser); 6158 6159 #define RTW89_TSSI_FAST_MODE_NUM 4 6160 6161 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_flat[RTW89_TSSI_FAST_MODE_NUM] = { 6162 {0xD934, 0xff0000}, 6163 {0xD934, 0xff000000}, 6164 {0xD938, 0xff}, 6165 {0xD934, 0xff00}, 6166 }; 6167 6168 static const struct rtw89_reg_def rtw89_tssi_fastmode_regs_level[RTW89_TSSI_FAST_MODE_NUM] = { 6169 {0xD930, 0xff0000}, 6170 {0xD930, 0xff000000}, 6171 {0xD934, 0xff}, 6172 {0xD930, 0xff00}, 6173 }; 6174 6175 static 6176 void rtw89_phy_tssi_ctrl_set_fast_mode_cfg(struct rtw89_dev *rtwdev, 6177 enum rtw89_mac_idx mac_idx, 6178 enum rtw89_tssi_bandedge_cfg bandedge_cfg, 6179 u32 val) 6180 { 6181 const struct rtw89_reg_def *regs; 6182 u32 reg; 6183 int i; 6184 6185 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 6186 regs = rtw89_tssi_fastmode_regs_flat; 6187 else 6188 regs = rtw89_tssi_fastmode_regs_level; 6189 6190 for (i = 0; i < RTW89_TSSI_FAST_MODE_NUM; i++) { 6191 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx); 6192 rtw89_write32_mask(rtwdev, reg, regs[i].mask, val); 6193 } 6194 } 6195 6196 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_flat[RTW89_TSSI_SBW_NUM] = { 6197 {0xD91C, 0xff000000}, 6198 {0xD920, 0xff}, 6199 {0xD920, 0xff00}, 6200 {0xD920, 0xff0000}, 6201 {0xD920, 0xff000000}, 6202 {0xD924, 0xff}, 6203 {0xD924, 0xff00}, 6204 {0xD914, 0xff000000}, 6205 {0xD918, 0xff}, 6206 {0xD918, 0xff00}, 6207 {0xD918, 0xff0000}, 6208 {0xD918, 0xff000000}, 6209 {0xD91C, 0xff}, 6210 {0xD91C, 0xff00}, 6211 {0xD91C, 0xff0000}, 6212 }; 6213 6214 static const struct rtw89_reg_def rtw89_tssi_bandedge_regs_level[RTW89_TSSI_SBW_NUM] = { 6215 {0xD910, 0xff}, 6216 {0xD910, 0xff00}, 6217 {0xD910, 0xff0000}, 6218 {0xD910, 0xff000000}, 6219 {0xD914, 0xff}, 6220 {0xD914, 0xff00}, 6221 {0xD914, 0xff0000}, 6222 {0xD908, 0xff}, 6223 {0xD908, 0xff00}, 6224 {0xD908, 0xff0000}, 6225 {0xD908, 0xff000000}, 6226 {0xD90C, 0xff}, 6227 {0xD90C, 0xff00}, 6228 {0xD90C, 0xff0000}, 6229 {0xD90C, 0xff000000}, 6230 }; 6231 6232 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, 6233 enum rtw89_mac_idx mac_idx, 6234 enum rtw89_tssi_bandedge_cfg bandedge_cfg) 6235 { 6236 const struct rtw89_chip_info *chip = rtwdev->chip; 6237 const struct rtw89_reg_def *regs; 6238 const u32 *data; 6239 u32 reg; 6240 int i; 6241 6242 if (bandedge_cfg >= RTW89_TSSI_CFG_NUM) 6243 return; 6244 6245 if (bandedge_cfg == RTW89_TSSI_BANDEDGE_FLAT) 6246 regs = rtw89_tssi_bandedge_regs_flat; 6247 else 6248 regs = rtw89_tssi_bandedge_regs_level; 6249 6250 data = chip->tssi_dbw_table->data[bandedge_cfg]; 6251 6252 for (i = 0; i < RTW89_TSSI_SBW_NUM; i++) { 6253 reg = rtw89_mac_reg_by_idx(rtwdev, regs[i].addr, mac_idx); 6254 rtw89_write32_mask(rtwdev, reg, regs[i].mask, data[i]); 6255 } 6256 6257 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BANDEDGE_CFG, mac_idx); 6258 rtw89_write32_mask(rtwdev, reg, B_AX_BANDEDGE_CFG_IDX_MASK, bandedge_cfg); 6259 6260 rtw89_phy_tssi_ctrl_set_fast_mode_cfg(rtwdev, mac_idx, bandedge_cfg, 6261 data[RTW89_TSSI_SBW20]); 6262 } 6263 EXPORT_SYMBOL(rtw89_phy_tssi_ctrl_set_bandedge_cfg); 6264 6265 static 6266 const u8 rtw89_ch_base_table[16] = {1, 0xff, 6267 36, 100, 132, 149, 0xff, 6268 1, 33, 65, 97, 129, 161, 193, 225, 0xff}; 6269 #define RTW89_CH_BASE_IDX_2G 0 6270 #define RTW89_CH_BASE_IDX_5G_FIRST 2 6271 #define RTW89_CH_BASE_IDX_5G_LAST 5 6272 #define RTW89_CH_BASE_IDX_6G_FIRST 7 6273 #define RTW89_CH_BASE_IDX_6G_LAST 14 6274 6275 #define RTW89_CH_BASE_IDX_MASK GENMASK(7, 4) 6276 #define RTW89_CH_OFFSET_MASK GENMASK(3, 0) 6277 6278 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band) 6279 { 6280 u8 chan_idx; 6281 u8 last, first; 6282 u8 idx; 6283 6284 switch (band) { 6285 case RTW89_BAND_2G: 6286 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, RTW89_CH_BASE_IDX_2G) | 6287 FIELD_PREP(RTW89_CH_OFFSET_MASK, central_ch); 6288 return chan_idx; 6289 case RTW89_BAND_5G: 6290 first = RTW89_CH_BASE_IDX_5G_FIRST; 6291 last = RTW89_CH_BASE_IDX_5G_LAST; 6292 break; 6293 case RTW89_BAND_6G: 6294 first = RTW89_CH_BASE_IDX_6G_FIRST; 6295 last = RTW89_CH_BASE_IDX_6G_LAST; 6296 break; 6297 default: 6298 rtw89_warn(rtwdev, "Unsupported band %d\n", band); 6299 return 0; 6300 } 6301 6302 for (idx = last; idx >= first; idx--) 6303 if (central_ch >= rtw89_ch_base_table[idx]) 6304 break; 6305 6306 if (idx < first) { 6307 rtw89_warn(rtwdev, "Unknown band %d channel %d\n", band, central_ch); 6308 return 0; 6309 } 6310 6311 chan_idx = FIELD_PREP(RTW89_CH_BASE_IDX_MASK, idx) | 6312 FIELD_PREP(RTW89_CH_OFFSET_MASK, 6313 (central_ch - rtw89_ch_base_table[idx]) >> 1); 6314 return chan_idx; 6315 } 6316 EXPORT_SYMBOL(rtw89_encode_chan_idx); 6317 6318 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx, 6319 u8 *ch, enum nl80211_band *band) 6320 { 6321 u8 idx, offset; 6322 6323 idx = FIELD_GET(RTW89_CH_BASE_IDX_MASK, chan_idx); 6324 offset = FIELD_GET(RTW89_CH_OFFSET_MASK, chan_idx); 6325 6326 if (idx == RTW89_CH_BASE_IDX_2G) { 6327 *band = NL80211_BAND_2GHZ; 6328 *ch = offset; 6329 return; 6330 } 6331 6332 *band = idx <= RTW89_CH_BASE_IDX_5G_LAST ? NL80211_BAND_5GHZ : NL80211_BAND_6GHZ; 6333 *ch = rtw89_ch_base_table[idx] + (offset << 1); 6334 } 6335 EXPORT_SYMBOL(rtw89_decode_chan_idx); 6336 6337 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan) 6338 { 6339 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 6340 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak; 6341 6342 if (scan) { 6343 edcca_bak->a = 6344 rtw89_phy_read32_mask(rtwdev, edcca_regs->edcca_level, 6345 edcca_regs->edcca_mask); 6346 edcca_bak->p = 6347 rtw89_phy_read32_mask(rtwdev, edcca_regs->edcca_level, 6348 edcca_regs->edcca_p_mask); 6349 edcca_bak->ppdu = 6350 rtw89_phy_read32_mask(rtwdev, edcca_regs->ppdu_level, 6351 edcca_regs->ppdu_mask); 6352 6353 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 6354 edcca_regs->edcca_mask, EDCCA_MAX); 6355 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 6356 edcca_regs->edcca_p_mask, EDCCA_MAX); 6357 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level, 6358 edcca_regs->ppdu_mask, EDCCA_MAX); 6359 } else { 6360 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 6361 edcca_regs->edcca_mask, 6362 edcca_bak->a); 6363 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 6364 edcca_regs->edcca_p_mask, 6365 edcca_bak->p); 6366 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level, 6367 edcca_regs->ppdu_mask, 6368 edcca_bak->ppdu); 6369 } 6370 } 6371 6372 static void rtw89_phy_edcca_log(struct rtw89_dev *rtwdev) 6373 { 6374 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 6375 bool flag_fb, flag_p20, flag_s20, flag_s40, flag_s80; 6376 s8 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80; 6377 u8 path, per20_bitmap; 6378 u8 pwdb[8]; 6379 u32 tmp; 6380 6381 if (!rtw89_debug_is_enabled(rtwdev, RTW89_DBG_EDCCA)) 6382 return; 6383 6384 if (rtwdev->chip->chip_id == RTL8922A) 6385 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, 6386 edcca_regs->rpt_sel_be_mask, 0); 6387 6388 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 6389 edcca_regs->rpt_sel_mask, 0); 6390 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b); 6391 path = u32_get_bits(tmp, B_EDCCA_RPT_B_PATH_MASK); 6392 flag_s80 = u32_get_bits(tmp, B_EDCCA_RPT_B_S80); 6393 flag_s40 = u32_get_bits(tmp, B_EDCCA_RPT_B_S40); 6394 flag_s20 = u32_get_bits(tmp, B_EDCCA_RPT_B_S20); 6395 flag_p20 = u32_get_bits(tmp, B_EDCCA_RPT_B_P20); 6396 flag_fb = u32_get_bits(tmp, B_EDCCA_RPT_B_FB); 6397 pwdb_s20 = u32_get_bits(tmp, MASKBYTE1); 6398 pwdb_p20 = u32_get_bits(tmp, MASKBYTE2); 6399 pwdb_fb = u32_get_bits(tmp, MASKBYTE3); 6400 6401 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 6402 edcca_regs->rpt_sel_mask, 4); 6403 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b); 6404 pwdb_s80 = u32_get_bits(tmp, MASKBYTE1); 6405 pwdb_s40 = u32_get_bits(tmp, MASKBYTE2); 6406 6407 per20_bitmap = rtw89_phy_read32_mask(rtwdev, edcca_regs->rpt_a, 6408 MASKBYTE0); 6409 6410 if (rtwdev->chip->chip_id == RTL8922A) { 6411 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, 6412 edcca_regs->rpt_sel_be_mask, 4); 6413 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b); 6414 pwdb[0] = u32_get_bits(tmp, MASKBYTE3); 6415 pwdb[1] = u32_get_bits(tmp, MASKBYTE2); 6416 pwdb[2] = u32_get_bits(tmp, MASKBYTE1); 6417 pwdb[3] = u32_get_bits(tmp, MASKBYTE0); 6418 6419 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel_be, 6420 edcca_regs->rpt_sel_be_mask, 5); 6421 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_b); 6422 pwdb[4] = u32_get_bits(tmp, MASKBYTE3); 6423 pwdb[5] = u32_get_bits(tmp, MASKBYTE2); 6424 pwdb[6] = u32_get_bits(tmp, MASKBYTE1); 6425 pwdb[7] = u32_get_bits(tmp, MASKBYTE0); 6426 } else { 6427 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 6428 edcca_regs->rpt_sel_mask, 0); 6429 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a); 6430 pwdb[0] = u32_get_bits(tmp, MASKBYTE3); 6431 pwdb[1] = u32_get_bits(tmp, MASKBYTE2); 6432 6433 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 6434 edcca_regs->rpt_sel_mask, 1); 6435 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a); 6436 pwdb[2] = u32_get_bits(tmp, MASKBYTE3); 6437 pwdb[3] = u32_get_bits(tmp, MASKBYTE2); 6438 6439 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 6440 edcca_regs->rpt_sel_mask, 2); 6441 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a); 6442 pwdb[4] = u32_get_bits(tmp, MASKBYTE3); 6443 pwdb[5] = u32_get_bits(tmp, MASKBYTE2); 6444 6445 rtw89_phy_write32_mask(rtwdev, edcca_regs->rpt_sel, 6446 edcca_regs->rpt_sel_mask, 3); 6447 tmp = rtw89_phy_read32(rtwdev, edcca_regs->rpt_a); 6448 pwdb[6] = u32_get_bits(tmp, MASKBYTE3); 6449 pwdb[7] = u32_get_bits(tmp, MASKBYTE2); 6450 } 6451 6452 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 6453 "[EDCCA]: edcca_bitmap = %04x\n", per20_bitmap); 6454 6455 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 6456 "[EDCCA]: pwdb per20{0,1,2,3,4,5,6,7} = {%d,%d,%d,%d,%d,%d,%d,%d}(dBm)\n", 6457 pwdb[0], pwdb[1], pwdb[2], pwdb[3], pwdb[4], pwdb[5], 6458 pwdb[6], pwdb[7]); 6459 6460 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 6461 "[EDCCA]: path=%d, flag {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}\n", 6462 path, flag_fb, flag_p20, flag_s20, flag_s40, flag_s80); 6463 6464 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 6465 "[EDCCA]: pwdb {FB,p20,s20,s40,s80} = {%d,%d,%d,%d,%d}(dBm)\n", 6466 pwdb_fb, pwdb_p20, pwdb_s20, pwdb_s40, pwdb_s80); 6467 } 6468 6469 static u8 rtw89_phy_edcca_get_thre_by_rssi(struct rtw89_dev *rtwdev) 6470 { 6471 struct rtw89_phy_ch_info *ch_info = &rtwdev->ch_info; 6472 bool is_linked = rtwdev->total_sta_assoc > 0; 6473 u8 rssi_min = ch_info->rssi_min >> 1; 6474 u8 edcca_thre; 6475 6476 if (!is_linked) { 6477 edcca_thre = EDCCA_MAX; 6478 } else { 6479 edcca_thre = rssi_min - RSSI_UNIT_CONVER + EDCCA_UNIT_CONVER - 6480 EDCCA_TH_REF; 6481 edcca_thre = max_t(u8, edcca_thre, EDCCA_TH_L2H_LB); 6482 } 6483 6484 return edcca_thre; 6485 } 6486 6487 void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev) 6488 { 6489 const struct rtw89_edcca_regs *edcca_regs = rtwdev->chip->edcca_regs; 6490 struct rtw89_edcca_bak *edcca_bak = &rtwdev->hal.edcca_bak; 6491 u8 th; 6492 6493 th = rtw89_phy_edcca_get_thre_by_rssi(rtwdev); 6494 if (th == edcca_bak->th_old) 6495 return; 6496 6497 edcca_bak->th_old = th; 6498 6499 rtw89_debug(rtwdev, RTW89_DBG_EDCCA, 6500 "[EDCCA]: Normal Mode, EDCCA_th = %d\n", th); 6501 6502 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 6503 edcca_regs->edcca_mask, th); 6504 rtw89_phy_write32_mask(rtwdev, edcca_regs->edcca_level, 6505 edcca_regs->edcca_p_mask, th); 6506 rtw89_phy_write32_mask(rtwdev, edcca_regs->ppdu_level, 6507 edcca_regs->ppdu_mask, th); 6508 } 6509 6510 void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev) 6511 { 6512 struct rtw89_hal *hal = &rtwdev->hal; 6513 6514 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_DYNAMIC_EDCCA)) 6515 return; 6516 6517 rtw89_phy_edcca_thre_calc(rtwdev); 6518 rtw89_phy_edcca_log(rtwdev); 6519 } 6520 6521 enum rtw89_rf_path_bit rtw89_phy_get_kpath(struct rtw89_dev *rtwdev, 6522 enum rtw89_phy_idx phy_idx) 6523 { 6524 rtw89_debug(rtwdev, RTW89_DBG_RFK, 6525 "[RFK] kpath dbcc_en: 0x%x, mode=0x%x, PHY%d\n", 6526 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx); 6527 6528 switch (rtwdev->mlo_dbcc_mode) { 6529 case MLO_1_PLUS_1_1RF: 6530 if (phy_idx == RTW89_PHY_0) 6531 return RF_A; 6532 else 6533 return RF_B; 6534 case MLO_1_PLUS_1_2RF: 6535 if (phy_idx == RTW89_PHY_0) 6536 return RF_A; 6537 else 6538 return RF_D; 6539 case MLO_0_PLUS_2_1RF: 6540 case MLO_2_PLUS_0_1RF: 6541 /* for both PHY 0/1 */ 6542 return RF_AB; 6543 case MLO_0_PLUS_2_2RF: 6544 case MLO_2_PLUS_0_2RF: 6545 case MLO_2_PLUS_2_2RF: 6546 default: 6547 if (phy_idx == RTW89_PHY_0) 6548 return RF_AB; 6549 else 6550 return RF_CD; 6551 } 6552 } 6553 EXPORT_SYMBOL(rtw89_phy_get_kpath); 6554 6555 enum rtw89_rf_path rtw89_phy_get_syn_sel(struct rtw89_dev *rtwdev, 6556 enum rtw89_phy_idx phy_idx) 6557 { 6558 rtw89_debug(rtwdev, RTW89_DBG_RFK, 6559 "[RFK] kpath dbcc_en: 0x%x, mode=0x%x, PHY%d\n", 6560 rtwdev->dbcc_en, rtwdev->mlo_dbcc_mode, phy_idx); 6561 6562 switch (rtwdev->mlo_dbcc_mode) { 6563 case MLO_1_PLUS_1_1RF: 6564 if (phy_idx == RTW89_PHY_0) 6565 return RF_PATH_A; 6566 else 6567 return RF_PATH_B; 6568 case MLO_1_PLUS_1_2RF: 6569 if (phy_idx == RTW89_PHY_0) 6570 return RF_PATH_A; 6571 else 6572 return RF_PATH_D; 6573 case MLO_0_PLUS_2_1RF: 6574 case MLO_2_PLUS_0_1RF: 6575 if (phy_idx == RTW89_PHY_0) 6576 return RF_PATH_A; 6577 else 6578 return RF_PATH_B; 6579 case MLO_0_PLUS_2_2RF: 6580 case MLO_2_PLUS_0_2RF: 6581 case MLO_2_PLUS_2_2RF: 6582 default: 6583 if (phy_idx == RTW89_PHY_0) 6584 return RF_PATH_A; 6585 else 6586 return RF_PATH_C; 6587 } 6588 } 6589 EXPORT_SYMBOL(rtw89_phy_get_syn_sel); 6590 6591 static const struct rtw89_ccx_regs rtw89_ccx_regs_ax = { 6592 .setting_addr = R_CCX, 6593 .edcca_opt_mask = B_CCX_EDCCA_OPT_MSK, 6594 .measurement_trig_mask = B_MEASUREMENT_TRIG_MSK, 6595 .trig_opt_mask = B_CCX_TRIG_OPT_MSK, 6596 .en_mask = B_CCX_EN_MSK, 6597 .ifs_cnt_addr = R_IFS_COUNTER, 6598 .ifs_clm_period_mask = B_IFS_CLM_PERIOD_MSK, 6599 .ifs_clm_cnt_unit_mask = B_IFS_CLM_COUNTER_UNIT_MSK, 6600 .ifs_clm_cnt_clear_mask = B_IFS_COUNTER_CLR_MSK, 6601 .ifs_collect_en_mask = B_IFS_COLLECT_EN, 6602 .ifs_t1_addr = R_IFS_T1, 6603 .ifs_t1_th_h_mask = B_IFS_T1_TH_HIGH_MSK, 6604 .ifs_t1_en_mask = B_IFS_T1_EN_MSK, 6605 .ifs_t1_th_l_mask = B_IFS_T1_TH_LOW_MSK, 6606 .ifs_t2_addr = R_IFS_T2, 6607 .ifs_t2_th_h_mask = B_IFS_T2_TH_HIGH_MSK, 6608 .ifs_t2_en_mask = B_IFS_T2_EN_MSK, 6609 .ifs_t2_th_l_mask = B_IFS_T2_TH_LOW_MSK, 6610 .ifs_t3_addr = R_IFS_T3, 6611 .ifs_t3_th_h_mask = B_IFS_T3_TH_HIGH_MSK, 6612 .ifs_t3_en_mask = B_IFS_T3_EN_MSK, 6613 .ifs_t3_th_l_mask = B_IFS_T3_TH_LOW_MSK, 6614 .ifs_t4_addr = R_IFS_T4, 6615 .ifs_t4_th_h_mask = B_IFS_T4_TH_HIGH_MSK, 6616 .ifs_t4_en_mask = B_IFS_T4_EN_MSK, 6617 .ifs_t4_th_l_mask = B_IFS_T4_TH_LOW_MSK, 6618 .ifs_clm_tx_cnt_addr = R_IFS_CLM_TX_CNT, 6619 .ifs_clm_edcca_excl_cca_fa_mask = B_IFS_CLM_EDCCA_EXCLUDE_CCA_FA_MSK, 6620 .ifs_clm_tx_cnt_msk = B_IFS_CLM_TX_CNT_MSK, 6621 .ifs_clm_cca_addr = R_IFS_CLM_CCA, 6622 .ifs_clm_ofdmcca_excl_fa_mask = B_IFS_CLM_OFDMCCA_EXCLUDE_FA_MSK, 6623 .ifs_clm_cckcca_excl_fa_mask = B_IFS_CLM_CCKCCA_EXCLUDE_FA_MSK, 6624 .ifs_clm_fa_addr = R_IFS_CLM_FA, 6625 .ifs_clm_ofdm_fa_mask = B_IFS_CLM_OFDM_FA_MSK, 6626 .ifs_clm_cck_fa_mask = B_IFS_CLM_CCK_FA_MSK, 6627 .ifs_his_addr = R_IFS_HIS, 6628 .ifs_t4_his_mask = B_IFS_T4_HIS_MSK, 6629 .ifs_t3_his_mask = B_IFS_T3_HIS_MSK, 6630 .ifs_t2_his_mask = B_IFS_T2_HIS_MSK, 6631 .ifs_t1_his_mask = B_IFS_T1_HIS_MSK, 6632 .ifs_avg_l_addr = R_IFS_AVG_L, 6633 .ifs_t2_avg_mask = B_IFS_T2_AVG_MSK, 6634 .ifs_t1_avg_mask = B_IFS_T1_AVG_MSK, 6635 .ifs_avg_h_addr = R_IFS_AVG_H, 6636 .ifs_t4_avg_mask = B_IFS_T4_AVG_MSK, 6637 .ifs_t3_avg_mask = B_IFS_T3_AVG_MSK, 6638 .ifs_cca_l_addr = R_IFS_CCA_L, 6639 .ifs_t2_cca_mask = B_IFS_T2_CCA_MSK, 6640 .ifs_t1_cca_mask = B_IFS_T1_CCA_MSK, 6641 .ifs_cca_h_addr = R_IFS_CCA_H, 6642 .ifs_t4_cca_mask = B_IFS_T4_CCA_MSK, 6643 .ifs_t3_cca_mask = B_IFS_T3_CCA_MSK, 6644 .ifs_total_addr = R_IFSCNT, 6645 .ifs_cnt_done_mask = B_IFSCNT_DONE_MSK, 6646 .ifs_total_mask = B_IFSCNT_TOTAL_CNT_MSK, 6647 }; 6648 6649 static const struct rtw89_physts_regs rtw89_physts_regs_ax = { 6650 .setting_addr = R_PLCP_HISTOGRAM, 6651 .dis_trigger_fail_mask = B_STS_DIS_TRIG_BY_FAIL, 6652 .dis_trigger_brk_mask = B_STS_DIS_TRIG_BY_BRK, 6653 }; 6654 6655 static const struct rtw89_cfo_regs rtw89_cfo_regs_ax = { 6656 .comp = R_DCFO_WEIGHT, 6657 .weighting_mask = B_DCFO_WEIGHT_MSK, 6658 .comp_seg0 = R_DCFO_OPT, 6659 .valid_0_mask = B_DCFO_OPT_EN, 6660 }; 6661 6662 const struct rtw89_phy_gen_def rtw89_phy_gen_ax = { 6663 .cr_base = 0x10000, 6664 .ccx = &rtw89_ccx_regs_ax, 6665 .physts = &rtw89_physts_regs_ax, 6666 .cfo = &rtw89_cfo_regs_ax, 6667 .phy0_phy1_offset = rtw89_phy0_phy1_offset_ax, 6668 .config_bb_gain = rtw89_phy_config_bb_gain_ax, 6669 .preinit_rf_nctl = rtw89_phy_preinit_rf_nctl_ax, 6670 .bb_wrap_init = NULL, 6671 .ch_info_init = NULL, 6672 6673 .set_txpwr_byrate = rtw89_phy_set_txpwr_byrate_ax, 6674 .set_txpwr_offset = rtw89_phy_set_txpwr_offset_ax, 6675 .set_txpwr_limit = rtw89_phy_set_txpwr_limit_ax, 6676 .set_txpwr_limit_ru = rtw89_phy_set_txpwr_limit_ru_ax, 6677 }; 6678 EXPORT_SYMBOL(rtw89_phy_gen_ax); 6679