1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_FW_H__ 6 #define __RTW89_FW_H__ 7 8 #include "core.h" 9 10 enum rtw89_fw_dl_status { 11 RTW89_FWDL_INITIAL_STATE = 0, 12 RTW89_FWDL_FWDL_ONGOING = 1, 13 RTW89_FWDL_CHECKSUM_FAIL = 2, 14 RTW89_FWDL_SECURITY_FAIL = 3, 15 RTW89_FWDL_CV_NOT_MATCH = 4, 16 RTW89_FWDL_RSVD0 = 5, 17 RTW89_FWDL_WCPU_FWDL_RDY = 6, 18 RTW89_FWDL_WCPU_FW_INIT_RDY = 7 19 }; 20 21 #define RTW89_GET_C2H_HDR_FUNC(info) \ 22 u32_get_bits(info, GENMASK(6, 0)) 23 #define RTW89_GET_C2H_HDR_LEN(info) \ 24 u32_get_bits(info, GENMASK(11, 8)) 25 26 #define RTW89_SET_H2CREG_HDR_FUNC(info, val) \ 27 u32p_replace_bits(info, val, GENMASK(6, 0)) 28 #define RTW89_SET_H2CREG_HDR_LEN(info, val) \ 29 u32p_replace_bits(info, val, GENMASK(11, 8)) 30 31 #define RTW89_H2CREG_MAX 4 32 #define RTW89_C2HREG_MAX 4 33 #define RTW89_C2HREG_HDR_LEN 2 34 #define RTW89_H2CREG_HDR_LEN 2 35 #define RTW89_C2H_TIMEOUT 1000000 36 struct rtw89_mac_c2h_info { 37 u8 id; 38 u8 content_len; 39 u32 c2hreg[RTW89_C2HREG_MAX]; 40 }; 41 42 struct rtw89_mac_h2c_info { 43 u8 id; 44 u8 content_len; 45 u32 h2creg[RTW89_H2CREG_MAX]; 46 }; 47 48 enum rtw89_mac_h2c_type { 49 RTW89_FWCMD_H2CREG_FUNC_H2CREG_LB = 0, 50 RTW89_FWCMD_H2CREG_FUNC_CNSL_CMD, 51 RTW89_FWCMD_H2CREG_FUNC_FWERR, 52 RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE, 53 RTW89_FWCMD_H2CREG_FUNC_GETPKT_INFORM, 54 RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN 55 }; 56 57 enum rtw89_mac_c2h_type { 58 RTW89_FWCMD_C2HREG_FUNC_C2HREG_LB = 0, 59 RTW89_FWCMD_C2HREG_FUNC_ERR_RPT, 60 RTW89_FWCMD_C2HREG_FUNC_ERR_MSG, 61 RTW89_FWCMD_C2HREG_FUNC_PHY_CAP, 62 RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT, 63 RTW89_FWCMD_C2HREG_FUNC_NULL = 0xFF 64 }; 65 66 struct rtw89_c2h_phy_cap { 67 u32 func:7; 68 u32 ack:1; 69 u32 len:4; 70 u32 seq:4; 71 u32 rx_nss:8; 72 u32 bw:8; 73 74 u32 tx_nss:8; 75 u32 prot:8; 76 u32 nic:8; 77 u32 wl_func:8; 78 79 u32 hw_type:8; 80 } __packed; 81 82 enum rtw89_fw_c2h_category { 83 RTW89_C2H_CAT_TEST, 84 RTW89_C2H_CAT_MAC, 85 RTW89_C2H_CAT_OUTSRC, 86 }; 87 88 enum rtw89_fw_log_level { 89 RTW89_FW_LOG_LEVEL_OFF, 90 RTW89_FW_LOG_LEVEL_CRT, 91 RTW89_FW_LOG_LEVEL_SER, 92 RTW89_FW_LOG_LEVEL_WARN, 93 RTW89_FW_LOG_LEVEL_LOUD, 94 RTW89_FW_LOG_LEVEL_TR, 95 }; 96 97 enum rtw89_fw_log_path { 98 RTW89_FW_LOG_LEVEL_UART, 99 RTW89_FW_LOG_LEVEL_C2H, 100 RTW89_FW_LOG_LEVEL_SNI, 101 }; 102 103 enum rtw89_fw_log_comp { 104 RTW89_FW_LOG_COMP_VER, 105 RTW89_FW_LOG_COMP_INIT, 106 RTW89_FW_LOG_COMP_TASK, 107 RTW89_FW_LOG_COMP_CNS, 108 RTW89_FW_LOG_COMP_H2C, 109 RTW89_FW_LOG_COMP_C2H, 110 RTW89_FW_LOG_COMP_TX, 111 RTW89_FW_LOG_COMP_RX, 112 RTW89_FW_LOG_COMP_IPSEC, 113 RTW89_FW_LOG_COMP_TIMER, 114 RTW89_FW_LOG_COMP_DBGPKT, 115 RTW89_FW_LOG_COMP_PS, 116 RTW89_FW_LOG_COMP_ERROR, 117 RTW89_FW_LOG_COMP_WOWLAN, 118 RTW89_FW_LOG_COMP_SECURE_BOOT, 119 RTW89_FW_LOG_COMP_BTC, 120 RTW89_FW_LOG_COMP_BB, 121 RTW89_FW_LOG_COMP_TWT, 122 RTW89_FW_LOG_COMP_RF, 123 RTW89_FW_LOG_COMP_MCC = 20, 124 }; 125 126 enum rtw89_pkt_offload_op { 127 RTW89_PKT_OFLD_OP_ADD, 128 RTW89_PKT_OFLD_OP_DEL, 129 RTW89_PKT_OFLD_OP_READ, 130 }; 131 132 enum rtw89_scanofld_notify_reason { 133 RTW89_SCAN_DWELL_NOTIFY, 134 RTW89_SCAN_PRE_TX_NOTIFY, 135 RTW89_SCAN_POST_TX_NOTIFY, 136 RTW89_SCAN_ENTER_CH_NOTIFY, 137 RTW89_SCAN_LEAVE_CH_NOTIFY, 138 RTW89_SCAN_END_SCAN_NOTIFY, 139 }; 140 141 enum rtw89_chan_type { 142 RTW89_CHAN_OPERATE = 0, 143 RTW89_CHAN_ACTIVE, 144 RTW89_CHAN_DFS, 145 }; 146 147 #define FWDL_SECTION_MAX_NUM 10 148 #define FWDL_SECTION_CHKSUM_LEN 8 149 #define FWDL_SECTION_PER_PKT_LEN 2020 150 151 struct rtw89_fw_hdr_section_info { 152 u8 redl; 153 const u8 *addr; 154 u32 len; 155 u32 dladdr; 156 }; 157 158 struct rtw89_fw_bin_info { 159 u8 section_num; 160 u32 hdr_len; 161 struct rtw89_fw_hdr_section_info section_info[FWDL_SECTION_MAX_NUM]; 162 }; 163 164 struct rtw89_fw_macid_pause_grp { 165 __le32 pause_grp[4]; 166 __le32 mask_grp[4]; 167 } __packed; 168 169 struct rtw89_h2creg_sch_tx_en { 170 u8 func:7; 171 u8 ack:1; 172 u8 total_len:4; 173 u8 seq_num:4; 174 u16 tx_en:16; 175 u16 mask:16; 176 u8 band:1; 177 u16 rsvd:15; 178 } __packed; 179 180 #define RTW89_CHANNEL_TIME 45 181 #define RTW89_DFS_CHAN_TIME 105 182 #define RTW89_OFF_CHAN_TIME 100 183 #define RTW89_DWELL_TIME 20 184 #define RTW89_SCAN_WIDTH 0 185 #define RTW89_SCANOFLD_MAX_SSID 8 186 #define RTW89_SCANOFLD_MAX_IE_LEN 512 187 #define RTW89_SCANOFLD_PKT_NONE 0xFF 188 #define RTW89_SCANOFLD_DEBUG_MASK 0x1F 189 #define RTW89_MAC_CHINFO_SIZE 20 190 191 struct rtw89_mac_chinfo { 192 u8 period; 193 u8 dwell_time; 194 u8 central_ch; 195 u8 pri_ch; 196 u8 bw:3; 197 u8 notify_action:5; 198 u8 num_pkt:4; 199 u8 tx_pkt:1; 200 u8 pause_data:1; 201 u8 ch_band:2; 202 u8 probe_id; 203 u8 dfs_ch:1; 204 u8 tx_null:1; 205 u8 rand_seq_num:1; 206 u8 cfg_tx_pwr:1; 207 u8 rsvd0: 4; 208 u8 pkt_id[RTW89_SCANOFLD_MAX_SSID]; 209 u16 tx_pwr_idx; 210 u8 rsvd1; 211 struct list_head list; 212 }; 213 214 struct rtw89_scan_option { 215 bool enable; 216 bool target_ch_mode; 217 }; 218 219 struct rtw89_pktofld_info { 220 struct list_head list; 221 u8 id; 222 }; 223 224 static inline void RTW89_SET_FWCMD_RA_IS_DIS(void *cmd, u32 val) 225 { 226 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(0)); 227 } 228 229 static inline void RTW89_SET_FWCMD_RA_MODE(void *cmd, u32 val) 230 { 231 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(5, 1)); 232 } 233 234 static inline void RTW89_SET_FWCMD_RA_BW_CAP(void *cmd, u32 val) 235 { 236 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 6)); 237 } 238 239 static inline void RTW89_SET_FWCMD_RA_MACID(void *cmd, u32 val) 240 { 241 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); 242 } 243 244 static inline void RTW89_SET_FWCMD_RA_DCM(void *cmd, u32 val) 245 { 246 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(16)); 247 } 248 249 static inline void RTW89_SET_FWCMD_RA_ER(void *cmd, u32 val) 250 { 251 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(17)); 252 } 253 254 static inline void RTW89_SET_FWCMD_RA_INIT_RATE_LV(void *cmd, u32 val) 255 { 256 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(19, 18)); 257 } 258 259 static inline void RTW89_SET_FWCMD_RA_UPD_ALL(void *cmd, u32 val) 260 { 261 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(20)); 262 } 263 264 static inline void RTW89_SET_FWCMD_RA_SGI(void *cmd, u32 val) 265 { 266 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(21)); 267 } 268 269 static inline void RTW89_SET_FWCMD_RA_LDPC(void *cmd, u32 val) 270 { 271 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(22)); 272 } 273 274 static inline void RTW89_SET_FWCMD_RA_STBC(void *cmd, u32 val) 275 { 276 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(23)); 277 } 278 279 static inline void RTW89_SET_FWCMD_RA_SS_NUM(void *cmd, u32 val) 280 { 281 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(26, 24)); 282 } 283 284 static inline void RTW89_SET_FWCMD_RA_GILTF(void *cmd, u32 val) 285 { 286 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(29, 27)); 287 } 288 289 static inline void RTW89_SET_FWCMD_RA_UPD_BW_NSS_MASK(void *cmd, u32 val) 290 { 291 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(30)); 292 } 293 294 static inline void RTW89_SET_FWCMD_RA_UPD_MASK(void *cmd, u32 val) 295 { 296 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(31)); 297 } 298 299 static inline void RTW89_SET_FWCMD_RA_MASK_0(void *cmd, u32 val) 300 { 301 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(7, 0)); 302 } 303 304 static inline void RTW89_SET_FWCMD_RA_MASK_1(void *cmd, u32 val) 305 { 306 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(15, 8)); 307 } 308 309 static inline void RTW89_SET_FWCMD_RA_MASK_2(void *cmd, u32 val) 310 { 311 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(23, 16)); 312 } 313 314 static inline void RTW89_SET_FWCMD_RA_MASK_3(void *cmd, u32 val) 315 { 316 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 24)); 317 } 318 319 static inline void RTW89_SET_FWCMD_RA_MASK_4(void *cmd, u32 val) 320 { 321 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(7, 0)); 322 } 323 324 static inline void RTW89_SET_FWCMD_RA_BFEE_CSI_CTL(void *cmd, u32 val) 325 { 326 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, BIT(31)); 327 } 328 329 static inline void RTW89_SET_FWCMD_RA_BAND_NUM(void *cmd, u32 val) 330 { 331 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(7, 0)); 332 } 333 334 static inline void RTW89_SET_FWCMD_RA_RA_CSI_RATE_EN(void *cmd, u32 val) 335 { 336 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(8)); 337 } 338 339 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_RATE_EN(void *cmd, u32 val) 340 { 341 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(9)); 342 } 343 344 static inline void RTW89_SET_FWCMD_RA_CR_TBL_SEL(void *cmd, u32 val) 345 { 346 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, BIT(10)); 347 } 348 349 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MCS_SS_IDX(void *cmd, u32 val) 350 { 351 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(23, 16)); 352 } 353 354 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_MODE(void *cmd, u32 val) 355 { 356 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(25, 24)); 357 } 358 359 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_GI_LTF(void *cmd, u32 val) 360 { 361 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(28, 26)); 362 } 363 364 static inline void RTW89_SET_FWCMD_RA_FIXED_CSI_BW(void *cmd, u32 val) 365 { 366 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 29)); 367 } 368 369 static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val) 370 { 371 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(7, 0)); 372 } 373 374 static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val) 375 { 376 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(15, 8)); 377 } 378 379 static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val) 380 { 381 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(23, 16)); 382 } 383 384 static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val) 385 { 386 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(3, 0)); 387 } 388 389 static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val) 390 { 391 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(4)); 392 } 393 394 static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val) 395 { 396 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, BIT(5)); 397 } 398 399 static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val) 400 { 401 le32p_replace_bits((__le32 *)(cmd) + 0x02, val, GENMASK(31, 0)); 402 } 403 404 static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val) 405 { 406 le32p_replace_bits((__le32 *)(cmd) + 0x03, val, GENMASK(31, 0)); 407 } 408 409 static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val) 410 { 411 le32p_replace_bits((__le32 *)(cmd) + 0x04, val, GENMASK(31, 0)); 412 } 413 414 static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val) 415 { 416 le32p_replace_bits((__le32 *)(cmd) + 0x05, val, GENMASK(31, 0)); 417 } 418 419 static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val) 420 { 421 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(1, 0)); 422 } 423 424 static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val) 425 { 426 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(3)); 427 } 428 429 static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val) 430 { 431 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, BIT(4)); 432 } 433 434 static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val) 435 { 436 le32p_replace_bits((__le32 *)(cmd) + 0x00, val, GENMASK(6, 5)); 437 } 438 439 static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val) 440 { 441 le32p_replace_bits((__le32 *)(cmd) + 0x01, val, GENMASK(31, 0)); 442 } 443 #define FW_EDCA_PARAM_TXOPLMT_MSK GENMASK(26, 16) 444 #define FW_EDCA_PARAM_CWMAX_MSK GENMASK(15, 12) 445 #define FW_EDCA_PARAM_CWMIN_MSK GENMASK(11, 8) 446 #define FW_EDCA_PARAM_AIFS_MSK GENMASK(7, 0) 447 448 #define GET_FWSECTION_HDR_SEC_SIZE(fwhdr) \ 449 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 0)) 450 #define GET_FWSECTION_HDR_CHECKSUM(fwhdr) \ 451 le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(28)) 452 #define GET_FWSECTION_HDR_REDL(fwhdr) \ 453 le32_get_bits(*((const __le32 *)(fwhdr) + 1), BIT(29)) 454 #define GET_FWSECTION_HDR_DL_ADDR(fwhdr) \ 455 le32_get_bits(*((const __le32 *)(fwhdr)), GENMASK(31, 0)) 456 457 #define GET_FW_HDR_MAJOR_VERSION(fwhdr) \ 458 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(7, 0)) 459 #define GET_FW_HDR_MINOR_VERSION(fwhdr) \ 460 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(15, 8)) 461 #define GET_FW_HDR_SUBVERSION(fwhdr) \ 462 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(23, 16)) 463 #define GET_FW_HDR_SUBINDEX(fwhdr) \ 464 le32_get_bits(*((const __le32 *)(fwhdr) + 1), GENMASK(31, 24)) 465 #define GET_FW_HDR_MONTH(fwhdr) \ 466 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(7, 0)) 467 #define GET_FW_HDR_DATE(fwhdr) \ 468 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(15, 8)) 469 #define GET_FW_HDR_HOUR(fwhdr) \ 470 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(23, 16)) 471 #define GET_FW_HDR_MIN(fwhdr) \ 472 le32_get_bits(*((const __le32 *)(fwhdr) + 4), GENMASK(31, 24)) 473 #define GET_FW_HDR_YEAR(fwhdr) \ 474 le32_get_bits(*((const __le32 *)(fwhdr) + 5), GENMASK(31, 0)) 475 #define GET_FW_HDR_SEC_NUM(fwhdr) \ 476 le32_get_bits(*((const __le32 *)(fwhdr) + 6), GENMASK(15, 8)) 477 #define GET_FW_HDR_CMD_VERSERION(fwhdr) \ 478 le32_get_bits(*((const __le32 *)(fwhdr) + 7), GENMASK(31, 24)) 479 static inline void SET_FW_HDR_PART_SIZE(void *fwhdr, u32 val) 480 { 481 le32p_replace_bits((__le32 *)fwhdr + 7, val, GENMASK(15, 0)); 482 } 483 484 static inline void SET_CTRL_INFO_MACID(void *table, u32 val) 485 { 486 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)); 487 } 488 489 static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val) 490 { 491 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)); 492 } 493 #define SET_CMC_TBL_MASK_DATARATE GENMASK(8, 0) 494 static inline void SET_CMC_TBL_DATARATE(void *table, u32 val) 495 { 496 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(8, 0)); 497 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATARATE, 498 GENMASK(8, 0)); 499 } 500 #define SET_CMC_TBL_MASK_FORCE_TXOP BIT(0) 501 static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val) 502 { 503 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(9)); 504 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_FORCE_TXOP, 505 BIT(9)); 506 } 507 #define SET_CMC_TBL_MASK_DATA_BW GENMASK(1, 0) 508 static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val) 509 { 510 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(11, 10)); 511 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_BW, 512 GENMASK(11, 10)); 513 } 514 #define SET_CMC_TBL_MASK_DATA_GI_LTF GENMASK(2, 0) 515 static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val) 516 { 517 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 12)); 518 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DATA_GI_LTF, 519 GENMASK(14, 12)); 520 } 521 #define SET_CMC_TBL_MASK_DARF_TC_INDEX BIT(0) 522 static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val) 523 { 524 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); 525 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DARF_TC_INDEX, 526 BIT(15)); 527 } 528 #define SET_CMC_TBL_MASK_ARFR_CTRL GENMASK(3, 0) 529 static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val) 530 { 531 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(19, 16)); 532 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ARFR_CTRL, 533 GENMASK(19, 16)); 534 } 535 #define SET_CMC_TBL_MASK_ACQ_RPT_EN BIT(0) 536 static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val) 537 { 538 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(20)); 539 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ACQ_RPT_EN, 540 BIT(20)); 541 } 542 #define SET_CMC_TBL_MASK_MGQ_RPT_EN BIT(0) 543 static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val) 544 { 545 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(21)); 546 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_MGQ_RPT_EN, 547 BIT(21)); 548 } 549 #define SET_CMC_TBL_MASK_ULQ_RPT_EN BIT(0) 550 static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val) 551 { 552 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(22)); 553 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_ULQ_RPT_EN, 554 BIT(22)); 555 } 556 #define SET_CMC_TBL_MASK_TWTQ_RPT_EN BIT(0) 557 static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val) 558 { 559 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(23)); 560 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TWTQ_RPT_EN, 561 BIT(23)); 562 } 563 #define SET_CMC_TBL_MASK_DISRTSFB BIT(0) 564 static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val) 565 { 566 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(25)); 567 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISRTSFB, 568 BIT(25)); 569 } 570 #define SET_CMC_TBL_MASK_DISDATAFB BIT(0) 571 static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val) 572 { 573 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(26)); 574 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_DISDATAFB, 575 BIT(26)); 576 } 577 #define SET_CMC_TBL_MASK_TRYRATE BIT(0) 578 static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val) 579 { 580 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(27)); 581 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_TRYRATE, 582 BIT(27)); 583 } 584 #define SET_CMC_TBL_MASK_AMPDU_DENSITY GENMASK(3, 0) 585 static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val) 586 { 587 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 28)); 588 le32p_replace_bits((__le32 *)(table) + 9, SET_CMC_TBL_MASK_AMPDU_DENSITY, 589 GENMASK(31, 28)); 590 } 591 #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE GENMASK(8, 0) 592 static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val) 593 { 594 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(8, 0)); 595 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE, 596 GENMASK(8, 0)); 597 } 598 #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL BIT(0) 599 static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val) 600 { 601 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(9)); 602 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_TIME_SEL, 603 BIT(9)); 604 } 605 #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL BIT(0) 606 static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val) 607 { 608 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(10)); 609 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_AMPDU_LEN_SEL, 610 BIT(10)); 611 } 612 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL BIT(0) 613 static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val) 614 { 615 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(11)); 616 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL, 617 BIT(11)); 618 } 619 #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT GENMASK(3, 0) 620 static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val) 621 { 622 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(15, 12)); 623 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_TXCNT_LMT, 624 GENMASK(15, 12)); 625 } 626 #define SET_CMC_TBL_MASK_RTSRATE GENMASK(8, 0) 627 static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val) 628 { 629 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(24, 16)); 630 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTSRATE, 631 GENMASK(24, 16)); 632 } 633 #define SET_CMC_TBL_MASK_VCS_STBC BIT(0) 634 static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val) 635 { 636 le32p_replace_bits((__le32 *)(table) + 2, val, BIT(27)); 637 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_VCS_STBC, 638 BIT(27)); 639 } 640 #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE GENMASK(3, 0) 641 static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val) 642 { 643 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 28)); 644 le32p_replace_bits((__le32 *)(table) + 10, SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE, 645 GENMASK(31, 28)); 646 } 647 #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT GENMASK(5, 0) 648 static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val) 649 { 650 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(5, 0)); 651 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TX_CNT_LMT, 652 GENMASK(5, 0)); 653 } 654 #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL BIT(0) 655 static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val) 656 { 657 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(6)); 658 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL, 659 BIT(6)); 660 } 661 #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL BIT(0) 662 static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val) 663 { 664 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(7)); 665 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL, 666 BIT(7)); 667 } 668 #define SET_CMC_TBL_MASK_RTS_EN BIT(0) 669 static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val) 670 { 671 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(8)); 672 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_EN, 673 BIT(8)); 674 } 675 #define SET_CMC_TBL_MASK_CTS2SELF_EN BIT(0) 676 static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val) 677 { 678 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(9)); 679 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CTS2SELF_EN, 680 BIT(9)); 681 } 682 #define SET_CMC_TBL_MASK_CCA_RTS GENMASK(1, 0) 683 static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val) 684 { 685 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 10)); 686 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_CCA_RTS, 687 GENMASK(11, 10)); 688 } 689 #define SET_CMC_TBL_MASK_HW_RTS_EN BIT(0) 690 static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val) 691 { 692 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(12)); 693 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_HW_RTS_EN, 694 BIT(12)); 695 } 696 #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE GENMASK(1, 0) 697 static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val) 698 { 699 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(14, 13)); 700 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE, 701 GENMASK(14, 13)); 702 } 703 #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN GENMASK(10, 0) 704 static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val) 705 { 706 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 16)); 707 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_LEN, 708 GENMASK(26, 16)); 709 } 710 #define SET_CMC_TBL_MASK_UL_MU_DIS BIT(0) 711 static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val) 712 { 713 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); 714 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_UL_MU_DIS, 715 BIT(27)); 716 } 717 #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME GENMASK(3, 0) 718 static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val) 719 { 720 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(31, 28)); 721 le32p_replace_bits((__le32 *)(table) + 11, SET_CMC_TBL_MASK_AMPDU_MAX_TIME, 722 GENMASK(31, 28)); 723 } 724 #define SET_CMC_TBL_MASK_MAX_AGG_NUM GENMASK(7, 0) 725 static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val) 726 { 727 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(7, 0)); 728 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_MAX_AGG_NUM, 729 GENMASK(7, 0)); 730 } 731 #define SET_CMC_TBL_MASK_BA_BMAP GENMASK(1, 0) 732 static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val) 733 { 734 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(9, 8)); 735 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BA_BMAP, 736 GENMASK(9, 8)); 737 } 738 #define SET_CMC_TBL_MASK_VO_LFTIME_SEL GENMASK(2, 0) 739 static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val) 740 { 741 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(18, 16)); 742 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VO_LFTIME_SEL, 743 GENMASK(18, 16)); 744 } 745 #define SET_CMC_TBL_MASK_VI_LFTIME_SEL GENMASK(2, 0) 746 static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val) 747 { 748 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(21, 19)); 749 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_VI_LFTIME_SEL, 750 GENMASK(21, 19)); 751 } 752 #define SET_CMC_TBL_MASK_BE_LFTIME_SEL GENMASK(2, 0) 753 static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val) 754 { 755 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(24, 22)); 756 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BE_LFTIME_SEL, 757 GENMASK(24, 22)); 758 } 759 #define SET_CMC_TBL_MASK_BK_LFTIME_SEL GENMASK(2, 0) 760 static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val) 761 { 762 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 25)); 763 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_BK_LFTIME_SEL, 764 GENMASK(27, 25)); 765 } 766 #define SET_CMC_TBL_MASK_SECTYPE GENMASK(3, 0) 767 static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val) 768 { 769 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 28)); 770 le32p_replace_bits((__le32 *)(table) + 12, SET_CMC_TBL_MASK_SECTYPE, 771 GENMASK(31, 28)); 772 } 773 #define SET_CMC_TBL_MASK_MULTI_PORT_ID GENMASK(2, 0) 774 static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val) 775 { 776 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(2, 0)); 777 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MULTI_PORT_ID, 778 GENMASK(2, 0)); 779 } 780 #define SET_CMC_TBL_MASK_BMC BIT(0) 781 static inline void SET_CMC_TBL_BMC(void *table, u32 val) 782 { 783 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(3)); 784 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_BMC, 785 BIT(3)); 786 } 787 #define SET_CMC_TBL_MASK_MBSSID GENMASK(3, 0) 788 static inline void SET_CMC_TBL_MBSSID(void *table, u32 val) 789 { 790 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 4)); 791 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_MBSSID, 792 GENMASK(7, 4)); 793 } 794 #define SET_CMC_TBL_MASK_NAVUSEHDR BIT(0) 795 static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val) 796 { 797 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); 798 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_NAVUSEHDR, 799 BIT(8)); 800 } 801 #define SET_CMC_TBL_MASK_TXPWR_MODE GENMASK(2, 0) 802 static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val) 803 { 804 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(11, 9)); 805 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_TXPWR_MODE, 806 GENMASK(11, 9)); 807 } 808 #define SET_CMC_TBL_MASK_DATA_DCM BIT(0) 809 static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val) 810 { 811 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(12)); 812 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_DCM, 813 BIT(12)); 814 } 815 #define SET_CMC_TBL_MASK_DATA_ER BIT(0) 816 static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val) 817 { 818 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(13)); 819 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_ER, 820 BIT(13)); 821 } 822 #define SET_CMC_TBL_MASK_DATA_LDPC BIT(0) 823 static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val) 824 { 825 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(14)); 826 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_LDPC, 827 BIT(14)); 828 } 829 #define SET_CMC_TBL_MASK_DATA_STBC BIT(0) 830 static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val) 831 { 832 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); 833 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_STBC, 834 BIT(15)); 835 } 836 #define SET_CMC_TBL_MASK_A_CTRL_BQR BIT(0) 837 static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val) 838 { 839 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(16)); 840 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BQR, 841 BIT(16)); 842 } 843 #define SET_CMC_TBL_MASK_A_CTRL_UPH BIT(0) 844 static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val) 845 { 846 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(17)); 847 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_UPH, 848 BIT(17)); 849 } 850 #define SET_CMC_TBL_MASK_A_CTRL_BSR BIT(0) 851 static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val) 852 { 853 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(18)); 854 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_BSR, 855 BIT(18)); 856 } 857 #define SET_CMC_TBL_MASK_A_CTRL_CAS BIT(0) 858 static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val) 859 { 860 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(19)); 861 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_A_CTRL_CAS, 862 BIT(19)); 863 } 864 #define SET_CMC_TBL_MASK_DATA_BW_ER BIT(0) 865 static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val) 866 { 867 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(20)); 868 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_DATA_BW_ER, 869 BIT(20)); 870 } 871 #define SET_CMC_TBL_MASK_LSIG_TXOP_EN BIT(0) 872 static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val) 873 { 874 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(21)); 875 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_LSIG_TXOP_EN, 876 BIT(21)); 877 } 878 #define SET_CMC_TBL_MASK_CTRL_CNT_VLD BIT(0) 879 static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val) 880 { 881 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(27)); 882 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT_VLD, 883 BIT(27)); 884 } 885 #define SET_CMC_TBL_MASK_CTRL_CNT GENMASK(3, 0) 886 static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val) 887 { 888 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 28)); 889 le32p_replace_bits((__le32 *)(table) + 13, SET_CMC_TBL_MASK_CTRL_CNT, 890 GENMASK(31, 28)); 891 } 892 #define SET_CMC_TBL_MASK_RESP_REF_RATE GENMASK(8, 0) 893 static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val) 894 { 895 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(8, 0)); 896 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_RESP_REF_RATE, 897 GENMASK(8, 0)); 898 } 899 #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT BIT(0) 900 static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val) 901 { 902 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(12)); 903 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ALL_ACK_SUPPORT, 904 BIT(12)); 905 } 906 #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT BIT(0) 907 static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val) 908 { 909 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(13)); 910 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT, 911 BIT(13)); 912 } 913 #define SET_CMC_TBL_MASK_NTX_PATH_EN GENMASK(3, 0) 914 static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val) 915 { 916 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(19, 16)); 917 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_NTX_PATH_EN, 918 GENMASK(19, 16)); 919 } 920 #define SET_CMC_TBL_MASK_PATH_MAP_A GENMASK(1, 0) 921 static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val) 922 { 923 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(21, 20)); 924 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_A, 925 GENMASK(21, 20)); 926 } 927 #define SET_CMC_TBL_MASK_PATH_MAP_B GENMASK(1, 0) 928 static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val) 929 { 930 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 22)); 931 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_B, 932 GENMASK(23, 22)); 933 } 934 #define SET_CMC_TBL_MASK_PATH_MAP_C GENMASK(1, 0) 935 static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val) 936 { 937 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(25, 24)); 938 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_C, 939 GENMASK(25, 24)); 940 } 941 #define SET_CMC_TBL_MASK_PATH_MAP_D GENMASK(1, 0) 942 static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val) 943 { 944 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(27, 26)); 945 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_PATH_MAP_D, 946 GENMASK(27, 26)); 947 } 948 #define SET_CMC_TBL_MASK_ANTSEL_A BIT(0) 949 static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val) 950 { 951 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(28)); 952 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_A, 953 BIT(28)); 954 } 955 #define SET_CMC_TBL_MASK_ANTSEL_B BIT(0) 956 static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val) 957 { 958 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(29)); 959 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_B, 960 BIT(29)); 961 } 962 #define SET_CMC_TBL_MASK_ANTSEL_C BIT(0) 963 static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val) 964 { 965 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(30)); 966 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_C, 967 BIT(30)); 968 } 969 #define SET_CMC_TBL_MASK_ANTSEL_D BIT(0) 970 static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val) 971 { 972 le32p_replace_bits((__le32 *)(table) + 6, val, BIT(31)); 973 le32p_replace_bits((__le32 *)(table) + 14, SET_CMC_TBL_MASK_ANTSEL_D, 974 BIT(31)); 975 } 976 977 #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING GENMASK(1, 0) 978 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val) 979 { 980 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(1, 0)); 981 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 982 GENMASK(1, 0)); 983 } 984 985 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val) 986 { 987 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(3, 2)); 988 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 989 GENMASK(3, 2)); 990 } 991 992 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val) 993 { 994 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(5, 4)); 995 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 996 GENMASK(5, 4)); 997 } 998 999 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val) 1000 { 1001 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 6)); 1002 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1003 GENMASK(7, 6)); 1004 } 1005 1006 #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX GENMASK(7, 0) 1007 static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val) 1008 { 1009 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); 1010 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ADDR_CAM_INDEX, 1011 GENMASK(7, 0)); 1012 } 1013 #define SET_CMC_TBL_MASK_PAID GENMASK(8, 0) 1014 static inline void SET_CMC_TBL_PAID(void *table, u32 val) 1015 { 1016 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(16, 8)); 1017 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_PAID, 1018 GENMASK(16, 8)); 1019 } 1020 #define SET_CMC_TBL_MASK_ULDL BIT(0) 1021 static inline void SET_CMC_TBL_ULDL(void *table, u32 val) 1022 { 1023 le32p_replace_bits((__le32 *)(table) + 7, val, BIT(17)); 1024 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_ULDL, 1025 BIT(17)); 1026 } 1027 #define SET_CMC_TBL_MASK_DOPPLER_CTRL GENMASK(1, 0) 1028 static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val) 1029 { 1030 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(19, 18)); 1031 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_DOPPLER_CTRL, 1032 GENMASK(19, 18)); 1033 } 1034 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val) 1035 { 1036 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(21, 20)); 1037 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1038 GENMASK(21, 20)); 1039 } 1040 1041 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val) 1042 { 1043 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 22)); 1044 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1045 GENMASK(23, 22)); 1046 } 1047 #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE GENMASK(3, 0) 1048 static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val) 1049 { 1050 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(27, 24)); 1051 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_TXPWR_TOLERENCE, 1052 GENMASK(27, 24)); 1053 } 1054 1055 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val) 1056 { 1057 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 30)); 1058 le32p_replace_bits((__le32 *)(table) + 15, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1059 GENMASK(31, 30)); 1060 } 1061 #define SET_CMC_TBL_MASK_NC GENMASK(2, 0) 1062 static inline void SET_CMC_TBL_NC(void *table, u32 val) 1063 { 1064 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(2, 0)); 1065 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NC, 1066 GENMASK(2, 0)); 1067 } 1068 #define SET_CMC_TBL_MASK_NR GENMASK(2, 0) 1069 static inline void SET_CMC_TBL_NR(void *table, u32 val) 1070 { 1071 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(5, 3)); 1072 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NR, 1073 GENMASK(5, 3)); 1074 } 1075 #define SET_CMC_TBL_MASK_NG GENMASK(1, 0) 1076 static inline void SET_CMC_TBL_NG(void *table, u32 val) 1077 { 1078 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(7, 6)); 1079 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NG, 1080 GENMASK(7, 6)); 1081 } 1082 #define SET_CMC_TBL_MASK_CB GENMASK(1, 0) 1083 static inline void SET_CMC_TBL_CB(void *table, u32 val) 1084 { 1085 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(9, 8)); 1086 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CB, 1087 GENMASK(9, 8)); 1088 } 1089 #define SET_CMC_TBL_MASK_CS GENMASK(1, 0) 1090 static inline void SET_CMC_TBL_CS(void *table, u32 val) 1091 { 1092 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(11, 10)); 1093 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CS, 1094 GENMASK(11, 10)); 1095 } 1096 #define SET_CMC_TBL_MASK_CSI_TXBF_EN BIT(0) 1097 static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val) 1098 { 1099 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(12)); 1100 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_TXBF_EN, 1101 BIT(12)); 1102 } 1103 #define SET_CMC_TBL_MASK_CSI_STBC_EN BIT(0) 1104 static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val) 1105 { 1106 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(13)); 1107 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_STBC_EN, 1108 BIT(13)); 1109 } 1110 #define SET_CMC_TBL_MASK_CSI_LDPC_EN BIT(0) 1111 static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val) 1112 { 1113 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(14)); 1114 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_LDPC_EN, 1115 BIT(14)); 1116 } 1117 #define SET_CMC_TBL_MASK_CSI_PARA_EN BIT(0) 1118 static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val) 1119 { 1120 le32p_replace_bits((__le32 *)(table) + 8, val, BIT(15)); 1121 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_PARA_EN, 1122 BIT(15)); 1123 } 1124 #define SET_CMC_TBL_MASK_CSI_FIX_RATE GENMASK(8, 0) 1125 static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val) 1126 { 1127 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(24, 16)); 1128 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_FIX_RATE, 1129 GENMASK(24, 16)); 1130 } 1131 #define SET_CMC_TBL_MASK_CSI_GI_LTF GENMASK(2, 0) 1132 static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val) 1133 { 1134 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(27, 25)); 1135 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_GI_LTF, 1136 GENMASK(27, 25)); 1137 } 1138 1139 static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val) 1140 { 1141 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(29, 28)); 1142 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING, 1143 GENMASK(29, 28)); 1144 } 1145 1146 #define SET_CMC_TBL_MASK_CSI_BW GENMASK(1, 0) 1147 static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val) 1148 { 1149 le32p_replace_bits((__le32 *)(table) + 8, val, GENMASK(31, 30)); 1150 le32p_replace_bits((__le32 *)(table) + 16, SET_CMC_TBL_MASK_CSI_BW, 1151 GENMASK(31, 30)); 1152 } 1153 1154 static inline void SET_DCTL_MACID_V1(void *table, u32 val) 1155 { 1156 le32p_replace_bits((__le32 *)(table) + 0, val, GENMASK(6, 0)); 1157 } 1158 1159 static inline void SET_DCTL_OPERATION_V1(void *table, u32 val) 1160 { 1161 le32p_replace_bits((__le32 *)(table) + 0, val, BIT(7)); 1162 } 1163 1164 #define SET_DCTL_MASK_QOS_FIELD_V1 GENMASK(7, 0) 1165 static inline void SET_DCTL_QOS_FIELD_V1(void *table, u32 val) 1166 { 1167 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(7, 0)); 1168 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_FIELD_V1, 1169 GENMASK(7, 0)); 1170 } 1171 1172 #define SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID GENMASK(6, 0) 1173 static inline void SET_DCTL_HW_EXSEQ_MACID_V1(void *table, u32 val) 1174 { 1175 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(14, 8)); 1176 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_SET_DCTL_HW_EXSEQ_MACID, 1177 GENMASK(14, 8)); 1178 } 1179 1180 #define SET_DCTL_MASK_QOS_DATA BIT(0) 1181 static inline void SET_DCTL_QOS_DATA_V1(void *table, u32 val) 1182 { 1183 le32p_replace_bits((__le32 *)(table) + 1, val, BIT(15)); 1184 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_QOS_DATA, 1185 BIT(15)); 1186 } 1187 1188 #define SET_DCTL_MASK_AES_IV_L GENMASK(15, 0) 1189 static inline void SET_DCTL_AES_IV_L_V1(void *table, u32 val) 1190 { 1191 le32p_replace_bits((__le32 *)(table) + 1, val, GENMASK(31, 16)); 1192 le32p_replace_bits((__le32 *)(table) + 9, SET_DCTL_MASK_AES_IV_L, 1193 GENMASK(31, 16)); 1194 } 1195 1196 #define SET_DCTL_MASK_AES_IV_H GENMASK(31, 0) 1197 static inline void SET_DCTL_AES_IV_H_V1(void *table, u32 val) 1198 { 1199 le32p_replace_bits((__le32 *)(table) + 2, val, GENMASK(31, 0)); 1200 le32p_replace_bits((__le32 *)(table) + 10, SET_DCTL_MASK_AES_IV_H, 1201 GENMASK(31, 0)); 1202 } 1203 1204 #define SET_DCTL_MASK_SEQ0 GENMASK(11, 0) 1205 static inline void SET_DCTL_SEQ0_V1(void *table, u32 val) 1206 { 1207 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(11, 0)); 1208 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ0, 1209 GENMASK(11, 0)); 1210 } 1211 1212 #define SET_DCTL_MASK_SEQ1 GENMASK(11, 0) 1213 static inline void SET_DCTL_SEQ1_V1(void *table, u32 val) 1214 { 1215 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(23, 12)); 1216 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_SEQ1, 1217 GENMASK(23, 12)); 1218 } 1219 1220 #define SET_DCTL_MASK_AMSDU_MAX_LEN GENMASK(2, 0) 1221 static inline void SET_DCTL_AMSDU_MAX_LEN_V1(void *table, u32 val) 1222 { 1223 le32p_replace_bits((__le32 *)(table) + 3, val, GENMASK(26, 24)); 1224 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_AMSDU_MAX_LEN, 1225 GENMASK(26, 24)); 1226 } 1227 1228 #define SET_DCTL_MASK_STA_AMSDU_EN BIT(0) 1229 static inline void SET_DCTL_STA_AMSDU_EN_V1(void *table, u32 val) 1230 { 1231 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(27)); 1232 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_STA_AMSDU_EN, 1233 BIT(27)); 1234 } 1235 1236 #define SET_DCTL_MASK_CHKSUM_OFLD_EN BIT(0) 1237 static inline void SET_DCTL_CHKSUM_OFLD_EN_V1(void *table, u32 val) 1238 { 1239 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(28)); 1240 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_CHKSUM_OFLD_EN, 1241 BIT(28)); 1242 } 1243 1244 #define SET_DCTL_MASK_WITH_LLC BIT(0) 1245 static inline void SET_DCTL_WITH_LLC_V1(void *table, u32 val) 1246 { 1247 le32p_replace_bits((__le32 *)(table) + 3, val, BIT(29)); 1248 le32p_replace_bits((__le32 *)(table) + 11, SET_DCTL_MASK_WITH_LLC, 1249 BIT(29)); 1250 } 1251 1252 #define SET_DCTL_MASK_SEQ2 GENMASK(11, 0) 1253 static inline void SET_DCTL_SEQ2_V1(void *table, u32 val) 1254 { 1255 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(11, 0)); 1256 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ2, 1257 GENMASK(11, 0)); 1258 } 1259 1260 #define SET_DCTL_MASK_SEQ3 GENMASK(11, 0) 1261 static inline void SET_DCTL_SEQ3_V1(void *table, u32 val) 1262 { 1263 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(23, 12)); 1264 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_SEQ3, 1265 GENMASK(23, 12)); 1266 } 1267 1268 #define SET_DCTL_MASK_TGT_IND GENMASK(3, 0) 1269 static inline void SET_DCTL_TGT_IND_V1(void *table, u32 val) 1270 { 1271 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(27, 24)); 1272 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND, 1273 GENMASK(27, 24)); 1274 } 1275 1276 #define SET_DCTL_MASK_TGT_IND_EN BIT(0) 1277 static inline void SET_DCTL_TGT_IND_EN_V1(void *table, u32 val) 1278 { 1279 le32p_replace_bits((__le32 *)(table) + 4, val, BIT(28)); 1280 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_TGT_IND_EN, 1281 BIT(28)); 1282 } 1283 1284 #define SET_DCTL_MASK_HTC_LB GENMASK(2, 0) 1285 static inline void SET_DCTL_HTC_LB_V1(void *table, u32 val) 1286 { 1287 le32p_replace_bits((__le32 *)(table) + 4, val, GENMASK(31, 29)); 1288 le32p_replace_bits((__le32 *)(table) + 12, SET_DCTL_MASK_HTC_LB, 1289 GENMASK(31, 29)); 1290 } 1291 1292 #define SET_DCTL_MASK_MHDR_LEN GENMASK(4, 0) 1293 static inline void SET_DCTL_MHDR_LEN_V1(void *table, u32 val) 1294 { 1295 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(4, 0)); 1296 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_MHDR_LEN, 1297 GENMASK(4, 0)); 1298 } 1299 1300 #define SET_DCTL_MASK_VLAN_TAG_VALID BIT(0) 1301 static inline void SET_DCTL_VLAN_TAG_VALID_V1(void *table, u32 val) 1302 { 1303 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(5)); 1304 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_VALID, 1305 BIT(5)); 1306 } 1307 1308 #define SET_DCTL_MASK_VLAN_TAG_SEL GENMASK(1, 0) 1309 static inline void SET_DCTL_VLAN_TAG_SEL_V1(void *table, u32 val) 1310 { 1311 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(7, 6)); 1312 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_VLAN_TAG_SEL, 1313 GENMASK(7, 6)); 1314 } 1315 1316 #define SET_DCTL_MASK_HTC_ORDER BIT(0) 1317 static inline void SET_DCTL_HTC_ORDER_V1(void *table, u32 val) 1318 { 1319 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(8)); 1320 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_HTC_ORDER, 1321 BIT(8)); 1322 } 1323 1324 #define SET_DCTL_MASK_SEC_KEY_ID GENMASK(1, 0) 1325 static inline void SET_DCTL_SEC_KEY_ID_V1(void *table, u32 val) 1326 { 1327 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(10, 9)); 1328 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_KEY_ID, 1329 GENMASK(10, 9)); 1330 } 1331 1332 #define SET_DCTL_MASK_WAPI BIT(0) 1333 static inline void SET_DCTL_WAPI_V1(void *table, u32 val) 1334 { 1335 le32p_replace_bits((__le32 *)(table) + 5, val, BIT(15)); 1336 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_WAPI, 1337 BIT(15)); 1338 } 1339 1340 #define SET_DCTL_MASK_SEC_ENT_MODE GENMASK(1, 0) 1341 static inline void SET_DCTL_SEC_ENT_MODE_V1(void *table, u32 val) 1342 { 1343 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(17, 16)); 1344 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENT_MODE, 1345 GENMASK(17, 16)); 1346 } 1347 1348 #define SET_DCTL_MASK_SEC_ENTX_KEYID GENMASK(1, 0) 1349 static inline void SET_DCTL_SEC_ENT0_KEYID_V1(void *table, u32 val) 1350 { 1351 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(19, 18)); 1352 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1353 GENMASK(19, 18)); 1354 } 1355 1356 static inline void SET_DCTL_SEC_ENT1_KEYID_V1(void *table, u32 val) 1357 { 1358 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(21, 20)); 1359 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1360 GENMASK(21, 20)); 1361 } 1362 1363 static inline void SET_DCTL_SEC_ENT2_KEYID_V1(void *table, u32 val) 1364 { 1365 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(23, 22)); 1366 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1367 GENMASK(23, 22)); 1368 } 1369 1370 static inline void SET_DCTL_SEC_ENT3_KEYID_V1(void *table, u32 val) 1371 { 1372 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(25, 24)); 1373 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1374 GENMASK(25, 24)); 1375 } 1376 1377 static inline void SET_DCTL_SEC_ENT4_KEYID_V1(void *table, u32 val) 1378 { 1379 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(27, 26)); 1380 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1381 GENMASK(27, 26)); 1382 } 1383 1384 static inline void SET_DCTL_SEC_ENT5_KEYID_V1(void *table, u32 val) 1385 { 1386 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(29, 28)); 1387 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1388 GENMASK(29, 28)); 1389 } 1390 1391 static inline void SET_DCTL_SEC_ENT6_KEYID_V1(void *table, u32 val) 1392 { 1393 le32p_replace_bits((__le32 *)(table) + 5, val, GENMASK(31, 30)); 1394 le32p_replace_bits((__le32 *)(table) + 13, SET_DCTL_MASK_SEC_ENTX_KEYID, 1395 GENMASK(31, 30)); 1396 } 1397 1398 #define SET_DCTL_MASK_SEC_ENT_VALID GENMASK(7, 0) 1399 static inline void SET_DCTL_SEC_ENT_VALID_V1(void *table, u32 val) 1400 { 1401 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(7, 0)); 1402 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENT_VALID, 1403 GENMASK(7, 0)); 1404 } 1405 1406 #define SET_DCTL_MASK_SEC_ENTX GENMASK(7, 0) 1407 static inline void SET_DCTL_SEC_ENT0_V1(void *table, u32 val) 1408 { 1409 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(15, 8)); 1410 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1411 GENMASK(15, 8)); 1412 } 1413 1414 static inline void SET_DCTL_SEC_ENT1_V1(void *table, u32 val) 1415 { 1416 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(23, 16)); 1417 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1418 GENMASK(23, 16)); 1419 } 1420 1421 static inline void SET_DCTL_SEC_ENT2_V1(void *table, u32 val) 1422 { 1423 le32p_replace_bits((__le32 *)(table) + 6, val, GENMASK(31, 24)); 1424 le32p_replace_bits((__le32 *)(table) + 14, SET_DCTL_MASK_SEC_ENTX, 1425 GENMASK(31, 24)); 1426 } 1427 1428 static inline void SET_DCTL_SEC_ENT3_V1(void *table, u32 val) 1429 { 1430 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(7, 0)); 1431 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1432 GENMASK(7, 0)); 1433 } 1434 1435 static inline void SET_DCTL_SEC_ENT4_V1(void *table, u32 val) 1436 { 1437 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(15, 8)); 1438 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1439 GENMASK(15, 8)); 1440 } 1441 1442 static inline void SET_DCTL_SEC_ENT5_V1(void *table, u32 val) 1443 { 1444 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(23, 16)); 1445 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1446 GENMASK(23, 16)); 1447 } 1448 1449 static inline void SET_DCTL_SEC_ENT6_V1(void *table, u32 val) 1450 { 1451 le32p_replace_bits((__le32 *)(table) + 7, val, GENMASK(31, 24)); 1452 le32p_replace_bits((__le32 *)(table) + 15, SET_DCTL_MASK_SEC_ENTX, 1453 GENMASK(31, 24)); 1454 } 1455 1456 static inline void SET_BCN_UPD_PORT(void *h2c, u32 val) 1457 { 1458 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1459 } 1460 1461 static inline void SET_BCN_UPD_MBSSID(void *h2c, u32 val) 1462 { 1463 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1464 } 1465 1466 static inline void SET_BCN_UPD_BAND(void *h2c, u32 val) 1467 { 1468 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1469 } 1470 1471 static inline void SET_BCN_UPD_GRP_IE_OFST(void *h2c, u32 val) 1472 { 1473 le32p_replace_bits((__le32 *)h2c, (val - 24) | BIT(7), GENMASK(31, 24)); 1474 } 1475 1476 static inline void SET_BCN_UPD_MACID(void *h2c, u32 val) 1477 { 1478 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 1479 } 1480 1481 static inline void SET_BCN_UPD_SSN_SEL(void *h2c, u32 val) 1482 { 1483 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(9, 8)); 1484 } 1485 1486 static inline void SET_BCN_UPD_SSN_MODE(void *h2c, u32 val) 1487 { 1488 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(11, 10)); 1489 } 1490 1491 static inline void SET_BCN_UPD_RATE(void *h2c, u32 val) 1492 { 1493 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(20, 12)); 1494 } 1495 1496 static inline void SET_BCN_UPD_TXPWR(void *h2c, u32 val) 1497 { 1498 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(23, 21)); 1499 } 1500 1501 static inline void SET_BCN_UPD_TXINFO_CTRL_EN(void *h2c, u32 val) 1502 { 1503 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(0)); 1504 } 1505 1506 static inline void SET_BCN_UPD_NTX_PATH_EN(void *h2c, u32 val) 1507 { 1508 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(4, 1)); 1509 } 1510 1511 static inline void SET_BCN_UPD_PATH_MAP_A(void *h2c, u32 val) 1512 { 1513 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(6, 5)); 1514 } 1515 1516 static inline void SET_BCN_UPD_PATH_MAP_B(void *h2c, u32 val) 1517 { 1518 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(8, 7)); 1519 } 1520 1521 static inline void SET_BCN_UPD_PATH_MAP_C(void *h2c, u32 val) 1522 { 1523 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(10, 9)); 1524 } 1525 1526 static inline void SET_BCN_UPD_PATH_MAP_D(void *h2c, u32 val) 1527 { 1528 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(12, 11)); 1529 } 1530 1531 static inline void SET_BCN_UPD_PATH_ANTSEL_A(void *h2c, u32 val) 1532 { 1533 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(13)); 1534 } 1535 1536 static inline void SET_BCN_UPD_PATH_ANTSEL_B(void *h2c, u32 val) 1537 { 1538 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(14)); 1539 } 1540 1541 static inline void SET_BCN_UPD_PATH_ANTSEL_C(void *h2c, u32 val) 1542 { 1543 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(15)); 1544 } 1545 1546 static inline void SET_BCN_UPD_PATH_ANTSEL_D(void *h2c, u32 val) 1547 { 1548 le32p_replace_bits((__le32 *)(h2c) + 2, val, BIT(16)); 1549 } 1550 1551 static inline void SET_BCN_UPD_CSA_OFST(void *h2c, u32 val) 1552 { 1553 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 17)); 1554 } 1555 1556 static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val) 1557 { 1558 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1559 } 1560 1561 static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val) 1562 { 1563 le32p_replace_bits((__le32 *)h2c, val, GENMASK(9, 8)); 1564 } 1565 1566 static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val) 1567 { 1568 le32p_replace_bits((__le32 *)h2c, val, GENMASK(12, 10)); 1569 } 1570 1571 static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val) 1572 { 1573 le32p_replace_bits((__le32 *)h2c, val, GENMASK(16, 13)); 1574 } 1575 1576 static inline void SET_JOININFO_MACID(void *h2c, u32 val) 1577 { 1578 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1579 } 1580 1581 static inline void SET_JOININFO_OP(void *h2c, u32 val) 1582 { 1583 le32p_replace_bits((__le32 *)h2c, val, BIT(8)); 1584 } 1585 1586 static inline void SET_JOININFO_BAND(void *h2c, u32 val) 1587 { 1588 le32p_replace_bits((__le32 *)h2c, val, BIT(9)); 1589 } 1590 1591 static inline void SET_JOININFO_WMM(void *h2c, u32 val) 1592 { 1593 le32p_replace_bits((__le32 *)h2c, val, GENMASK(11, 10)); 1594 } 1595 1596 static inline void SET_JOININFO_TGR(void *h2c, u32 val) 1597 { 1598 le32p_replace_bits((__le32 *)h2c, val, BIT(12)); 1599 } 1600 1601 static inline void SET_JOININFO_ISHESTA(void *h2c, u32 val) 1602 { 1603 le32p_replace_bits((__le32 *)h2c, val, BIT(13)); 1604 } 1605 1606 static inline void SET_JOININFO_DLBW(void *h2c, u32 val) 1607 { 1608 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 14)); 1609 } 1610 1611 static inline void SET_JOININFO_TF_MAC_PAD(void *h2c, u32 val) 1612 { 1613 le32p_replace_bits((__le32 *)h2c, val, GENMASK(17, 16)); 1614 } 1615 1616 static inline void SET_JOININFO_DL_T_PE(void *h2c, u32 val) 1617 { 1618 le32p_replace_bits((__le32 *)h2c, val, GENMASK(20, 18)); 1619 } 1620 1621 static inline void SET_JOININFO_PORT_ID(void *h2c, u32 val) 1622 { 1623 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 21)); 1624 } 1625 1626 static inline void SET_JOININFO_NET_TYPE(void *h2c, u32 val) 1627 { 1628 le32p_replace_bits((__le32 *)h2c, val, GENMASK(25, 24)); 1629 } 1630 1631 static inline void SET_JOININFO_WIFI_ROLE(void *h2c, u32 val) 1632 { 1633 le32p_replace_bits((__le32 *)h2c, val, GENMASK(29, 26)); 1634 } 1635 1636 static inline void SET_JOININFO_SELF_ROLE(void *h2c, u32 val) 1637 { 1638 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 30)); 1639 } 1640 1641 static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val) 1642 { 1643 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1644 } 1645 1646 static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val) 1647 { 1648 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1649 } 1650 1651 static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val) 1652 { 1653 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 16)); 1654 } 1655 1656 static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val) 1657 { 1658 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1659 } 1660 1661 static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val) 1662 { 1663 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(7, 0)); 1664 } 1665 1666 static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val) 1667 { 1668 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); 1669 } 1670 1671 static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val) 1672 { 1673 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1674 } 1675 1676 static inline void SET_LOG_CFG_PATH(void *h2c, u32 val) 1677 { 1678 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1679 } 1680 1681 static inline void SET_LOG_CFG_COMP(void *h2c, u32 val) 1682 { 1683 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(31, 0)); 1684 } 1685 1686 static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val) 1687 { 1688 le32p_replace_bits((__le32 *)(h2c) + 2, val, GENMASK(31, 0)); 1689 } 1690 1691 static inline void SET_BA_CAM_VALID(void *h2c, u32 val) 1692 { 1693 le32p_replace_bits((__le32 *)h2c, val, BIT(0)); 1694 } 1695 1696 static inline void SET_BA_CAM_INIT_REQ(void *h2c, u32 val) 1697 { 1698 le32p_replace_bits((__le32 *)h2c, val, BIT(1)); 1699 } 1700 1701 static inline void SET_BA_CAM_ENTRY_IDX(void *h2c, u32 val) 1702 { 1703 le32p_replace_bits((__le32 *)h2c, val, GENMASK(3, 2)); 1704 } 1705 1706 static inline void SET_BA_CAM_TID(void *h2c, u32 val) 1707 { 1708 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 4)); 1709 } 1710 1711 static inline void SET_BA_CAM_MACID(void *h2c, u32 val) 1712 { 1713 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1714 } 1715 1716 static inline void SET_BA_CAM_BMAP_SIZE(void *h2c, u32 val) 1717 { 1718 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)); 1719 } 1720 1721 static inline void SET_BA_CAM_SSN(void *h2c, u32 val) 1722 { 1723 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 20)); 1724 } 1725 1726 static inline void SET_BA_CAM_UID(void *h2c, u32 val) 1727 { 1728 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(7, 0)); 1729 } 1730 1731 static inline void SET_BA_CAM_STD_EN(void *h2c, u32 val) 1732 { 1733 le32p_replace_bits((__le32 *)h2c + 1, val, BIT(8)); 1734 } 1735 1736 static inline void SET_BA_CAM_BAND(void *h2c, u32 val) 1737 { 1738 le32p_replace_bits((__le32 *)h2c + 1, val, BIT(9)); 1739 } 1740 1741 static inline void SET_BA_CAM_ENTRY_IDX_V1(void *h2c, u32 val) 1742 { 1743 le32p_replace_bits((__le32 *)h2c + 1, val, GENMASK(31, 28)); 1744 } 1745 1746 static inline void SET_LPS_PARM_MACID(void *h2c, u32 val) 1747 { 1748 le32p_replace_bits((__le32 *)h2c, val, GENMASK(7, 0)); 1749 } 1750 1751 static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val) 1752 { 1753 le32p_replace_bits((__le32 *)h2c, val, GENMASK(15, 8)); 1754 } 1755 1756 static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val) 1757 { 1758 le32p_replace_bits((__le32 *)h2c, val, GENMASK(19, 16)); 1759 } 1760 1761 static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val) 1762 { 1763 le32p_replace_bits((__le32 *)h2c, val, GENMASK(23, 20)); 1764 } 1765 1766 static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val) 1767 { 1768 le32p_replace_bits((__le32 *)h2c, val, GENMASK(31, 24)); 1769 } 1770 1771 static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val) 1772 { 1773 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(0)); 1774 } 1775 1776 static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val) 1777 { 1778 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(1)); 1779 } 1780 1781 static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val) 1782 { 1783 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(2)); 1784 } 1785 1786 static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val) 1787 { 1788 le32p_replace_bits((__le32 *)(h2c) + 1, val, BIT(3)); 1789 } 1790 1791 static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val) 1792 { 1793 le32p_replace_bits((__le32 *)(h2c) + 1, val, GENMASK(15, 8)); 1794 } 1795 1796 static inline void RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val) 1797 { 1798 le32p_replace_bits((__le32 *)cmd, val, GENMASK(31, 0)); 1799 } 1800 1801 enum rtw89_btc_btf_h2c_class { 1802 BTFC_SET = 0x10, 1803 BTFC_GET = 0x11, 1804 BTFC_FW_EVENT = 0x12, 1805 }; 1806 1807 enum rtw89_btc_btf_set { 1808 SET_REPORT_EN = 0x0, 1809 SET_SLOT_TABLE, 1810 SET_MREG_TABLE, 1811 SET_CX_POLICY, 1812 SET_GPIO_DBG, 1813 SET_DRV_INFO, 1814 SET_DRV_EVENT, 1815 SET_BT_WREG_ADDR, 1816 SET_BT_WREG_VAL, 1817 SET_BT_RREG_ADDR, 1818 SET_BT_WL_CH_INFO, 1819 SET_BT_INFO_REPORT, 1820 SET_BT_IGNORE_WLAN_ACT, 1821 SET_BT_TX_PWR, 1822 SET_BT_LNA_CONSTRAIN, 1823 SET_BT_GOLDEN_RX_RANGE, 1824 SET_BT_PSD_REPORT, 1825 SET_H2C_TEST, 1826 SET_MAX1, 1827 }; 1828 1829 enum rtw89_btc_cxdrvinfo { 1830 CXDRVINFO_INIT = 0, 1831 CXDRVINFO_ROLE, 1832 CXDRVINFO_DBCC, 1833 CXDRVINFO_SMAP, 1834 CXDRVINFO_RFK, 1835 CXDRVINFO_RUN, 1836 CXDRVINFO_CTRL, 1837 CXDRVINFO_SCAN, 1838 CXDRVINFO_MAX, 1839 }; 1840 1841 enum rtw89_scan_mode { 1842 RTW89_SCAN_IMMEDIATE, 1843 }; 1844 1845 enum rtw89_scan_type { 1846 RTW89_SCAN_ONCE, 1847 }; 1848 1849 static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val) 1850 { 1851 u8p_replace_bits((u8 *)(cmd) + 0, val, GENMASK(7, 0)); 1852 } 1853 1854 static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val) 1855 { 1856 u8p_replace_bits((u8 *)(cmd) + 1, val, GENMASK(7, 0)); 1857 } 1858 1859 static inline void RTW89_SET_FWCMD_CXINIT_ANT_TYPE(void *cmd, u8 val) 1860 { 1861 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)); 1862 } 1863 1864 static inline void RTW89_SET_FWCMD_CXINIT_ANT_NUM(void *cmd, u8 val) 1865 { 1866 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)); 1867 } 1868 1869 static inline void RTW89_SET_FWCMD_CXINIT_ANT_ISO(void *cmd, u8 val) 1870 { 1871 u8p_replace_bits((u8 *)(cmd) + 4, val, GENMASK(7, 0)); 1872 } 1873 1874 static inline void RTW89_SET_FWCMD_CXINIT_ANT_POS(void *cmd, u8 val) 1875 { 1876 u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(0)); 1877 } 1878 1879 static inline void RTW89_SET_FWCMD_CXINIT_ANT_DIVERSITY(void *cmd, u8 val) 1880 { 1881 u8p_replace_bits((u8 *)(cmd) + 5, val, BIT(1)); 1882 } 1883 1884 static inline void RTW89_SET_FWCMD_CXINIT_MOD_RFE(void *cmd, u8 val) 1885 { 1886 u8p_replace_bits((u8 *)(cmd) + 6, val, GENMASK(7, 0)); 1887 } 1888 1889 static inline void RTW89_SET_FWCMD_CXINIT_MOD_CV(void *cmd, u8 val) 1890 { 1891 u8p_replace_bits((u8 *)(cmd) + 7, val, GENMASK(7, 0)); 1892 } 1893 1894 static inline void RTW89_SET_FWCMD_CXINIT_MOD_BT_SOLO(void *cmd, u8 val) 1895 { 1896 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(0)); 1897 } 1898 1899 static inline void RTW89_SET_FWCMD_CXINIT_MOD_BT_POS(void *cmd, u8 val) 1900 { 1901 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(1)); 1902 } 1903 1904 static inline void RTW89_SET_FWCMD_CXINIT_MOD_SW_TYPE(void *cmd, u8 val) 1905 { 1906 u8p_replace_bits((u8 *)(cmd) + 8, val, BIT(2)); 1907 } 1908 1909 static inline void RTW89_SET_FWCMD_CXINIT_WL_GCH(void *cmd, u8 val) 1910 { 1911 u8p_replace_bits((u8 *)(cmd) + 10, val, GENMASK(7, 0)); 1912 } 1913 1914 static inline void RTW89_SET_FWCMD_CXINIT_WL_ONLY(void *cmd, u8 val) 1915 { 1916 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(0)); 1917 } 1918 1919 static inline void RTW89_SET_FWCMD_CXINIT_WL_INITOK(void *cmd, u8 val) 1920 { 1921 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(1)); 1922 } 1923 1924 static inline void RTW89_SET_FWCMD_CXINIT_DBCC_EN(void *cmd, u8 val) 1925 { 1926 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(2)); 1927 } 1928 1929 static inline void RTW89_SET_FWCMD_CXINIT_CX_OTHER(void *cmd, u8 val) 1930 { 1931 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(3)); 1932 } 1933 1934 static inline void RTW89_SET_FWCMD_CXINIT_BT_ONLY(void *cmd, u8 val) 1935 { 1936 u8p_replace_bits((u8 *)(cmd) + 11, val, BIT(4)); 1937 } 1938 1939 static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val) 1940 { 1941 u8p_replace_bits((u8 *)(cmd) + 2, val, GENMASK(7, 0)); 1942 } 1943 1944 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val) 1945 { 1946 u8p_replace_bits((u8 *)(cmd) + 3, val, GENMASK(7, 0)); 1947 } 1948 1949 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val) 1950 { 1951 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(0)); 1952 } 1953 1954 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val) 1955 { 1956 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(1)); 1957 } 1958 1959 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val) 1960 { 1961 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(2)); 1962 } 1963 1964 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val) 1965 { 1966 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(3)); 1967 } 1968 1969 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val) 1970 { 1971 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(4)); 1972 } 1973 1974 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val) 1975 { 1976 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(5)); 1977 } 1978 1979 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val) 1980 { 1981 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(6)); 1982 } 1983 1984 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val) 1985 { 1986 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(7)); 1987 } 1988 1989 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val) 1990 { 1991 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(8)); 1992 } 1993 1994 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val) 1995 { 1996 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(9)); 1997 } 1998 1999 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val) 2000 { 2001 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(10)); 2002 } 2003 2004 static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val) 2005 { 2006 le16p_replace_bits((__le16 *)((u8 *)(cmd) + 4), val, BIT(11)); 2007 } 2008 2009 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset) 2010 { 2011 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(0)); 2012 } 2013 2014 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset) 2015 { 2016 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(3, 1)); 2017 } 2018 2019 static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset) 2020 { 2021 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(4)); 2022 } 2023 2024 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset) 2025 { 2026 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, BIT(5)); 2027 } 2028 2029 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset) 2030 { 2031 u8p_replace_bits((u8 *)cmd + (6 + (12 + offset) * n), val, GENMASK(7, 6)); 2032 } 2033 2034 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset) 2035 { 2036 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, BIT(0)); 2037 } 2038 2039 static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset) 2040 { 2041 u8p_replace_bits((u8 *)cmd + (7 + (12 + offset) * n), val, GENMASK(7, 1)); 2042 } 2043 2044 static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset) 2045 { 2046 u8p_replace_bits((u8 *)cmd + (8 + (12 + offset) * n), val, GENMASK(7, 0)); 2047 } 2048 2049 static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset) 2050 { 2051 u8p_replace_bits((u8 *)cmd + (9 + (12 + offset) * n), val, GENMASK(7, 0)); 2052 } 2053 2054 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset) 2055 { 2056 le16p_replace_bits((__le16 *)((u8 *)cmd + (10 + (12 + offset) * n)), val, GENMASK(15, 0)); 2057 } 2058 2059 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset) 2060 { 2061 le16p_replace_bits((__le16 *)((u8 *)cmd + (12 + (12 + offset) * n)), val, GENMASK(15, 0)); 2062 } 2063 2064 static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset) 2065 { 2066 le16p_replace_bits((__le16 *)((u8 *)cmd + (14 + (12 + offset) * n)), val, GENMASK(15, 0)); 2067 } 2068 2069 static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset) 2070 { 2071 le16p_replace_bits((__le16 *)((u8 *)cmd + (16 + (12 + offset) * n)), val, GENMASK(15, 0)); 2072 } 2073 2074 static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset) 2075 { 2076 le32p_replace_bits((__le32 *)((u8 *)cmd + (20 + (12 + offset) * n)), val, GENMASK(31, 0)); 2077 } 2078 2079 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset) 2080 { 2081 le32p_replace_bits((__le32 *)((u8 *)cmd + offset), val, GENMASK(31, 0)); 2082 } 2083 2084 static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset) 2085 { 2086 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 4), val, GENMASK(31, 0)); 2087 } 2088 2089 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset) 2090 { 2091 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(0)); 2092 } 2093 2094 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset) 2095 { 2096 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(1)); 2097 } 2098 2099 static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset) 2100 { 2101 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, GENMASK(3, 2)); 2102 } 2103 2104 static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset) 2105 { 2106 le32p_replace_bits((__le32 *)((u8 *)cmd + offset + 8), val, BIT(4)); 2107 } 2108 2109 static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val) 2110 { 2111 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(0)); 2112 } 2113 2114 static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val) 2115 { 2116 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(1)); 2117 } 2118 2119 static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val) 2120 { 2121 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, BIT(2)); 2122 } 2123 2124 static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val) 2125 { 2126 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(18, 3)); 2127 } 2128 2129 static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val) 2130 { 2131 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(1, 0)); 2132 } 2133 2134 static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val) 2135 { 2136 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(5, 2)); 2137 } 2138 2139 static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val) 2140 { 2141 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(7, 6)); 2142 } 2143 2144 static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val) 2145 { 2146 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(9, 8)); 2147 } 2148 2149 static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val) 2150 { 2151 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 2), val, GENMASK(17, 10)); 2152 } 2153 2154 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val) 2155 { 2156 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2157 } 2158 2159 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val) 2160 { 2161 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(10, 8)); 2162 } 2163 2164 static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val) 2165 { 2166 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 16)); 2167 } 2168 2169 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_NUM(void *cmd, u32 val) 2170 { 2171 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2172 } 2173 2174 static inline void RTW89_SET_FWCMD_SCANOFLD_CH_SIZE(void *cmd, u32 val) 2175 { 2176 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8)); 2177 } 2178 2179 static inline void RTW89_SET_FWCMD_CHINFO_PERIOD(void *cmd, u32 val) 2180 { 2181 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2182 } 2183 2184 static inline void RTW89_SET_FWCMD_CHINFO_DWELL(void *cmd, u32 val) 2185 { 2186 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8)); 2187 } 2188 2189 static inline void RTW89_SET_FWCMD_CHINFO_CENTER_CH(void *cmd, u32 val) 2190 { 2191 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(23, 16)); 2192 } 2193 2194 static inline void RTW89_SET_FWCMD_CHINFO_PRI_CH(void *cmd, u32 val) 2195 { 2196 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(31, 24)); 2197 } 2198 2199 static inline void RTW89_SET_FWCMD_CHINFO_BW(void *cmd, u32 val) 2200 { 2201 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(2, 0)); 2202 } 2203 2204 static inline void RTW89_SET_FWCMD_CHINFO_ACTION(void *cmd, u32 val) 2205 { 2206 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(7, 3)); 2207 } 2208 2209 static inline void RTW89_SET_FWCMD_CHINFO_NUM_PKT(void *cmd, u32 val) 2210 { 2211 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(11, 8)); 2212 } 2213 2214 static inline void RTW89_SET_FWCMD_CHINFO_TX(void *cmd, u32 val) 2215 { 2216 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(12)); 2217 } 2218 2219 static inline void RTW89_SET_FWCMD_CHINFO_PAUSE_DATA(void *cmd, u32 val) 2220 { 2221 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(13)); 2222 } 2223 2224 static inline void RTW89_SET_FWCMD_CHINFO_BAND(void *cmd, u32 val) 2225 { 2226 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(15, 14)); 2227 } 2228 2229 static inline void RTW89_SET_FWCMD_CHINFO_PKT_ID(void *cmd, u32 val) 2230 { 2231 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(23, 16)); 2232 } 2233 2234 static inline void RTW89_SET_FWCMD_CHINFO_DFS(void *cmd, u32 val) 2235 { 2236 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(24)); 2237 } 2238 2239 static inline void RTW89_SET_FWCMD_CHINFO_TX_NULL(void *cmd, u32 val) 2240 { 2241 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(25)); 2242 } 2243 2244 static inline void RTW89_SET_FWCMD_CHINFO_RANDOM(void *cmd, u32 val) 2245 { 2246 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(26)); 2247 } 2248 2249 static inline void RTW89_SET_FWCMD_CHINFO_CFG_TX(void *cmd, u32 val) 2250 { 2251 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(27)); 2252 } 2253 2254 static inline void RTW89_SET_FWCMD_CHINFO_PKT0(void *cmd, u32 val) 2255 { 2256 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(7, 0)); 2257 } 2258 2259 static inline void RTW89_SET_FWCMD_CHINFO_PKT1(void *cmd, u32 val) 2260 { 2261 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(15, 8)); 2262 } 2263 2264 static inline void RTW89_SET_FWCMD_CHINFO_PKT2(void *cmd, u32 val) 2265 { 2266 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(23, 16)); 2267 } 2268 2269 static inline void RTW89_SET_FWCMD_CHINFO_PKT3(void *cmd, u32 val) 2270 { 2271 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(31, 24)); 2272 } 2273 2274 static inline void RTW89_SET_FWCMD_CHINFO_PKT4(void *cmd, u32 val) 2275 { 2276 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(7, 0)); 2277 } 2278 2279 static inline void RTW89_SET_FWCMD_CHINFO_PKT5(void *cmd, u32 val) 2280 { 2281 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(15, 8)); 2282 } 2283 2284 static inline void RTW89_SET_FWCMD_CHINFO_PKT6(void *cmd, u32 val) 2285 { 2286 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(23, 16)); 2287 } 2288 2289 static inline void RTW89_SET_FWCMD_CHINFO_PKT7(void *cmd, u32 val) 2290 { 2291 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(31, 24)); 2292 } 2293 2294 static inline void RTW89_SET_FWCMD_CHINFO_POWER_IDX(void *cmd, u32 val) 2295 { 2296 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 16), val, GENMASK(15, 0)); 2297 } 2298 2299 static inline void RTW89_SET_FWCMD_SCANOFLD_MACID(void *cmd, u32 val) 2300 { 2301 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(7, 0)); 2302 } 2303 2304 static inline void RTW89_SET_FWCMD_SCANOFLD_NORM_CY(void *cmd, u32 val) 2305 { 2306 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(15, 8)); 2307 } 2308 2309 static inline void RTW89_SET_FWCMD_SCANOFLD_PORT_ID(void *cmd, u32 val) 2310 { 2311 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(18, 16)); 2312 } 2313 2314 static inline void RTW89_SET_FWCMD_SCANOFLD_BAND(void *cmd, u32 val) 2315 { 2316 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, BIT(19)); 2317 } 2318 2319 static inline void RTW89_SET_FWCMD_SCANOFLD_OPERATION(void *cmd, u32 val) 2320 { 2321 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(21, 20)); 2322 } 2323 2324 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_BAND(void *cmd, u32 val) 2325 { 2326 le32p_replace_bits((__le32 *)((u8 *)(cmd)), val, GENMASK(23, 22)); 2327 } 2328 2329 static inline void RTW89_SET_FWCMD_SCANOFLD_NOTIFY_END(void *cmd, u32 val) 2330 { 2331 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(0)); 2332 } 2333 2334 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_MODE(void *cmd, u32 val) 2335 { 2336 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(1)); 2337 } 2338 2339 static inline void RTW89_SET_FWCMD_SCANOFLD_START_MODE(void *cmd, u32 val) 2340 { 2341 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, BIT(2)); 2342 } 2343 2344 static inline void RTW89_SET_FWCMD_SCANOFLD_SCAN_TYPE(void *cmd, u32 val) 2345 { 2346 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(4, 3)); 2347 } 2348 2349 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CH_BW(void *cmd, u32 val) 2350 { 2351 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(7, 5)); 2352 } 2353 2354 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_PRI_CH(void *cmd, u32 val) 2355 { 2356 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(15, 8)); 2357 } 2358 2359 static inline void RTW89_SET_FWCMD_SCANOFLD_TARGET_CENTRAL_CH(void *cmd, 2360 u32 val) 2361 { 2362 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(23, 16)); 2363 } 2364 2365 static inline void RTW89_SET_FWCMD_SCANOFLD_PROBE_REQ_PKT_ID(void *cmd, u32 val) 2366 { 2367 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 4), val, GENMASK(31, 24)); 2368 } 2369 2370 static inline void RTW89_SET_FWCMD_SCANOFLD_NORM_PD(void *cmd, u32 val) 2371 { 2372 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(15, 0)); 2373 } 2374 2375 static inline void RTW89_SET_FWCMD_SCANOFLD_SLOW_PD(void *cmd, u32 val) 2376 { 2377 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 8), val, GENMASK(23, 16)); 2378 } 2379 2380 static inline void RTW89_SET_FWCMD_SCANOFLD_TSF_HIGH(void *cmd, u32 val) 2381 { 2382 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 12), val, GENMASK(31, 0)); 2383 } 2384 2385 static inline void RTW89_SET_FWCMD_SCANOFLD_TSF_SLOW(void *cmd, u32 val) 2386 { 2387 le32p_replace_bits((__le32 *)((u8 *)(cmd) + 16), val, GENMASK(31, 0)); 2388 } 2389 2390 #define RTW89_C2H_HEADER_LEN 8 2391 2392 #define RTW89_GET_C2H_CATEGORY(c2h) \ 2393 le32_get_bits(*((const __le32 *)c2h), GENMASK(1, 0)) 2394 #define RTW89_GET_C2H_CLASS(c2h) \ 2395 le32_get_bits(*((const __le32 *)c2h), GENMASK(7, 2)) 2396 #define RTW89_GET_C2H_FUNC(c2h) \ 2397 le32_get_bits(*((const __le32 *)c2h), GENMASK(15, 8)) 2398 #define RTW89_GET_C2H_LEN(c2h) \ 2399 le32_get_bits(*((const __le32 *)(c2h) + 1), GENMASK(13, 0)) 2400 2401 #define RTW89_GET_C2H_LOG_SRT_PRT(c2h) (char *)((__le32 *)(c2h) + 2) 2402 #define RTW89_GET_C2H_LOG_LEN(len) ((len) - RTW89_C2H_HEADER_LEN) 2403 2404 #define RTW89_GET_MAC_C2H_DONE_ACK_CAT(c2h) \ 2405 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 2406 #define RTW89_GET_MAC_C2H_DONE_ACK_CLASS(c2h) \ 2407 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) 2408 #define RTW89_GET_MAC_C2H_DONE_ACK_FUNC(c2h) \ 2409 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 2410 #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_RETURN(c2h) \ 2411 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 2412 #define RTW89_GET_MAC_C2H_DONE_ACK_H2C_SEQ(c2h) \ 2413 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 24)) 2414 2415 #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) \ 2416 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(1, 0)) 2417 #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) \ 2418 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 2)) 2419 #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) \ 2420 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 8)) 2421 #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) \ 2422 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 2423 2424 #define RTW89_GET_PHY_C2H_RA_RPT_MACID(c2h) \ 2425 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(15, 0)) 2426 #define RTW89_GET_PHY_C2H_RA_RPT_RETRY_RATIO(c2h) \ 2427 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 16)) 2428 #define RTW89_GET_PHY_C2H_RA_RPT_MCSNSS(c2h) \ 2429 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(6, 0)) 2430 #define RTW89_GET_PHY_C2H_RA_RPT_MD_SEL(c2h) \ 2431 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(9, 8)) 2432 #define RTW89_GET_PHY_C2H_RA_RPT_GILTF(c2h) \ 2433 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(12, 10)) 2434 #define RTW89_GET_PHY_C2H_RA_RPT_BW(c2h) \ 2435 le32_get_bits(*((const __le32 *)(c2h) + 3), GENMASK(14, 13)) 2436 2437 /* VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS 2438 * HT-new: [6:5]: NA, [4:0]: MCS 2439 */ 2440 #define RTW89_RA_RATE_MASK_NSS GENMASK(6, 4) 2441 #define RTW89_RA_RATE_MASK_MCS GENMASK(3, 0) 2442 #define RTW89_RA_RATE_MASK_HT_MCS GENMASK(4, 0) 2443 #define RTW89_MK_HT_RATE(nss, mcs) (FIELD_PREP(GENMASK(4, 3), nss) | \ 2444 FIELD_PREP(GENMASK(2, 0), mcs)) 2445 2446 #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) \ 2447 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0)) 2448 #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) \ 2449 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(10, 8)) 2450 #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) \ 2451 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(31, 16)) 2452 2453 #define RTW89_GET_MAC_C2H_SCANOFLD_PRI_CH(c2h) \ 2454 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(7, 0)) 2455 #define RTW89_GET_MAC_C2H_SCANOFLD_RSP(c2h) \ 2456 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(19, 16)) 2457 #define RTW89_GET_MAC_C2H_SCANOFLD_STATUS(c2h) \ 2458 le32_get_bits(*((const __le32 *)(c2h) + 2), GENMASK(23, 20)) 2459 #define RTW89_GET_MAC_C2H_SCANOFLD_TX_FAIL(c2h) \ 2460 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(3, 0)) 2461 #define RTW89_GET_MAC_C2H_SCANOFLD_AIR_DENSITY(c2h) \ 2462 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(7, 4)) 2463 #define RTW89_GET_MAC_C2H_SCANOFLD_BAND(c2h) \ 2464 le32_get_bits(*((const __le32 *)(c2h) + 5), GENMASK(25, 24)) 2465 2466 #define RTW89_FW_HDR_SIZE 32 2467 #define RTW89_FW_SECTION_HDR_SIZE 16 2468 2469 #define RTW89_MFW_SIG 0xFF 2470 2471 struct rtw89_mfw_info { 2472 u8 cv; 2473 u8 type; /* enum rtw89_fw_type */ 2474 u8 mp; 2475 u8 rsvd; 2476 __le32 shift; 2477 __le32 size; 2478 u8 rsvd2[4]; 2479 } __packed; 2480 2481 struct rtw89_mfw_hdr { 2482 u8 sig; /* RTW89_MFW_SIG */ 2483 u8 fw_nr; 2484 u8 rsvd0[2]; 2485 struct { 2486 u8 major; 2487 u8 minor; 2488 u8 sub; 2489 u8 idx; 2490 } ver; 2491 u8 rsvd1[8]; 2492 struct rtw89_mfw_info info[]; 2493 } __packed; 2494 2495 struct fwcmd_hdr { 2496 __le32 hdr0; 2497 __le32 hdr1; 2498 }; 2499 2500 #define RTW89_H2C_RF_PAGE_SIZE 500 2501 #define RTW89_H2C_RF_PAGE_NUM 3 2502 struct rtw89_fw_h2c_rf_reg_info { 2503 enum rtw89_rf_path rf_path; 2504 __le32 rtw89_phy_config_rf_h2c[RTW89_H2C_RF_PAGE_NUM][RTW89_H2C_RF_PAGE_SIZE]; 2505 u16 curr_idx; 2506 }; 2507 2508 #define H2C_SEC_CAM_LEN 24 2509 2510 #define H2C_HEADER_LEN 8 2511 #define H2C_HDR_CAT GENMASK(1, 0) 2512 #define H2C_HDR_CLASS GENMASK(7, 2) 2513 #define H2C_HDR_FUNC GENMASK(15, 8) 2514 #define H2C_HDR_DEL_TYPE GENMASK(19, 16) 2515 #define H2C_HDR_H2C_SEQ GENMASK(31, 24) 2516 #define H2C_HDR_TOTAL_LEN GENMASK(13, 0) 2517 #define H2C_HDR_REC_ACK BIT(14) 2518 #define H2C_HDR_DONE_ACK BIT(15) 2519 2520 #define FWCMD_TYPE_H2C 0 2521 2522 #define H2C_CAT_TEST 0x0 2523 2524 /* CLASS 5 - FW STATUS TEST */ 2525 #define H2C_CL_FW_STATUS_TEST 0x5 2526 #define H2C_FUNC_CPU_EXCEPTION 0x1 2527 2528 #define H2C_CAT_MAC 0x1 2529 2530 /* CLASS 0 - FW INFO */ 2531 #define H2C_CL_FW_INFO 0x0 2532 #define H2C_FUNC_LOG_CFG 0x0 2533 #define H2C_FUNC_MAC_GENERAL_PKT 0x1 2534 2535 /* CLASS 2 - PS */ 2536 #define H2C_CL_MAC_PS 0x2 2537 #define H2C_FUNC_MAC_LPS_PARM 0x0 2538 2539 /* CLASS 3 - FW download */ 2540 #define H2C_CL_MAC_FWDL 0x3 2541 #define H2C_FUNC_MAC_FWHDR_DL 0x0 2542 2543 /* CLASS 5 - Frame Exchange */ 2544 #define H2C_CL_MAC_FR_EXCHG 0x5 2545 #define H2C_FUNC_MAC_CCTLINFO_UD 0x2 2546 #define H2C_FUNC_MAC_BCN_UPD 0x5 2547 #define H2C_FUNC_MAC_DCTLINFO_UD_V1 0x9 2548 #define H2C_FUNC_MAC_CCTLINFO_UD_V1 0xa 2549 2550 /* CLASS 6 - Address CAM */ 2551 #define H2C_CL_MAC_ADDR_CAM_UPDATE 0x6 2552 #define H2C_FUNC_MAC_ADDR_CAM_UPD 0x0 2553 2554 /* CLASS 8 - Media Status Report */ 2555 #define H2C_CL_MAC_MEDIA_RPT 0x8 2556 #define H2C_FUNC_MAC_JOININFO 0x0 2557 #define H2C_FUNC_MAC_FWROLE_MAINTAIN 0x4 2558 2559 /* CLASS 9 - FW offload */ 2560 #define H2C_CL_MAC_FW_OFLD 0x9 2561 #define H2C_FUNC_PACKET_OFLD 0x1 2562 #define H2C_FUNC_MAC_MACID_PAUSE 0x8 2563 #define H2C_FUNC_USR_EDCA 0xF 2564 #define H2C_FUNC_OFLD_CFG 0x14 2565 #define H2C_FUNC_ADD_SCANOFLD_CH 0x16 2566 #define H2C_FUNC_SCANOFLD 0x17 2567 2568 /* CLASS 10 - Security CAM */ 2569 #define H2C_CL_MAC_SEC_CAM 0xa 2570 #define H2C_FUNC_MAC_SEC_UPD 0x1 2571 2572 /* CLASS 12 - BA CAM */ 2573 #define H2C_CL_BA_CAM 0xc 2574 #define H2C_FUNC_MAC_BA_CAM 0x0 2575 2576 #define H2C_CAT_OUTSRC 0x2 2577 2578 #define H2C_CL_OUTSRC_RA 0x1 2579 #define H2C_FUNC_OUTSRC_RA_MACIDCFG 0x0 2580 2581 #define H2C_CL_OUTSRC_RF_REG_A 0x8 2582 #define H2C_CL_OUTSRC_RF_REG_B 0x9 2583 #define H2C_CL_OUTSRC_RF_FW_NOTIFY 0xa 2584 #define H2C_FUNC_OUTSRC_RF_GET_MCCCH 0x2 2585 2586 struct rtw89_fw_h2c_rf_get_mccch { 2587 __le32 ch_0; 2588 __le32 ch_1; 2589 __le32 band_0; 2590 __le32 band_1; 2591 __le32 current_channel; 2592 __le32 current_band_type; 2593 } __packed; 2594 2595 #define RTW89_FW_RSVD_PLE_SIZE 0x800 2596 2597 #define RTW89_WCPU_BASE_ADDR 0xA0000000 2598 2599 #define RTW89_FW_BACKTRACE_INFO_SIZE 8 2600 #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) \ 2601 ((_size) % RTW89_FW_BACKTRACE_INFO_SIZE == 0) 2602 2603 #define RTW89_FW_BACKTRACE_MAX_SIZE 512 /* 8 * 64 (entries) */ 2604 #define RTW89_FW_BACKTRACE_KEY 0xBACEBACE 2605 2606 int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev); 2607 int rtw89_fw_recognize(struct rtw89_dev *rtwdev); 2608 void rtw89_early_fw_feature_recognize(struct device *device, 2609 const struct rtw89_chip_info *chip, 2610 u32 *early_feat_map); 2611 int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type); 2612 int rtw89_load_firmware(struct rtw89_dev *rtwdev); 2613 void rtw89_unload_firmware(struct rtw89_dev *rtwdev); 2614 int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev); 2615 void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb, 2616 u8 type, u8 cat, u8 class, u8 func, 2617 bool rack, bool dack, u32 len); 2618 int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev, 2619 struct rtw89_vif *rtwvif); 2620 int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, 2621 struct ieee80211_vif *vif, 2622 struct ieee80211_sta *sta); 2623 int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev, 2624 struct rtw89_sta *rtwsta); 2625 int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev, 2626 struct rtw89_vif *rtwvif); 2627 int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif, 2628 struct rtw89_sta *rtwsta, const u8 *scan_mac_addr); 2629 int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev, 2630 struct rtw89_vif *rtwvif, 2631 struct rtw89_sta *rtwsta); 2632 void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h); 2633 void rtw89_fw_c2h_work(struct work_struct *work); 2634 int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev, 2635 struct rtw89_vif *rtwvif, 2636 struct rtw89_sta *rtwsta, 2637 enum rtw89_upd_mode upd_mode); 2638 int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 2639 struct rtw89_sta *rtwsta, bool dis_conn); 2640 int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp, 2641 bool pause); 2642 int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 2643 u8 ac, u32 val); 2644 int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev); 2645 int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi); 2646 int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev); 2647 int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev); 2648 int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev); 2649 int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev); 2650 int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev); 2651 int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id); 2652 int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id, 2653 struct sk_buff *skb_ofld); 2654 int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int len, 2655 struct list_head *chan_list); 2656 int rtw89_fw_h2c_scan_offload(struct rtw89_dev *rtwdev, 2657 struct rtw89_scan_option *opt, 2658 struct rtw89_vif *vif); 2659 int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev, 2660 struct rtw89_fw_h2c_rf_reg_info *info, 2661 u16 len, u8 page); 2662 int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev); 2663 int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, 2664 u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, 2665 bool rack, bool dack); 2666 int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len); 2667 void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev); 2668 void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev); 2669 int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, u8 macid); 2670 int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 2671 bool valid, struct ieee80211_ampdu_params *params); 2672 void rtw89_fw_h2c_init_ba_cam_v1(struct rtw89_dev *rtwdev); 2673 2674 int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev, 2675 struct rtw89_lps_parm *lps_param); 2676 struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len); 2677 struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len); 2678 int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev, 2679 struct rtw89_mac_h2c_info *h2c_info, 2680 struct rtw89_mac_c2h_info *c2h_info); 2681 int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable); 2682 void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev); 2683 void rtw89_store_op_chan(struct rtw89_dev *rtwdev, bool backup); 2684 void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 2685 struct ieee80211_scan_request *req); 2686 void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 2687 bool aborted); 2688 int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 2689 bool enable); 2690 void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 2691 int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev); 2692 2693 static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev) 2694 { 2695 const struct rtw89_chip_info *chip = rtwdev->chip; 2696 2697 if (chip->bacam_v1) 2698 rtw89_fw_h2c_init_ba_cam_v1(rtwdev); 2699 } 2700 2701 #endif 2702