1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #if defined(__FreeBSD__) 6 #define LINUXKPI_PARAM_PREFIX rtw89_debug_ 7 #endif 8 9 #include <linux/vmalloc.h> 10 11 #include "coex.h" 12 #include "debug.h" 13 #include "fw.h" 14 #include "mac.h" 15 #include "ps.h" 16 #include "reg.h" 17 #include "sar.h" 18 #if defined(__FreeBSD__) 19 #ifdef CONFIG_RTW89_DEBUGFS 20 #include <linux/debugfs.h> 21 #endif 22 #endif 23 24 #ifdef CONFIG_RTW89_DEBUGMSG 25 unsigned int rtw89_debug_mask; 26 EXPORT_SYMBOL(rtw89_debug_mask); 27 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); 28 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 29 #endif 30 31 #ifdef CONFIG_RTW89_DEBUGFS 32 struct rtw89_debugfs_priv { 33 struct rtw89_dev *rtwdev; 34 int (*cb_read)(struct seq_file *m, void *v); 35 ssize_t (*cb_write)(struct file *filp, const char __user *buffer, 36 size_t count, loff_t *loff); 37 union { 38 u32 cb_data; 39 struct { 40 u32 addr; 41 u8 len; 42 } read_reg; 43 struct { 44 u32 addr; 45 u32 mask; 46 u8 path; 47 } read_rf; 48 struct { 49 u8 ss_dbg:1; 50 u8 dle_dbg:1; 51 u8 dmac_dbg:1; 52 u8 cmac_dbg:1; 53 u8 dbg_port:1; 54 } dbgpkg_en; 55 struct { 56 u32 start; 57 u32 len; 58 u8 sel; 59 } mac_mem; 60 }; 61 }; 62 63 static int rtw89_debugfs_single_show(struct seq_file *m, void *v) 64 { 65 struct rtw89_debugfs_priv *debugfs_priv = m->private; 66 67 return debugfs_priv->cb_read(m, v); 68 } 69 70 static ssize_t rtw89_debugfs_single_write(struct file *filp, 71 const char __user *buffer, 72 size_t count, loff_t *loff) 73 { 74 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 75 76 return debugfs_priv->cb_write(filp, buffer, count, loff); 77 } 78 79 static ssize_t rtw89_debugfs_seq_file_write(struct file *filp, 80 const char __user *buffer, 81 size_t count, loff_t *loff) 82 { 83 struct seq_file *seqpriv = (struct seq_file *)filp->private_data; 84 struct rtw89_debugfs_priv *debugfs_priv = seqpriv->private; 85 86 return debugfs_priv->cb_write(filp, buffer, count, loff); 87 } 88 89 static int rtw89_debugfs_single_open(struct inode *inode, struct file *filp) 90 { 91 return single_open(filp, rtw89_debugfs_single_show, inode->i_private); 92 } 93 94 static int rtw89_debugfs_close(struct inode *inode, struct file *filp) 95 { 96 return 0; 97 } 98 99 static const struct file_operations file_ops_single_r = { 100 .owner = THIS_MODULE, 101 .open = rtw89_debugfs_single_open, 102 .read = seq_read, 103 .llseek = seq_lseek, 104 .release = single_release, 105 }; 106 107 static const struct file_operations file_ops_common_rw = { 108 .owner = THIS_MODULE, 109 .open = rtw89_debugfs_single_open, 110 .release = single_release, 111 .read = seq_read, 112 .llseek = seq_lseek, 113 .write = rtw89_debugfs_seq_file_write, 114 }; 115 116 static const struct file_operations file_ops_single_w = { 117 .owner = THIS_MODULE, 118 .write = rtw89_debugfs_single_write, 119 .open = simple_open, 120 .release = rtw89_debugfs_close, 121 }; 122 123 static ssize_t 124 rtw89_debug_priv_read_reg_select(struct file *filp, 125 const char __user *user_buf, 126 size_t count, loff_t *loff) 127 { 128 struct seq_file *m = (struct seq_file *)filp->private_data; 129 struct rtw89_debugfs_priv *debugfs_priv = m->private; 130 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 131 char buf[32]; 132 size_t buf_size; 133 u32 addr, len; 134 int num; 135 136 buf_size = min(count, sizeof(buf) - 1); 137 if (copy_from_user(buf, user_buf, buf_size)) 138 return -EFAULT; 139 140 buf[buf_size] = '\0'; 141 num = sscanf(buf, "%x %x", &addr, &len); 142 if (num != 2) { 143 rtw89_info(rtwdev, "invalid format: <addr> <len>\n"); 144 return -EINVAL; 145 } 146 147 debugfs_priv->read_reg.addr = addr; 148 debugfs_priv->read_reg.len = len; 149 150 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); 151 152 return count; 153 } 154 155 static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v) 156 { 157 struct rtw89_debugfs_priv *debugfs_priv = m->private; 158 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 159 u32 addr, data; 160 u8 len; 161 162 len = debugfs_priv->read_reg.len; 163 addr = debugfs_priv->read_reg.addr; 164 165 switch (len) { 166 case 1: 167 data = rtw89_read8(rtwdev, addr); 168 break; 169 case 2: 170 data = rtw89_read16(rtwdev, addr); 171 break; 172 case 4: 173 data = rtw89_read32(rtwdev, addr); 174 break; 175 default: 176 rtw89_info(rtwdev, "invalid read reg len %d\n", len); 177 return -EINVAL; 178 } 179 180 seq_printf(m, "get %d bytes at 0x%08x=0x%08x\n", len, addr, data); 181 182 return 0; 183 } 184 185 static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp, 186 const char __user *user_buf, 187 size_t count, loff_t *loff) 188 { 189 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 190 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 191 char buf[32]; 192 size_t buf_size; 193 u32 addr, val, len; 194 int num; 195 196 buf_size = min(count, sizeof(buf) - 1); 197 if (copy_from_user(buf, user_buf, buf_size)) 198 return -EFAULT; 199 200 buf[buf_size] = '\0'; 201 num = sscanf(buf, "%x %x %x", &addr, &val, &len); 202 if (num != 3) { 203 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n"); 204 return -EINVAL; 205 } 206 207 switch (len) { 208 case 1: 209 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); 210 rtw89_write8(rtwdev, addr, (u8)val); 211 break; 212 case 2: 213 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); 214 rtw89_write16(rtwdev, addr, (u16)val); 215 break; 216 case 4: 217 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); 218 rtw89_write32(rtwdev, addr, (u32)val); 219 break; 220 default: 221 rtw89_info(rtwdev, "invalid read write len %d\n", len); 222 break; 223 } 224 225 return count; 226 } 227 228 static ssize_t 229 rtw89_debug_priv_read_rf_select(struct file *filp, 230 const char __user *user_buf, 231 size_t count, loff_t *loff) 232 { 233 struct seq_file *m = (struct seq_file *)filp->private_data; 234 struct rtw89_debugfs_priv *debugfs_priv = m->private; 235 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 236 char buf[32]; 237 size_t buf_size; 238 u32 addr, mask; 239 u8 path; 240 int num; 241 242 buf_size = min(count, sizeof(buf) - 1); 243 if (copy_from_user(buf, user_buf, buf_size)) 244 return -EFAULT; 245 246 buf[buf_size] = '\0'; 247 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); 248 if (num != 3) { 249 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n"); 250 return -EINVAL; 251 } 252 253 if (path >= rtwdev->chip->rf_path_num) { 254 rtw89_info(rtwdev, "wrong rf path\n"); 255 return -EINVAL; 256 } 257 debugfs_priv->read_rf.addr = addr; 258 debugfs_priv->read_rf.mask = mask; 259 debugfs_priv->read_rf.path = path; 260 261 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); 262 263 return count; 264 } 265 266 static int rtw89_debug_priv_read_rf_get(struct seq_file *m, void *v) 267 { 268 struct rtw89_debugfs_priv *debugfs_priv = m->private; 269 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 270 u32 addr, data, mask; 271 u8 path; 272 273 addr = debugfs_priv->read_rf.addr; 274 mask = debugfs_priv->read_rf.mask; 275 path = debugfs_priv->read_rf.path; 276 277 data = rtw89_read_rf(rtwdev, path, addr, mask); 278 279 seq_printf(m, "path %d, rf register 0x%08x=0x%08x\n", path, addr, data); 280 281 return 0; 282 } 283 284 static ssize_t rtw89_debug_priv_write_rf_set(struct file *filp, 285 const char __user *user_buf, 286 size_t count, loff_t *loff) 287 { 288 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 289 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 290 char buf[32]; 291 size_t buf_size; 292 u32 addr, val, mask; 293 u8 path; 294 int num; 295 296 buf_size = min(count, sizeof(buf) - 1); 297 if (copy_from_user(buf, user_buf, buf_size)) 298 return -EFAULT; 299 300 buf[buf_size] = '\0'; 301 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); 302 if (num != 4) { 303 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n"); 304 return -EINVAL; 305 } 306 307 if (path >= rtwdev->chip->rf_path_num) { 308 rtw89_info(rtwdev, "wrong rf path\n"); 309 return -EINVAL; 310 } 311 312 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", 313 path, addr, val, mask); 314 rtw89_write_rf(rtwdev, path, addr, mask, val); 315 316 return count; 317 } 318 319 static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v) 320 { 321 struct rtw89_debugfs_priv *debugfs_priv = m->private; 322 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 323 const struct rtw89_chip_info *chip = rtwdev->chip; 324 u32 addr, offset, data; 325 u8 path; 326 327 for (path = 0; path < chip->rf_path_num; path++) { 328 seq_printf(m, "RF path %d:\n\n", path); 329 for (addr = 0; addr < 0x100; addr += 4) { 330 seq_printf(m, "0x%08x: ", addr); 331 for (offset = 0; offset < 4; offset++) { 332 data = rtw89_read_rf(rtwdev, path, 333 addr + offset, RFREG_MASK); 334 seq_printf(m, "0x%05x ", data); 335 } 336 seq_puts(m, "\n"); 337 } 338 seq_puts(m, "\n"); 339 } 340 341 return 0; 342 } 343 344 struct txpwr_ent { 345 const char *txt; 346 u8 len; 347 }; 348 349 struct txpwr_map { 350 const struct txpwr_ent *ent; 351 u8 size; 352 u32 addr_from; 353 u32 addr_to; 354 }; 355 356 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ 357 { .len = 2, .txt = _t "\t- " _e0 " " _e1 } 358 359 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ 360 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } 361 362 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ 363 { .len = 8, .txt = _t "\t- " \ 364 _e0 " " _e1 " " _e2 " " _e3 " " \ 365 _e4 " " _e5 " " _e6 " " _e7 } 366 367 static const struct txpwr_ent __txpwr_ent_byr[] = { 368 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 369 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 370 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 371 /* 1NSS */ 372 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 373 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 374 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 375 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 376 /* 2NSS */ 377 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 378 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 379 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 380 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 381 }; 382 383 #if defined(__linux__) 384 static_assert((ARRAY_SIZE(__txpwr_ent_byr) * 4) == 385 #elif defined(__FreeBSD__) 386 rtw89_static_assert((ARRAY_SIZE(__txpwr_ent_byr) * 4) == 387 #endif 388 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); 389 390 static const struct txpwr_map __txpwr_map_byr = { 391 .ent = __txpwr_ent_byr, 392 .size = ARRAY_SIZE(__txpwr_ent_byr), 393 .addr_from = R_AX_PWR_BY_RATE, 394 .addr_to = R_AX_PWR_BY_RATE_MAX, 395 }; 396 397 static const struct txpwr_ent __txpwr_ent_lmt[] = { 398 /* 1TX */ 399 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), 400 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), 401 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), 402 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), 403 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), 404 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), 405 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), 406 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), 407 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), 408 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), 409 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), 410 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), 411 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), 412 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), 413 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), 414 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), 415 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), 416 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), 417 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), 418 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), 419 /* 2TX */ 420 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), 421 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), 422 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), 423 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), 424 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), 425 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), 426 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), 427 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), 428 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), 429 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), 430 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), 431 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), 432 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), 433 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), 434 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), 435 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), 436 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), 437 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), 438 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), 439 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), 440 }; 441 442 #if defined(__linux__) 443 static_assert((ARRAY_SIZE(__txpwr_ent_lmt) * 2) == 444 #elif defined(__FreeBSD__) 445 rtw89_static_assert((ARRAY_SIZE(__txpwr_ent_lmt) * 2) == 446 #endif 447 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); 448 449 static const struct txpwr_map __txpwr_map_lmt = { 450 .ent = __txpwr_ent_lmt, 451 .size = ARRAY_SIZE(__txpwr_ent_lmt), 452 .addr_from = R_AX_PWR_LMT, 453 .addr_to = R_AX_PWR_LMT_MAX, 454 }; 455 456 static const struct txpwr_ent __txpwr_ent_lmt_ru[] = { 457 /* 1TX */ 458 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 459 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 460 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 461 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 462 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 463 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 464 /* 2TX */ 465 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 466 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 467 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 468 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 469 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 470 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 471 }; 472 473 #if defined(__linux__) 474 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru) * 8) == 475 #elif defined(__FreeBSD__) 476 rtw89_static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru) * 8) == 477 #endif 478 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); 479 480 static const struct txpwr_map __txpwr_map_lmt_ru = { 481 .ent = __txpwr_ent_lmt_ru, 482 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru), 483 .addr_from = R_AX_PWR_RU_LMT, 484 .addr_to = R_AX_PWR_RU_LMT_MAX, 485 }; 486 487 static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent, 488 const u8 *buf, const u8 cur) 489 { 490 char *fmt; 491 492 switch (ent->len) { 493 case 2: 494 fmt = "%s\t| %3d, %3d,\tdBm\n"; 495 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1]); 496 return 2; 497 case 4: 498 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; 499 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 500 buf[cur + 2], buf[cur + 3]); 501 return 4; 502 case 8: 503 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; 504 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 505 buf[cur + 2], buf[cur + 3], buf[cur + 4], 506 buf[cur + 5], buf[cur + 6], buf[cur + 7]); 507 return 8; 508 default: 509 return 0; 510 } 511 } 512 513 static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev, 514 const struct txpwr_map *map) 515 { 516 u8 fct = rtwdev->chip->txpwr_factor_mac; 517 u8 *buf, cur, i; 518 u32 val, addr; 519 int ret; 520 521 buf = vzalloc(map->addr_to - map->addr_from + 4); 522 if (!buf) 523 return -ENOMEM; 524 525 for (addr = map->addr_from; addr <= map->addr_to; addr += 4) { 526 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); 527 if (ret) 528 val = MASKDWORD; 529 530 cur = addr - map->addr_from; 531 for (i = 0; i < 4; i++, val >>= 8) 532 buf[cur + i] = FIELD_GET(MASKBYTE0, val) >> fct; 533 } 534 535 for (cur = 0, i = 0; i < map->size; i++) 536 cur += __print_txpwr_ent(m, &map->ent[i], buf, cur); 537 538 vfree(buf); 539 return 0; 540 } 541 542 #define case_REGD(_regd) \ 543 case RTW89_ ## _regd: \ 544 seq_puts(m, #_regd "\n"); \ 545 break 546 547 static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev) 548 { 549 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 550 u8 band = chan->band_type; 551 u8 regd = rtw89_regd_get(rtwdev, band); 552 553 switch (regd) { 554 default: 555 seq_printf(m, "UNKNOWN: %d\n", regd); 556 break; 557 case_REGD(WW); 558 case_REGD(ETSI); 559 case_REGD(FCC); 560 case_REGD(MKK); 561 case_REGD(NA); 562 case_REGD(IC); 563 case_REGD(KCC); 564 case_REGD(NCC); 565 case_REGD(CHILE); 566 case_REGD(ACMA); 567 case_REGD(MEXICO); 568 case_REGD(UKRAINE); 569 case_REGD(CN); 570 } 571 } 572 573 #undef case_REGD 574 575 static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v) 576 { 577 struct rtw89_debugfs_priv *debugfs_priv = m->private; 578 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 579 int ret = 0; 580 581 mutex_lock(&rtwdev->mutex); 582 rtw89_leave_ps_mode(rtwdev); 583 584 seq_puts(m, "[Regulatory] "); 585 __print_regd(m, rtwdev); 586 587 seq_puts(m, "[SAR]\n"); 588 rtw89_print_sar(m, rtwdev); 589 590 seq_puts(m, "\n[TX power byrate]\n"); 591 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_byr); 592 if (ret) 593 goto err; 594 595 seq_puts(m, "\n[TX power limit]\n"); 596 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt); 597 if (ret) 598 goto err; 599 600 seq_puts(m, "\n[TX power limit_ru]\n"); 601 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt_ru); 602 if (ret) 603 goto err; 604 605 err: 606 mutex_unlock(&rtwdev->mutex); 607 return ret; 608 } 609 610 static ssize_t 611 rtw89_debug_priv_mac_reg_dump_select(struct file *filp, 612 const char __user *user_buf, 613 size_t count, loff_t *loff) 614 { 615 struct seq_file *m = (struct seq_file *)filp->private_data; 616 struct rtw89_debugfs_priv *debugfs_priv = m->private; 617 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 618 char buf[32]; 619 size_t buf_size; 620 int sel; 621 int ret; 622 623 buf_size = min(count, sizeof(buf) - 1); 624 if (copy_from_user(buf, user_buf, buf_size)) 625 return -EFAULT; 626 627 buf[buf_size] = '\0'; 628 ret = kstrtoint(buf, 0, &sel); 629 if (ret) 630 return ret; 631 632 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { 633 rtw89_info(rtwdev, "invalid args: %d\n", sel); 634 return -EINVAL; 635 } 636 637 debugfs_priv->cb_data = sel; 638 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); 639 640 return count; 641 } 642 643 #define RTW89_MAC_PAGE_SIZE 0x100 644 645 static int rtw89_debug_priv_mac_reg_dump_get(struct seq_file *m, void *v) 646 { 647 struct rtw89_debugfs_priv *debugfs_priv = m->private; 648 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 649 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; 650 u32 start, end; 651 u32 i, j, k, page; 652 u32 val; 653 654 switch (reg_sel) { 655 case RTW89_DBG_SEL_MAC_00: 656 seq_puts(m, "Debug selected MAC page 0x00\n"); 657 start = 0x000; 658 end = 0x014; 659 break; 660 case RTW89_DBG_SEL_MAC_30: 661 seq_puts(m, "Debug selected MAC page 0x30\n"); 662 start = 0x030; 663 end = 0x033; 664 break; 665 case RTW89_DBG_SEL_MAC_40: 666 seq_puts(m, "Debug selected MAC page 0x40\n"); 667 start = 0x040; 668 end = 0x07f; 669 break; 670 case RTW89_DBG_SEL_MAC_80: 671 seq_puts(m, "Debug selected MAC page 0x80\n"); 672 start = 0x080; 673 end = 0x09f; 674 break; 675 case RTW89_DBG_SEL_MAC_C0: 676 seq_puts(m, "Debug selected MAC page 0xc0\n"); 677 start = 0x0c0; 678 end = 0x0df; 679 break; 680 case RTW89_DBG_SEL_MAC_E0: 681 seq_puts(m, "Debug selected MAC page 0xe0\n"); 682 start = 0x0e0; 683 end = 0x0ff; 684 break; 685 case RTW89_DBG_SEL_BB: 686 seq_puts(m, "Debug selected BB register\n"); 687 start = 0x100; 688 end = 0x17f; 689 break; 690 case RTW89_DBG_SEL_IQK: 691 seq_puts(m, "Debug selected IQK register\n"); 692 start = 0x180; 693 end = 0x1bf; 694 break; 695 case RTW89_DBG_SEL_RFC: 696 seq_puts(m, "Debug selected RFC register\n"); 697 start = 0x1c0; 698 end = 0x1ff; 699 break; 700 default: 701 seq_puts(m, "Selected invalid register page\n"); 702 return -EINVAL; 703 } 704 705 for (i = start; i <= end; i++) { 706 page = i << 8; 707 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { 708 seq_printf(m, "%08xh : ", 0x18600000 + j); 709 for (k = 0; k < 4; k++) { 710 val = rtw89_read32(rtwdev, j + (k << 2)); 711 seq_printf(m, "%08x ", val); 712 } 713 seq_puts(m, "\n"); 714 } 715 } 716 717 return 0; 718 } 719 720 static ssize_t 721 rtw89_debug_priv_mac_mem_dump_select(struct file *filp, 722 const char __user *user_buf, 723 size_t count, loff_t *loff) 724 { 725 struct seq_file *m = (struct seq_file *)filp->private_data; 726 struct rtw89_debugfs_priv *debugfs_priv = m->private; 727 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 728 char buf[32]; 729 size_t buf_size; 730 u32 sel, start_addr, len; 731 int num; 732 733 buf_size = min(count, sizeof(buf) - 1); 734 if (copy_from_user(buf, user_buf, buf_size)) 735 return -EFAULT; 736 737 buf[buf_size] = '\0'; 738 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); 739 if (num != 3) { 740 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n"); 741 return -EINVAL; 742 } 743 744 debugfs_priv->mac_mem.sel = sel; 745 debugfs_priv->mac_mem.start = start_addr; 746 debugfs_priv->mac_mem.len = len; 747 748 rtw89_info(rtwdev, "select mem %d start %d len %d\n", 749 sel, start_addr, len); 750 751 return count; 752 } 753 754 static void rtw89_debug_dump_mac_mem(struct seq_file *m, 755 struct rtw89_dev *rtwdev, 756 u8 sel, u32 start_addr, u32 len) 757 { 758 u32 base_addr, start_page, residue; 759 u32 i, j, p, pages; 760 u32 dump_len, remain; 761 u32 val; 762 763 remain = len; 764 pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1; 765 start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE; 766 residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE; 767 base_addr = rtw89_mac_mem_base_addrs[sel]; 768 base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE; 769 770 for (p = 0; p < pages; p++) { 771 dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE); 772 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, base_addr); 773 for (i = R_AX_INDIR_ACCESS_ENTRY + residue; 774 i < R_AX_INDIR_ACCESS_ENTRY + dump_len;) { 775 seq_printf(m, "%08xh:", i); 776 for (j = 0; 777 j < 4 && i < R_AX_INDIR_ACCESS_ENTRY + dump_len; 778 j++, i += 4) { 779 val = rtw89_read32(rtwdev, i); 780 seq_printf(m, " %08x", val); 781 remain -= 4; 782 } 783 seq_puts(m, "\n"); 784 } 785 base_addr += MAC_MEM_DUMP_PAGE_SIZE; 786 } 787 } 788 789 static int 790 rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v) 791 { 792 struct rtw89_debugfs_priv *debugfs_priv = m->private; 793 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 794 795 mutex_lock(&rtwdev->mutex); 796 rtw89_leave_ps_mode(rtwdev); 797 rtw89_debug_dump_mac_mem(m, rtwdev, 798 debugfs_priv->mac_mem.sel, 799 debugfs_priv->mac_mem.start, 800 debugfs_priv->mac_mem.len); 801 mutex_unlock(&rtwdev->mutex); 802 803 return 0; 804 } 805 806 static ssize_t 807 rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp, 808 const char __user *user_buf, 809 size_t count, loff_t *loff) 810 { 811 struct seq_file *m = (struct seq_file *)filp->private_data; 812 struct rtw89_debugfs_priv *debugfs_priv = m->private; 813 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 814 char buf[32]; 815 size_t buf_size; 816 int sel, set; 817 int num; 818 bool enable; 819 820 buf_size = min(count, sizeof(buf) - 1); 821 if (copy_from_user(buf, user_buf, buf_size)) 822 return -EFAULT; 823 824 buf[buf_size] = '\0'; 825 num = sscanf(buf, "%d %d", &sel, &set); 826 if (num != 2) { 827 rtw89_info(rtwdev, "invalid format: <sel> <set>\n"); 828 return -EINVAL; 829 } 830 831 enable = set != 0; 832 switch (sel) { 833 case 0: 834 debugfs_priv->dbgpkg_en.ss_dbg = enable; 835 break; 836 case 1: 837 debugfs_priv->dbgpkg_en.dle_dbg = enable; 838 break; 839 case 2: 840 debugfs_priv->dbgpkg_en.dmac_dbg = enable; 841 break; 842 case 3: 843 debugfs_priv->dbgpkg_en.cmac_dbg = enable; 844 break; 845 case 4: 846 debugfs_priv->dbgpkg_en.dbg_port = enable; 847 break; 848 default: 849 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); 850 return -EINVAL; 851 } 852 853 rtw89_info(rtwdev, "%s debug port dump %d\n", 854 enable ? "Enable" : "Disable", sel); 855 856 return count; 857 } 858 859 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, 860 struct seq_file *m) 861 { 862 return 0; 863 } 864 865 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, 866 struct seq_file *m) 867 { 868 #define DLE_DFI_DUMP(__type, __target, __sel) \ 869 ({ \ 870 u32 __ctrl; \ 871 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ 872 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ 873 u32 __data, __val32; \ 874 int __ret; \ 875 \ 876 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ 877 DLE_DFI_TYPE_##__target) | \ 878 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ 879 B_AX_WDE_DFI_ACTIVE; \ 880 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ 881 __ret = read_poll_timeout(rtw89_read32, __val32, \ 882 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ 883 1000, 50000, false, \ 884 rtwdev, __reg_ctrl); \ 885 if (__ret) { \ 886 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ 887 #__type, #__target, __sel); \ 888 return __ret; \ 889 } \ 890 \ 891 __data = rtw89_read32(rtwdev, __reg_data); \ 892 __data; \ 893 }) 894 895 #define DLE_DFI_FREE_PAGE_DUMP(__m, __type) \ 896 ({ \ 897 u32 __freepg, __pubpg; \ 898 u32 __freepg_head, __freepg_tail, __pubpg_num; \ 899 \ 900 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ 901 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ 902 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ 903 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ 904 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ 905 seq_printf(__m, "[%s] freepg head: %d\n", \ 906 #__type, __freepg_head); \ 907 seq_printf(__m, "[%s] freepg tail: %d\n", \ 908 #__type, __freepg_tail); \ 909 seq_printf(__m, "[%s] pubpg num : %d\n", \ 910 #__type, __pubpg_num); \ 911 }) 912 913 #define case_QUOTA(__m, __type, __id) \ 914 case __type##_QTAID_##__id: \ 915 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ 916 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ 917 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ 918 seq_printf(__m, "[%s][%s] rsv_pgnum: %d\n", \ 919 #__type, #__id, rsv_pgnum); \ 920 seq_printf(__m, "[%s][%s] use_pgnum: %d\n", \ 921 #__type, #__id, use_pgnum); \ 922 break 923 u32 quota_id; 924 u32 val32; 925 u16 rsv_pgnum, use_pgnum; 926 int ret; 927 928 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 929 if (ret) { 930 seq_puts(m, "[DLE] : DMAC not enabled\n"); 931 return ret; 932 } 933 934 DLE_DFI_FREE_PAGE_DUMP(m, WDE); 935 DLE_DFI_FREE_PAGE_DUMP(m, PLE); 936 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { 937 switch (quota_id) { 938 case_QUOTA(m, WDE, HOST_IF); 939 case_QUOTA(m, WDE, WLAN_CPU); 940 case_QUOTA(m, WDE, DATA_CPU); 941 case_QUOTA(m, WDE, PKTIN); 942 case_QUOTA(m, WDE, CPUIO); 943 } 944 } 945 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { 946 switch (quota_id) { 947 case_QUOTA(m, PLE, B0_TXPL); 948 case_QUOTA(m, PLE, B1_TXPL); 949 case_QUOTA(m, PLE, C2H); 950 case_QUOTA(m, PLE, H2C); 951 case_QUOTA(m, PLE, WLAN_CPU); 952 case_QUOTA(m, PLE, MPDU); 953 case_QUOTA(m, PLE, CMAC0_RX); 954 case_QUOTA(m, PLE, CMAC1_RX); 955 case_QUOTA(m, PLE, CMAC1_BBRPT); 956 case_QUOTA(m, PLE, WDRLS); 957 case_QUOTA(m, PLE, CPUIO); 958 } 959 } 960 961 return 0; 962 963 #undef case_QUOTA 964 #undef DLE_DFI_DUMP 965 #undef DLE_DFI_FREE_PAGE_DUMP 966 } 967 968 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, 969 struct seq_file *m) 970 { 971 int ret; 972 973 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 974 if (ret) { 975 seq_puts(m, "[DMAC] : DMAC not enabled\n"); 976 return ret; 977 } 978 979 seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n", 980 rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR)); 981 seq_printf(m, "[0]R_AX_WDRLS_ERR_ISR=0x%08x\n", 982 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 983 seq_printf(m, "[1]R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 984 rtw89_read32(rtwdev, R_AX_SEC_ERR_IMR_ISR)); 985 seq_printf(m, "[2.1]R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 986 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 987 seq_printf(m, "[2.2]R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 988 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 989 seq_printf(m, "[3]R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 990 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 991 seq_printf(m, "[4]R_AX_WDE_ERR_ISR=0x%08x\n", 992 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 993 seq_printf(m, "[5.1]R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 994 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 995 seq_printf(m, "[5.2]R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 996 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 997 seq_printf(m, "[6]R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 998 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 999 seq_printf(m, "[7]R_AX_PKTIN_ERR_ISR=0x%08x\n", 1000 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 1001 seq_printf(m, "[8.1]R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 1002 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 1003 seq_printf(m, "[8.2]R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 1004 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 1005 seq_printf(m, "[8.3]R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 1006 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 1007 seq_printf(m, "[10]R_AX_CPUIO_ERR_ISR=0x%08x\n", 1008 rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR)); 1009 seq_printf(m, "[11.1]R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 1010 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 1011 seq_printf(m, "[11.2]R_AX_BBRPT_CHINFO_ERR_IMR_ISR=0x%08x\n", 1012 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR_ISR)); 1013 seq_printf(m, "[11.3]R_AX_BBRPT_DFS_ERR_IMR_ISR=0x%08x\n", 1014 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR_ISR)); 1015 seq_printf(m, "[11.4]R_AX_LA_ERRFLAG=0x%08x\n", 1016 rtw89_read32(rtwdev, R_AX_LA_ERRFLAG)); 1017 1018 return 0; 1019 } 1020 1021 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, 1022 struct seq_file *m) 1023 { 1024 int ret; 1025 1026 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL); 1027 if (ret) { 1028 seq_puts(m, "[CMAC] : CMAC 0 not enabled\n"); 1029 return ret; 1030 } 1031 1032 seq_printf(m, "R_AX_CMAC_ERR_ISR=0x%08x\n", 1033 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR)); 1034 seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR=0x%08x\n", 1035 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR)); 1036 seq_printf(m, "[1]R_AX_PTCL_ISR0=0x%08x\n", 1037 rtw89_read32(rtwdev, R_AX_PTCL_ISR0)); 1038 seq_printf(m, "[3]R_AX_DLE_CTRL=0x%08x\n", 1039 rtw89_read32(rtwdev, R_AX_DLE_CTRL)); 1040 seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR=0x%08x\n", 1041 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR)); 1042 seq_printf(m, "[5]R_AX_TXPWR_ISR=0x%08x\n", 1043 rtw89_read32(rtwdev, R_AX_TXPWR_ISR)); 1044 seq_printf(m, "[6]R_AX_RMAC_ERR_ISR=0x%08x\n", 1045 rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR)); 1046 seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR=0x%08x\n", 1047 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR)); 1048 1049 ret = rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL); 1050 if (ret) { 1051 seq_puts(m, "[CMAC] : CMAC 1 not enabled\n"); 1052 return ret; 1053 } 1054 1055 seq_printf(m, "R_AX_CMAC_ERR_ISR_C1=0x%08x\n", 1056 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR_C1)); 1057 seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR_C1=0x%08x\n", 1058 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR_C1)); 1059 seq_printf(m, "[1]R_AX_PTCL_ISR0_C1=0x%08x\n", 1060 rtw89_read32(rtwdev, R_AX_PTCL_ISR0_C1)); 1061 seq_printf(m, "[3]R_AX_DLE_CTRL_C1=0x%08x\n", 1062 rtw89_read32(rtwdev, R_AX_DLE_CTRL_C1)); 1063 seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR_C1=0x%02x\n", 1064 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR_C1)); 1065 seq_printf(m, "[5]R_AX_TXPWR_ISR_C1=0x%08x\n", 1066 rtw89_read32(rtwdev, R_AX_TXPWR_ISR_C1)); 1067 seq_printf(m, "[6]R_AX_RMAC_ERR_ISR_C1=0x%08x\n", 1068 rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR_C1)); 1069 seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR_C1=0x%08x\n", 1070 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR_C1)); 1071 1072 return 0; 1073 } 1074 1075 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { 1076 .sel_addr = R_AX_PTCL_DBG, 1077 .sel_byte = 1, 1078 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1079 .srt = 0x00, 1080 .end = 0x3F, 1081 .rd_addr = R_AX_PTCL_DBG_INFO, 1082 .rd_byte = 4, 1083 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1084 }; 1085 1086 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { 1087 .sel_addr = R_AX_PTCL_DBG_C1, 1088 .sel_byte = 1, 1089 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1090 .srt = 0x00, 1091 .end = 0x3F, 1092 .rd_addr = R_AX_PTCL_DBG_INFO_C1, 1093 .rd_byte = 4, 1094 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1095 }; 1096 1097 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { 1098 .sel_addr = R_AX_SCH_DBG_SEL, 1099 .sel_byte = 1, 1100 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1101 .srt = 0x00, 1102 .end = 0x2F, 1103 .rd_addr = R_AX_SCH_DBG, 1104 .rd_byte = 4, 1105 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1106 }; 1107 1108 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { 1109 .sel_addr = R_AX_SCH_DBG_SEL_C1, 1110 .sel_byte = 1, 1111 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1112 .srt = 0x00, 1113 .end = 0x2F, 1114 .rd_addr = R_AX_SCH_DBG_C1, 1115 .rd_byte = 4, 1116 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1117 }; 1118 1119 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { 1120 .sel_addr = R_AX_MACTX_DBG_SEL_CNT, 1121 .sel_byte = 1, 1122 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 1123 .srt = 0x00, 1124 .end = 0x19, 1125 .rd_addr = R_AX_DBG_PORT_SEL, 1126 .rd_byte = 4, 1127 .rd_msk = B_AX_DEBUG_ST_MASK 1128 }; 1129 1130 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { 1131 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, 1132 .sel_byte = 1, 1133 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 1134 .srt = 0x00, 1135 .end = 0x19, 1136 .rd_addr = R_AX_DBG_PORT_SEL, 1137 .rd_byte = 4, 1138 .rd_msk = B_AX_DEBUG_ST_MASK 1139 }; 1140 1141 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { 1142 .sel_addr = R_AX_RX_DEBUG_SELECT, 1143 .sel_byte = 1, 1144 .sel_msk = B_AX_DEBUG_SEL_MASK, 1145 .srt = 0x00, 1146 .end = 0x58, 1147 .rd_addr = R_AX_DBG_PORT_SEL, 1148 .rd_byte = 4, 1149 .rd_msk = B_AX_DEBUG_ST_MASK 1150 }; 1151 1152 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { 1153 .sel_addr = R_AX_RX_DEBUG_SELECT_C1, 1154 .sel_byte = 1, 1155 .sel_msk = B_AX_DEBUG_SEL_MASK, 1156 .srt = 0x00, 1157 .end = 0x58, 1158 .rd_addr = R_AX_DBG_PORT_SEL, 1159 .rd_byte = 4, 1160 .rd_msk = B_AX_DEBUG_ST_MASK 1161 }; 1162 1163 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { 1164 .sel_addr = R_AX_RX_STATE_MONITOR, 1165 .sel_byte = 1, 1166 .sel_msk = B_AX_STATE_SEL_MASK, 1167 .srt = 0x00, 1168 .end = 0x17, 1169 .rd_addr = R_AX_RX_STATE_MONITOR, 1170 .rd_byte = 4, 1171 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 1172 }; 1173 1174 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { 1175 .sel_addr = R_AX_RX_STATE_MONITOR_C1, 1176 .sel_byte = 1, 1177 .sel_msk = B_AX_STATE_SEL_MASK, 1178 .srt = 0x00, 1179 .end = 0x17, 1180 .rd_addr = R_AX_RX_STATE_MONITOR_C1, 1181 .rd_byte = 4, 1182 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 1183 }; 1184 1185 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { 1186 .sel_addr = R_AX_RMAC_PLCP_MON, 1187 .sel_byte = 4, 1188 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 1189 .srt = 0x0, 1190 .end = 0xF, 1191 .rd_addr = R_AX_RMAC_PLCP_MON, 1192 .rd_byte = 4, 1193 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 1194 }; 1195 1196 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { 1197 .sel_addr = R_AX_RMAC_PLCP_MON_C1, 1198 .sel_byte = 4, 1199 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 1200 .srt = 0x0, 1201 .end = 0xF, 1202 .rd_addr = R_AX_RMAC_PLCP_MON_C1, 1203 .rd_byte = 4, 1204 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 1205 }; 1206 1207 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { 1208 .sel_addr = R_AX_DBGSEL_TRXPTCL, 1209 .sel_byte = 1, 1210 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 1211 .srt = 0x08, 1212 .end = 0x10, 1213 .rd_addr = R_AX_DBG_PORT_SEL, 1214 .rd_byte = 4, 1215 .rd_msk = B_AX_DEBUG_ST_MASK 1216 }; 1217 1218 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { 1219 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, 1220 .sel_byte = 1, 1221 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 1222 .srt = 0x08, 1223 .end = 0x10, 1224 .rd_addr = R_AX_DBG_PORT_SEL, 1225 .rd_byte = 4, 1226 .rd_msk = B_AX_DEBUG_ST_MASK 1227 }; 1228 1229 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { 1230 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 1231 .sel_byte = 1, 1232 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1233 .srt = 0x00, 1234 .end = 0x07, 1235 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, 1236 .rd_byte = 4, 1237 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 1238 }; 1239 1240 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { 1241 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 1242 .sel_byte = 1, 1243 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1244 .srt = 0x00, 1245 .end = 0x07, 1246 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, 1247 .rd_byte = 4, 1248 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 1249 }; 1250 1251 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { 1252 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 1253 .sel_byte = 1, 1254 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1255 .srt = 0x00, 1256 .end = 0x07, 1257 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, 1258 .rd_byte = 4, 1259 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 1260 }; 1261 1262 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { 1263 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 1264 .sel_byte = 1, 1265 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1266 .srt = 0x00, 1267 .end = 0x07, 1268 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, 1269 .rd_byte = 4, 1270 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 1271 }; 1272 1273 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { 1274 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 1275 .sel_byte = 1, 1276 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1277 .srt = 0x00, 1278 .end = 0x04, 1279 .rd_addr = R_AX_WMAC_TX_TF_INFO_1, 1280 .rd_byte = 4, 1281 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 1282 }; 1283 1284 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { 1285 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 1286 .sel_byte = 1, 1287 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1288 .srt = 0x00, 1289 .end = 0x04, 1290 .rd_addr = R_AX_WMAC_TX_TF_INFO_2, 1291 .rd_byte = 4, 1292 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 1293 }; 1294 1295 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { 1296 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 1297 .sel_byte = 1, 1298 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1299 .srt = 0x00, 1300 .end = 0x04, 1301 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, 1302 .rd_byte = 4, 1303 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 1304 }; 1305 1306 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { 1307 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 1308 .sel_byte = 1, 1309 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1310 .srt = 0x00, 1311 .end = 0x04, 1312 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, 1313 .rd_byte = 4, 1314 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 1315 }; 1316 1317 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { 1318 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1319 .sel_byte = 4, 1320 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1321 .srt = 0x80000000, 1322 .end = 0x80000001, 1323 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1324 .rd_byte = 4, 1325 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1326 }; 1327 1328 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { 1329 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1330 .sel_byte = 4, 1331 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1332 .srt = 0x80010000, 1333 .end = 0x80010004, 1334 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1335 .rd_byte = 4, 1336 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1337 }; 1338 1339 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { 1340 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1341 .sel_byte = 4, 1342 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1343 .srt = 0x80020000, 1344 .end = 0x80020FFF, 1345 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1346 .rd_byte = 4, 1347 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1348 }; 1349 1350 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { 1351 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1352 .sel_byte = 4, 1353 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1354 .srt = 0x80030000, 1355 .end = 0x80030FFF, 1356 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1357 .rd_byte = 4, 1358 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1359 }; 1360 1361 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { 1362 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1363 .sel_byte = 4, 1364 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1365 .srt = 0x80040000, 1366 .end = 0x80040FFF, 1367 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1368 .rd_byte = 4, 1369 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1370 }; 1371 1372 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { 1373 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1374 .sel_byte = 4, 1375 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1376 .srt = 0x80050000, 1377 .end = 0x80050FFF, 1378 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1379 .rd_byte = 4, 1380 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1381 }; 1382 1383 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { 1384 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1385 .sel_byte = 4, 1386 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1387 .srt = 0x80060000, 1388 .end = 0x80060453, 1389 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1390 .rd_byte = 4, 1391 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1392 }; 1393 1394 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { 1395 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1396 .sel_byte = 4, 1397 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1398 .srt = 0x80070000, 1399 .end = 0x80070011, 1400 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1401 .rd_byte = 4, 1402 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1403 }; 1404 1405 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { 1406 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1407 .sel_byte = 4, 1408 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1409 .srt = 0x80000000, 1410 .end = 0x80000001, 1411 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1412 .rd_byte = 4, 1413 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1414 }; 1415 1416 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { 1417 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1418 .sel_byte = 4, 1419 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1420 .srt = 0x80010000, 1421 .end = 0x8001000A, 1422 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1423 .rd_byte = 4, 1424 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1425 }; 1426 1427 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { 1428 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1429 .sel_byte = 4, 1430 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1431 .srt = 0x80020000, 1432 .end = 0x80020DBF, 1433 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1434 .rd_byte = 4, 1435 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1436 }; 1437 1438 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { 1439 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1440 .sel_byte = 4, 1441 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1442 .srt = 0x80030000, 1443 .end = 0x80030DBF, 1444 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1445 .rd_byte = 4, 1446 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1447 }; 1448 1449 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { 1450 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1451 .sel_byte = 4, 1452 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1453 .srt = 0x80040000, 1454 .end = 0x80040DBF, 1455 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1456 .rd_byte = 4, 1457 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1458 }; 1459 1460 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { 1461 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1462 .sel_byte = 4, 1463 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1464 .srt = 0x80050000, 1465 .end = 0x80050DBF, 1466 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1467 .rd_byte = 4, 1468 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1469 }; 1470 1471 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { 1472 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1473 .sel_byte = 4, 1474 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1475 .srt = 0x80060000, 1476 .end = 0x80060041, 1477 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1478 .rd_byte = 4, 1479 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1480 }; 1481 1482 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { 1483 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1484 .sel_byte = 4, 1485 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1486 .srt = 0x80070000, 1487 .end = 0x80070001, 1488 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1489 .rd_byte = 4, 1490 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1491 }; 1492 1493 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { 1494 .sel_addr = R_AX_DBG_FUN_INTF_CTL, 1495 .sel_byte = 4, 1496 .sel_msk = B_AX_DFI_DATA_MASK, 1497 .srt = 0x80000000, 1498 .end = 0x8000017f, 1499 .rd_addr = R_AX_DBG_FUN_INTF_DATA, 1500 .rd_byte = 4, 1501 .rd_msk = B_AX_DFI_DATA_MASK 1502 }; 1503 1504 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { 1505 .sel_addr = R_AX_PCIE_DBG_CTRL, 1506 .sel_byte = 2, 1507 .sel_msk = B_AX_DBG_SEL_MASK, 1508 .srt = 0x00, 1509 .end = 0x03, 1510 .rd_addr = R_AX_DBG_PORT_SEL, 1511 .rd_byte = 4, 1512 .rd_msk = B_AX_DEBUG_ST_MASK 1513 }; 1514 1515 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { 1516 .sel_addr = R_AX_PCIE_DBG_CTRL, 1517 .sel_byte = 2, 1518 .sel_msk = B_AX_DBG_SEL_MASK, 1519 .srt = 0x00, 1520 .end = 0x04, 1521 .rd_addr = R_AX_DBG_PORT_SEL, 1522 .rd_byte = 4, 1523 .rd_msk = B_AX_DEBUG_ST_MASK 1524 }; 1525 1526 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { 1527 .sel_addr = R_AX_PCIE_DBG_CTRL, 1528 .sel_byte = 2, 1529 .sel_msk = B_AX_DBG_SEL_MASK, 1530 .srt = 0x00, 1531 .end = 0x01, 1532 .rd_addr = R_AX_DBG_PORT_SEL, 1533 .rd_byte = 4, 1534 .rd_msk = B_AX_DEBUG_ST_MASK 1535 }; 1536 1537 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { 1538 .sel_addr = R_AX_PCIE_DBG_CTRL, 1539 .sel_byte = 2, 1540 .sel_msk = B_AX_DBG_SEL_MASK, 1541 .srt = 0x00, 1542 .end = 0x05, 1543 .rd_addr = R_AX_DBG_PORT_SEL, 1544 .rd_byte = 4, 1545 .rd_msk = B_AX_DEBUG_ST_MASK 1546 }; 1547 1548 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { 1549 .sel_addr = R_AX_PCIE_DBG_CTRL, 1550 .sel_byte = 2, 1551 .sel_msk = B_AX_DBG_SEL_MASK, 1552 .srt = 0x00, 1553 .end = 0x05, 1554 .rd_addr = R_AX_DBG_PORT_SEL, 1555 .rd_byte = 4, 1556 .rd_msk = B_AX_DEBUG_ST_MASK 1557 }; 1558 1559 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { 1560 .sel_addr = R_AX_PCIE_DBG_CTRL, 1561 .sel_byte = 2, 1562 .sel_msk = B_AX_DBG_SEL_MASK, 1563 .srt = 0x00, 1564 .end = 0x06, 1565 .rd_addr = R_AX_DBG_PORT_SEL, 1566 .rd_byte = 4, 1567 .rd_msk = B_AX_DEBUG_ST_MASK 1568 }; 1569 1570 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { 1571 .sel_addr = R_AX_DBG_CTRL, 1572 .sel_byte = 1, 1573 .sel_msk = B_AX_DBG_SEL0, 1574 .srt = 0x34, 1575 .end = 0x3C, 1576 .rd_addr = R_AX_DBG_PORT_SEL, 1577 .rd_byte = 4, 1578 .rd_msk = B_AX_DEBUG_ST_MASK 1579 }; 1580 1581 static const struct rtw89_mac_dbg_port_info * 1582 rtw89_debug_mac_dbg_port_sel(struct seq_file *m, 1583 struct rtw89_dev *rtwdev, u32 sel) 1584 { 1585 const struct rtw89_mac_dbg_port_info *info; 1586 u32 val32; 1587 u16 val16; 1588 u8 val8; 1589 1590 switch (sel) { 1591 case RTW89_DBG_PORT_SEL_PTCL_C0: 1592 info = &dbg_port_ptcl_c0; 1593 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); 1594 val16 |= B_AX_PTCL_DBG_EN; 1595 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); 1596 seq_puts(m, "Enable PTCL C0 dbgport.\n"); 1597 break; 1598 case RTW89_DBG_PORT_SEL_PTCL_C1: 1599 info = &dbg_port_ptcl_c1; 1600 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); 1601 val16 |= B_AX_PTCL_DBG_EN; 1602 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); 1603 seq_puts(m, "Enable PTCL C1 dbgport.\n"); 1604 break; 1605 case RTW89_DBG_PORT_SEL_SCH_C0: 1606 info = &dbg_port_sch_c0; 1607 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); 1608 val32 |= B_AX_SCH_DBG_EN; 1609 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); 1610 seq_puts(m, "Enable SCH C0 dbgport.\n"); 1611 break; 1612 case RTW89_DBG_PORT_SEL_SCH_C1: 1613 info = &dbg_port_sch_c1; 1614 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); 1615 val32 |= B_AX_SCH_DBG_EN; 1616 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); 1617 seq_puts(m, "Enable SCH C1 dbgport.\n"); 1618 break; 1619 case RTW89_DBG_PORT_SEL_TMAC_C0: 1620 info = &dbg_port_tmac_c0; 1621 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 1622 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 1623 B_AX_DBGSEL_TRXPTCL_MASK); 1624 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 1625 1626 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1627 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 1628 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 1629 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1630 1631 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1632 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1633 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1634 seq_puts(m, "Enable TMAC C0 dbgport.\n"); 1635 break; 1636 case RTW89_DBG_PORT_SEL_TMAC_C1: 1637 info = &dbg_port_tmac_c1; 1638 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 1639 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 1640 B_AX_DBGSEL_TRXPTCL_MASK); 1641 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 1642 1643 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1644 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 1645 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 1646 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1647 1648 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1649 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1650 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1651 seq_puts(m, "Enable TMAC C1 dbgport.\n"); 1652 break; 1653 case RTW89_DBG_PORT_SEL_RMAC_C0: 1654 info = &dbg_port_rmac_c0; 1655 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 1656 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 1657 B_AX_DBGSEL_TRXPTCL_MASK); 1658 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 1659 1660 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1661 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 1662 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 1663 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1664 1665 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1666 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1667 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1668 1669 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); 1670 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 1671 B_AX_DBGSEL_TRXPTCL_MASK); 1672 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); 1673 seq_puts(m, "Enable RMAC C0 dbgport.\n"); 1674 break; 1675 case RTW89_DBG_PORT_SEL_RMAC_C1: 1676 info = &dbg_port_rmac_c1; 1677 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 1678 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 1679 B_AX_DBGSEL_TRXPTCL_MASK); 1680 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 1681 1682 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1683 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 1684 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 1685 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1686 1687 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1688 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1689 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1690 1691 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 1692 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 1693 B_AX_DBGSEL_TRXPTCL_MASK); 1694 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); 1695 seq_puts(m, "Enable RMAC C1 dbgport.\n"); 1696 break; 1697 case RTW89_DBG_PORT_SEL_RMACST_C0: 1698 info = &dbg_port_rmacst_c0; 1699 seq_puts(m, "Enable RMAC state C0 dbgport.\n"); 1700 break; 1701 case RTW89_DBG_PORT_SEL_RMACST_C1: 1702 info = &dbg_port_rmacst_c1; 1703 seq_puts(m, "Enable RMAC state C1 dbgport.\n"); 1704 break; 1705 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: 1706 info = &dbg_port_rmac_plcp_c0; 1707 seq_puts(m, "Enable RMAC PLCP C0 dbgport.\n"); 1708 break; 1709 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: 1710 info = &dbg_port_rmac_plcp_c1; 1711 seq_puts(m, "Enable RMAC PLCP C1 dbgport.\n"); 1712 break; 1713 case RTW89_DBG_PORT_SEL_TRXPTCL_C0: 1714 info = &dbg_port_trxptcl_c0; 1715 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1716 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); 1717 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); 1718 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1719 1720 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1721 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1722 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1723 seq_puts(m, "Enable TRXPTCL C0 dbgport.\n"); 1724 break; 1725 case RTW89_DBG_PORT_SEL_TRXPTCL_C1: 1726 info = &dbg_port_trxptcl_c1; 1727 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1728 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); 1729 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); 1730 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1731 1732 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1733 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1734 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1735 seq_puts(m, "Enable TRXPTCL C1 dbgport.\n"); 1736 break; 1737 case RTW89_DBG_PORT_SEL_TX_INFOL_C0: 1738 info = &dbg_port_tx_infol_c0; 1739 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1740 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1741 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1742 seq_puts(m, "Enable tx infol dump.\n"); 1743 break; 1744 case RTW89_DBG_PORT_SEL_TX_INFOH_C0: 1745 info = &dbg_port_tx_infoh_c0; 1746 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1747 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1748 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1749 seq_puts(m, "Enable tx infoh dump.\n"); 1750 break; 1751 case RTW89_DBG_PORT_SEL_TX_INFOL_C1: 1752 info = &dbg_port_tx_infol_c1; 1753 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1754 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1755 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1756 seq_puts(m, "Enable tx infol dump.\n"); 1757 break; 1758 case RTW89_DBG_PORT_SEL_TX_INFOH_C1: 1759 info = &dbg_port_tx_infoh_c1; 1760 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1761 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1762 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1763 seq_puts(m, "Enable tx infoh dump.\n"); 1764 break; 1765 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: 1766 info = &dbg_port_txtf_infol_c0; 1767 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1768 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1769 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1770 seq_puts(m, "Enable tx tf infol dump.\n"); 1771 break; 1772 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: 1773 info = &dbg_port_txtf_infoh_c0; 1774 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1775 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1776 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1777 seq_puts(m, "Enable tx tf infoh dump.\n"); 1778 break; 1779 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: 1780 info = &dbg_port_txtf_infol_c1; 1781 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1782 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1783 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1784 seq_puts(m, "Enable tx tf infol dump.\n"); 1785 break; 1786 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: 1787 info = &dbg_port_txtf_infoh_c1; 1788 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1789 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1790 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1791 seq_puts(m, "Enable tx tf infoh dump.\n"); 1792 break; 1793 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: 1794 info = &dbg_port_wde_bufmgn_freepg; 1795 seq_puts(m, "Enable wde bufmgn freepg dump.\n"); 1796 break; 1797 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: 1798 info = &dbg_port_wde_bufmgn_quota; 1799 seq_puts(m, "Enable wde bufmgn quota dump.\n"); 1800 break; 1801 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: 1802 info = &dbg_port_wde_bufmgn_pagellt; 1803 seq_puts(m, "Enable wde bufmgn pagellt dump.\n"); 1804 break; 1805 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: 1806 info = &dbg_port_wde_bufmgn_pktinfo; 1807 seq_puts(m, "Enable wde bufmgn pktinfo dump.\n"); 1808 break; 1809 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: 1810 info = &dbg_port_wde_quemgn_prepkt; 1811 seq_puts(m, "Enable wde quemgn prepkt dump.\n"); 1812 break; 1813 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: 1814 info = &dbg_port_wde_quemgn_nxtpkt; 1815 seq_puts(m, "Enable wde quemgn nxtpkt dump.\n"); 1816 break; 1817 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: 1818 info = &dbg_port_wde_quemgn_qlnktbl; 1819 seq_puts(m, "Enable wde quemgn qlnktbl dump.\n"); 1820 break; 1821 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: 1822 info = &dbg_port_wde_quemgn_qempty; 1823 seq_puts(m, "Enable wde quemgn qempty dump.\n"); 1824 break; 1825 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: 1826 info = &dbg_port_ple_bufmgn_freepg; 1827 seq_puts(m, "Enable ple bufmgn freepg dump.\n"); 1828 break; 1829 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: 1830 info = &dbg_port_ple_bufmgn_quota; 1831 seq_puts(m, "Enable ple bufmgn quota dump.\n"); 1832 break; 1833 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: 1834 info = &dbg_port_ple_bufmgn_pagellt; 1835 seq_puts(m, "Enable ple bufmgn pagellt dump.\n"); 1836 break; 1837 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: 1838 info = &dbg_port_ple_bufmgn_pktinfo; 1839 seq_puts(m, "Enable ple bufmgn pktinfo dump.\n"); 1840 break; 1841 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: 1842 info = &dbg_port_ple_quemgn_prepkt; 1843 seq_puts(m, "Enable ple quemgn prepkt dump.\n"); 1844 break; 1845 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: 1846 info = &dbg_port_ple_quemgn_nxtpkt; 1847 seq_puts(m, "Enable ple quemgn nxtpkt dump.\n"); 1848 break; 1849 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: 1850 info = &dbg_port_ple_quemgn_qlnktbl; 1851 seq_puts(m, "Enable ple quemgn qlnktbl dump.\n"); 1852 break; 1853 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: 1854 info = &dbg_port_ple_quemgn_qempty; 1855 seq_puts(m, "Enable ple quemgn qempty dump.\n"); 1856 break; 1857 case RTW89_DBG_PORT_SEL_PKTINFO: 1858 info = &dbg_port_pktinfo; 1859 seq_puts(m, "Enable pktinfo dump.\n"); 1860 break; 1861 case RTW89_DBG_PORT_SEL_PCIE_TXDMA: 1862 info = &dbg_port_pcie_txdma; 1863 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1864 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); 1865 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); 1866 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1867 seq_puts(m, "Enable pcie txdma dump.\n"); 1868 break; 1869 case RTW89_DBG_PORT_SEL_PCIE_RXDMA: 1870 info = &dbg_port_pcie_rxdma; 1871 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1872 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); 1873 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); 1874 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1875 seq_puts(m, "Enable pcie rxdma dump.\n"); 1876 break; 1877 case RTW89_DBG_PORT_SEL_PCIE_CVT: 1878 info = &dbg_port_pcie_cvt; 1879 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1880 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); 1881 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); 1882 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1883 seq_puts(m, "Enable pcie cvt dump.\n"); 1884 break; 1885 case RTW89_DBG_PORT_SEL_PCIE_CXPL: 1886 info = &dbg_port_pcie_cxpl; 1887 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1888 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); 1889 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); 1890 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1891 seq_puts(m, "Enable pcie cxpl dump.\n"); 1892 break; 1893 case RTW89_DBG_PORT_SEL_PCIE_IO: 1894 info = &dbg_port_pcie_io; 1895 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1896 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); 1897 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); 1898 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1899 seq_puts(m, "Enable pcie io dump.\n"); 1900 break; 1901 case RTW89_DBG_PORT_SEL_PCIE_MISC: 1902 info = &dbg_port_pcie_misc; 1903 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1904 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); 1905 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); 1906 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1907 seq_puts(m, "Enable pcie misc dump.\n"); 1908 break; 1909 case RTW89_DBG_PORT_SEL_PCIE_MISC2: 1910 info = &dbg_port_pcie_misc2; 1911 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); 1912 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, 1913 B_AX_DBG_SEL_MASK); 1914 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); 1915 seq_puts(m, "Enable pcie misc2 dump.\n"); 1916 break; 1917 default: 1918 seq_puts(m, "Dbg port select err\n"); 1919 return NULL; 1920 } 1921 1922 return info; 1923 } 1924 1925 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) 1926 { 1927 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && 1928 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && 1929 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) 1930 return false; 1931 if (rtwdev->chip->chip_id == RTL8852B && 1932 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 1933 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 1934 return false; 1935 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 1936 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && 1937 sel <= RTW89_DBG_PORT_SEL_PKTINFO) 1938 return false; 1939 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && 1940 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && 1941 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) 1942 return false; 1943 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && 1944 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 1945 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 1946 return false; 1947 1948 return true; 1949 } 1950 1951 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, 1952 struct seq_file *m, u32 sel) 1953 { 1954 const struct rtw89_mac_dbg_port_info *info; 1955 u8 val8; 1956 u16 val16; 1957 u32 val32; 1958 u32 i; 1959 1960 info = rtw89_debug_mac_dbg_port_sel(m, rtwdev, sel); 1961 if (!info) { 1962 rtw89_err(rtwdev, "failed to select debug port %d\n", sel); 1963 return -EINVAL; 1964 } 1965 1966 #define case_DBG_SEL(__sel) \ 1967 case RTW89_DBG_PORT_SEL_##__sel: \ 1968 seq_puts(m, "Dump debug port " #__sel ":\n"); \ 1969 break 1970 1971 switch (sel) { 1972 case_DBG_SEL(PTCL_C0); 1973 case_DBG_SEL(PTCL_C1); 1974 case_DBG_SEL(SCH_C0); 1975 case_DBG_SEL(SCH_C1); 1976 case_DBG_SEL(TMAC_C0); 1977 case_DBG_SEL(TMAC_C1); 1978 case_DBG_SEL(RMAC_C0); 1979 case_DBG_SEL(RMAC_C1); 1980 case_DBG_SEL(RMACST_C0); 1981 case_DBG_SEL(RMACST_C1); 1982 case_DBG_SEL(TRXPTCL_C0); 1983 case_DBG_SEL(TRXPTCL_C1); 1984 case_DBG_SEL(TX_INFOL_C0); 1985 case_DBG_SEL(TX_INFOH_C0); 1986 case_DBG_SEL(TX_INFOL_C1); 1987 case_DBG_SEL(TX_INFOH_C1); 1988 case_DBG_SEL(TXTF_INFOL_C0); 1989 case_DBG_SEL(TXTF_INFOH_C0); 1990 case_DBG_SEL(TXTF_INFOL_C1); 1991 case_DBG_SEL(TXTF_INFOH_C1); 1992 case_DBG_SEL(WDE_BUFMGN_FREEPG); 1993 case_DBG_SEL(WDE_BUFMGN_QUOTA); 1994 case_DBG_SEL(WDE_BUFMGN_PAGELLT); 1995 case_DBG_SEL(WDE_BUFMGN_PKTINFO); 1996 case_DBG_SEL(WDE_QUEMGN_PREPKT); 1997 case_DBG_SEL(WDE_QUEMGN_NXTPKT); 1998 case_DBG_SEL(WDE_QUEMGN_QLNKTBL); 1999 case_DBG_SEL(WDE_QUEMGN_QEMPTY); 2000 case_DBG_SEL(PLE_BUFMGN_FREEPG); 2001 case_DBG_SEL(PLE_BUFMGN_QUOTA); 2002 case_DBG_SEL(PLE_BUFMGN_PAGELLT); 2003 case_DBG_SEL(PLE_BUFMGN_PKTINFO); 2004 case_DBG_SEL(PLE_QUEMGN_PREPKT); 2005 case_DBG_SEL(PLE_QUEMGN_NXTPKT); 2006 case_DBG_SEL(PLE_QUEMGN_QLNKTBL); 2007 case_DBG_SEL(PLE_QUEMGN_QEMPTY); 2008 case_DBG_SEL(PKTINFO); 2009 case_DBG_SEL(PCIE_TXDMA); 2010 case_DBG_SEL(PCIE_RXDMA); 2011 case_DBG_SEL(PCIE_CVT); 2012 case_DBG_SEL(PCIE_CXPL); 2013 case_DBG_SEL(PCIE_IO); 2014 case_DBG_SEL(PCIE_MISC); 2015 case_DBG_SEL(PCIE_MISC2); 2016 } 2017 2018 #undef case_DBG_SEL 2019 2020 seq_printf(m, "Sel addr = 0x%X\n", info->sel_addr); 2021 seq_printf(m, "Read addr = 0x%X\n", info->rd_addr); 2022 2023 for (i = info->srt; i <= info->end; i++) { 2024 switch (info->sel_byte) { 2025 case 1: 2026 default: 2027 rtw89_write8_mask(rtwdev, info->sel_addr, 2028 info->sel_msk, i); 2029 seq_printf(m, "0x%02X: ", i); 2030 break; 2031 case 2: 2032 rtw89_write16_mask(rtwdev, info->sel_addr, 2033 info->sel_msk, i); 2034 seq_printf(m, "0x%04X: ", i); 2035 break; 2036 case 4: 2037 rtw89_write32_mask(rtwdev, info->sel_addr, 2038 info->sel_msk, i); 2039 seq_printf(m, "0x%04X: ", i); 2040 break; 2041 } 2042 2043 udelay(10); 2044 2045 switch (info->rd_byte) { 2046 case 1: 2047 default: 2048 val8 = rtw89_read8_mask(rtwdev, 2049 info->rd_addr, info->rd_msk); 2050 seq_printf(m, "0x%02X\n", val8); 2051 break; 2052 case 2: 2053 val16 = rtw89_read16_mask(rtwdev, 2054 info->rd_addr, info->rd_msk); 2055 seq_printf(m, "0x%04X\n", val16); 2056 break; 2057 case 4: 2058 val32 = rtw89_read32_mask(rtwdev, 2059 info->rd_addr, info->rd_msk); 2060 seq_printf(m, "0x%08X\n", val32); 2061 break; 2062 } 2063 } 2064 2065 return 0; 2066 } 2067 2068 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, 2069 struct seq_file *m) 2070 { 2071 u32 sel; 2072 int ret = 0; 2073 2074 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; 2075 sel < RTW89_DBG_PORT_SEL_LAST; sel++) { 2076 if (!is_dbg_port_valid(rtwdev, sel)) 2077 continue; 2078 ret = rtw89_debug_mac_dbg_port_dump(rtwdev, m, sel); 2079 if (ret) { 2080 rtw89_err(rtwdev, 2081 "failed to dump debug port %d\n", sel); 2082 break; 2083 } 2084 } 2085 2086 return ret; 2087 } 2088 2089 static int 2090 rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file *m, void *v) 2091 { 2092 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2093 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2094 2095 if (debugfs_priv->dbgpkg_en.ss_dbg) 2096 rtw89_debug_mac_dump_ss_dbg(rtwdev, m); 2097 if (debugfs_priv->dbgpkg_en.dle_dbg) 2098 rtw89_debug_mac_dump_dle_dbg(rtwdev, m); 2099 if (debugfs_priv->dbgpkg_en.dmac_dbg) 2100 rtw89_debug_mac_dump_dmac_dbg(rtwdev, m); 2101 if (debugfs_priv->dbgpkg_en.cmac_dbg) 2102 rtw89_debug_mac_dump_cmac_dbg(rtwdev, m); 2103 if (debugfs_priv->dbgpkg_en.dbg_port) 2104 rtw89_debug_mac_dump_dbg_port(rtwdev, m); 2105 2106 return 0; 2107 }; 2108 2109 static u8 *rtw89_hex2bin_user(struct rtw89_dev *rtwdev, 2110 const char __user *user_buf, size_t count) 2111 { 2112 char *buf; 2113 u8 *bin; 2114 int num; 2115 int err = 0; 2116 2117 buf = memdup_user(user_buf, count); 2118 if (IS_ERR(buf)) 2119 return buf; 2120 2121 num = count / 2; 2122 bin = kmalloc(num, GFP_KERNEL); 2123 if (!bin) { 2124 err = -EFAULT; 2125 goto out; 2126 } 2127 2128 if (hex2bin(bin, buf, num)) { 2129 rtw89_info(rtwdev, "valid format: H1H2H3...\n"); 2130 kfree(bin); 2131 err = -EINVAL; 2132 } 2133 2134 out: 2135 kfree(buf); 2136 2137 return err ? ERR_PTR(err) : bin; 2138 } 2139 2140 static ssize_t rtw89_debug_priv_send_h2c_set(struct file *filp, 2141 const char __user *user_buf, 2142 size_t count, loff_t *loff) 2143 { 2144 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 2145 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2146 u8 *h2c; 2147 u16 h2c_len = count / 2; 2148 2149 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 2150 if (IS_ERR(h2c)) 2151 return -EFAULT; 2152 2153 rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len); 2154 2155 kfree(h2c); 2156 2157 return count; 2158 } 2159 2160 static int 2161 rtw89_debug_priv_early_h2c_get(struct seq_file *m, void *v) 2162 { 2163 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2164 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2165 struct rtw89_early_h2c *early_h2c; 2166 int seq = 0; 2167 2168 mutex_lock(&rtwdev->mutex); 2169 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) 2170 seq_printf(m, "%d: %*ph\n", ++seq, early_h2c->h2c_len, early_h2c->h2c); 2171 mutex_unlock(&rtwdev->mutex); 2172 2173 return 0; 2174 } 2175 2176 static ssize_t 2177 rtw89_debug_priv_early_h2c_set(struct file *filp, const char __user *user_buf, 2178 size_t count, loff_t *loff) 2179 { 2180 struct seq_file *m = (struct seq_file *)filp->private_data; 2181 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2182 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2183 struct rtw89_early_h2c *early_h2c; 2184 u8 *h2c; 2185 u16 h2c_len = count / 2; 2186 2187 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 2188 if (IS_ERR(h2c)) 2189 return -EFAULT; 2190 2191 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) { 2192 kfree(h2c); 2193 rtw89_fw_free_all_early_h2c(rtwdev); 2194 goto out; 2195 } 2196 2197 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL); 2198 if (!early_h2c) { 2199 kfree(h2c); 2200 return -EFAULT; 2201 } 2202 2203 early_h2c->h2c = h2c; 2204 early_h2c->h2c_len = h2c_len; 2205 2206 mutex_lock(&rtwdev->mutex); 2207 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list); 2208 mutex_unlock(&rtwdev->mutex); 2209 2210 out: 2211 return count; 2212 } 2213 2214 static int 2215 rtw89_debug_priv_fw_crash_get(struct seq_file *m, void *v) 2216 { 2217 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2218 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2219 2220 seq_printf(m, "%d\n", 2221 test_bit(RTW89_FLAG_RESTART_TRIGGER, rtwdev->flags)); 2222 return 0; 2223 } 2224 2225 static ssize_t 2226 rtw89_debug_priv_fw_crash_set(struct file *filp, const char __user *user_buf, 2227 size_t count, loff_t *loff) 2228 { 2229 struct seq_file *m = (struct seq_file *)filp->private_data; 2230 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2231 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2232 bool fw_crash; 2233 int ret; 2234 2235 if (!RTW89_CHK_FW_FEATURE(CRASH_TRIGGER, &rtwdev->fw)) 2236 return -EOPNOTSUPP; 2237 2238 ret = kstrtobool_from_user(user_buf, count, &fw_crash); 2239 if (ret) 2240 return -EINVAL; 2241 2242 if (!fw_crash) 2243 return -EINVAL; 2244 2245 mutex_lock(&rtwdev->mutex); 2246 set_bit(RTW89_FLAG_RESTART_TRIGGER, rtwdev->flags); 2247 ret = rtw89_fw_h2c_trigger_cpu_exception(rtwdev); 2248 mutex_unlock(&rtwdev->mutex); 2249 2250 if (ret) 2251 return ret; 2252 2253 return count; 2254 } 2255 2256 static int rtw89_debug_priv_btc_info_get(struct seq_file *m, void *v) 2257 { 2258 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2259 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2260 2261 rtw89_btc_dump_info(rtwdev, m); 2262 2263 return 0; 2264 } 2265 2266 static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp, 2267 const char __user *user_buf, 2268 size_t count, loff_t *loff) 2269 { 2270 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 2271 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2272 struct rtw89_btc *btc = &rtwdev->btc; 2273 bool btc_manual; 2274 2275 if (kstrtobool_from_user(user_buf, count, &btc_manual)) 2276 goto out; 2277 2278 btc->ctrl.manual = btc_manual; 2279 out: 2280 return count; 2281 } 2282 2283 static ssize_t rtw89_debug_fw_log_btc_manual_set(struct file *filp, 2284 const char __user *user_buf, 2285 size_t count, loff_t *loff) 2286 { 2287 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 2288 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2289 struct rtw89_fw_info *fw_info = &rtwdev->fw; 2290 bool fw_log_manual; 2291 2292 if (kstrtobool_from_user(user_buf, count, &fw_log_manual)) 2293 goto out; 2294 2295 mutex_lock(&rtwdev->mutex); 2296 fw_info->fw_log_enable = fw_log_manual; 2297 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); 2298 mutex_unlock(&rtwdev->mutex); 2299 out: 2300 return count; 2301 } 2302 2303 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) 2304 { 2305 static const char * const he_gi_str[] = { 2306 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", 2307 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", 2308 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", 2309 }; 2310 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2311 struct rate_info *rate = &rtwsta->ra_report.txrate; 2312 struct ieee80211_rx_status *status = &rtwsta->rx_status; 2313 struct seq_file *m = (struct seq_file *)data; 2314 u8 rssi; 2315 2316 seq_printf(m, "TX rate [%d]: ", rtwsta->mac_id); 2317 2318 if (rate->flags & RATE_INFO_FLAGS_MCS) 2319 seq_printf(m, "HT MCS-%d%s", rate->mcs, 2320 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 2321 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) 2322 seq_printf(m, "VHT %dSS MCS-%d%s", rate->nss, rate->mcs, 2323 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 2324 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) 2325 seq_printf(m, "HE %dSS MCS-%d GI:%s", rate->nss, rate->mcs, 2326 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 2327 he_gi_str[rate->he_gi] : "N/A"); 2328 else 2329 seq_printf(m, "Legacy %d", rate->legacy); 2330 seq_printf(m, "%s", rtwsta->ra_report.might_fallback_legacy ? " FB_G" : ""); 2331 seq_printf(m, "\t(hw_rate=0x%x)", rtwsta->ra_report.hw_rate); 2332 seq_printf(m, "\t==> agg_wait=%d (%d)\n", rtwsta->max_agg_wait, 2333 sta->max_rc_amsdu_len); 2334 2335 seq_printf(m, "RX rate [%d]: ", rtwsta->mac_id); 2336 2337 switch (status->encoding) { 2338 case RX_ENC_LEGACY: 2339 seq_printf(m, "Legacy %d", status->rate_idx + 2340 (status->band != NL80211_BAND_2GHZ ? 4 : 0)); 2341 break; 2342 case RX_ENC_HT: 2343 seq_printf(m, "HT MCS-%d%s", status->rate_idx, 2344 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 2345 break; 2346 case RX_ENC_VHT: 2347 seq_printf(m, "VHT %dSS MCS-%d%s", status->nss, status->rate_idx, 2348 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 2349 break; 2350 case RX_ENC_HE: 2351 seq_printf(m, "HE %dSS MCS-%d GI:%s", status->nss, status->rate_idx, 2352 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 2353 he_gi_str[rate->he_gi] : "N/A"); 2354 break; 2355 } 2356 seq_printf(m, "\t(hw_rate=0x%x)\n", rtwsta->rx_hw_rate); 2357 2358 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 2359 seq_printf(m, "RSSI: %d dBm (raw=%d, prev=%d)\n", 2360 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta->prev_rssi); 2361 } 2362 2363 static void 2364 rtw89_debug_append_rx_rate(struct seq_file *m, struct rtw89_pkt_stat *pkt_stat, 2365 enum rtw89_hw_rate first_rate, int len) 2366 { 2367 int i; 2368 2369 for (i = 0; i < len; i++) 2370 seq_printf(m, "%s%u", i == 0 ? "" : ", ", 2371 pkt_stat->rx_rate_cnt[first_rate + i]); 2372 } 2373 2374 static const struct rtw89_rx_rate_cnt_info { 2375 enum rtw89_hw_rate first_rate; 2376 int len; 2377 int ext; 2378 const char *rate_mode; 2379 } rtw89_rx_rate_cnt_infos[] = { 2380 {RTW89_HW_RATE_CCK1, 4, 0, "Legacy:"}, 2381 {RTW89_HW_RATE_OFDM6, 8, 0, "OFDM:"}, 2382 {RTW89_HW_RATE_MCS0, 8, 0, "HT 0:"}, 2383 {RTW89_HW_RATE_MCS8, 8, 0, "HT 1:"}, 2384 {RTW89_HW_RATE_VHT_NSS1_MCS0, 10, 2, "VHT 1SS:"}, 2385 {RTW89_HW_RATE_VHT_NSS2_MCS0, 10, 2, "VHT 2SS:"}, 2386 {RTW89_HW_RATE_HE_NSS1_MCS0, 12, 0, "HE 1SS:"}, 2387 {RTW89_HW_RATE_HE_NSS2_MCS0, 12, 0, "HE 2ss:"}, 2388 }; 2389 2390 static int rtw89_debug_priv_phy_info_get(struct seq_file *m, void *v) 2391 { 2392 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2393 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2394 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2395 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 2396 const struct rtw89_rx_rate_cnt_info *info; 2397 int i; 2398 2399 seq_printf(m, "TP TX: %u [%u] Mbps (lv: %d), RX: %u [%u] Mbps (lv: %d)\n", 2400 stats->tx_throughput, stats->tx_throughput_raw, stats->tx_tfc_lv, 2401 stats->rx_throughput, stats->rx_throughput_raw, stats->rx_tfc_lv); 2402 seq_printf(m, "Beacon: %u, TF: %u\n", pkt_stat->beacon_nr, 2403 stats->rx_tf_periodic); 2404 seq_printf(m, "Avg packet length: TX=%u, RX=%u\n", stats->tx_avg_len, 2405 stats->rx_avg_len); 2406 2407 seq_puts(m, "RX count:\n"); 2408 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { 2409 info = &rtw89_rx_rate_cnt_infos[i]; 2410 seq_printf(m, "%10s [", info->rate_mode); 2411 rtw89_debug_append_rx_rate(m, pkt_stat, 2412 info->first_rate, info->len); 2413 if (info->ext) { 2414 seq_puts(m, "]["); 2415 rtw89_debug_append_rx_rate(m, pkt_stat, 2416 info->first_rate + info->len, info->ext); 2417 } 2418 seq_puts(m, "]\n"); 2419 } 2420 2421 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, m); 2422 2423 return 0; 2424 } 2425 2426 static void rtw89_dump_addr_cam(struct seq_file *m, 2427 struct rtw89_addr_cam_entry *addr_cam) 2428 { 2429 struct rtw89_sec_cam_entry *sec_entry; 2430 int i; 2431 2432 seq_printf(m, "\taddr_cam_idx=%u\n", addr_cam->addr_cam_idx); 2433 seq_printf(m, "\t-> bssid_cam_idx=%u\n", addr_cam->bssid_cam_idx); 2434 seq_printf(m, "\tsec_cam_bitmap=%*ph\n", (int)sizeof(addr_cam->sec_cam_map), 2435 addr_cam->sec_cam_map); 2436 for (i = 0; i < RTW89_SEC_CAM_IN_ADDR_CAM; i++) { 2437 sec_entry = addr_cam->sec_entries[i]; 2438 if (!sec_entry) 2439 continue; 2440 seq_printf(m, "\tsec[%d]: sec_cam_idx %u", i, sec_entry->sec_cam_idx); 2441 if (sec_entry->ext_key) 2442 seq_printf(m, ", %u", sec_entry->sec_cam_idx + 1); 2443 seq_puts(m, "\n"); 2444 } 2445 } 2446 2447 static 2448 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 2449 { 2450 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2451 struct seq_file *m = (struct seq_file *)data; 2452 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam; 2453 2454 seq_printf(m, "VIF [%d] %pM\n", rtwvif->mac_id, rtwvif->mac_addr); 2455 seq_printf(m, "\tbssid_cam_idx=%u\n", bssid_cam->bssid_cam_idx); 2456 rtw89_dump_addr_cam(m, &rtwvif->addr_cam); 2457 } 2458 2459 static void rtw89_dump_ba_cam(struct seq_file *m, struct rtw89_sta *rtwsta) 2460 { 2461 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 2462 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 2463 struct rtw89_ba_cam_entry *entry; 2464 bool first = true; 2465 2466 list_for_each_entry(entry, &rtwsta->ba_cam_list, list) { 2467 if (first) { 2468 seq_puts(m, "\tba_cam "); 2469 first = false; 2470 } else { 2471 seq_puts(m, ", "); 2472 } 2473 seq_printf(m, "tid[%u]=%d", entry->tid, 2474 (int)(entry - rtwdev->cam_info.ba_cam_entry)); 2475 } 2476 seq_puts(m, "\n"); 2477 } 2478 2479 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta) 2480 { 2481 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2482 struct seq_file *m = (struct seq_file *)data; 2483 2484 seq_printf(m, "STA [%d] %pM %s\n", rtwsta->mac_id, sta->addr, 2485 sta->tdls ? "(TDLS)" : ""); 2486 rtw89_dump_addr_cam(m, &rtwsta->addr_cam); 2487 rtw89_dump_ba_cam(m, rtwsta); 2488 } 2489 2490 static int rtw89_debug_priv_stations_get(struct seq_file *m, void *v) 2491 { 2492 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2493 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2494 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 2495 2496 mutex_lock(&rtwdev->mutex); 2497 2498 seq_puts(m, "map:\n"); 2499 seq_printf(m, "\tmac_id: %*ph\n", (int)sizeof(rtwdev->mac_id_map), 2500 rtwdev->mac_id_map); 2501 seq_printf(m, "\taddr_cam: %*ph\n", (int)sizeof(cam_info->addr_cam_map), 2502 cam_info->addr_cam_map); 2503 seq_printf(m, "\tbssid_cam: %*ph\n", (int)sizeof(cam_info->bssid_cam_map), 2504 cam_info->bssid_cam_map); 2505 seq_printf(m, "\tsec_cam: %*ph\n", (int)sizeof(cam_info->sec_cam_map), 2506 cam_info->sec_cam_map); 2507 seq_printf(m, "\tba_cam: %*ph\n", (int)sizeof(cam_info->ba_cam_map), 2508 cam_info->ba_cam_map); 2509 2510 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw, 2511 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, m); 2512 2513 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, m); 2514 2515 mutex_unlock(&rtwdev->mutex); 2516 2517 return 0; 2518 } 2519 2520 static struct rtw89_debugfs_priv rtw89_debug_priv_read_reg = { 2521 .cb_read = rtw89_debug_priv_read_reg_get, 2522 .cb_write = rtw89_debug_priv_read_reg_select, 2523 }; 2524 2525 static struct rtw89_debugfs_priv rtw89_debug_priv_write_reg = { 2526 .cb_write = rtw89_debug_priv_write_reg_set, 2527 }; 2528 2529 static struct rtw89_debugfs_priv rtw89_debug_priv_read_rf = { 2530 .cb_read = rtw89_debug_priv_read_rf_get, 2531 .cb_write = rtw89_debug_priv_read_rf_select, 2532 }; 2533 2534 static struct rtw89_debugfs_priv rtw89_debug_priv_write_rf = { 2535 .cb_write = rtw89_debug_priv_write_rf_set, 2536 }; 2537 2538 static struct rtw89_debugfs_priv rtw89_debug_priv_rf_reg_dump = { 2539 .cb_read = rtw89_debug_priv_rf_reg_dump_get, 2540 }; 2541 2542 static struct rtw89_debugfs_priv rtw89_debug_priv_txpwr_table = { 2543 .cb_read = rtw89_debug_priv_txpwr_table_get, 2544 }; 2545 2546 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_reg_dump = { 2547 .cb_read = rtw89_debug_priv_mac_reg_dump_get, 2548 .cb_write = rtw89_debug_priv_mac_reg_dump_select, 2549 }; 2550 2551 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_mem_dump = { 2552 .cb_read = rtw89_debug_priv_mac_mem_dump_get, 2553 .cb_write = rtw89_debug_priv_mac_mem_dump_select, 2554 }; 2555 2556 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_dbg_port_dump = { 2557 .cb_read = rtw89_debug_priv_mac_dbg_port_dump_get, 2558 .cb_write = rtw89_debug_priv_mac_dbg_port_dump_select, 2559 }; 2560 2561 static struct rtw89_debugfs_priv rtw89_debug_priv_send_h2c = { 2562 .cb_write = rtw89_debug_priv_send_h2c_set, 2563 }; 2564 2565 static struct rtw89_debugfs_priv rtw89_debug_priv_early_h2c = { 2566 .cb_read = rtw89_debug_priv_early_h2c_get, 2567 .cb_write = rtw89_debug_priv_early_h2c_set, 2568 }; 2569 2570 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_crash = { 2571 .cb_read = rtw89_debug_priv_fw_crash_get, 2572 .cb_write = rtw89_debug_priv_fw_crash_set, 2573 }; 2574 2575 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_info = { 2576 .cb_read = rtw89_debug_priv_btc_info_get, 2577 }; 2578 2579 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_manual = { 2580 .cb_write = rtw89_debug_priv_btc_manual_set, 2581 }; 2582 2583 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_log_manual = { 2584 .cb_write = rtw89_debug_fw_log_btc_manual_set, 2585 }; 2586 2587 static struct rtw89_debugfs_priv rtw89_debug_priv_phy_info = { 2588 .cb_read = rtw89_debug_priv_phy_info_get, 2589 }; 2590 2591 static struct rtw89_debugfs_priv rtw89_debug_priv_stations = { 2592 .cb_read = rtw89_debug_priv_stations_get, 2593 }; 2594 2595 #define rtw89_debugfs_add(name, mode, fopname, parent) \ 2596 do { \ 2597 rtw89_debug_priv_ ##name.rtwdev = rtwdev; \ 2598 if (!debugfs_create_file(#name, mode, \ 2599 parent, &rtw89_debug_priv_ ##name, \ 2600 &file_ops_ ##fopname)) \ 2601 pr_debug("Unable to initialize debugfs:%s\n", #name); \ 2602 } while (0) 2603 2604 #define rtw89_debugfs_add_w(name) \ 2605 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) 2606 #define rtw89_debugfs_add_rw(name) \ 2607 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) 2608 #define rtw89_debugfs_add_r(name) \ 2609 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) 2610 2611 void rtw89_debugfs_init(struct rtw89_dev *rtwdev) 2612 { 2613 struct dentry *debugfs_topdir; 2614 2615 debugfs_topdir = debugfs_create_dir("rtw89", 2616 rtwdev->hw->wiphy->debugfsdir); 2617 2618 rtw89_debugfs_add_rw(read_reg); 2619 rtw89_debugfs_add_w(write_reg); 2620 rtw89_debugfs_add_rw(read_rf); 2621 rtw89_debugfs_add_w(write_rf); 2622 rtw89_debugfs_add_r(rf_reg_dump); 2623 rtw89_debugfs_add_r(txpwr_table); 2624 rtw89_debugfs_add_rw(mac_reg_dump); 2625 rtw89_debugfs_add_rw(mac_mem_dump); 2626 rtw89_debugfs_add_rw(mac_dbg_port_dump); 2627 rtw89_debugfs_add_w(send_h2c); 2628 rtw89_debugfs_add_rw(early_h2c); 2629 rtw89_debugfs_add_rw(fw_crash); 2630 rtw89_debugfs_add_r(btc_info); 2631 rtw89_debugfs_add_w(btc_manual); 2632 rtw89_debugfs_add_w(fw_log_manual); 2633 rtw89_debugfs_add_r(phy_info); 2634 rtw89_debugfs_add_r(stations); 2635 } 2636 #endif 2637 2638 #ifdef CONFIG_RTW89_DEBUGMSG 2639 void __rtw89_debug(struct rtw89_dev *rtwdev, 2640 enum rtw89_debug_mask mask, 2641 const char *fmt, ...) 2642 { 2643 struct va_format vaf = { 2644 .fmt = fmt, 2645 }; 2646 2647 va_list args; 2648 2649 va_start(args, fmt); 2650 vaf.va = &args; 2651 2652 if (rtw89_debug_mask & mask) 2653 #if defined(__linux__) 2654 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); 2655 #elif defined(__FreeBSD__) 2656 { 2657 char *str; 2658 vasprintf(&str, M_KMALLOC, vaf.fmt, args); 2659 dev_printk(KERN_DEBUG, rtwdev->dev, "%s", str); 2660 free(str, M_KMALLOC); 2661 } 2662 #endif 2663 2664 va_end(args); 2665 } 2666 EXPORT_SYMBOL(__rtw89_debug); 2667 #endif 2668