1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #if defined(__FreeBSD__) 6 #define LINUXKPI_PARAM_PREFIX rtw89_debug_ 7 #endif 8 9 #include <linux/vmalloc.h> 10 11 #include "coex.h" 12 #include "debug.h" 13 #include "fw.h" 14 #include "mac.h" 15 #include "pci.h" 16 #include "phy.h" 17 #include "ps.h" 18 #include "reg.h" 19 #include "sar.h" 20 #include "util.h" 21 #if defined(__FreeBSD__) 22 #ifdef CONFIG_RTW89_DEBUGFS 23 #include <linux/debugfs.h> 24 #endif 25 #endif 26 27 #ifdef CONFIG_RTW89_DEBUGMSG 28 unsigned int rtw89_debug_mask; 29 EXPORT_SYMBOL(rtw89_debug_mask); 30 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); 31 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 32 #endif 33 34 #ifdef CONFIG_RTW89_DEBUGFS 35 struct rtw89_debugfs_priv_opt { 36 bool rlock:1; 37 bool wlock:1; 38 size_t rsize; 39 }; 40 41 struct rtw89_debugfs_priv { 42 struct rtw89_dev *rtwdev; 43 ssize_t (*cb_read)(struct rtw89_dev *rtwdev, 44 struct rtw89_debugfs_priv *debugfs_priv, 45 char *buf, size_t bufsz); 46 ssize_t (*cb_write)(struct rtw89_dev *rtwdev, 47 struct rtw89_debugfs_priv *debugfs_priv, 48 const char *buf, size_t count); 49 struct rtw89_debugfs_priv_opt opt; 50 union { 51 u32 cb_data; 52 struct { 53 u32 addr; 54 u32 len; 55 } read_reg; 56 struct { 57 u32 addr; 58 u32 mask; 59 u8 path; 60 } read_rf; 61 struct { 62 u8 ss_dbg:1; 63 u8 dle_dbg:1; 64 u8 dmac_dbg:1; 65 u8 cmac_dbg:1; 66 u8 dbg_port:1; 67 } dbgpkg_en; 68 struct { 69 u32 start; 70 u32 len; 71 u8 sel; 72 } mac_mem; 73 }; 74 ssize_t rused; 75 char *rbuf; 76 }; 77 78 struct rtw89_debugfs { 79 struct rtw89_debugfs_priv read_reg; 80 struct rtw89_debugfs_priv write_reg; 81 struct rtw89_debugfs_priv read_rf; 82 struct rtw89_debugfs_priv write_rf; 83 struct rtw89_debugfs_priv rf_reg_dump; 84 struct rtw89_debugfs_priv txpwr_table; 85 struct rtw89_debugfs_priv mac_reg_dump; 86 struct rtw89_debugfs_priv mac_mem_dump; 87 struct rtw89_debugfs_priv mac_dbg_port_dump; 88 struct rtw89_debugfs_priv send_h2c; 89 struct rtw89_debugfs_priv early_h2c; 90 struct rtw89_debugfs_priv fw_crash; 91 struct rtw89_debugfs_priv btc_info; 92 struct rtw89_debugfs_priv btc_manual; 93 struct rtw89_debugfs_priv fw_log_manual; 94 struct rtw89_debugfs_priv phy_info; 95 struct rtw89_debugfs_priv stations; 96 struct rtw89_debugfs_priv disable_dm; 97 struct rtw89_debugfs_priv mlo_mode; 98 struct rtw89_debugfs_priv beacon_info; 99 struct rtw89_debugfs_priv diag_mac; 100 }; 101 102 struct rtw89_debugfs_iter_data { 103 char *buf; 104 size_t bufsz; 105 int written_sz; 106 }; 107 108 static void rtw89_debugfs_iter_data_setup(struct rtw89_debugfs_iter_data *iter_data, 109 char *buf, size_t bufsz) 110 { 111 iter_data->buf = buf; 112 iter_data->bufsz = bufsz; 113 iter_data->written_sz = 0; 114 } 115 116 static void rtw89_debugfs_iter_data_next(struct rtw89_debugfs_iter_data *iter_data, 117 char *buf, size_t bufsz, int written_sz) 118 { 119 iter_data->buf = buf; 120 iter_data->bufsz = bufsz; 121 iter_data->written_sz += written_sz; 122 } 123 124 static const u16 rtw89_rate_info_bw_to_mhz_map[] = { 125 [RATE_INFO_BW_20] = 20, 126 [RATE_INFO_BW_40] = 40, 127 [RATE_INFO_BW_80] = 80, 128 [RATE_INFO_BW_160] = 160, 129 [RATE_INFO_BW_320] = 320, 130 }; 131 132 static u16 rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw) 133 { 134 if (bw < ARRAY_SIZE(rtw89_rate_info_bw_to_mhz_map)) 135 return rtw89_rate_info_bw_to_mhz_map[bw]; 136 137 return 0; 138 } 139 140 static ssize_t rtw89_debugfs_file_read_helper(struct wiphy *wiphy, struct file *file, 141 char *buf, size_t bufsz, void *data) 142 { 143 struct rtw89_debugfs_priv *debugfs_priv = data; 144 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 145 ssize_t n; 146 147 n = debugfs_priv->cb_read(rtwdev, debugfs_priv, buf, bufsz); 148 rtw89_might_trailing_ellipsis(buf, bufsz, n); 149 150 return n; 151 } 152 153 static ssize_t rtw89_debugfs_file_read(struct file *file, char __user *userbuf, 154 size_t count, loff_t *ppos) 155 { 156 struct rtw89_debugfs_priv *debugfs_priv = file->private_data; 157 struct rtw89_debugfs_priv_opt *opt = &debugfs_priv->opt; 158 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 159 size_t bufsz = opt->rsize ? opt->rsize : PAGE_SIZE; 160 char *buf; 161 ssize_t n; 162 163 if (!debugfs_priv->rbuf) 164 debugfs_priv->rbuf = devm_kzalloc(rtwdev->dev, bufsz, GFP_KERNEL); 165 166 buf = debugfs_priv->rbuf; 167 if (!buf) 168 return -ENOMEM; 169 170 if (*ppos) { 171 n = debugfs_priv->rused; 172 goto out; 173 } 174 175 if (opt->rlock) { 176 n = wiphy_locked_debugfs_read(rtwdev->hw->wiphy, file, buf, bufsz, 177 userbuf, count, ppos, 178 rtw89_debugfs_file_read_helper, 179 debugfs_priv); 180 debugfs_priv->rused = n; 181 182 return n; 183 } 184 185 n = rtw89_debugfs_file_read_helper(rtwdev->hw->wiphy, file, buf, bufsz, 186 debugfs_priv); 187 debugfs_priv->rused = n; 188 189 out: 190 return simple_read_from_buffer(userbuf, count, ppos, buf, n); 191 } 192 193 static ssize_t rtw89_debugfs_file_write_helper(struct wiphy *wiphy, struct file *file, 194 char *buf, size_t count, void *data) 195 { 196 struct rtw89_debugfs_priv *debugfs_priv = data; 197 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 198 199 return debugfs_priv->cb_write(rtwdev, debugfs_priv, buf, count); 200 } 201 202 static ssize_t rtw89_debugfs_file_write(struct file *file, 203 const char __user *userbuf, 204 size_t count, loff_t *loff) 205 { 206 struct rtw89_debugfs_priv *debugfs_priv = file->private_data; 207 struct rtw89_debugfs_priv_opt *opt = &debugfs_priv->opt; 208 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 209 char *buf __free(kfree) = kmalloc(count + 1, GFP_KERNEL); 210 ssize_t n; 211 212 if (!buf) 213 return -ENOMEM; 214 215 if (opt->wlock) { 216 n = wiphy_locked_debugfs_write(rtwdev->hw->wiphy, 217 file, buf, count + 1, 218 userbuf, count, 219 rtw89_debugfs_file_write_helper, 220 debugfs_priv); 221 return n; 222 } 223 224 if (copy_from_user(buf, userbuf, count)) 225 return -EFAULT; 226 227 buf[count] = '\0'; 228 229 return debugfs_priv->cb_write(rtwdev, debugfs_priv, buf, count); 230 } 231 232 static const struct debugfs_short_fops file_ops_single_r = { 233 .read = rtw89_debugfs_file_read, 234 .llseek = generic_file_llseek, 235 }; 236 237 static const struct debugfs_short_fops file_ops_common_rw = { 238 .read = rtw89_debugfs_file_read, 239 .write = rtw89_debugfs_file_write, 240 .llseek = generic_file_llseek, 241 }; 242 243 static const struct debugfs_short_fops file_ops_single_w = { 244 .write = rtw89_debugfs_file_write, 245 .llseek = generic_file_llseek, 246 }; 247 248 static ssize_t 249 rtw89_debug_priv_read_reg_select(struct rtw89_dev *rtwdev, 250 struct rtw89_debugfs_priv *debugfs_priv, 251 const char *buf, size_t count) 252 { 253 u32 addr, len; 254 int num; 255 256 num = sscanf(buf, "%x %x", &addr, &len); 257 if (num != 2) { 258 rtw89_info(rtwdev, "invalid format: <addr> <len>\n"); 259 return -EINVAL; 260 } 261 262 debugfs_priv->read_reg.addr = addr; 263 debugfs_priv->read_reg.len = len; 264 265 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); 266 267 return count; 268 } 269 270 static 271 ssize_t rtw89_debug_priv_read_reg_get(struct rtw89_dev *rtwdev, 272 struct rtw89_debugfs_priv *debugfs_priv, 273 char *buf, size_t bufsz) 274 { 275 char *p = buf, *end = buf + bufsz; 276 u32 addr, addr_end, data, k; 277 u32 len; 278 279 len = debugfs_priv->read_reg.len; 280 addr = debugfs_priv->read_reg.addr; 281 282 if (len > 4) 283 goto ndata; 284 285 switch (len) { 286 case 1: 287 data = rtw89_read8(rtwdev, addr); 288 break; 289 case 2: 290 data = rtw89_read16(rtwdev, addr); 291 break; 292 case 4: 293 data = rtw89_read32(rtwdev, addr); 294 break; 295 default: 296 rtw89_info(rtwdev, "invalid read reg len %d\n", len); 297 return -EINVAL; 298 } 299 300 p += scnprintf(p, end - p, "get %d bytes at 0x%08x=0x%08x\n", len, 301 addr, data); 302 303 return p - buf; 304 305 ndata: 306 addr_end = addr + len; 307 308 for (; addr < addr_end; addr += 16) { 309 p += scnprintf(p, end - p, "%08xh : ", 0x18600000 + addr); 310 for (k = 0; k < 16; k += 4) { 311 data = rtw89_read32(rtwdev, addr + k); 312 p += scnprintf(p, end - p, "%08x ", data); 313 } 314 p += scnprintf(p, end - p, "\n"); 315 } 316 317 return p - buf; 318 } 319 320 static 321 ssize_t rtw89_debug_priv_write_reg_set(struct rtw89_dev *rtwdev, 322 struct rtw89_debugfs_priv *debugfs_priv, 323 const char *buf, size_t count) 324 { 325 u32 addr, val, len; 326 int num; 327 328 num = sscanf(buf, "%x %x %x", &addr, &val, &len); 329 if (num != 3) { 330 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n"); 331 return -EINVAL; 332 } 333 334 switch (len) { 335 case 1: 336 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); 337 rtw89_write8(rtwdev, addr, (u8)val); 338 break; 339 case 2: 340 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); 341 rtw89_write16(rtwdev, addr, (u16)val); 342 break; 343 case 4: 344 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); 345 rtw89_write32(rtwdev, addr, (u32)val); 346 break; 347 default: 348 rtw89_info(rtwdev, "invalid read write len %d\n", len); 349 break; 350 } 351 352 return count; 353 } 354 355 static ssize_t 356 rtw89_debug_priv_read_rf_select(struct rtw89_dev *rtwdev, 357 struct rtw89_debugfs_priv *debugfs_priv, 358 const char *buf, size_t count) 359 { 360 u32 addr, mask; 361 u8 path; 362 int num; 363 364 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); 365 if (num != 3) { 366 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n"); 367 return -EINVAL; 368 } 369 370 if (path >= rtwdev->chip->rf_path_num) { 371 rtw89_info(rtwdev, "wrong rf path\n"); 372 return -EINVAL; 373 } 374 debugfs_priv->read_rf.addr = addr; 375 debugfs_priv->read_rf.mask = mask; 376 debugfs_priv->read_rf.path = path; 377 378 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); 379 380 return count; 381 } 382 383 static 384 ssize_t rtw89_debug_priv_read_rf_get(struct rtw89_dev *rtwdev, 385 struct rtw89_debugfs_priv *debugfs_priv, 386 char *buf, size_t bufsz) 387 { 388 char *p = buf, *end = buf + bufsz; 389 u32 addr, data, mask; 390 u8 path; 391 392 addr = debugfs_priv->read_rf.addr; 393 mask = debugfs_priv->read_rf.mask; 394 path = debugfs_priv->read_rf.path; 395 396 data = rtw89_read_rf(rtwdev, path, addr, mask); 397 398 p += scnprintf(p, end - p, "path %d, rf register 0x%08x=0x%08x\n", 399 path, addr, data); 400 401 return p - buf; 402 } 403 404 static 405 ssize_t rtw89_debug_priv_write_rf_set(struct rtw89_dev *rtwdev, 406 struct rtw89_debugfs_priv *debugfs_priv, 407 const char *buf, size_t count) 408 { 409 u32 addr, val, mask; 410 u8 path; 411 int num; 412 413 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); 414 if (num != 4) { 415 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n"); 416 return -EINVAL; 417 } 418 419 if (path >= rtwdev->chip->rf_path_num) { 420 rtw89_info(rtwdev, "wrong rf path\n"); 421 return -EINVAL; 422 } 423 424 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", 425 path, addr, val, mask); 426 rtw89_write_rf(rtwdev, path, addr, mask, val); 427 428 return count; 429 } 430 431 static 432 ssize_t rtw89_debug_priv_rf_reg_dump_get(struct rtw89_dev *rtwdev, 433 struct rtw89_debugfs_priv *debugfs_priv, 434 char *buf, size_t bufsz) 435 { 436 const struct rtw89_chip_info *chip = rtwdev->chip; 437 char *p = buf, *end = buf + bufsz; 438 u32 addr, offset, data; 439 u8 path; 440 441 for (path = 0; path < chip->rf_path_num; path++) { 442 p += scnprintf(p, end - p, "RF path %d:\n\n", path); 443 for (addr = 0; addr < 0x100; addr += 4) { 444 p += scnprintf(p, end - p, "0x%08x: ", addr); 445 for (offset = 0; offset < 4; offset++) { 446 data = rtw89_read_rf(rtwdev, path, 447 addr + offset, RFREG_MASK); 448 p += scnprintf(p, end - p, "0x%05x ", data); 449 } 450 p += scnprintf(p, end - p, "\n"); 451 } 452 p += scnprintf(p, end - p, "\n"); 453 } 454 455 return p - buf; 456 } 457 458 struct txpwr_ent { 459 bool nested; 460 union { 461 const char *txt; 462 const struct txpwr_ent *ptr; 463 }; 464 u8 len; 465 }; 466 467 struct txpwr_map { 468 const struct txpwr_ent *ent; 469 u8 size; 470 u32 addr_from; 471 u32 addr_to; 472 u32 addr_to_1ss; 473 }; 474 475 #define __GEN_TXPWR_ENT_NESTED(_e) \ 476 { .nested = true, .ptr = __txpwr_ent_##_e, \ 477 .len = ARRAY_SIZE(__txpwr_ent_##_e) } 478 479 #define __GEN_TXPWR_ENT0(_t) { .len = 0, .txt = _t } 480 481 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ 482 { .len = 2, .txt = _t "\t- " _e0 " " _e1 } 483 484 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ 485 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } 486 487 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ 488 { .len = 8, .txt = _t "\t- " \ 489 _e0 " " _e1 " " _e2 " " _e3 " " \ 490 _e4 " " _e5 " " _e6 " " _e7 } 491 492 static const struct txpwr_ent __txpwr_ent_byr_ax[] = { 493 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 494 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 495 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 496 /* 1NSS */ 497 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 498 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 499 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 500 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 501 /* 2NSS */ 502 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 503 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 504 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 505 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 506 }; 507 508 static_assert((ARRAY_SIZE(__txpwr_ent_byr_ax) * 4) == 509 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); 510 511 static const struct txpwr_map __txpwr_map_byr_ax = { 512 .ent = __txpwr_ent_byr_ax, 513 .size = ARRAY_SIZE(__txpwr_ent_byr_ax), 514 .addr_from = R_AX_PWR_BY_RATE, 515 .addr_to = R_AX_PWR_BY_RATE_MAX, 516 .addr_to_1ss = R_AX_PWR_BY_RATE_1SS_MAX, 517 }; 518 519 static const struct txpwr_ent __txpwr_ent_lmt_ax[] = { 520 /* 1TX */ 521 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), 522 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), 523 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), 524 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), 525 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), 526 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), 527 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), 528 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), 529 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), 530 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), 531 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), 532 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), 533 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), 534 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), 535 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), 536 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), 537 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), 538 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), 539 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), 540 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), 541 /* 2TX */ 542 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), 543 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), 544 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), 545 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), 546 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), 547 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), 548 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), 549 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), 550 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), 551 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), 552 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), 553 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), 554 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), 555 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), 556 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), 557 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), 558 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), 559 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), 560 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), 561 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), 562 }; 563 564 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ax) * 2) == 565 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); 566 567 static const struct txpwr_map __txpwr_map_lmt_ax = { 568 .ent = __txpwr_ent_lmt_ax, 569 .size = ARRAY_SIZE(__txpwr_ent_lmt_ax), 570 .addr_from = R_AX_PWR_LMT, 571 .addr_to = R_AX_PWR_LMT_MAX, 572 .addr_to_1ss = R_AX_PWR_LMT_1SS_MAX, 573 }; 574 575 static const struct txpwr_ent __txpwr_ent_lmt_ru_ax[] = { 576 /* 1TX */ 577 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 578 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 579 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 580 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 581 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 582 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 583 /* 2TX */ 584 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 585 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 586 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 587 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 588 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 589 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 590 }; 591 592 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru_ax) * 8) == 593 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); 594 595 static const struct txpwr_map __txpwr_map_lmt_ru_ax = { 596 .ent = __txpwr_ent_lmt_ru_ax, 597 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_ax), 598 .addr_from = R_AX_PWR_RU_LMT, 599 .addr_to = R_AX_PWR_RU_LMT_MAX, 600 .addr_to_1ss = R_AX_PWR_RU_LMT_1SS_MAX, 601 }; 602 603 static const struct txpwr_ent __txpwr_ent_byr_mcs_be[] = { 604 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 605 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 606 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 607 __GEN_TXPWR_ENT2("MCS_1SS ", "MCS12 ", "MCS13 \t"), 608 __GEN_TXPWR_ENT4("HEDCM_1SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 609 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 610 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 611 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 612 __GEN_TXPWR_ENT2("DLRU_MCS_1SS ", "MCS12 ", "MCS13 \t"), 613 __GEN_TXPWR_ENT4("DLRU_HEDCM_1SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 614 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 615 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 616 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 617 __GEN_TXPWR_ENT2("MCS_2SS ", "MCS12 ", "MCS13 \t"), 618 __GEN_TXPWR_ENT4("HEDCM_2SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 619 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 620 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 621 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 622 __GEN_TXPWR_ENT2("DLRU_MCS_2SS ", "MCS12 ", "MCS13 \t"), 623 __GEN_TXPWR_ENT4("DLRU_HEDCM_2SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 624 }; 625 626 static const struct txpwr_ent __txpwr_ent_byr_be[] = { 627 __GEN_TXPWR_ENT0("BW20"), 628 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 629 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 630 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 631 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 632 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 633 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 634 635 __GEN_TXPWR_ENT0("BW40"), 636 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 637 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 638 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 639 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 640 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 641 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 642 643 /* there is no CCK section after BW80 */ 644 __GEN_TXPWR_ENT0("BW80"), 645 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 646 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 647 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 648 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 649 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 650 651 __GEN_TXPWR_ENT0("BW160"), 652 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 653 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 654 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 655 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 656 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 657 658 __GEN_TXPWR_ENT0("BW320"), 659 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 660 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 661 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 662 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 663 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 664 }; 665 666 static const struct txpwr_map __txpwr_map_byr_be = { 667 .ent = __txpwr_ent_byr_be, 668 .size = ARRAY_SIZE(__txpwr_ent_byr_be), 669 .addr_from = R_BE_PWR_BY_RATE, 670 .addr_to = R_BE_PWR_BY_RATE_MAX, 671 .addr_to_1ss = 0, /* not support */ 672 }; 673 674 static const struct txpwr_ent __txpwr_ent_lmt_mcs_be[] = { 675 __GEN_TXPWR_ENT2("MCS_20M_0 ", "NON_BF", "BF"), 676 __GEN_TXPWR_ENT2("MCS_20M_1 ", "NON_BF", "BF"), 677 __GEN_TXPWR_ENT2("MCS_20M_2 ", "NON_BF", "BF"), 678 __GEN_TXPWR_ENT2("MCS_20M_3 ", "NON_BF", "BF"), 679 __GEN_TXPWR_ENT2("MCS_20M_4 ", "NON_BF", "BF"), 680 __GEN_TXPWR_ENT2("MCS_20M_5 ", "NON_BF", "BF"), 681 __GEN_TXPWR_ENT2("MCS_20M_6 ", "NON_BF", "BF"), 682 __GEN_TXPWR_ENT2("MCS_20M_7 ", "NON_BF", "BF"), 683 __GEN_TXPWR_ENT2("MCS_20M_8 ", "NON_BF", "BF"), 684 __GEN_TXPWR_ENT2("MCS_20M_9 ", "NON_BF", "BF"), 685 __GEN_TXPWR_ENT2("MCS_20M_10 ", "NON_BF", "BF"), 686 __GEN_TXPWR_ENT2("MCS_20M_11 ", "NON_BF", "BF"), 687 __GEN_TXPWR_ENT2("MCS_20M_12 ", "NON_BF", "BF"), 688 __GEN_TXPWR_ENT2("MCS_20M_13 ", "NON_BF", "BF"), 689 __GEN_TXPWR_ENT2("MCS_20M_14 ", "NON_BF", "BF"), 690 __GEN_TXPWR_ENT2("MCS_20M_15 ", "NON_BF", "BF"), 691 __GEN_TXPWR_ENT2("MCS_40M_0 ", "NON_BF", "BF"), 692 __GEN_TXPWR_ENT2("MCS_40M_1 ", "NON_BF", "BF"), 693 __GEN_TXPWR_ENT2("MCS_40M_2 ", "NON_BF", "BF"), 694 __GEN_TXPWR_ENT2("MCS_40M_3 ", "NON_BF", "BF"), 695 __GEN_TXPWR_ENT2("MCS_40M_4 ", "NON_BF", "BF"), 696 __GEN_TXPWR_ENT2("MCS_40M_5 ", "NON_BF", "BF"), 697 __GEN_TXPWR_ENT2("MCS_40M_6 ", "NON_BF", "BF"), 698 __GEN_TXPWR_ENT2("MCS_40M_7 ", "NON_BF", "BF"), 699 __GEN_TXPWR_ENT2("MCS_80M_0 ", "NON_BF", "BF"), 700 __GEN_TXPWR_ENT2("MCS_80M_1 ", "NON_BF", "BF"), 701 __GEN_TXPWR_ENT2("MCS_80M_2 ", "NON_BF", "BF"), 702 __GEN_TXPWR_ENT2("MCS_80M_3 ", "NON_BF", "BF"), 703 __GEN_TXPWR_ENT2("MCS_160M_0 ", "NON_BF", "BF"), 704 __GEN_TXPWR_ENT2("MCS_160M_1 ", "NON_BF", "BF"), 705 __GEN_TXPWR_ENT2("MCS_320M ", "NON_BF", "BF"), 706 __GEN_TXPWR_ENT2("MCS_40M_0p5", "NON_BF", "BF"), 707 __GEN_TXPWR_ENT2("MCS_40M_2p5", "NON_BF", "BF"), 708 __GEN_TXPWR_ENT2("MCS_40M_4p5", "NON_BF", "BF"), 709 __GEN_TXPWR_ENT2("MCS_40M_6p5", "NON_BF", "BF"), 710 }; 711 712 static const struct txpwr_ent __txpwr_ent_lmt_be[] = { 713 __GEN_TXPWR_ENT0("1TX"), 714 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"), 715 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"), 716 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"), 717 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be), 718 719 __GEN_TXPWR_ENT0("2TX"), 720 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"), 721 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"), 722 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"), 723 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be), 724 }; 725 726 static const struct txpwr_map __txpwr_map_lmt_be = { 727 .ent = __txpwr_ent_lmt_be, 728 .size = ARRAY_SIZE(__txpwr_ent_lmt_be), 729 .addr_from = R_BE_PWR_LMT, 730 .addr_to = R_BE_PWR_LMT_MAX, 731 .addr_to_1ss = 0, /* not support */ 732 }; 733 734 static const struct txpwr_ent __txpwr_ent_lmt_ru_indexes_be[] = { 735 __GEN_TXPWR_ENT8("RU26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 736 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 737 __GEN_TXPWR_ENT8("RU26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 738 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 739 __GEN_TXPWR_ENT8("RU52 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 740 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 741 __GEN_TXPWR_ENT8("RU52 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 742 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 743 __GEN_TXPWR_ENT8("RU106 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 744 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 745 __GEN_TXPWR_ENT8("RU106 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 746 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 747 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 748 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 749 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 750 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 751 __GEN_TXPWR_ENT8("RU106_26", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 752 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 753 __GEN_TXPWR_ENT8("RU106_26", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 754 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 755 }; 756 757 static const struct txpwr_ent __txpwr_ent_lmt_ru_be[] = { 758 __GEN_TXPWR_ENT0("1TX"), 759 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be), 760 761 __GEN_TXPWR_ENT0("2TX"), 762 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be), 763 }; 764 765 static const struct txpwr_map __txpwr_map_lmt_ru_be = { 766 .ent = __txpwr_ent_lmt_ru_be, 767 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_be), 768 .addr_from = R_BE_PWR_RU_LMT, 769 .addr_to = R_BE_PWR_RU_LMT_MAX, 770 .addr_to_1ss = 0, /* not support */ 771 }; 772 773 static unsigned int 774 __print_txpwr_ent(char *buf, size_t bufsz, const struct txpwr_ent *ent, 775 const s8 *bufp, const unsigned int cur, unsigned int *ate) 776 { 777 char *p = buf, *end = buf + bufsz; 778 unsigned int cnt, i; 779 unsigned int eaten; 780 char *fmt; 781 782 if (ent->nested) { 783 for (cnt = 0, i = 0; i < ent->len; i++, cnt += eaten) 784 p += __print_txpwr_ent(p, end - p, ent->ptr + i, bufp, 785 cur + cnt, &eaten); 786 *ate = cnt; 787 goto out; 788 } 789 790 switch (ent->len) { 791 case 0: 792 p += scnprintf(p, end - p, "\t<< %s >>\n", ent->txt); 793 *ate = 0; 794 goto out; 795 case 2: 796 fmt = "%s\t| %3d, %3d,\t\tdBm\n"; 797 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur], 798 bufp[cur + 1]); 799 *ate = 2; 800 goto out; 801 case 4: 802 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; 803 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur], 804 bufp[cur + 1], 805 bufp[cur + 2], bufp[cur + 3]); 806 *ate = 4; 807 goto out; 808 case 8: 809 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; 810 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur], 811 bufp[cur + 1], 812 bufp[cur + 2], bufp[cur + 3], bufp[cur + 4], 813 bufp[cur + 5], bufp[cur + 6], bufp[cur + 7]); 814 *ate = 8; 815 goto out; 816 default: 817 return 0; 818 } 819 820 out: 821 return p - buf; 822 } 823 824 static ssize_t __print_txpwr_map(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 825 const struct txpwr_map *map) 826 { 827 u8 fct = rtwdev->chip->txpwr_factor_mac; 828 u8 path_num = rtwdev->chip->rf_path_num; 829 char *p = buf, *end = buf + bufsz; 830 unsigned int cur, i; 831 unsigned int eaten; 832 u32 max_valid_addr; 833 u32 val, addr; 834 s8 *bufp, tmp; 835 int ret; 836 837 bufp = vzalloc(map->addr_to - map->addr_from + 4); 838 if (!bufp) 839 return -ENOMEM; 840 841 if (path_num == 1) 842 max_valid_addr = map->addr_to_1ss; 843 else 844 max_valid_addr = map->addr_to; 845 846 if (max_valid_addr == 0) 847 return -EOPNOTSUPP; 848 849 for (addr = map->addr_from; addr <= max_valid_addr; addr += 4) { 850 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); 851 if (ret) 852 val = MASKDWORD; 853 854 cur = addr - map->addr_from; 855 for (i = 0; i < 4; i++, val >>= 8) { 856 /* signed 7 bits, and reserved BIT(7) */ 857 tmp = sign_extend32(val, 6); 858 bufp[cur + i] = tmp >> fct; 859 } 860 } 861 862 for (cur = 0, i = 0; i < map->size; i++, cur += eaten) 863 p += __print_txpwr_ent(p, end - p, &map->ent[i], bufp, cur, &eaten); 864 865 vfree(bufp); 866 return p - buf; 867 } 868 869 static int __print_regd(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 870 const struct rtw89_chan *chan) 871 { 872 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 873 char *p = buf, *end = buf + bufsz; 874 u8 band = chan->band_type; 875 u8 regd = rtw89_regd_get(rtwdev, band); 876 877 p += scnprintf(p, end - p, "%s\n", rtw89_regd_get_string(regd)); 878 p += scnprintf(p, end - p, "\t(txpwr UK follow ETSI: %s)\n", 879 str_yes_no(regulatory->txpwr_uk_follow_etsi)); 880 881 return p - buf; 882 } 883 884 struct dbgfs_txpwr_table { 885 const struct txpwr_map *byr; 886 const struct txpwr_map *lmt; 887 const struct txpwr_map *lmt_ru; 888 }; 889 890 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_ax = { 891 .byr = &__txpwr_map_byr_ax, 892 .lmt = &__txpwr_map_lmt_ax, 893 .lmt_ru = &__txpwr_map_lmt_ru_ax, 894 }; 895 896 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_be = { 897 .byr = &__txpwr_map_byr_be, 898 .lmt = &__txpwr_map_lmt_be, 899 .lmt_ru = &__txpwr_map_lmt_ru_be, 900 }; 901 902 static const struct dbgfs_txpwr_table *dbgfs_txpwr_tables[RTW89_CHIP_GEN_NUM] = { 903 [RTW89_CHIP_AX] = &dbgfs_txpwr_table_ax, 904 [RTW89_CHIP_BE] = &dbgfs_txpwr_table_be, 905 }; 906 907 static 908 int rtw89_debug_priv_txpwr_table_get_regd(struct rtw89_dev *rtwdev, 909 char *buf, size_t bufsz, 910 const struct rtw89_chan *chan) 911 { 912 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 913 const struct rtw89_reg_6ghz_tpe *tpe6 = ®ulatory->reg_6ghz_tpe; 914 char *p = buf, *end = buf + bufsz; 915 916 p += scnprintf(p, end - p, "[Chanctx] band %u, ch %u, bw %u\n", 917 chan->band_type, chan->channel, chan->band_width); 918 919 p += scnprintf(p, end - p, "[Regulatory] "); 920 p += __print_regd(rtwdev, p, end - p, chan); 921 922 if (chan->band_type == RTW89_BAND_6G) { 923 p += scnprintf(p, end - p, "[reg6_pwr_type] %u\n", 924 regulatory->reg_6ghz_power); 925 926 if (tpe6->valid) 927 p += scnprintf(p, end - p, "[TPE] %d dBm\n", 928 tpe6->constraint); 929 } 930 931 return p - buf; 932 } 933 934 static 935 ssize_t rtw89_debug_priv_txpwr_table_get(struct rtw89_dev *rtwdev, 936 struct rtw89_debugfs_priv *debugfs_priv, 937 char *buf, size_t bufsz) 938 { 939 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 940 struct rtw89_sar_parm sar_parm = {}; 941 const struct dbgfs_txpwr_table *tbl; 942 const struct rtw89_chan *chan; 943 char *p = buf, *end = buf + bufsz; 944 ssize_t n; 945 946 lockdep_assert_wiphy(rtwdev->hw->wiphy); 947 948 rtw89_leave_ps_mode(rtwdev); 949 chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 950 sar_parm.center_freq = chan->freq; 951 952 p += rtw89_debug_priv_txpwr_table_get_regd(rtwdev, p, end - p, chan); 953 954 p += scnprintf(p, end - p, "[SAR]\n"); 955 p += rtw89_print_sar(rtwdev, p, end - p, &sar_parm); 956 957 p += scnprintf(p, end - p, "[TAS]\n"); 958 p += rtw89_print_tas(rtwdev, p, end - p); 959 960 p += scnprintf(p, end - p, "[DAG]\n"); 961 p += rtw89_print_ant_gain(rtwdev, p, end - p, chan); 962 963 tbl = dbgfs_txpwr_tables[chip_gen]; 964 if (!tbl) 965 return -EOPNOTSUPP; 966 967 p += scnprintf(p, end - p, "\n[TX power byrate]\n"); 968 n = __print_txpwr_map(rtwdev, p, end - p, tbl->byr); 969 if (n < 0) 970 return n; 971 p += n; 972 973 p += scnprintf(p, end - p, "\n[TX power limit]\n"); 974 n = __print_txpwr_map(rtwdev, p, end - p, tbl->lmt); 975 if (n < 0) 976 return n; 977 p += n; 978 979 p += scnprintf(p, end - p, "\n[TX power limit_ru]\n"); 980 n = __print_txpwr_map(rtwdev, p, end - p, tbl->lmt_ru); 981 if (n < 0) 982 return n; 983 p += n; 984 985 return p - buf; 986 } 987 988 static ssize_t 989 rtw89_debug_priv_mac_reg_dump_select(struct rtw89_dev *rtwdev, 990 struct rtw89_debugfs_priv *debugfs_priv, 991 const char *buf, size_t count) 992 { 993 const struct rtw89_chip_info *chip = rtwdev->chip; 994 int sel; 995 int ret; 996 997 ret = kstrtoint(buf, 0, &sel); 998 if (ret) 999 return ret; 1000 1001 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { 1002 rtw89_info(rtwdev, "invalid args: %d\n", sel); 1003 return -EINVAL; 1004 } 1005 1006 if (sel == RTW89_DBG_SEL_MAC_30 && chip->chip_id != RTL8852C) { 1007 rtw89_info(rtwdev, "sel %d is address hole on chip %d\n", sel, 1008 chip->chip_id); 1009 return -EINVAL; 1010 } 1011 1012 debugfs_priv->cb_data = sel; 1013 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); 1014 1015 return count; 1016 } 1017 1018 #define RTW89_MAC_PAGE_SIZE 0x100 1019 1020 static 1021 ssize_t rtw89_debug_priv_mac_reg_dump_get(struct rtw89_dev *rtwdev, 1022 struct rtw89_debugfs_priv *debugfs_priv, 1023 char *buf, size_t bufsz) 1024 { 1025 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; 1026 char *p = buf, *end = buf + bufsz; 1027 u32 start, end_addr; 1028 u32 i, j, k, page; 1029 u32 val; 1030 1031 switch (reg_sel) { 1032 case RTW89_DBG_SEL_MAC_00: 1033 p += scnprintf(p, end - p, "Debug selected MAC page 0x00\n"); 1034 start = 0x000; 1035 end_addr = 0x014; 1036 break; 1037 case RTW89_DBG_SEL_MAC_30: 1038 p += scnprintf(p, end - p, "Debug selected MAC page 0x30\n"); 1039 start = 0x030; 1040 end_addr = 0x033; 1041 break; 1042 case RTW89_DBG_SEL_MAC_40: 1043 p += scnprintf(p, end - p, "Debug selected MAC page 0x40\n"); 1044 start = 0x040; 1045 end_addr = 0x07f; 1046 break; 1047 case RTW89_DBG_SEL_MAC_80: 1048 p += scnprintf(p, end - p, "Debug selected MAC page 0x80\n"); 1049 start = 0x080; 1050 end_addr = 0x09f; 1051 break; 1052 case RTW89_DBG_SEL_MAC_C0: 1053 p += scnprintf(p, end - p, "Debug selected MAC page 0xc0\n"); 1054 start = 0x0c0; 1055 end_addr = 0x0df; 1056 break; 1057 case RTW89_DBG_SEL_MAC_E0: 1058 p += scnprintf(p, end - p, "Debug selected MAC page 0xe0\n"); 1059 start = 0x0e0; 1060 end_addr = 0x0ff; 1061 break; 1062 case RTW89_DBG_SEL_BB: 1063 p += scnprintf(p, end - p, "Debug selected BB register\n"); 1064 start = 0x100; 1065 end_addr = 0x17f; 1066 break; 1067 case RTW89_DBG_SEL_IQK: 1068 p += scnprintf(p, end - p, "Debug selected IQK register\n"); 1069 start = 0x180; 1070 end_addr = 0x1bf; 1071 break; 1072 case RTW89_DBG_SEL_RFC: 1073 p += scnprintf(p, end - p, "Debug selected RFC register\n"); 1074 start = 0x1c0; 1075 end_addr = 0x1ff; 1076 break; 1077 default: 1078 p += scnprintf(p, end - p, "Selected invalid register page\n"); 1079 return -EINVAL; 1080 } 1081 1082 for (i = start; i <= end_addr; i++) { 1083 page = i << 8; 1084 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { 1085 p += scnprintf(p, end - p, "%08xh : ", 0x18600000 + j); 1086 for (k = 0; k < 4; k++) { 1087 val = rtw89_read32(rtwdev, j + (k << 2)); 1088 p += scnprintf(p, end - p, "%08x ", val); 1089 } 1090 p += scnprintf(p, end - p, "\n"); 1091 } 1092 } 1093 1094 return p - buf; 1095 } 1096 1097 static ssize_t 1098 rtw89_debug_priv_mac_mem_dump_select(struct rtw89_dev *rtwdev, 1099 struct rtw89_debugfs_priv *debugfs_priv, 1100 const char *buf, size_t count) 1101 { 1102 u32 sel, start_addr, len; 1103 int num; 1104 1105 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); 1106 if (num != 3) { 1107 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n"); 1108 return -EINVAL; 1109 } 1110 1111 debugfs_priv->mac_mem.sel = sel; 1112 debugfs_priv->mac_mem.start = start_addr; 1113 debugfs_priv->mac_mem.len = len; 1114 1115 rtw89_info(rtwdev, "select mem %d start %d len %d\n", 1116 sel, start_addr, len); 1117 1118 return count; 1119 } 1120 1121 static int rtw89_debug_dump_mac_mem(struct rtw89_dev *rtwdev, 1122 char *buf, size_t bufsz, 1123 u8 sel, u32 start_addr, u32 len) 1124 { 1125 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1126 u32 filter_model_addr = mac->filter_model_addr; 1127 u32 indir_access_addr = mac->indir_access_addr; 1128 u32 mem_page_size = mac->mem_page_size; 1129 u32 base_addr, start_page, residue; 1130 char *p = buf, *end = buf + bufsz; 1131 u32 i, j, pp, pages; 1132 u32 dump_len, remain; 1133 u32 val; 1134 1135 remain = len; 1136 pages = len / mem_page_size + 1; 1137 start_page = start_addr / mem_page_size; 1138 residue = start_addr % mem_page_size; 1139 base_addr = mac->mem_base_addrs[sel]; 1140 base_addr += start_page * mem_page_size; 1141 1142 for (pp = 0; pp < pages; pp++) { 1143 dump_len = min_t(u32, remain, mem_page_size); 1144 rtw89_write32(rtwdev, filter_model_addr, base_addr); 1145 for (i = indir_access_addr + residue; 1146 i < indir_access_addr + dump_len;) { 1147 p += scnprintf(p, end - p, "%08xh:", i); 1148 for (j = 0; 1149 j < 4 && i < indir_access_addr + dump_len; 1150 j++, i += 4) { 1151 val = rtw89_read32(rtwdev, i); 1152 p += scnprintf(p, end - p, " %08x", val); 1153 remain -= 4; 1154 } 1155 p += scnprintf(p, end - p, "\n"); 1156 } 1157 base_addr += mem_page_size; 1158 } 1159 1160 return p - buf; 1161 } 1162 1163 static ssize_t 1164 rtw89_debug_priv_mac_mem_dump_get(struct rtw89_dev *rtwdev, 1165 struct rtw89_debugfs_priv *debugfs_priv, 1166 char *buf, size_t bufsz) 1167 { 1168 char *p = buf, *end = buf + bufsz; 1169 bool grant_read = false; 1170 1171 lockdep_assert_wiphy(rtwdev->hw->wiphy); 1172 1173 if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM) 1174 return -ENOENT; 1175 1176 if (rtwdev->chip->chip_id == RTL8852C) { 1177 switch (debugfs_priv->mac_mem.sel) { 1178 case RTW89_MAC_MEM_TXD_FIFO_0_V1: 1179 case RTW89_MAC_MEM_TXD_FIFO_1_V1: 1180 case RTW89_MAC_MEM_TXDATA_FIFO_0: 1181 case RTW89_MAC_MEM_TXDATA_FIFO_1: 1182 grant_read = true; 1183 break; 1184 default: 1185 break; 1186 } 1187 } 1188 1189 rtw89_leave_ps_mode(rtwdev); 1190 if (grant_read) 1191 rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 1192 p += rtw89_debug_dump_mac_mem(rtwdev, p, end - p, 1193 debugfs_priv->mac_mem.sel, 1194 debugfs_priv->mac_mem.start, 1195 debugfs_priv->mac_mem.len); 1196 if (grant_read) 1197 rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 1198 1199 return p - buf; 1200 } 1201 1202 static ssize_t 1203 rtw89_debug_priv_mac_dbg_port_dump_select(struct rtw89_dev *rtwdev, 1204 struct rtw89_debugfs_priv *debugfs_priv, 1205 const char *buf, size_t count) 1206 { 1207 int sel, set; 1208 int num; 1209 bool enable; 1210 1211 num = sscanf(buf, "%d %d", &sel, &set); 1212 if (num != 2) { 1213 rtw89_info(rtwdev, "invalid format: <sel> <set>\n"); 1214 return -EINVAL; 1215 } 1216 1217 enable = set != 0; 1218 switch (sel) { 1219 case 0: 1220 debugfs_priv->dbgpkg_en.ss_dbg = enable; 1221 break; 1222 case 1: 1223 debugfs_priv->dbgpkg_en.dle_dbg = enable; 1224 break; 1225 case 2: 1226 debugfs_priv->dbgpkg_en.dmac_dbg = enable; 1227 break; 1228 case 3: 1229 debugfs_priv->dbgpkg_en.cmac_dbg = enable; 1230 break; 1231 case 4: 1232 debugfs_priv->dbgpkg_en.dbg_port = enable; 1233 break; 1234 default: 1235 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); 1236 return -EINVAL; 1237 } 1238 1239 rtw89_info(rtwdev, "%s debug port dump %d\n", 1240 enable ? "Enable" : "Disable", sel); 1241 1242 return count; 1243 } 1244 1245 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, 1246 char *buf, size_t bufsz) 1247 { 1248 return 0; 1249 } 1250 1251 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, 1252 char *buf, size_t bufsz) 1253 { 1254 #define DLE_DFI_DUMP(__type, __target, __sel) \ 1255 ({ \ 1256 u32 __ctrl; \ 1257 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ 1258 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ 1259 u32 __data, __val32; \ 1260 int __ret; \ 1261 \ 1262 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ 1263 DLE_DFI_TYPE_##__target) | \ 1264 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ 1265 B_AX_WDE_DFI_ACTIVE; \ 1266 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ 1267 __ret = read_poll_timeout(rtw89_read32, __val32, \ 1268 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ 1269 1000, 50000, false, \ 1270 rtwdev, __reg_ctrl); \ 1271 if (__ret) { \ 1272 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ 1273 #__type, #__target, __sel); \ 1274 return __ret; \ 1275 } \ 1276 \ 1277 __data = rtw89_read32(rtwdev, __reg_data); \ 1278 __data; \ 1279 }) 1280 1281 #define DLE_DFI_FREE_PAGE_DUMP(__p, __end, __type) \ 1282 ({ \ 1283 u32 __freepg, __pubpg; \ 1284 u32 __freepg_head, __freepg_tail, __pubpg_num; \ 1285 \ 1286 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ 1287 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ 1288 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ 1289 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ 1290 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ 1291 __p += scnprintf(__p, __end - __p, "[%s] freepg head: %d\n", \ 1292 #__type, __freepg_head); \ 1293 __p += scnprintf(__p, __end - __p, "[%s] freepg tail: %d\n", \ 1294 #__type, __freepg_tail); \ 1295 __p += scnprintf(__p, __end - __p, "[%s] pubpg num : %d\n", \ 1296 #__type, __pubpg_num); \ 1297 }) 1298 1299 #define case_QUOTA(__p, __end, __type, __id) \ 1300 case __type##_QTAID_##__id: \ 1301 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ 1302 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ 1303 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ 1304 __p += scnprintf(__p, __end - __p, "[%s][%s] rsv_pgnum: %d\n", \ 1305 #__type, #__id, rsv_pgnum); \ 1306 __p += scnprintf(__p, __end - __p, "[%s][%s] use_pgnum: %d\n", \ 1307 #__type, #__id, use_pgnum); \ 1308 break 1309 char *p = buf, *end = buf + bufsz; 1310 u32 quota_id; 1311 u32 val32; 1312 u16 rsv_pgnum, use_pgnum; 1313 int ret; 1314 1315 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1316 if (ret) { 1317 p += scnprintf(p, end - p, "[DLE] : DMAC not enabled\n"); 1318 goto out; 1319 } 1320 1321 DLE_DFI_FREE_PAGE_DUMP(p, end, WDE); 1322 DLE_DFI_FREE_PAGE_DUMP(p, end, PLE); 1323 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { 1324 switch (quota_id) { 1325 case_QUOTA(p, end, WDE, HOST_IF); 1326 case_QUOTA(p, end, WDE, WLAN_CPU); 1327 case_QUOTA(p, end, WDE, DATA_CPU); 1328 case_QUOTA(p, end, WDE, PKTIN); 1329 case_QUOTA(p, end, WDE, CPUIO); 1330 } 1331 } 1332 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { 1333 switch (quota_id) { 1334 case_QUOTA(p, end, PLE, B0_TXPL); 1335 case_QUOTA(p, end, PLE, B1_TXPL); 1336 case_QUOTA(p, end, PLE, C2H); 1337 case_QUOTA(p, end, PLE, H2C); 1338 case_QUOTA(p, end, PLE, WLAN_CPU); 1339 case_QUOTA(p, end, PLE, MPDU); 1340 case_QUOTA(p, end, PLE, CMAC0_RX); 1341 case_QUOTA(p, end, PLE, CMAC1_RX); 1342 case_QUOTA(p, end, PLE, CMAC1_BBRPT); 1343 case_QUOTA(p, end, PLE, WDRLS); 1344 case_QUOTA(p, end, PLE, CPUIO); 1345 } 1346 } 1347 1348 out: 1349 return p - buf; 1350 1351 #undef case_QUOTA 1352 #undef DLE_DFI_DUMP 1353 #undef DLE_DFI_FREE_PAGE_DUMP 1354 } 1355 1356 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, 1357 char *buf, size_t bufsz) 1358 { 1359 const struct rtw89_chip_info *chip = rtwdev->chip; 1360 char *p = buf, *end = buf + bufsz; 1361 u32 dmac_err; 1362 int i, ret; 1363 1364 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1365 if (ret) { 1366 p += scnprintf(p, end - p, "[DMAC] : DMAC not enabled\n"); 1367 goto out; 1368 } 1369 1370 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 1371 p += scnprintf(p, end - p, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 1372 p += scnprintf(p, end - p, "R_AX_DMAC_ERR_IMR=0x%08x\n", 1373 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 1374 1375 if (dmac_err) { 1376 p += scnprintf(p, end - p, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 1377 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 1378 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 1379 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 1380 if (chip->chip_id == RTL8852C) { 1381 p += scnprintf(p, end - p, 1382 "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 1383 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 1384 p += scnprintf(p, end - p, 1385 "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 1386 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 1387 p += scnprintf(p, end - p, 1388 "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 1389 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 1390 p += scnprintf(p, end - p, 1391 "R_AX_PLE_DBGERR_STS=0x%08x\n", 1392 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 1393 } 1394 } 1395 1396 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 1397 p += scnprintf(p, end - p, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 1398 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 1399 p += scnprintf(p, end - p, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 1400 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 1401 if (chip->chip_id == RTL8852C) 1402 p += scnprintf(p, end - p, 1403 "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1404 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 1405 else 1406 p += scnprintf(p, end - p, 1407 "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1408 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 1409 } 1410 1411 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 1412 if (chip->chip_id == RTL8852C) { 1413 p += scnprintf(p, end - p, 1414 "R_AX_SEC_ERR_IMR=0x%08x\n", 1415 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 1416 p += scnprintf(p, end - p, 1417 "R_AX_SEC_ERR_ISR=0x%08x\n", 1418 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 1419 p += scnprintf(p, end - p, 1420 "R_AX_SEC_ENG_CTRL=0x%08x\n", 1421 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1422 p += scnprintf(p, end - p, 1423 "R_AX_SEC_MPDU_PROC=0x%08x\n", 1424 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1425 p += scnprintf(p, end - p, 1426 "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1427 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1428 p += scnprintf(p, end - p, 1429 "R_AX_SEC_CAM_RDATA=0x%08x\n", 1430 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1431 p += scnprintf(p, end - p, "R_AX_SEC_DEBUG1=0x%08x\n", 1432 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 1433 p += scnprintf(p, end - p, 1434 "R_AX_SEC_TX_DEBUG=0x%08x\n", 1435 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1436 p += scnprintf(p, end - p, 1437 "R_AX_SEC_RX_DEBUG=0x%08x\n", 1438 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1439 1440 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1441 B_AX_DBG_SEL0, 0x8B); 1442 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1443 B_AX_DBG_SEL1, 0x8B); 1444 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 1445 B_AX_SEL_0XC0_MASK, 1); 1446 for (i = 0; i < 0x10; i++) { 1447 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 1448 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 1449 p += scnprintf(p, end - p, 1450 "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 1451 i, 1452 rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 1453 } 1454 } else { 1455 p += scnprintf(p, end - p, 1456 "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 1457 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 1458 p += scnprintf(p, end - p, 1459 "R_AX_SEC_ENG_CTRL=0x%08x\n", 1460 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1461 p += scnprintf(p, end - p, 1462 "R_AX_SEC_MPDU_PROC=0x%08x\n", 1463 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1464 p += scnprintf(p, end - p, 1465 "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1466 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1467 p += scnprintf(p, end - p, 1468 "R_AX_SEC_CAM_RDATA=0x%08x\n", 1469 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1470 p += scnprintf(p, end - p, 1471 "R_AX_SEC_CAM_WDATA=0x%08x\n", 1472 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 1473 p += scnprintf(p, end - p, 1474 "R_AX_SEC_TX_DEBUG=0x%08x\n", 1475 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1476 p += scnprintf(p, end - p, 1477 "R_AX_SEC_RX_DEBUG=0x%08x\n", 1478 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1479 p += scnprintf(p, end - p, 1480 "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 1481 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 1482 p += scnprintf(p, end - p, 1483 "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 1484 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 1485 } 1486 } 1487 1488 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 1489 p += scnprintf(p, end - p, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 1490 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 1491 p += scnprintf(p, end - p, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 1492 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 1493 p += scnprintf(p, end - p, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 1494 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 1495 p += scnprintf(p, end - p, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 1496 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 1497 } 1498 1499 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 1500 p += scnprintf(p, end - p, 1501 "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 1502 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 1503 p += scnprintf(p, end - p, 1504 "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 1505 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 1506 } 1507 1508 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 1509 p += scnprintf(p, end - p, "R_AX_WDE_ERR_IMR=0x%08x\n", 1510 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1511 p += scnprintf(p, end - p, "R_AX_WDE_ERR_ISR=0x%08x\n", 1512 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1513 p += scnprintf(p, end - p, "R_AX_PLE_ERR_IMR=0x%08x\n", 1514 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1515 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1516 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1517 } 1518 1519 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 1520 if (chip->chip_id == RTL8852C) { 1521 p += scnprintf(p, end - p, 1522 "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 1523 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 1524 p += scnprintf(p, end - p, 1525 "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 1526 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 1527 p += scnprintf(p, end - p, 1528 "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 1529 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 1530 p += scnprintf(p, end - p, 1531 "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 1532 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 1533 } else { 1534 p += scnprintf(p, end - p, 1535 "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 1536 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 1537 p += scnprintf(p, end - p, 1538 "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 1539 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 1540 } 1541 } 1542 1543 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 1544 p += scnprintf(p, end - p, "R_AX_WDE_ERR_IMR=0x%08x\n", 1545 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1546 p += scnprintf(p, end - p, "R_AX_WDE_ERR_ISR=0x%08x\n", 1547 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1548 p += scnprintf(p, end - p, "R_AX_PLE_ERR_IMR=0x%08x\n", 1549 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1550 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1551 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1552 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 1553 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 1554 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 1555 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 1556 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 1557 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 1558 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 1559 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 1560 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 1561 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 1562 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 1563 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 1564 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 1565 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 1566 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 1567 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 1568 if (chip->chip_id == RTL8852C) { 1569 p += scnprintf(p, end - p, "R_AX_RX_CTRL0=0x%08x\n", 1570 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 1571 p += scnprintf(p, end - p, "R_AX_RX_CTRL1=0x%08x\n", 1572 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 1573 p += scnprintf(p, end - p, "R_AX_RX_CTRL2=0x%08x\n", 1574 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 1575 } else { 1576 p += scnprintf(p, end - p, 1577 "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 1578 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 1579 p += scnprintf(p, end - p, 1580 "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 1581 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 1582 p += scnprintf(p, end - p, 1583 "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 1584 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 1585 } 1586 } 1587 1588 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 1589 p += scnprintf(p, end - p, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 1590 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 1591 p += scnprintf(p, end - p, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 1592 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 1593 } 1594 1595 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 1596 p += scnprintf(p, end - p, 1597 "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 1598 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 1599 p += scnprintf(p, end - p, 1600 "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 1601 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 1602 p += scnprintf(p, end - p, 1603 "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 1604 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 1605 p += scnprintf(p, end - p, 1606 "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 1607 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 1608 p += scnprintf(p, end - p, 1609 "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 1610 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 1611 p += scnprintf(p, end - p, 1612 "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 1613 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 1614 } 1615 1616 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 1617 if (chip->chip_id == RTL8852C) { 1618 p += scnprintf(p, end - p, 1619 "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 1620 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 1621 p += scnprintf(p, end - p, 1622 "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 1623 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 1624 p += scnprintf(p, end - p, 1625 "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1626 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1627 p += scnprintf(p, end - p, 1628 "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1629 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1630 p += scnprintf(p, end - p, 1631 "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1632 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1633 p += scnprintf(p, end - p, 1634 "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1635 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1636 } else { 1637 p += scnprintf(p, end - p, 1638 "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 1639 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 1640 p += scnprintf(p, end - p, 1641 "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1642 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1643 p += scnprintf(p, end - p, 1644 "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1645 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1646 p += scnprintf(p, end - p, 1647 "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1648 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1649 p += scnprintf(p, end - p, 1650 "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1651 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1652 } 1653 } 1654 1655 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 1656 p += scnprintf(p, end - p, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 1657 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 1658 p += scnprintf(p, end - p, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 1659 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 1660 } 1661 1662 out: 1663 return p - buf; 1664 } 1665 1666 static int rtw89_debug_mac_dump_cmac_err(struct rtw89_dev *rtwdev, 1667 char *buf, size_t bufsz, 1668 enum rtw89_mac_idx band) 1669 { 1670 const struct rtw89_chip_info *chip = rtwdev->chip; 1671 char *p = buf, *end = buf + bufsz; 1672 u32 offset = 0; 1673 u32 cmac_err; 1674 int ret; 1675 1676 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 1677 if (ret) { 1678 if (band) 1679 p += scnprintf(p, end - p, 1680 "[CMAC] : CMAC1 not enabled\n"); 1681 else 1682 p += scnprintf(p, end - p, 1683 "[CMAC] : CMAC0 not enabled\n"); 1684 goto out; 1685 } 1686 1687 if (band) 1688 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 1689 1690 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 1691 p += scnprintf(p, end - p, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 1692 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 1693 p += scnprintf(p, end - p, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 1694 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 1695 p += scnprintf(p, end - p, "R_AX_CK_EN [%d]=0x%08x\n", band, 1696 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 1697 1698 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 1699 p += scnprintf(p, end - p, 1700 "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 1701 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 1702 p += scnprintf(p, end - p, 1703 "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 1704 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 1705 } 1706 1707 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 1708 p += scnprintf(p, end - p, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", 1709 band, 1710 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 1711 p += scnprintf(p, end - p, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", 1712 band, 1713 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 1714 } 1715 1716 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 1717 if (chip->chip_id == RTL8852C) { 1718 p += scnprintf(p, end - p, 1719 "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 1720 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 1721 p += scnprintf(p, end - p, 1722 "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", 1723 band, 1724 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 1725 } else { 1726 p += scnprintf(p, end - p, 1727 "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 1728 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 1729 } 1730 } 1731 1732 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 1733 if (chip->chip_id == RTL8852C) { 1734 p += scnprintf(p, end - p, 1735 "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", 1736 band, 1737 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 1738 p += scnprintf(p, end - p, 1739 "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", 1740 band, 1741 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1742 } else { 1743 p += scnprintf(p, end - p, 1744 "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", 1745 band, 1746 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1747 } 1748 } 1749 1750 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 1751 p += scnprintf(p, end - p, "R_AX_TXPWR_IMR [%d]=0x%08x\n", 1752 band, 1753 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 1754 p += scnprintf(p, end - p, "R_AX_TXPWR_ISR [%d]=0x%08x\n", 1755 band, 1756 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 1757 } 1758 1759 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 1760 if (chip->chip_id == RTL8852C) { 1761 p += scnprintf(p, end - p, 1762 "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", 1763 band, 1764 rtw89_read32(rtwdev, 1765 R_AX_TRXPTCL_ERROR_INDICA + offset)); 1766 p += scnprintf(p, end - p, 1767 "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", 1768 band, 1769 rtw89_read32(rtwdev, 1770 R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 1771 } else { 1772 p += scnprintf(p, end - p, 1773 "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", 1774 band, 1775 rtw89_read32(rtwdev, 1776 R_AX_TMAC_ERR_IMR_ISR + offset)); 1777 } 1778 p += scnprintf(p, end - p, 1779 "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 1780 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 1781 } 1782 1783 p += scnprintf(p, end - p, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 1784 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 1785 1786 out: 1787 return p - buf; 1788 } 1789 1790 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, 1791 char *buf, size_t bufsz) 1792 { 1793 char *p = buf, *end = buf + bufsz; 1794 1795 p += rtw89_debug_mac_dump_cmac_err(rtwdev, p, end - p, RTW89_MAC_0); 1796 if (rtwdev->dbcc_en) 1797 p += rtw89_debug_mac_dump_cmac_err(rtwdev, p, end - p, RTW89_MAC_1); 1798 1799 return p - buf; 1800 } 1801 1802 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { 1803 .sel_addr = R_AX_PTCL_DBG, 1804 .sel_byte = 1, 1805 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1806 .srt = 0x00, 1807 .end = 0x3F, 1808 .rd_addr = R_AX_PTCL_DBG_INFO, 1809 .rd_byte = 4, 1810 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1811 }; 1812 1813 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { 1814 .sel_addr = R_AX_PTCL_DBG_C1, 1815 .sel_byte = 1, 1816 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1817 .srt = 0x00, 1818 .end = 0x3F, 1819 .rd_addr = R_AX_PTCL_DBG_INFO_C1, 1820 .rd_byte = 4, 1821 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1822 }; 1823 1824 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx0_5 = { 1825 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1826 .sel_byte = 2, 1827 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1828 .srt = 0x0, 1829 .end = 0xD, 1830 .rd_addr = R_AX_DBG_PORT_SEL, 1831 .rd_byte = 4, 1832 .rd_msk = B_AX_DEBUG_ST_MASK 1833 }; 1834 1835 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx6 = { 1836 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1837 .sel_byte = 2, 1838 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1839 .srt = 0x0, 1840 .end = 0x5, 1841 .rd_addr = R_AX_DBG_PORT_SEL, 1842 .rd_byte = 4, 1843 .rd_msk = B_AX_DEBUG_ST_MASK 1844 }; 1845 1846 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx7 = { 1847 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1848 .sel_byte = 2, 1849 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1850 .srt = 0x0, 1851 .end = 0x9, 1852 .rd_addr = R_AX_DBG_PORT_SEL, 1853 .rd_byte = 4, 1854 .rd_msk = B_AX_DEBUG_ST_MASK 1855 }; 1856 1857 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx8 = { 1858 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1859 .sel_byte = 2, 1860 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1861 .srt = 0x0, 1862 .end = 0x3, 1863 .rd_addr = R_AX_DBG_PORT_SEL, 1864 .rd_byte = 4, 1865 .rd_msk = B_AX_DEBUG_ST_MASK 1866 }; 1867 1868 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx9_C = { 1869 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1870 .sel_byte = 2, 1871 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1872 .srt = 0x0, 1873 .end = 0x1, 1874 .rd_addr = R_AX_DBG_PORT_SEL, 1875 .rd_byte = 4, 1876 .rd_msk = B_AX_DEBUG_ST_MASK 1877 }; 1878 1879 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_txD = { 1880 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1881 .sel_byte = 2, 1882 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1883 .srt = 0x0, 1884 .end = 0x0, 1885 .rd_addr = R_AX_DBG_PORT_SEL, 1886 .rd_byte = 4, 1887 .rd_msk = B_AX_DEBUG_ST_MASK 1888 }; 1889 1890 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx0 = { 1891 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1892 .sel_byte = 2, 1893 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1894 .srt = 0x0, 1895 .end = 0xB, 1896 .rd_addr = R_AX_DBG_PORT_SEL, 1897 .rd_byte = 4, 1898 .rd_msk = B_AX_DEBUG_ST_MASK 1899 }; 1900 1901 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx1 = { 1902 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1903 .sel_byte = 2, 1904 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1905 .srt = 0x0, 1906 .end = 0x4, 1907 .rd_addr = R_AX_DBG_PORT_SEL, 1908 .rd_byte = 4, 1909 .rd_msk = B_AX_DEBUG_ST_MASK 1910 }; 1911 1912 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx3 = { 1913 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1914 .sel_byte = 2, 1915 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1916 .srt = 0x0, 1917 .end = 0x8, 1918 .rd_addr = R_AX_DBG_PORT_SEL, 1919 .rd_byte = 4, 1920 .rd_msk = B_AX_DEBUG_ST_MASK 1921 }; 1922 1923 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx4 = { 1924 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1925 .sel_byte = 2, 1926 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1927 .srt = 0x0, 1928 .end = 0x7, 1929 .rd_addr = R_AX_DBG_PORT_SEL, 1930 .rd_byte = 4, 1931 .rd_msk = B_AX_DEBUG_ST_MASK 1932 }; 1933 1934 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx5_8 = { 1935 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1936 .sel_byte = 2, 1937 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1938 .srt = 0x0, 1939 .end = 0x1, 1940 .rd_addr = R_AX_DBG_PORT_SEL, 1941 .rd_byte = 4, 1942 .rd_msk = B_AX_DEBUG_ST_MASK 1943 }; 1944 1945 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx9 = { 1946 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1947 .sel_byte = 2, 1948 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1949 .srt = 0x0, 1950 .end = 0x3, 1951 .rd_addr = R_AX_DBG_PORT_SEL, 1952 .rd_byte = 4, 1953 .rd_msk = B_AX_DEBUG_ST_MASK 1954 }; 1955 1956 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_txA_C = { 1957 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1958 .sel_byte = 2, 1959 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1960 .srt = 0x0, 1961 .end = 0x0, 1962 .rd_addr = R_AX_DBG_PORT_SEL, 1963 .rd_byte = 4, 1964 .rd_msk = B_AX_DEBUG_ST_MASK 1965 }; 1966 1967 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx0 = { 1968 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1969 .sel_byte = 2, 1970 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1971 .srt = 0x0, 1972 .end = 0x8, 1973 .rd_addr = R_AX_DBG_PORT_SEL, 1974 .rd_byte = 4, 1975 .rd_msk = B_AX_DEBUG_ST_MASK 1976 }; 1977 1978 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx1_2 = { 1979 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1980 .sel_byte = 2, 1981 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1982 .srt = 0x0, 1983 .end = 0x0, 1984 .rd_addr = R_AX_DBG_PORT_SEL, 1985 .rd_byte = 4, 1986 .rd_msk = B_AX_DEBUG_ST_MASK 1987 }; 1988 1989 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx3 = { 1990 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1991 .sel_byte = 2, 1992 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1993 .srt = 0x0, 1994 .end = 0x6, 1995 .rd_addr = R_AX_DBG_PORT_SEL, 1996 .rd_byte = 4, 1997 .rd_msk = B_AX_DEBUG_ST_MASK 1998 }; 1999 2000 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx4 = { 2001 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2002 .sel_byte = 2, 2003 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2004 .srt = 0x0, 2005 .end = 0x0, 2006 .rd_addr = R_AX_DBG_PORT_SEL, 2007 .rd_byte = 4, 2008 .rd_msk = B_AX_DEBUG_ST_MASK 2009 }; 2010 2011 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx5 = { 2012 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2013 .sel_byte = 2, 2014 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2015 .srt = 0x0, 2016 .end = 0x0, 2017 .rd_addr = R_AX_DBG_PORT_SEL, 2018 .rd_byte = 4, 2019 .rd_msk = B_AX_DEBUG_ST_MASK 2020 }; 2021 2022 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_0 = { 2023 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2024 .sel_byte = 1, 2025 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2026 .srt = 0x0, 2027 .end = 0x3, 2028 .rd_addr = R_AX_DBG_PORT_SEL, 2029 .rd_byte = 4, 2030 .rd_msk = B_AX_DEBUG_ST_MASK 2031 }; 2032 2033 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_1 = { 2034 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2035 .sel_byte = 1, 2036 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2037 .srt = 0x0, 2038 .end = 0x6, 2039 .rd_addr = R_AX_DBG_PORT_SEL, 2040 .rd_byte = 4, 2041 .rd_msk = B_AX_DEBUG_ST_MASK 2042 }; 2043 2044 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_2 = { 2045 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2046 .sel_byte = 1, 2047 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2048 .srt = 0x0, 2049 .end = 0x0, 2050 .rd_addr = R_AX_DBG_PORT_SEL, 2051 .rd_byte = 4, 2052 .rd_msk = B_AX_DEBUG_ST_MASK 2053 }; 2054 2055 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p1 = { 2056 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2057 .sel_byte = 1, 2058 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2059 .srt = 0x8, 2060 .end = 0xE, 2061 .rd_addr = R_AX_DBG_PORT_SEL, 2062 .rd_byte = 4, 2063 .rd_msk = B_AX_DEBUG_ST_MASK 2064 }; 2065 2066 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_stf_ctrl = { 2067 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2068 .sel_byte = 1, 2069 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2070 .srt = 0x0, 2071 .end = 0x5, 2072 .rd_addr = R_AX_DBG_PORT_SEL, 2073 .rd_byte = 4, 2074 .rd_msk = B_AX_DEBUG_ST_MASK 2075 }; 2076 2077 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_addr_ctrl = { 2078 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2079 .sel_byte = 1, 2080 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2081 .srt = 0x0, 2082 .end = 0x6, 2083 .rd_addr = R_AX_DBG_PORT_SEL, 2084 .rd_byte = 4, 2085 .rd_msk = B_AX_DEBUG_ST_MASK 2086 }; 2087 2088 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_wde_intf = { 2089 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2090 .sel_byte = 1, 2091 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2092 .srt = 0x0, 2093 .end = 0xF, 2094 .rd_addr = R_AX_DBG_PORT_SEL, 2095 .rd_byte = 4, 2096 .rd_msk = B_AX_DEBUG_ST_MASK 2097 }; 2098 2099 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_ple_intf = { 2100 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2101 .sel_byte = 1, 2102 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2103 .srt = 0x0, 2104 .end = 0x9, 2105 .rd_addr = R_AX_DBG_PORT_SEL, 2106 .rd_byte = 4, 2107 .rd_msk = B_AX_DEBUG_ST_MASK 2108 }; 2109 2110 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_flow_ctrl = { 2111 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2112 .sel_byte = 1, 2113 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2114 .srt = 0x0, 2115 .end = 0x3, 2116 .rd_addr = R_AX_DBG_PORT_SEL, 2117 .rd_byte = 4, 2118 .rd_msk = B_AX_DEBUG_ST_MASK 2119 }; 2120 2121 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { 2122 .sel_addr = R_AX_SCH_DBG_SEL, 2123 .sel_byte = 1, 2124 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 2125 .srt = 0x00, 2126 .end = 0x2F, 2127 .rd_addr = R_AX_SCH_DBG, 2128 .rd_byte = 4, 2129 .rd_msk = B_AX_SCHEDULER_DBG_MASK 2130 }; 2131 2132 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { 2133 .sel_addr = R_AX_SCH_DBG_SEL_C1, 2134 .sel_byte = 1, 2135 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 2136 .srt = 0x00, 2137 .end = 0x2F, 2138 .rd_addr = R_AX_SCH_DBG_C1, 2139 .rd_byte = 4, 2140 .rd_msk = B_AX_SCHEDULER_DBG_MASK 2141 }; 2142 2143 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { 2144 .sel_addr = R_AX_MACTX_DBG_SEL_CNT, 2145 .sel_byte = 1, 2146 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 2147 .srt = 0x00, 2148 .end = 0x19, 2149 .rd_addr = R_AX_DBG_PORT_SEL, 2150 .rd_byte = 4, 2151 .rd_msk = B_AX_DEBUG_ST_MASK 2152 }; 2153 2154 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { 2155 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, 2156 .sel_byte = 1, 2157 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 2158 .srt = 0x00, 2159 .end = 0x19, 2160 .rd_addr = R_AX_DBG_PORT_SEL, 2161 .rd_byte = 4, 2162 .rd_msk = B_AX_DEBUG_ST_MASK 2163 }; 2164 2165 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { 2166 .sel_addr = R_AX_RX_DEBUG_SELECT, 2167 .sel_byte = 1, 2168 .sel_msk = B_AX_DEBUG_SEL_MASK, 2169 .srt = 0x00, 2170 .end = 0x58, 2171 .rd_addr = R_AX_DBG_PORT_SEL, 2172 .rd_byte = 4, 2173 .rd_msk = B_AX_DEBUG_ST_MASK 2174 }; 2175 2176 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { 2177 .sel_addr = R_AX_RX_DEBUG_SELECT_C1, 2178 .sel_byte = 1, 2179 .sel_msk = B_AX_DEBUG_SEL_MASK, 2180 .srt = 0x00, 2181 .end = 0x58, 2182 .rd_addr = R_AX_DBG_PORT_SEL, 2183 .rd_byte = 4, 2184 .rd_msk = B_AX_DEBUG_ST_MASK 2185 }; 2186 2187 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { 2188 .sel_addr = R_AX_RX_STATE_MONITOR, 2189 .sel_byte = 1, 2190 .sel_msk = B_AX_STATE_SEL_MASK, 2191 .srt = 0x00, 2192 .end = 0x17, 2193 .rd_addr = R_AX_RX_STATE_MONITOR, 2194 .rd_byte = 4, 2195 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 2196 }; 2197 2198 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { 2199 .sel_addr = R_AX_RX_STATE_MONITOR_C1, 2200 .sel_byte = 1, 2201 .sel_msk = B_AX_STATE_SEL_MASK, 2202 .srt = 0x00, 2203 .end = 0x17, 2204 .rd_addr = R_AX_RX_STATE_MONITOR_C1, 2205 .rd_byte = 4, 2206 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 2207 }; 2208 2209 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { 2210 .sel_addr = R_AX_RMAC_PLCP_MON, 2211 .sel_byte = 4, 2212 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 2213 .srt = 0x0, 2214 .end = 0xF, 2215 .rd_addr = R_AX_RMAC_PLCP_MON, 2216 .rd_byte = 4, 2217 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 2218 }; 2219 2220 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { 2221 .sel_addr = R_AX_RMAC_PLCP_MON_C1, 2222 .sel_byte = 4, 2223 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 2224 .srt = 0x0, 2225 .end = 0xF, 2226 .rd_addr = R_AX_RMAC_PLCP_MON_C1, 2227 .rd_byte = 4, 2228 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 2229 }; 2230 2231 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { 2232 .sel_addr = R_AX_DBGSEL_TRXPTCL, 2233 .sel_byte = 1, 2234 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 2235 .srt = 0x08, 2236 .end = 0x10, 2237 .rd_addr = R_AX_DBG_PORT_SEL, 2238 .rd_byte = 4, 2239 .rd_msk = B_AX_DEBUG_ST_MASK 2240 }; 2241 2242 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { 2243 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, 2244 .sel_byte = 1, 2245 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 2246 .srt = 0x08, 2247 .end = 0x10, 2248 .rd_addr = R_AX_DBG_PORT_SEL, 2249 .rd_byte = 4, 2250 .rd_msk = B_AX_DEBUG_ST_MASK 2251 }; 2252 2253 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { 2254 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 2255 .sel_byte = 1, 2256 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2257 .srt = 0x00, 2258 .end = 0x07, 2259 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, 2260 .rd_byte = 4, 2261 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 2262 }; 2263 2264 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { 2265 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 2266 .sel_byte = 1, 2267 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2268 .srt = 0x00, 2269 .end = 0x07, 2270 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, 2271 .rd_byte = 4, 2272 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 2273 }; 2274 2275 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { 2276 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 2277 .sel_byte = 1, 2278 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2279 .srt = 0x00, 2280 .end = 0x07, 2281 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, 2282 .rd_byte = 4, 2283 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 2284 }; 2285 2286 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { 2287 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 2288 .sel_byte = 1, 2289 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2290 .srt = 0x00, 2291 .end = 0x07, 2292 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, 2293 .rd_byte = 4, 2294 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 2295 }; 2296 2297 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { 2298 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 2299 .sel_byte = 1, 2300 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2301 .srt = 0x00, 2302 .end = 0x04, 2303 .rd_addr = R_AX_WMAC_TX_TF_INFO_1, 2304 .rd_byte = 4, 2305 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 2306 }; 2307 2308 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { 2309 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 2310 .sel_byte = 1, 2311 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2312 .srt = 0x00, 2313 .end = 0x04, 2314 .rd_addr = R_AX_WMAC_TX_TF_INFO_2, 2315 .rd_byte = 4, 2316 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 2317 }; 2318 2319 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { 2320 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 2321 .sel_byte = 1, 2322 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2323 .srt = 0x00, 2324 .end = 0x04, 2325 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, 2326 .rd_byte = 4, 2327 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 2328 }; 2329 2330 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { 2331 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 2332 .sel_byte = 1, 2333 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2334 .srt = 0x00, 2335 .end = 0x04, 2336 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, 2337 .rd_byte = 4, 2338 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 2339 }; 2340 2341 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { 2342 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2343 .sel_byte = 4, 2344 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2345 .srt = 0x80000000, 2346 .end = 0x80000001, 2347 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2348 .rd_byte = 4, 2349 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2350 }; 2351 2352 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { 2353 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2354 .sel_byte = 4, 2355 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2356 .srt = 0x80010000, 2357 .end = 0x80010004, 2358 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2359 .rd_byte = 4, 2360 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2361 }; 2362 2363 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { 2364 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2365 .sel_byte = 4, 2366 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2367 .srt = 0x80020000, 2368 .end = 0x80020FFF, 2369 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2370 .rd_byte = 4, 2371 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2372 }; 2373 2374 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { 2375 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2376 .sel_byte = 4, 2377 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2378 .srt = 0x80030000, 2379 .end = 0x80030FFF, 2380 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2381 .rd_byte = 4, 2382 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2383 }; 2384 2385 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { 2386 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2387 .sel_byte = 4, 2388 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2389 .srt = 0x80040000, 2390 .end = 0x80040FFF, 2391 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2392 .rd_byte = 4, 2393 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2394 }; 2395 2396 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { 2397 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2398 .sel_byte = 4, 2399 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2400 .srt = 0x80050000, 2401 .end = 0x80050FFF, 2402 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2403 .rd_byte = 4, 2404 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2405 }; 2406 2407 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { 2408 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2409 .sel_byte = 4, 2410 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2411 .srt = 0x80060000, 2412 .end = 0x80060453, 2413 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2414 .rd_byte = 4, 2415 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2416 }; 2417 2418 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { 2419 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2420 .sel_byte = 4, 2421 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2422 .srt = 0x80070000, 2423 .end = 0x80070011, 2424 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2425 .rd_byte = 4, 2426 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2427 }; 2428 2429 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { 2430 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2431 .sel_byte = 4, 2432 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2433 .srt = 0x80000000, 2434 .end = 0x80000001, 2435 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2436 .rd_byte = 4, 2437 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2438 }; 2439 2440 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { 2441 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2442 .sel_byte = 4, 2443 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2444 .srt = 0x80010000, 2445 .end = 0x8001000A, 2446 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2447 .rd_byte = 4, 2448 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2449 }; 2450 2451 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { 2452 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2453 .sel_byte = 4, 2454 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2455 .srt = 0x80020000, 2456 .end = 0x80020DBF, 2457 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2458 .rd_byte = 4, 2459 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2460 }; 2461 2462 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { 2463 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2464 .sel_byte = 4, 2465 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2466 .srt = 0x80030000, 2467 .end = 0x80030DBF, 2468 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2469 .rd_byte = 4, 2470 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2471 }; 2472 2473 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { 2474 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2475 .sel_byte = 4, 2476 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2477 .srt = 0x80040000, 2478 .end = 0x80040DBF, 2479 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2480 .rd_byte = 4, 2481 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2482 }; 2483 2484 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { 2485 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2486 .sel_byte = 4, 2487 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2488 .srt = 0x80050000, 2489 .end = 0x80050DBF, 2490 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2491 .rd_byte = 4, 2492 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2493 }; 2494 2495 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { 2496 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2497 .sel_byte = 4, 2498 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2499 .srt = 0x80060000, 2500 .end = 0x80060041, 2501 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2502 .rd_byte = 4, 2503 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2504 }; 2505 2506 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { 2507 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2508 .sel_byte = 4, 2509 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2510 .srt = 0x80070000, 2511 .end = 0x80070001, 2512 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2513 .rd_byte = 4, 2514 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2515 }; 2516 2517 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { 2518 .sel_addr = R_AX_DBG_FUN_INTF_CTL, 2519 .sel_byte = 4, 2520 .sel_msk = B_AX_DFI_DATA_MASK, 2521 .srt = 0x80000000, 2522 .end = 0x8000017f, 2523 .rd_addr = R_AX_DBG_FUN_INTF_DATA, 2524 .rd_byte = 4, 2525 .rd_msk = B_AX_DFI_DATA_MASK 2526 }; 2527 2528 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { 2529 .sel_addr = R_AX_PCIE_DBG_CTRL, 2530 .sel_byte = 2, 2531 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2532 .srt = 0x00, 2533 .end = 0x03, 2534 .rd_addr = R_AX_DBG_PORT_SEL, 2535 .rd_byte = 4, 2536 .rd_msk = B_AX_DEBUG_ST_MASK 2537 }; 2538 2539 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { 2540 .sel_addr = R_AX_PCIE_DBG_CTRL, 2541 .sel_byte = 2, 2542 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2543 .srt = 0x00, 2544 .end = 0x04, 2545 .rd_addr = R_AX_DBG_PORT_SEL, 2546 .rd_byte = 4, 2547 .rd_msk = B_AX_DEBUG_ST_MASK 2548 }; 2549 2550 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { 2551 .sel_addr = R_AX_PCIE_DBG_CTRL, 2552 .sel_byte = 2, 2553 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2554 .srt = 0x00, 2555 .end = 0x01, 2556 .rd_addr = R_AX_DBG_PORT_SEL, 2557 .rd_byte = 4, 2558 .rd_msk = B_AX_DEBUG_ST_MASK 2559 }; 2560 2561 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { 2562 .sel_addr = R_AX_PCIE_DBG_CTRL, 2563 .sel_byte = 2, 2564 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2565 .srt = 0x00, 2566 .end = 0x05, 2567 .rd_addr = R_AX_DBG_PORT_SEL, 2568 .rd_byte = 4, 2569 .rd_msk = B_AX_DEBUG_ST_MASK 2570 }; 2571 2572 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { 2573 .sel_addr = R_AX_PCIE_DBG_CTRL, 2574 .sel_byte = 2, 2575 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2576 .srt = 0x00, 2577 .end = 0x05, 2578 .rd_addr = R_AX_DBG_PORT_SEL, 2579 .rd_byte = 4, 2580 .rd_msk = B_AX_DEBUG_ST_MASK 2581 }; 2582 2583 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { 2584 .sel_addr = R_AX_PCIE_DBG_CTRL, 2585 .sel_byte = 2, 2586 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2587 .srt = 0x00, 2588 .end = 0x06, 2589 .rd_addr = R_AX_DBG_PORT_SEL, 2590 .rd_byte = 4, 2591 .rd_msk = B_AX_DEBUG_ST_MASK 2592 }; 2593 2594 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { 2595 .sel_addr = R_AX_DBG_CTRL, 2596 .sel_byte = 1, 2597 .sel_msk = B_AX_DBG_SEL0, 2598 .srt = 0x34, 2599 .end = 0x3C, 2600 .rd_addr = R_AX_DBG_PORT_SEL, 2601 .rd_byte = 4, 2602 .rd_msk = B_AX_DEBUG_ST_MASK 2603 }; 2604 2605 static int 2606 rtw89_debug_mac_dbg_port_sel(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 2607 u32 sel, const struct rtw89_mac_dbg_port_info **ppinfo) 2608 { 2609 const struct rtw89_mac_dbg_port_info *info = NULL; 2610 char *p = buf, *end = buf + bufsz; 2611 u32 index; 2612 u32 val32; 2613 u16 val16; 2614 u8 val8; 2615 2616 switch (sel) { 2617 case RTW89_DBG_PORT_SEL_PTCL_C0: 2618 info = &dbg_port_ptcl_c0; 2619 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); 2620 val16 |= B_AX_PTCL_DBG_EN; 2621 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); 2622 p += scnprintf(p, end - p, "Enable PTCL C0 dbgport.\n"); 2623 break; 2624 case RTW89_DBG_PORT_SEL_PTCL_C1: 2625 info = &dbg_port_ptcl_c1; 2626 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); 2627 val16 |= B_AX_PTCL_DBG_EN; 2628 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); 2629 p += scnprintf(p, end - p, "Enable PTCL C1 dbgport.\n"); 2630 break; 2631 case RTW89_DBG_PORT_SEL_SCH_C0: 2632 info = &dbg_port_sch_c0; 2633 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); 2634 val32 |= B_AX_SCH_DBG_EN; 2635 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); 2636 p += scnprintf(p, end - p, "Enable SCH C0 dbgport.\n"); 2637 break; 2638 case RTW89_DBG_PORT_SEL_SCH_C1: 2639 info = &dbg_port_sch_c1; 2640 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); 2641 val32 |= B_AX_SCH_DBG_EN; 2642 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); 2643 p += scnprintf(p, end - p, "Enable SCH C1 dbgport.\n"); 2644 break; 2645 case RTW89_DBG_PORT_SEL_TMAC_C0: 2646 info = &dbg_port_tmac_c0; 2647 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2648 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2649 B_AX_DBGSEL_TRXPTCL_MASK); 2650 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2651 2652 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2653 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2654 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2655 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2656 2657 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2658 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2659 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2660 p += scnprintf(p, end - p, "Enable TMAC C0 dbgport.\n"); 2661 break; 2662 case RTW89_DBG_PORT_SEL_TMAC_C1: 2663 info = &dbg_port_tmac_c1; 2664 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2665 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2666 B_AX_DBGSEL_TRXPTCL_MASK); 2667 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2668 2669 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2670 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2671 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2672 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2673 2674 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2675 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2676 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2677 p += scnprintf(p, end - p, "Enable TMAC C1 dbgport.\n"); 2678 break; 2679 case RTW89_DBG_PORT_SEL_RMAC_C0: 2680 info = &dbg_port_rmac_c0; 2681 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2682 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2683 B_AX_DBGSEL_TRXPTCL_MASK); 2684 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2685 2686 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2687 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2688 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2689 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2690 2691 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2692 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2693 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2694 2695 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); 2696 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2697 B_AX_DBGSEL_TRXPTCL_MASK); 2698 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); 2699 p += scnprintf(p, end - p, "Enable RMAC C0 dbgport.\n"); 2700 break; 2701 case RTW89_DBG_PORT_SEL_RMAC_C1: 2702 info = &dbg_port_rmac_c1; 2703 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2704 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2705 B_AX_DBGSEL_TRXPTCL_MASK); 2706 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2707 2708 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2709 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2710 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2711 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2712 2713 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2714 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2715 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2716 2717 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2718 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2719 B_AX_DBGSEL_TRXPTCL_MASK); 2720 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); 2721 p += scnprintf(p, end - p, "Enable RMAC C1 dbgport.\n"); 2722 break; 2723 case RTW89_DBG_PORT_SEL_RMACST_C0: 2724 info = &dbg_port_rmacst_c0; 2725 p += scnprintf(p, end - p, "Enable RMAC state C0 dbgport.\n"); 2726 break; 2727 case RTW89_DBG_PORT_SEL_RMACST_C1: 2728 info = &dbg_port_rmacst_c1; 2729 p += scnprintf(p, end - p, "Enable RMAC state C1 dbgport.\n"); 2730 break; 2731 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: 2732 info = &dbg_port_rmac_plcp_c0; 2733 p += scnprintf(p, end - p, "Enable RMAC PLCP C0 dbgport.\n"); 2734 break; 2735 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: 2736 info = &dbg_port_rmac_plcp_c1; 2737 p += scnprintf(p, end - p, "Enable RMAC PLCP C1 dbgport.\n"); 2738 break; 2739 case RTW89_DBG_PORT_SEL_TRXPTCL_C0: 2740 info = &dbg_port_trxptcl_c0; 2741 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2742 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); 2743 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); 2744 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2745 2746 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2747 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2748 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2749 p += scnprintf(p, end - p, "Enable TRXPTCL C0 dbgport.\n"); 2750 break; 2751 case RTW89_DBG_PORT_SEL_TRXPTCL_C1: 2752 info = &dbg_port_trxptcl_c1; 2753 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2754 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); 2755 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); 2756 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2757 2758 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2759 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2760 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2761 p += scnprintf(p, end - p, "Enable TRXPTCL C1 dbgport.\n"); 2762 break; 2763 case RTW89_DBG_PORT_SEL_TX_INFOL_C0: 2764 info = &dbg_port_tx_infol_c0; 2765 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2766 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2767 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2768 p += scnprintf(p, end - p, "Enable tx infol dump.\n"); 2769 break; 2770 case RTW89_DBG_PORT_SEL_TX_INFOH_C0: 2771 info = &dbg_port_tx_infoh_c0; 2772 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2773 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2774 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2775 p += scnprintf(p, end - p, "Enable tx infoh dump.\n"); 2776 break; 2777 case RTW89_DBG_PORT_SEL_TX_INFOL_C1: 2778 info = &dbg_port_tx_infol_c1; 2779 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2780 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2781 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2782 p += scnprintf(p, end - p, "Enable tx infol dump.\n"); 2783 break; 2784 case RTW89_DBG_PORT_SEL_TX_INFOH_C1: 2785 info = &dbg_port_tx_infoh_c1; 2786 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2787 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2788 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2789 p += scnprintf(p, end - p, "Enable tx infoh dump.\n"); 2790 break; 2791 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: 2792 info = &dbg_port_txtf_infol_c0; 2793 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2794 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2795 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2796 p += scnprintf(p, end - p, "Enable tx tf infol dump.\n"); 2797 break; 2798 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: 2799 info = &dbg_port_txtf_infoh_c0; 2800 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2801 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2802 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2803 p += scnprintf(p, end - p, "Enable tx tf infoh dump.\n"); 2804 break; 2805 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: 2806 info = &dbg_port_txtf_infol_c1; 2807 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2808 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2809 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2810 p += scnprintf(p, end - p, "Enable tx tf infol dump.\n"); 2811 break; 2812 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: 2813 info = &dbg_port_txtf_infoh_c1; 2814 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2815 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2816 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2817 p += scnprintf(p, end - p, "Enable tx tf infoh dump.\n"); 2818 break; 2819 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: 2820 info = &dbg_port_wde_bufmgn_freepg; 2821 p += scnprintf(p, end - p, "Enable wde bufmgn freepg dump.\n"); 2822 break; 2823 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: 2824 info = &dbg_port_wde_bufmgn_quota; 2825 p += scnprintf(p, end - p, "Enable wde bufmgn quota dump.\n"); 2826 break; 2827 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: 2828 info = &dbg_port_wde_bufmgn_pagellt; 2829 p += scnprintf(p, end - p, 2830 "Enable wde bufmgn pagellt dump.\n"); 2831 break; 2832 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: 2833 info = &dbg_port_wde_bufmgn_pktinfo; 2834 p += scnprintf(p, end - p, 2835 "Enable wde bufmgn pktinfo dump.\n"); 2836 break; 2837 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: 2838 info = &dbg_port_wde_quemgn_prepkt; 2839 p += scnprintf(p, end - p, "Enable wde quemgn prepkt dump.\n"); 2840 break; 2841 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: 2842 info = &dbg_port_wde_quemgn_nxtpkt; 2843 p += scnprintf(p, end - p, "Enable wde quemgn nxtpkt dump.\n"); 2844 break; 2845 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: 2846 info = &dbg_port_wde_quemgn_qlnktbl; 2847 p += scnprintf(p, end - p, 2848 "Enable wde quemgn qlnktbl dump.\n"); 2849 break; 2850 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: 2851 info = &dbg_port_wde_quemgn_qempty; 2852 p += scnprintf(p, end - p, "Enable wde quemgn qempty dump.\n"); 2853 break; 2854 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: 2855 info = &dbg_port_ple_bufmgn_freepg; 2856 p += scnprintf(p, end - p, "Enable ple bufmgn freepg dump.\n"); 2857 break; 2858 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: 2859 info = &dbg_port_ple_bufmgn_quota; 2860 p += scnprintf(p, end - p, "Enable ple bufmgn quota dump.\n"); 2861 break; 2862 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: 2863 info = &dbg_port_ple_bufmgn_pagellt; 2864 p += scnprintf(p, end - p, 2865 "Enable ple bufmgn pagellt dump.\n"); 2866 break; 2867 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: 2868 info = &dbg_port_ple_bufmgn_pktinfo; 2869 p += scnprintf(p, end - p, 2870 "Enable ple bufmgn pktinfo dump.\n"); 2871 break; 2872 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: 2873 info = &dbg_port_ple_quemgn_prepkt; 2874 p += scnprintf(p, end - p, "Enable ple quemgn prepkt dump.\n"); 2875 break; 2876 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: 2877 info = &dbg_port_ple_quemgn_nxtpkt; 2878 p += scnprintf(p, end - p, "Enable ple quemgn nxtpkt dump.\n"); 2879 break; 2880 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: 2881 info = &dbg_port_ple_quemgn_qlnktbl; 2882 p += scnprintf(p, end - p, 2883 "Enable ple quemgn qlnktbl dump.\n"); 2884 break; 2885 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: 2886 info = &dbg_port_ple_quemgn_qempty; 2887 p += scnprintf(p, end - p, "Enable ple quemgn qempty dump.\n"); 2888 break; 2889 case RTW89_DBG_PORT_SEL_PKTINFO: 2890 info = &dbg_port_pktinfo; 2891 p += scnprintf(p, end - p, "Enable pktinfo dump.\n"); 2892 break; 2893 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX0: 2894 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 2895 B_AX_DBG_SEL0, 0x80); 2896 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 2897 B_AX_SEL_0XC0_MASK, 1); 2898 fallthrough; 2899 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX1: 2900 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX2: 2901 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX3: 2902 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX4: 2903 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX5: 2904 info = &dbg_port_dspt_hdt_tx0_5; 2905 index = sel - RTW89_DBG_PORT_SEL_DSPT_HDT_TX0; 2906 rtw89_write16_mask(rtwdev, info->sel_addr, 2907 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2908 rtw89_write16_mask(rtwdev, info->sel_addr, 2909 B_AX_DISPATCHER_CH_SEL_MASK, index); 2910 p += scnprintf(p, end - p, 2911 "Enable Dispatcher hdt tx%x dump.\n", index); 2912 break; 2913 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX6: 2914 info = &dbg_port_dspt_hdt_tx6; 2915 rtw89_write16_mask(rtwdev, info->sel_addr, 2916 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2917 rtw89_write16_mask(rtwdev, info->sel_addr, 2918 B_AX_DISPATCHER_CH_SEL_MASK, 6); 2919 p += scnprintf(p, end - p, 2920 "Enable Dispatcher hdt tx6 dump.\n"); 2921 break; 2922 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX7: 2923 info = &dbg_port_dspt_hdt_tx7; 2924 rtw89_write16_mask(rtwdev, info->sel_addr, 2925 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2926 rtw89_write16_mask(rtwdev, info->sel_addr, 2927 B_AX_DISPATCHER_CH_SEL_MASK, 7); 2928 p += scnprintf(p, end - p, 2929 "Enable Dispatcher hdt tx7 dump.\n"); 2930 break; 2931 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX8: 2932 info = &dbg_port_dspt_hdt_tx8; 2933 rtw89_write16_mask(rtwdev, info->sel_addr, 2934 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2935 rtw89_write16_mask(rtwdev, info->sel_addr, 2936 B_AX_DISPATCHER_CH_SEL_MASK, 8); 2937 p += scnprintf(p, end - p, 2938 "Enable Dispatcher hdt tx8 dump.\n"); 2939 break; 2940 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX9: 2941 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXA: 2942 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXB: 2943 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXC: 2944 info = &dbg_port_dspt_hdt_tx9_C; 2945 index = sel + 9 - RTW89_DBG_PORT_SEL_DSPT_HDT_TX9; 2946 rtw89_write16_mask(rtwdev, info->sel_addr, 2947 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2948 rtw89_write16_mask(rtwdev, info->sel_addr, 2949 B_AX_DISPATCHER_CH_SEL_MASK, index); 2950 p += scnprintf(p, end - p, 2951 "Enable Dispatcher hdt tx%x dump.\n", index); 2952 break; 2953 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXD: 2954 info = &dbg_port_dspt_hdt_txD; 2955 rtw89_write16_mask(rtwdev, info->sel_addr, 2956 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2957 rtw89_write16_mask(rtwdev, info->sel_addr, 2958 B_AX_DISPATCHER_CH_SEL_MASK, 0xD); 2959 p += scnprintf(p, end - p, 2960 "Enable Dispatcher hdt txD dump.\n"); 2961 break; 2962 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX0: 2963 info = &dbg_port_dspt_cdt_tx0; 2964 rtw89_write16_mask(rtwdev, info->sel_addr, 2965 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2966 rtw89_write16_mask(rtwdev, info->sel_addr, 2967 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2968 p += scnprintf(p, end - p, 2969 "Enable Dispatcher cdt tx0 dump.\n"); 2970 break; 2971 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX1: 2972 info = &dbg_port_dspt_cdt_tx1; 2973 rtw89_write16_mask(rtwdev, info->sel_addr, 2974 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2975 rtw89_write16_mask(rtwdev, info->sel_addr, 2976 B_AX_DISPATCHER_CH_SEL_MASK, 1); 2977 p += scnprintf(p, end - p, 2978 "Enable Dispatcher cdt tx1 dump.\n"); 2979 break; 2980 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX3: 2981 info = &dbg_port_dspt_cdt_tx3; 2982 rtw89_write16_mask(rtwdev, info->sel_addr, 2983 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2984 rtw89_write16_mask(rtwdev, info->sel_addr, 2985 B_AX_DISPATCHER_CH_SEL_MASK, 3); 2986 p += scnprintf(p, end - p, 2987 "Enable Dispatcher cdt tx3 dump.\n"); 2988 break; 2989 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX4: 2990 info = &dbg_port_dspt_cdt_tx4; 2991 rtw89_write16_mask(rtwdev, info->sel_addr, 2992 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2993 rtw89_write16_mask(rtwdev, info->sel_addr, 2994 B_AX_DISPATCHER_CH_SEL_MASK, 4); 2995 p += scnprintf(p, end - p, 2996 "Enable Dispatcher cdt tx4 dump.\n"); 2997 break; 2998 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX5: 2999 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX6: 3000 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX7: 3001 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX8: 3002 info = &dbg_port_dspt_cdt_tx5_8; 3003 index = sel + 5 - RTW89_DBG_PORT_SEL_DSPT_CDT_TX5; 3004 rtw89_write16_mask(rtwdev, info->sel_addr, 3005 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3006 rtw89_write16_mask(rtwdev, info->sel_addr, 3007 B_AX_DISPATCHER_CH_SEL_MASK, index); 3008 p += scnprintf(p, end - p, 3009 "Enable Dispatcher cdt tx%x dump.\n", index); 3010 break; 3011 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX9: 3012 info = &dbg_port_dspt_cdt_tx9; 3013 rtw89_write16_mask(rtwdev, info->sel_addr, 3014 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3015 rtw89_write16_mask(rtwdev, info->sel_addr, 3016 B_AX_DISPATCHER_CH_SEL_MASK, 9); 3017 p += scnprintf(p, end - p, 3018 "Enable Dispatcher cdt tx9 dump.\n"); 3019 break; 3020 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXA: 3021 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXB: 3022 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXC: 3023 info = &dbg_port_dspt_cdt_txA_C; 3024 index = sel + 0xA - RTW89_DBG_PORT_SEL_DSPT_CDT_TXA; 3025 rtw89_write16_mask(rtwdev, info->sel_addr, 3026 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3027 rtw89_write16_mask(rtwdev, info->sel_addr, 3028 B_AX_DISPATCHER_CH_SEL_MASK, index); 3029 p += scnprintf(p, end - p, 3030 "Enable Dispatcher cdt tx%x dump.\n", index); 3031 break; 3032 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX0: 3033 info = &dbg_port_dspt_hdt_rx0; 3034 rtw89_write16_mask(rtwdev, info->sel_addr, 3035 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3036 rtw89_write16_mask(rtwdev, info->sel_addr, 3037 B_AX_DISPATCHER_CH_SEL_MASK, 0); 3038 p += scnprintf(p, end - p, 3039 "Enable Dispatcher hdt rx0 dump.\n"); 3040 break; 3041 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX1: 3042 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX2: 3043 info = &dbg_port_dspt_hdt_rx1_2; 3044 index = sel + 1 - RTW89_DBG_PORT_SEL_DSPT_HDT_RX1; 3045 rtw89_write16_mask(rtwdev, info->sel_addr, 3046 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3047 rtw89_write16_mask(rtwdev, info->sel_addr, 3048 B_AX_DISPATCHER_CH_SEL_MASK, index); 3049 p += scnprintf(p, end - p, 3050 "Enable Dispatcher hdt rx%x dump.\n", index); 3051 break; 3052 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX3: 3053 info = &dbg_port_dspt_hdt_rx3; 3054 rtw89_write16_mask(rtwdev, info->sel_addr, 3055 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3056 rtw89_write16_mask(rtwdev, info->sel_addr, 3057 B_AX_DISPATCHER_CH_SEL_MASK, 3); 3058 p += scnprintf(p, end - p, 3059 "Enable Dispatcher hdt rx3 dump.\n"); 3060 break; 3061 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX4: 3062 info = &dbg_port_dspt_hdt_rx4; 3063 rtw89_write16_mask(rtwdev, info->sel_addr, 3064 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3065 rtw89_write16_mask(rtwdev, info->sel_addr, 3066 B_AX_DISPATCHER_CH_SEL_MASK, 4); 3067 p += scnprintf(p, end - p, 3068 "Enable Dispatcher hdt rx4 dump.\n"); 3069 break; 3070 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX5: 3071 info = &dbg_port_dspt_hdt_rx5; 3072 rtw89_write16_mask(rtwdev, info->sel_addr, 3073 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3074 rtw89_write16_mask(rtwdev, info->sel_addr, 3075 B_AX_DISPATCHER_CH_SEL_MASK, 5); 3076 p += scnprintf(p, end - p, 3077 "Enable Dispatcher hdt rx5 dump.\n"); 3078 break; 3079 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0: 3080 info = &dbg_port_dspt_cdt_rx_p0_0; 3081 rtw89_write16_mask(rtwdev, info->sel_addr, 3082 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3083 rtw89_write16_mask(rtwdev, info->sel_addr, 3084 B_AX_DISPATCHER_CH_SEL_MASK, 0); 3085 p += scnprintf(p, end - p, 3086 "Enable Dispatcher cdt rx part0 0 dump.\n"); 3087 break; 3088 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0: 3089 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1: 3090 info = &dbg_port_dspt_cdt_rx_p0_1; 3091 rtw89_write16_mask(rtwdev, info->sel_addr, 3092 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3093 rtw89_write16_mask(rtwdev, info->sel_addr, 3094 B_AX_DISPATCHER_CH_SEL_MASK, 1); 3095 p += scnprintf(p, end - p, 3096 "Enable Dispatcher cdt rx part0 1 dump.\n"); 3097 break; 3098 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2: 3099 info = &dbg_port_dspt_cdt_rx_p0_2; 3100 rtw89_write16_mask(rtwdev, info->sel_addr, 3101 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3102 rtw89_write16_mask(rtwdev, info->sel_addr, 3103 B_AX_DISPATCHER_CH_SEL_MASK, 2); 3104 p += scnprintf(p, end - p, 3105 "Enable Dispatcher cdt rx part0 2 dump.\n"); 3106 break; 3107 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1: 3108 info = &dbg_port_dspt_cdt_rx_p1; 3109 rtw89_write8_mask(rtwdev, info->sel_addr, 3110 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3111 p += scnprintf(p, end - p, 3112 "Enable Dispatcher cdt rx part1 dump.\n"); 3113 break; 3114 case RTW89_DBG_PORT_SEL_DSPT_STF_CTRL: 3115 info = &dbg_port_dspt_stf_ctrl; 3116 rtw89_write8_mask(rtwdev, info->sel_addr, 3117 B_AX_DISPATCHER_INTN_SEL_MASK, 4); 3118 p += scnprintf(p, end - p, 3119 "Enable Dispatcher stf control dump.\n"); 3120 break; 3121 case RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL: 3122 info = &dbg_port_dspt_addr_ctrl; 3123 rtw89_write8_mask(rtwdev, info->sel_addr, 3124 B_AX_DISPATCHER_INTN_SEL_MASK, 5); 3125 p += scnprintf(p, end - p, 3126 "Enable Dispatcher addr control dump.\n"); 3127 break; 3128 case RTW89_DBG_PORT_SEL_DSPT_WDE_INTF: 3129 info = &dbg_port_dspt_wde_intf; 3130 rtw89_write8_mask(rtwdev, info->sel_addr, 3131 B_AX_DISPATCHER_INTN_SEL_MASK, 6); 3132 p += scnprintf(p, end - p, 3133 "Enable Dispatcher wde interface dump.\n"); 3134 break; 3135 case RTW89_DBG_PORT_SEL_DSPT_PLE_INTF: 3136 info = &dbg_port_dspt_ple_intf; 3137 rtw89_write8_mask(rtwdev, info->sel_addr, 3138 B_AX_DISPATCHER_INTN_SEL_MASK, 7); 3139 p += scnprintf(p, end - p, 3140 "Enable Dispatcher ple interface dump.\n"); 3141 break; 3142 case RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL: 3143 info = &dbg_port_dspt_flow_ctrl; 3144 rtw89_write8_mask(rtwdev, info->sel_addr, 3145 B_AX_DISPATCHER_INTN_SEL_MASK, 8); 3146 p += scnprintf(p, end - p, 3147 "Enable Dispatcher flow control dump.\n"); 3148 break; 3149 case RTW89_DBG_PORT_SEL_PCIE_TXDMA: 3150 info = &dbg_port_pcie_txdma; 3151 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3152 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); 3153 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); 3154 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3155 p += scnprintf(p, end - p, "Enable pcie txdma dump.\n"); 3156 break; 3157 case RTW89_DBG_PORT_SEL_PCIE_RXDMA: 3158 info = &dbg_port_pcie_rxdma; 3159 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3160 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); 3161 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); 3162 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3163 p += scnprintf(p, end - p, "Enable pcie rxdma dump.\n"); 3164 break; 3165 case RTW89_DBG_PORT_SEL_PCIE_CVT: 3166 info = &dbg_port_pcie_cvt; 3167 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3168 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); 3169 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); 3170 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3171 p += scnprintf(p, end - p, "Enable pcie cvt dump.\n"); 3172 break; 3173 case RTW89_DBG_PORT_SEL_PCIE_CXPL: 3174 info = &dbg_port_pcie_cxpl; 3175 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3176 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); 3177 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); 3178 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3179 p += scnprintf(p, end - p, "Enable pcie cxpl dump.\n"); 3180 break; 3181 case RTW89_DBG_PORT_SEL_PCIE_IO: 3182 info = &dbg_port_pcie_io; 3183 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3184 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); 3185 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); 3186 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3187 p += scnprintf(p, end - p, "Enable pcie io dump.\n"); 3188 break; 3189 case RTW89_DBG_PORT_SEL_PCIE_MISC: 3190 info = &dbg_port_pcie_misc; 3191 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3192 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); 3193 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); 3194 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3195 p += scnprintf(p, end - p, "Enable pcie misc dump.\n"); 3196 break; 3197 case RTW89_DBG_PORT_SEL_PCIE_MISC2: 3198 info = &dbg_port_pcie_misc2; 3199 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); 3200 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, 3201 B_AX_PCIE_DBG_SEL_MASK); 3202 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); 3203 p += scnprintf(p, end - p, "Enable pcie misc2 dump.\n"); 3204 break; 3205 default: 3206 p += scnprintf(p, end - p, "Dbg port select err\n"); 3207 break; 3208 } 3209 3210 *ppinfo = info; 3211 3212 return p - buf; 3213 } 3214 3215 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) 3216 { 3217 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && 3218 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && 3219 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) 3220 return false; 3221 if (rtw89_is_rtl885xb(rtwdev) && 3222 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 3223 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 3224 return false; 3225 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 3226 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && 3227 sel <= RTW89_DBG_PORT_SEL_PKTINFO) 3228 return false; 3229 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 3230 sel >= RTW89_DBG_PORT_SEL_DSPT_HDT_TX0 && 3231 sel <= RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL) 3232 return false; 3233 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && 3234 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && 3235 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) 3236 return false; 3237 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && 3238 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 3239 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 3240 return false; 3241 3242 return true; 3243 } 3244 3245 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, 3246 char *buf, size_t bufsz, u32 sel) 3247 { 3248 const struct rtw89_mac_dbg_port_info *info = NULL; 3249 char *p = buf, *end = buf + bufsz; 3250 u32 val32; 3251 u16 val16; 3252 u8 val8; 3253 u32 i; 3254 3255 p += rtw89_debug_mac_dbg_port_sel(rtwdev, p, end - p, sel, &info); 3256 3257 if (!info) { 3258 rtw89_err(rtwdev, "failed to select debug port %d\n", sel); 3259 goto out; 3260 } 3261 3262 #define case_DBG_SEL(__sel) \ 3263 case RTW89_DBG_PORT_SEL_##__sel: \ 3264 p += scnprintf(p, end - p, "Dump debug port " #__sel ":\n"); \ 3265 break 3266 3267 switch (sel) { 3268 case_DBG_SEL(PTCL_C0); 3269 case_DBG_SEL(PTCL_C1); 3270 case_DBG_SEL(SCH_C0); 3271 case_DBG_SEL(SCH_C1); 3272 case_DBG_SEL(TMAC_C0); 3273 case_DBG_SEL(TMAC_C1); 3274 case_DBG_SEL(RMAC_C0); 3275 case_DBG_SEL(RMAC_C1); 3276 case_DBG_SEL(RMACST_C0); 3277 case_DBG_SEL(RMACST_C1); 3278 case_DBG_SEL(TRXPTCL_C0); 3279 case_DBG_SEL(TRXPTCL_C1); 3280 case_DBG_SEL(TX_INFOL_C0); 3281 case_DBG_SEL(TX_INFOH_C0); 3282 case_DBG_SEL(TX_INFOL_C1); 3283 case_DBG_SEL(TX_INFOH_C1); 3284 case_DBG_SEL(TXTF_INFOL_C0); 3285 case_DBG_SEL(TXTF_INFOH_C0); 3286 case_DBG_SEL(TXTF_INFOL_C1); 3287 case_DBG_SEL(TXTF_INFOH_C1); 3288 case_DBG_SEL(WDE_BUFMGN_FREEPG); 3289 case_DBG_SEL(WDE_BUFMGN_QUOTA); 3290 case_DBG_SEL(WDE_BUFMGN_PAGELLT); 3291 case_DBG_SEL(WDE_BUFMGN_PKTINFO); 3292 case_DBG_SEL(WDE_QUEMGN_PREPKT); 3293 case_DBG_SEL(WDE_QUEMGN_NXTPKT); 3294 case_DBG_SEL(WDE_QUEMGN_QLNKTBL); 3295 case_DBG_SEL(WDE_QUEMGN_QEMPTY); 3296 case_DBG_SEL(PLE_BUFMGN_FREEPG); 3297 case_DBG_SEL(PLE_BUFMGN_QUOTA); 3298 case_DBG_SEL(PLE_BUFMGN_PAGELLT); 3299 case_DBG_SEL(PLE_BUFMGN_PKTINFO); 3300 case_DBG_SEL(PLE_QUEMGN_PREPKT); 3301 case_DBG_SEL(PLE_QUEMGN_NXTPKT); 3302 case_DBG_SEL(PLE_QUEMGN_QLNKTBL); 3303 case_DBG_SEL(PLE_QUEMGN_QEMPTY); 3304 case_DBG_SEL(PKTINFO); 3305 case_DBG_SEL(DSPT_HDT_TX0); 3306 case_DBG_SEL(DSPT_HDT_TX1); 3307 case_DBG_SEL(DSPT_HDT_TX2); 3308 case_DBG_SEL(DSPT_HDT_TX3); 3309 case_DBG_SEL(DSPT_HDT_TX4); 3310 case_DBG_SEL(DSPT_HDT_TX5); 3311 case_DBG_SEL(DSPT_HDT_TX6); 3312 case_DBG_SEL(DSPT_HDT_TX7); 3313 case_DBG_SEL(DSPT_HDT_TX8); 3314 case_DBG_SEL(DSPT_HDT_TX9); 3315 case_DBG_SEL(DSPT_HDT_TXA); 3316 case_DBG_SEL(DSPT_HDT_TXB); 3317 case_DBG_SEL(DSPT_HDT_TXC); 3318 case_DBG_SEL(DSPT_HDT_TXD); 3319 case_DBG_SEL(DSPT_HDT_TXE); 3320 case_DBG_SEL(DSPT_HDT_TXF); 3321 case_DBG_SEL(DSPT_CDT_TX0); 3322 case_DBG_SEL(DSPT_CDT_TX1); 3323 case_DBG_SEL(DSPT_CDT_TX3); 3324 case_DBG_SEL(DSPT_CDT_TX4); 3325 case_DBG_SEL(DSPT_CDT_TX5); 3326 case_DBG_SEL(DSPT_CDT_TX6); 3327 case_DBG_SEL(DSPT_CDT_TX7); 3328 case_DBG_SEL(DSPT_CDT_TX8); 3329 case_DBG_SEL(DSPT_CDT_TX9); 3330 case_DBG_SEL(DSPT_CDT_TXA); 3331 case_DBG_SEL(DSPT_CDT_TXB); 3332 case_DBG_SEL(DSPT_CDT_TXC); 3333 case_DBG_SEL(DSPT_HDT_RX0); 3334 case_DBG_SEL(DSPT_HDT_RX1); 3335 case_DBG_SEL(DSPT_HDT_RX2); 3336 case_DBG_SEL(DSPT_HDT_RX3); 3337 case_DBG_SEL(DSPT_HDT_RX4); 3338 case_DBG_SEL(DSPT_HDT_RX5); 3339 case_DBG_SEL(DSPT_CDT_RX_P0); 3340 case_DBG_SEL(DSPT_CDT_RX_P0_0); 3341 case_DBG_SEL(DSPT_CDT_RX_P0_1); 3342 case_DBG_SEL(DSPT_CDT_RX_P0_2); 3343 case_DBG_SEL(DSPT_CDT_RX_P1); 3344 case_DBG_SEL(DSPT_STF_CTRL); 3345 case_DBG_SEL(DSPT_ADDR_CTRL); 3346 case_DBG_SEL(DSPT_WDE_INTF); 3347 case_DBG_SEL(DSPT_PLE_INTF); 3348 case_DBG_SEL(DSPT_FLOW_CTRL); 3349 case_DBG_SEL(PCIE_TXDMA); 3350 case_DBG_SEL(PCIE_RXDMA); 3351 case_DBG_SEL(PCIE_CVT); 3352 case_DBG_SEL(PCIE_CXPL); 3353 case_DBG_SEL(PCIE_IO); 3354 case_DBG_SEL(PCIE_MISC); 3355 case_DBG_SEL(PCIE_MISC2); 3356 } 3357 3358 #undef case_DBG_SEL 3359 3360 p += scnprintf(p, end - p, "Sel addr = 0x%X\n", info->sel_addr); 3361 p += scnprintf(p, end - p, "Read addr = 0x%X\n", info->rd_addr); 3362 3363 for (i = info->srt; i <= info->end; i++) { 3364 switch (info->sel_byte) { 3365 case 1: 3366 default: 3367 rtw89_write8_mask(rtwdev, info->sel_addr, 3368 info->sel_msk, i); 3369 p += scnprintf(p, end - p, "0x%02X: ", i); 3370 break; 3371 case 2: 3372 rtw89_write16_mask(rtwdev, info->sel_addr, 3373 info->sel_msk, i); 3374 p += scnprintf(p, end - p, "0x%04X: ", i); 3375 break; 3376 case 4: 3377 rtw89_write32_mask(rtwdev, info->sel_addr, 3378 info->sel_msk, i); 3379 p += scnprintf(p, end - p, "0x%04X: ", i); 3380 break; 3381 } 3382 3383 udelay(10); 3384 3385 switch (info->rd_byte) { 3386 case 1: 3387 default: 3388 val8 = rtw89_read8_mask(rtwdev, 3389 info->rd_addr, info->rd_msk); 3390 p += scnprintf(p, end - p, "0x%02X\n", val8); 3391 break; 3392 case 2: 3393 val16 = rtw89_read16_mask(rtwdev, 3394 info->rd_addr, info->rd_msk); 3395 p += scnprintf(p, end - p, "0x%04X\n", val16); 3396 break; 3397 case 4: 3398 val32 = rtw89_read32_mask(rtwdev, 3399 info->rd_addr, info->rd_msk); 3400 p += scnprintf(p, end - p, "0x%08X\n", val32); 3401 break; 3402 } 3403 } 3404 3405 out: 3406 return p - buf; 3407 } 3408 3409 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, 3410 char *buf, size_t bufsz) 3411 { 3412 char *p = buf, *end = buf + bufsz; 3413 ssize_t n; 3414 u32 sel; 3415 3416 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; 3417 sel < RTW89_DBG_PORT_SEL_LAST; sel++) { 3418 if (!is_dbg_port_valid(rtwdev, sel)) 3419 continue; 3420 n = rtw89_debug_mac_dbg_port_dump(rtwdev, p, end - p, sel); 3421 if (n < 0) { 3422 rtw89_err(rtwdev, 3423 "failed to dump debug port %d\n", sel); 3424 break; 3425 } 3426 p += n; 3427 } 3428 3429 return p - buf; 3430 } 3431 3432 static ssize_t 3433 rtw89_debug_priv_mac_dbg_port_dump_get(struct rtw89_dev *rtwdev, 3434 struct rtw89_debugfs_priv *debugfs_priv, 3435 char *buf, size_t bufsz) 3436 { 3437 char *p = buf, *end = buf + bufsz; 3438 3439 if (debugfs_priv->dbgpkg_en.ss_dbg) 3440 p += rtw89_debug_mac_dump_ss_dbg(rtwdev, p, end - p); 3441 if (debugfs_priv->dbgpkg_en.dle_dbg) 3442 p += rtw89_debug_mac_dump_dle_dbg(rtwdev, p, end - p); 3443 if (debugfs_priv->dbgpkg_en.dmac_dbg) 3444 p += rtw89_debug_mac_dump_dmac_dbg(rtwdev, p, end - p); 3445 if (debugfs_priv->dbgpkg_en.cmac_dbg) 3446 p += rtw89_debug_mac_dump_cmac_dbg(rtwdev, p, end - p); 3447 if (debugfs_priv->dbgpkg_en.dbg_port) 3448 p += rtw89_debug_mac_dump_dbg_port(rtwdev, p, end - p); 3449 3450 return p - buf; 3451 }; 3452 3453 static u8 *rtw89_hex2bin(struct rtw89_dev *rtwdev, const char *buf, size_t count) 3454 { 3455 u8 *bin; 3456 int num; 3457 int err = 0; 3458 3459 num = count / 2; 3460 bin = kmalloc(num, GFP_KERNEL); 3461 if (!bin) { 3462 err = -EFAULT; 3463 goto out; 3464 } 3465 3466 if (hex2bin(bin, buf, num)) { 3467 rtw89_info(rtwdev, "valid format: H1H2H3...\n"); 3468 kfree(bin); 3469 err = -EINVAL; 3470 } 3471 3472 out: 3473 return err ? ERR_PTR(err) : bin; 3474 } 3475 3476 static ssize_t rtw89_debug_priv_send_h2c_set(struct rtw89_dev *rtwdev, 3477 struct rtw89_debugfs_priv *debugfs_priv, 3478 const char *buf, size_t count) 3479 { 3480 u8 *h2c; 3481 int ret; 3482 u16 h2c_len = count / 2; 3483 3484 h2c = rtw89_hex2bin(rtwdev, buf, count); 3485 if (IS_ERR(h2c)) 3486 return -EFAULT; 3487 3488 ret = rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len); 3489 3490 kfree(h2c); 3491 3492 return ret ? ret : count; 3493 } 3494 3495 static ssize_t 3496 rtw89_debug_priv_early_h2c_get(struct rtw89_dev *rtwdev, 3497 struct rtw89_debugfs_priv *debugfs_priv, 3498 char *buf, size_t bufsz) 3499 { 3500 struct rtw89_early_h2c *early_h2c; 3501 char *p = buf, *end = buf + bufsz; 3502 int seq = 0; 3503 3504 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3505 3506 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) 3507 p += scnprintf(p, end - p, "%d: %*ph\n", ++seq, 3508 early_h2c->h2c_len, early_h2c->h2c); 3509 3510 return p - buf; 3511 } 3512 3513 static ssize_t 3514 rtw89_debug_priv_early_h2c_set(struct rtw89_dev *rtwdev, 3515 struct rtw89_debugfs_priv *debugfs_priv, 3516 const char *buf, size_t count) 3517 { 3518 struct rtw89_early_h2c *early_h2c; 3519 u8 *h2c; 3520 u16 h2c_len = count / 2; 3521 3522 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3523 3524 h2c = rtw89_hex2bin(rtwdev, buf, count); 3525 if (IS_ERR(h2c)) 3526 return -EFAULT; 3527 3528 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) { 3529 kfree(h2c); 3530 rtw89_fw_free_all_early_h2c(rtwdev); 3531 goto out; 3532 } 3533 3534 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL); 3535 if (!early_h2c) { 3536 kfree(h2c); 3537 return -EFAULT; 3538 } 3539 3540 early_h2c->h2c = h2c; 3541 early_h2c->h2c_len = h2c_len; 3542 3543 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list); 3544 3545 out: 3546 return count; 3547 } 3548 3549 static int rtw89_dbg_trigger_ctrl_error(struct rtw89_dev *rtwdev) 3550 { 3551 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3552 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3553 u16 pkt_id; 3554 int ret; 3555 3556 rtw89_leave_ps_mode(rtwdev); 3557 3558 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3559 if (ret) 3560 return ret; 3561 3562 /* intentionally, enqueue two pkt, but has only one pkt id */ 3563 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3564 ctrl_para.start_pktid = pkt_id; 3565 ctrl_para.end_pktid = pkt_id; 3566 ctrl_para.pkt_num = 1; /* start from 0 */ 3567 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3568 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3569 3570 if (mac->set_cpuio(rtwdev, &ctrl_para, true)) 3571 return -EFAULT; 3572 3573 return 0; 3574 } 3575 3576 static int rtw89_dbg_trigger_mac_error_ax(struct rtw89_dev *rtwdev) 3577 { 3578 u16 val16; 3579 u8 val8; 3580 int ret; 3581 3582 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3583 if (ret) 3584 return ret; 3585 3586 val8 = rtw89_read8(rtwdev, R_AX_CMAC_FUNC_EN); 3587 rtw89_write8(rtwdev, R_AX_CMAC_FUNC_EN, val8 & ~B_AX_TMAC_EN); 3588 mdelay(1); 3589 rtw89_write8(rtwdev, R_AX_CMAC_FUNC_EN, val8); 3590 3591 val16 = rtw89_read16(rtwdev, R_AX_PTCL_IMR0); 3592 rtw89_write16(rtwdev, R_AX_PTCL_IMR0, val16 | B_AX_F2PCMD_EMPTY_ERR_INT_EN); 3593 rtw89_write16(rtwdev, R_AX_PTCL_IMR0, val16); 3594 3595 return 0; 3596 } 3597 3598 static int rtw89_dbg_trigger_mac_error_be(struct rtw89_dev *rtwdev) 3599 { 3600 int ret; 3601 3602 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3603 if (ret) 3604 return ret; 3605 3606 rtw89_write32_set(rtwdev, R_BE_CMAC_FW_TRIGGER_IDCT_ISR, 3607 B_BE_CMAC_FW_TRIG_IDCT | B_BE_CMAC_FW_ERR_IDCT_IMR); 3608 3609 return 0; 3610 } 3611 3612 static int rtw89_dbg_trigger_mac_error(struct rtw89_dev *rtwdev) 3613 { 3614 const struct rtw89_chip_info *chip = rtwdev->chip; 3615 3616 rtw89_leave_ps_mode(rtwdev); 3617 3618 switch (chip->chip_gen) { 3619 case RTW89_CHIP_AX: 3620 return rtw89_dbg_trigger_mac_error_ax(rtwdev); 3621 case RTW89_CHIP_BE: 3622 return rtw89_dbg_trigger_mac_error_be(rtwdev); 3623 default: 3624 return -EOPNOTSUPP; 3625 } 3626 } 3627 3628 static ssize_t 3629 rtw89_debug_priv_fw_crash_get(struct rtw89_dev *rtwdev, 3630 struct rtw89_debugfs_priv *debugfs_priv, 3631 char *buf, size_t bufsz) 3632 { 3633 char *p = buf, *end = buf + bufsz; 3634 3635 p += scnprintf(p, end - p, "%d\n", 3636 test_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags)); 3637 return p - buf; 3638 } 3639 3640 enum rtw89_dbg_crash_simulation_type { 3641 RTW89_DBG_SIM_CPU_EXCEPTION = 1, 3642 RTW89_DBG_SIM_CTRL_ERROR = 2, 3643 RTW89_DBG_SIM_MAC_ERROR = 3, 3644 }; 3645 3646 static ssize_t 3647 rtw89_debug_priv_fw_crash_set(struct rtw89_dev *rtwdev, 3648 struct rtw89_debugfs_priv *debugfs_priv, 3649 const char *buf, size_t count) 3650 { 3651 int (*sim)(struct rtw89_dev *rtwdev); 3652 bool announce = true; 3653 u8 crash_type; 3654 int ret; 3655 3656 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3657 3658 ret = kstrtou8(buf, 0, &crash_type); 3659 if (ret) 3660 return -EINVAL; 3661 3662 switch (crash_type) { 3663 case RTW89_DBG_SIM_CPU_EXCEPTION: 3664 if (!RTW89_CHK_FW_FEATURE_GROUP(CRASH_TRIGGER, &rtwdev->fw)) 3665 return -EOPNOTSUPP; 3666 sim = rtw89_fw_h2c_trigger_cpu_exception; 3667 break; 3668 case RTW89_DBG_SIM_CTRL_ERROR: 3669 sim = rtw89_dbg_trigger_ctrl_error; 3670 break; 3671 case RTW89_DBG_SIM_MAC_ERROR: 3672 sim = rtw89_dbg_trigger_mac_error; 3673 3674 /* Driver SER flow won't get involved; only FW will. */ 3675 announce = false; 3676 break; 3677 default: 3678 return -EINVAL; 3679 } 3680 3681 if (announce) 3682 set_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags); 3683 3684 ret = sim(rtwdev); 3685 3686 if (ret) 3687 return ret; 3688 3689 return count; 3690 } 3691 3692 static ssize_t rtw89_debug_priv_btc_info_get(struct rtw89_dev *rtwdev, 3693 struct rtw89_debugfs_priv *debugfs_priv, 3694 char *buf, size_t bufsz) 3695 { 3696 return rtw89_btc_dump_info(rtwdev, buf, bufsz); 3697 } 3698 3699 static ssize_t rtw89_debug_priv_btc_manual_set(struct rtw89_dev *rtwdev, 3700 struct rtw89_debugfs_priv *debugfs_priv, 3701 const char *buf, size_t count) 3702 { 3703 struct rtw89_btc *btc = &rtwdev->btc; 3704 const struct rtw89_btc_ver *ver = btc->ver; 3705 int ret; 3706 3707 ret = kstrtobool(buf, &btc->manual_ctrl); 3708 if (ret) 3709 return ret; 3710 3711 if (ver->fcxctrl == 7) 3712 btc->ctrl.ctrl_v7.manual = btc->manual_ctrl; 3713 else 3714 btc->ctrl.ctrl.manual = btc->manual_ctrl; 3715 3716 return count; 3717 } 3718 3719 static ssize_t rtw89_debug_priv_fw_log_manual_set(struct rtw89_dev *rtwdev, 3720 struct rtw89_debugfs_priv *debugfs_priv, 3721 const char *buf, size_t count) 3722 { 3723 struct rtw89_fw_log *log = &rtwdev->fw.log; 3724 bool fw_log_manual; 3725 3726 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3727 3728 if (kstrtobool(buf, &fw_log_manual)) 3729 goto out; 3730 3731 log->enable = fw_log_manual; 3732 if (log->enable) 3733 rtw89_fw_log_prepare(rtwdev); 3734 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); 3735 out: 3736 return count; 3737 } 3738 3739 static int rtw89_sta_link_info_get_iter(struct rtw89_dev *rtwdev, 3740 char *buf, size_t bufsz, 3741 struct rtw89_sta_link *rtwsta_link) 3742 { 3743 static const char * const he_gi_str[] = { 3744 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", 3745 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", 3746 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", 3747 }; 3748 static const char * const eht_gi_str[] = { 3749 [NL80211_RATE_INFO_EHT_GI_0_8] = "0.8", 3750 [NL80211_RATE_INFO_EHT_GI_1_6] = "1.6", 3751 [NL80211_RATE_INFO_EHT_GI_3_2] = "3.2", 3752 }; 3753 struct rate_info *rate = &rtwsta_link->ra_report.txrate; 3754 struct ieee80211_rx_status *status = &rtwsta_link->rx_status; 3755 struct rtw89_hal *hal = &rtwdev->hal; 3756 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3757 bool ant_asterisk = hal->tx_path_diversity || hal->ant_diversity; 3758 struct ieee80211_link_sta *link_sta; 3759 char *p = buf, *end = buf + bufsz; 3760 u8 evm_min, evm_max, evm_1ss; 3761 u16 max_rc_amsdu_len; 3762 u8 rssi; 3763 u8 snr; 3764 int i; 3765 3766 rcu_read_lock(); 3767 3768 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 3769 max_rc_amsdu_len = link_sta->agg.max_rc_amsdu_len; 3770 3771 rcu_read_unlock(); 3772 3773 p += scnprintf(p, end - p, "TX rate [%u, %u]: ", rtwsta_link->mac_id, 3774 rtwsta_link->link_id); 3775 3776 if (rate->flags & RATE_INFO_FLAGS_MCS) 3777 p += scnprintf(p, end - p, "HT MCS-%d%s", rate->mcs, 3778 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3779 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) 3780 p += scnprintf(p, end - p, "VHT %dSS MCS-%d%s", rate->nss, 3781 rate->mcs, 3782 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3783 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) 3784 p += scnprintf(p, end - p, "HE %dSS MCS-%d GI:%s", rate->nss, 3785 rate->mcs, 3786 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3787 he_gi_str[rate->he_gi] : "N/A"); 3788 else if (rate->flags & RATE_INFO_FLAGS_EHT_MCS) 3789 p += scnprintf(p, end - p, "EHT %dSS MCS-%d GI:%s", rate->nss, 3790 rate->mcs, 3791 rate->eht_gi < ARRAY_SIZE(eht_gi_str) ? 3792 eht_gi_str[rate->eht_gi] : "N/A"); 3793 else 3794 p += scnprintf(p, end - p, "Legacy %d", rate->legacy); 3795 p += scnprintf(p, end - p, "%s", 3796 rtwsta_link->ra_report.might_fallback_legacy ? " FB_G" : ""); 3797 p += scnprintf(p, end - p, " BW:%u", 3798 rtw89_rate_info_bw_to_mhz(rate->bw)); 3799 p += scnprintf(p, end - p, " (hw_rate=0x%x)", 3800 rtwsta_link->ra_report.hw_rate); 3801 p += scnprintf(p, end - p, " ==> agg_wait=%d (%d)\n", 3802 rtwsta_link->max_agg_wait, 3803 max_rc_amsdu_len); 3804 3805 p += scnprintf(p, end - p, "RX rate [%u, %u]: ", rtwsta_link->mac_id, 3806 rtwsta_link->link_id); 3807 3808 switch (status->encoding) { 3809 case RX_ENC_LEGACY: 3810 p += scnprintf(p, end - p, "Legacy %d", status->rate_idx + 3811 (status->band != NL80211_BAND_2GHZ ? 4 : 0)); 3812 break; 3813 case RX_ENC_HT: 3814 p += scnprintf(p, end - p, "HT MCS-%d%s", status->rate_idx, 3815 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3816 break; 3817 case RX_ENC_VHT: 3818 p += scnprintf(p, end - p, "VHT %dSS MCS-%d%s", status->nss, 3819 status->rate_idx, 3820 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3821 break; 3822 case RX_ENC_HE: 3823 p += scnprintf(p, end - p, "HE %dSS MCS-%d GI:%s", 3824 status->nss, status->rate_idx, 3825 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3826 he_gi_str[status->he_gi] : "N/A"); 3827 break; 3828 case RX_ENC_EHT: 3829 p += scnprintf(p, end - p, "EHT %dSS MCS-%d GI:%s", 3830 status->nss, status->rate_idx, 3831 status->eht.gi < ARRAY_SIZE(eht_gi_str) ? 3832 eht_gi_str[status->eht.gi] : "N/A"); 3833 break; 3834 } 3835 p += scnprintf(p, end - p, " BW:%u", 3836 rtw89_rate_info_bw_to_mhz(status->bw)); 3837 p += scnprintf(p, end - p, " (hw_rate=0x%x)\n", 3838 rtwsta_link->rx_hw_rate); 3839 3840 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi); 3841 p += scnprintf(p, end - p, "RSSI: %d dBm (raw=%d, prev=%d) [", 3842 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, 3843 rtwsta_link->prev_rssi); 3844 for (i = 0; i < ant_num; i++) { 3845 rssi = ewma_rssi_read(&rtwsta_link->rssi[i]); 3846 p += scnprintf(p, end - p, "%d%s%s", 3847 RTW89_RSSI_RAW_TO_DBM(rssi), 3848 ant_asterisk && (hal->antenna_tx & BIT(i)) ? "*" : "", 3849 i + 1 == ant_num ? "" : ", "); 3850 } 3851 p += scnprintf(p, end - p, "]\n"); 3852 3853 evm_1ss = ewma_evm_read(&rtwsta_link->evm_1ss); 3854 p += scnprintf(p, end - p, "EVM: [%2u.%02u, ", evm_1ss >> 2, 3855 (evm_1ss & 0x3) * 25); 3856 for (i = 0; i < (hal->ant_diversity ? 2 : 1); i++) { 3857 evm_min = ewma_evm_read(&rtwsta_link->evm_min[i]); 3858 evm_max = ewma_evm_read(&rtwsta_link->evm_max[i]); 3859 3860 p += scnprintf(p, end - p, "%s(%2u.%02u, %2u.%02u)", 3861 i == 0 ? "" : " ", 3862 evm_min >> 2, (evm_min & 0x3) * 25, 3863 evm_max >> 2, (evm_max & 0x3) * 25); 3864 } 3865 p += scnprintf(p, end - p, "]\t"); 3866 3867 snr = ewma_snr_read(&rtwsta_link->avg_snr); 3868 p += scnprintf(p, end - p, "SNR: %u\n", snr); 3869 3870 return p - buf; 3871 } 3872 3873 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) 3874 { 3875 struct rtw89_debugfs_iter_data *iter_data = 3876 (struct rtw89_debugfs_iter_data *)data; 3877 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3878 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3879 struct rtw89_sta_link *rtwsta_link; 3880 size_t bufsz = iter_data->bufsz; 3881 char *buf = iter_data->buf; 3882 char *p = buf, *end = buf + bufsz; 3883 unsigned int link_id; 3884 3885 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 3886 p += rtw89_sta_link_info_get_iter(rtwdev, p, end - p, rtwsta_link); 3887 3888 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf); 3889 } 3890 3891 static int 3892 rtw89_debug_append_rx_rate(char *buf, size_t bufsz, struct rtw89_pkt_stat *pkt_stat, 3893 enum rtw89_hw_rate first_rate, int len) 3894 { 3895 char *p = buf, *end = buf + bufsz; 3896 int i; 3897 3898 for (i = 0; i < len; i++) 3899 p += scnprintf(p, end - p, "%s%u", i == 0 ? "" : ", ", 3900 pkt_stat->rx_rate_cnt[first_rate + i]); 3901 3902 return p - buf; 3903 } 3904 3905 #define FIRST_RATE_SAME(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_ ## rate} 3906 #define FIRST_RATE_ENUM(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_V1_ ## rate} 3907 #define FIRST_RATE_GEV1(rate) {RTW89_HW_RATE_INVAL, RTW89_HW_RATE_V1_ ## rate} 3908 3909 static const struct rtw89_rx_rate_cnt_info { 3910 enum rtw89_hw_rate first_rate[RTW89_CHIP_GEN_NUM]; 3911 int len; 3912 int ext; 3913 const char *rate_mode; 3914 } rtw89_rx_rate_cnt_infos[] = { 3915 {FIRST_RATE_SAME(CCK1), 4, 0, "Legacy:"}, 3916 {FIRST_RATE_SAME(OFDM6), 8, 0, "OFDM:"}, 3917 {FIRST_RATE_ENUM(MCS0), 8, 0, "HT 0:"}, 3918 {FIRST_RATE_ENUM(MCS8), 8, 0, "HT 1:"}, 3919 {FIRST_RATE_ENUM(VHT_NSS1_MCS0), 10, 2, "VHT 1SS:"}, 3920 {FIRST_RATE_ENUM(VHT_NSS2_MCS0), 10, 2, "VHT 2SS:"}, 3921 {FIRST_RATE_ENUM(HE_NSS1_MCS0), 12, 0, "HE 1SS:"}, 3922 {FIRST_RATE_ENUM(HE_NSS2_MCS0), 12, 0, "HE 2SS:"}, 3923 {FIRST_RATE_GEV1(EHT_NSS1_MCS0), 14, 2, "EHT 1SS:"}, 3924 {FIRST_RATE_GEV1(EHT_NSS2_MCS0), 14, 0, "EHT 2SS:"}, 3925 }; 3926 3927 static ssize_t rtw89_debug_priv_phy_info_get(struct rtw89_dev *rtwdev, 3928 struct rtw89_debugfs_priv *debugfs_priv, 3929 char *buf, size_t bufsz) 3930 { 3931 struct rtw89_traffic_stats *stats = &rtwdev->stats; 3932 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 3933 const struct rtw89_chip_info *chip = rtwdev->chip; 3934 struct rtw89_debugfs_iter_data iter_data; 3935 const struct rtw89_rx_rate_cnt_info *info; 3936 struct rtw89_hal *hal = &rtwdev->hal; 3937 char *p = buf, *end = buf + bufsz; 3938 enum rtw89_hw_rate first_rate; 3939 u8 rssi; 3940 int i; 3941 3942 rssi = ewma_rssi_read(&rtwdev->phystat.bcn_rssi); 3943 3944 p += scnprintf(p, end - p, "TP TX: %u [%u] Mbps (lv: %d", 3945 stats->tx_throughput, stats->tx_throughput_raw, 3946 stats->tx_tfc_lv); 3947 if (hal->thermal_prot_lv) 3948 p += scnprintf(p, end - p, ", duty: %d%%", 3949 100 - hal->thermal_prot_lv * RTW89_THERMAL_PROT_STEP); 3950 p += scnprintf(p, end - p, "), RX: %u [%u] Mbps (lv: %d)\n", 3951 stats->rx_throughput, stats->rx_throughput_raw, 3952 stats->rx_tfc_lv); 3953 p += scnprintf(p, end - p, "Beacon: %u (%d dBm), TF: %u\n", 3954 pkt_stat->beacon_nr, 3955 RTW89_RSSI_RAW_TO_DBM(rssi), stats->rx_tf_periodic); 3956 p += scnprintf(p, end - p, "Avg packet length: TX=%u, RX=%u\n", 3957 stats->tx_avg_len, 3958 stats->rx_avg_len); 3959 3960 p += scnprintf(p, end - p, "RX count:\n"); 3961 3962 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { 3963 info = &rtw89_rx_rate_cnt_infos[i]; 3964 first_rate = info->first_rate[chip->chip_gen]; 3965 if (first_rate >= RTW89_HW_RATE_NR) 3966 continue; 3967 3968 p += scnprintf(p, end - p, "%10s [", info->rate_mode); 3969 p += rtw89_debug_append_rx_rate(p, end - p, pkt_stat, 3970 first_rate, info->len); 3971 if (info->ext) { 3972 p += scnprintf(p, end - p, "]["); 3973 p += rtw89_debug_append_rx_rate(p, end - p, pkt_stat, 3974 first_rate + info->len, info->ext); 3975 } 3976 p += scnprintf(p, end - p, "]\n"); 3977 } 3978 3979 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 3980 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, &iter_data); 3981 p += iter_data.written_sz; 3982 3983 return p - buf; 3984 } 3985 3986 static int rtw89_dump_addr_cam(struct rtw89_dev *rtwdev, 3987 char *buf, size_t bufsz, 3988 struct rtw89_addr_cam_entry *addr_cam) 3989 { 3990 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3991 const struct rtw89_sec_cam_entry *sec_entry; 3992 char *p = buf, *end = buf + bufsz; 3993 u8 sec_cam_idx; 3994 int i; 3995 3996 p += scnprintf(p, end - p, "\taddr_cam_idx=%u\n", 3997 addr_cam->addr_cam_idx); 3998 p += scnprintf(p, end - p, "\t-> bssid_cam_idx=%u\n", 3999 addr_cam->bssid_cam_idx); 4000 p += scnprintf(p, end - p, "\tsec_cam_bitmap=%*ph\n", 4001 (int)sizeof(addr_cam->sec_cam_map), 4002 addr_cam->sec_cam_map); 4003 for_each_set_bit(i, addr_cam->sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM) { 4004 sec_cam_idx = addr_cam->sec_ent[i]; 4005 sec_entry = cam_info->sec_entries[sec_cam_idx]; 4006 if (!sec_entry) 4007 continue; 4008 p += scnprintf(p, end - p, "\tsec[%d]: sec_cam_idx %u", i, 4009 sec_entry->sec_cam_idx); 4010 if (sec_entry->ext_key) 4011 p += scnprintf(p, end - p, ", %u", 4012 sec_entry->sec_cam_idx + 1); 4013 p += scnprintf(p, end - p, "\n"); 4014 } 4015 4016 return p - buf; 4017 } 4018 4019 __printf(4, 5) 4020 static int rtw89_dump_pkt_offload(char *buf, size_t bufsz, struct list_head *pkt_list, 4021 const char *fmt, ...) 4022 { 4023 char *p = buf, *end = buf + bufsz; 4024 struct rtw89_pktofld_info *info; 4025 struct va_format vaf; 4026 va_list args; 4027 4028 if (list_empty(pkt_list)) 4029 return 0; 4030 4031 va_start(args, fmt); 4032 vaf.va = &args; 4033 vaf.fmt = fmt; 4034 4035 p += scnprintf(p, end - p, "%pV", &vaf); 4036 4037 va_end(args); 4038 4039 list_for_each_entry(info, pkt_list, list) 4040 p += scnprintf(p, end - p, "%d ", info->id); 4041 4042 p += scnprintf(p, end - p, "\n"); 4043 4044 return p - buf; 4045 } 4046 4047 static int rtw89_vif_link_ids_get(struct rtw89_dev *rtwdev, 4048 char *buf, size_t bufsz, u8 *mac, 4049 struct rtw89_vif_link *rtwvif_link, 4050 bool designated) 4051 { 4052 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif_link->bssid_cam; 4053 char *p = buf, *end = buf + bufsz; 4054 4055 p += scnprintf(p, end - p, " [%u] %pM\n", rtwvif_link->mac_id, 4056 rtwvif_link->mac_addr); 4057 p += scnprintf(p, end - p, "\tlink_id=%u%s\n", rtwvif_link->link_id, 4058 designated ? " (*)" : ""); 4059 p += scnprintf(p, end - p, "\tbssid_cam_idx=%u\n", 4060 bssid_cam->bssid_cam_idx); 4061 p += rtw89_dump_addr_cam(rtwdev, p, end - p, &rtwvif_link->addr_cam); 4062 p += rtw89_dump_pkt_offload(p, end - p, &rtwvif_link->general_pkt_list, 4063 "\tpkt_ofld[GENERAL]: "); 4064 4065 return p - buf; 4066 } 4067 4068 static 4069 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 4070 { 4071 struct rtw89_debugfs_iter_data *iter_data = 4072 (struct rtw89_debugfs_iter_data *)data; 4073 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 4074 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 4075 struct rtw89_vif_link *designated_link; 4076 struct rtw89_vif_link *rtwvif_link; 4077 size_t bufsz = iter_data->bufsz; 4078 char *buf = iter_data->buf; 4079 char *p = buf, *end = buf + bufsz; 4080 unsigned int link_id; 4081 4082 designated_link = rtw89_get_designated_link(rtwvif); 4083 4084 p += scnprintf(p, end - p, "VIF %pM\n", rtwvif->mac_addr); 4085 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4086 p += rtw89_vif_link_ids_get(rtwdev, p, end - p, mac, rtwvif_link, 4087 rtwvif_link == designated_link); 4088 4089 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf); 4090 } 4091 4092 static int rtw89_dump_ba_cam(struct rtw89_dev *rtwdev, 4093 char *buf, size_t bufsz, 4094 struct rtw89_sta_link *rtwsta_link) 4095 { 4096 struct rtw89_ba_cam_entry *entry; 4097 char *p = buf, *end = buf + bufsz; 4098 bool first = true; 4099 4100 list_for_each_entry(entry, &rtwsta_link->ba_cam_list, list) { 4101 if (first) { 4102 p += scnprintf(p, end - p, "\tba_cam "); 4103 first = false; 4104 } else { 4105 p += scnprintf(p, end - p, ", "); 4106 } 4107 p += scnprintf(p, end - p, "tid[%u]=%d", entry->tid, 4108 (int)(entry - rtwdev->cam_info.ba_cam_entry)); 4109 } 4110 p += scnprintf(p, end - p, "\n"); 4111 4112 return p - buf; 4113 } 4114 4115 static int rtw89_sta_link_ids_get(struct rtw89_dev *rtwdev, 4116 char *buf, size_t bufsz, 4117 struct rtw89_sta_link *rtwsta_link, 4118 bool designated) 4119 { 4120 struct ieee80211_link_sta *link_sta; 4121 char *p = buf, *end = buf + bufsz; 4122 4123 rcu_read_lock(); 4124 4125 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 4126 4127 p += scnprintf(p, end - p, " [%u] %pM\n", rtwsta_link->mac_id, 4128 link_sta->addr); 4129 4130 rcu_read_unlock(); 4131 4132 p += scnprintf(p, end - p, "\tlink_id=%u%s\n", rtwsta_link->link_id, 4133 designated ? " (*)" : ""); 4134 p += rtw89_dump_addr_cam(rtwdev, p, end - p, &rtwsta_link->addr_cam); 4135 p += rtw89_dump_ba_cam(rtwdev, p, end - p, rtwsta_link); 4136 4137 return p - buf; 4138 } 4139 4140 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta) 4141 { 4142 struct rtw89_debugfs_iter_data *iter_data = 4143 (struct rtw89_debugfs_iter_data *)data; 4144 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 4145 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 4146 struct rtw89_sta_link *designated_link; 4147 struct rtw89_sta_link *rtwsta_link; 4148 size_t bufsz = iter_data->bufsz; 4149 char *buf = iter_data->buf; 4150 char *p = buf, *end = buf + bufsz; 4151 unsigned int link_id; 4152 4153 designated_link = rtw89_get_designated_link(rtwsta); 4154 4155 p += scnprintf(p, end - p, "STA %pM %s\n", sta->addr, 4156 sta->tdls ? "(TDLS)" : ""); 4157 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 4158 p += rtw89_sta_link_ids_get(rtwdev, p, end - p, rtwsta_link, 4159 rtwsta_link == designated_link); 4160 4161 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf); 4162 } 4163 4164 static ssize_t rtw89_debug_priv_stations_get(struct rtw89_dev *rtwdev, 4165 struct rtw89_debugfs_priv *debugfs_priv, 4166 char *buf, size_t bufsz) 4167 { 4168 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 4169 struct rtw89_debugfs_iter_data iter_data; 4170 char *p = buf, *end = buf + bufsz; 4171 u8 idx; 4172 4173 lockdep_assert_wiphy(rtwdev->hw->wiphy); 4174 4175 p += scnprintf(p, end - p, "map:\n"); 4176 p += scnprintf(p, end - p, "\tmac_id: %*ph\n", 4177 (int)sizeof(rtwdev->mac_id_map), 4178 rtwdev->mac_id_map); 4179 p += scnprintf(p, end - p, "\taddr_cam: %*ph\n", 4180 (int)sizeof(cam_info->addr_cam_map), 4181 cam_info->addr_cam_map); 4182 p += scnprintf(p, end - p, "\tbssid_cam: %*ph\n", 4183 (int)sizeof(cam_info->bssid_cam_map), 4184 cam_info->bssid_cam_map); 4185 p += scnprintf(p, end - p, "\tsec_cam: %*ph\n", 4186 (int)sizeof(cam_info->sec_cam_map), 4187 cam_info->sec_cam_map); 4188 p += scnprintf(p, end - p, "\tba_cam: %*ph\n", 4189 (int)sizeof(cam_info->ba_cam_map), 4190 cam_info->ba_cam_map); 4191 p += scnprintf(p, end - p, "\tpkt_ofld: %*ph\n", 4192 (int)sizeof(rtwdev->pkt_offload), 4193 rtwdev->pkt_offload); 4194 4195 for (idx = NL80211_BAND_2GHZ; idx < NUM_NL80211_BANDS; idx++) { 4196 if (!(rtwdev->chip->support_bands & BIT(idx))) 4197 continue; 4198 p += rtw89_dump_pkt_offload(p, end - p, &rtwdev->scan_info.pkt_list[idx], 4199 "\t\t[SCAN %u]: ", idx); 4200 } 4201 4202 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 4203 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw, 4204 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, &iter_data); 4205 p += iter_data.written_sz; 4206 4207 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 4208 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, &iter_data); 4209 p += iter_data.written_sz; 4210 4211 return p - buf; 4212 } 4213 4214 static void rtw89_debug_disable_dm_cfg_bmap(struct rtw89_dev *rtwdev, u32 new) 4215 { 4216 struct rtw89_hal *hal = &rtwdev->hal; 4217 u32 old = hal->disabled_dm_bitmap; 4218 4219 if (new == old) 4220 return; 4221 4222 hal->disabled_dm_bitmap = new; 4223 4224 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Disable DM: 0x%x -> 0x%x\n", old, new); 4225 } 4226 4227 static void rtw89_debug_disable_dm_set_flag(struct rtw89_dev *rtwdev, u8 flag) 4228 { 4229 struct rtw89_hal *hal = &rtwdev->hal; 4230 u32 cur = hal->disabled_dm_bitmap; 4231 4232 rtw89_debug_disable_dm_cfg_bmap(rtwdev, cur | BIT(flag)); 4233 } 4234 4235 static void rtw89_debug_disable_dm_clr_flag(struct rtw89_dev *rtwdev, u8 flag) 4236 { 4237 struct rtw89_hal *hal = &rtwdev->hal; 4238 u32 cur = hal->disabled_dm_bitmap; 4239 4240 rtw89_debug_disable_dm_cfg_bmap(rtwdev, cur & ~BIT(flag)); 4241 } 4242 4243 #define DM_INFO(type) {RTW89_DM_ ## type, #type} 4244 4245 static const struct rtw89_disabled_dm_info { 4246 enum rtw89_dm_type type; 4247 const char *name; 4248 } rtw89_disabled_dm_infos[] = { 4249 DM_INFO(DYNAMIC_EDCCA), 4250 DM_INFO(THERMAL_PROTECT), 4251 DM_INFO(TAS), 4252 DM_INFO(MLO), 4253 }; 4254 4255 static ssize_t 4256 rtw89_debug_priv_disable_dm_get(struct rtw89_dev *rtwdev, 4257 struct rtw89_debugfs_priv *debugfs_priv, 4258 char *buf, size_t bufsz) 4259 { 4260 const struct rtw89_disabled_dm_info *info; 4261 struct rtw89_hal *hal = &rtwdev->hal; 4262 char *p = buf, *end = buf + bufsz; 4263 u32 disabled; 4264 int i; 4265 4266 p += scnprintf(p, end - p, "Disabled DM: 0x%x\n", 4267 hal->disabled_dm_bitmap); 4268 4269 for (i = 0; i < ARRAY_SIZE(rtw89_disabled_dm_infos); i++) { 4270 info = &rtw89_disabled_dm_infos[i]; 4271 disabled = BIT(info->type) & hal->disabled_dm_bitmap; 4272 4273 p += scnprintf(p, end - p, "[%d] %s: %c\n", info->type, 4274 info->name, 4275 disabled ? 'X' : 'O'); 4276 } 4277 4278 return p - buf; 4279 } 4280 4281 static ssize_t 4282 rtw89_debug_priv_disable_dm_set(struct rtw89_dev *rtwdev, 4283 struct rtw89_debugfs_priv *debugfs_priv, 4284 const char *buf, size_t count) 4285 { 4286 u32 conf; 4287 int ret; 4288 4289 ret = kstrtou32(buf, 0, &conf); 4290 if (ret) 4291 return -EINVAL; 4292 4293 rtw89_debug_disable_dm_cfg_bmap(rtwdev, conf); 4294 4295 return count; 4296 } 4297 4298 static void rtw89_debug_mlo_mode_set_mlsr(struct rtw89_dev *rtwdev, 4299 unsigned int link_id) 4300 { 4301 struct ieee80211_vif *vif; 4302 struct rtw89_vif *rtwvif; 4303 4304 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4305 vif = rtwvif_to_vif(rtwvif); 4306 if (!ieee80211_vif_is_mld(vif)) 4307 continue; 4308 4309 rtw89_core_mlsr_switch(rtwdev, rtwvif, link_id); 4310 } 4311 } 4312 4313 static ssize_t 4314 rtw89_debug_priv_mlo_mode_get(struct rtw89_dev *rtwdev, 4315 struct rtw89_debugfs_priv *debugfs_priv, 4316 char *buf, size_t bufsz) 4317 { 4318 bool mlo_dm_dis = rtwdev->hal.disabled_dm_bitmap & BIT(RTW89_DM_MLO); 4319 char *p = buf, *end = buf + bufsz; 4320 struct ieee80211_vif *vif; 4321 struct rtw89_vif *rtwvif; 4322 int count = 0; 4323 4324 p += scnprintf(p, end - p, "MLD(s) status: (MLO DM: %s)\n", 4325 str_disable_enable(mlo_dm_dis)); 4326 4327 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4328 vif = rtwvif_to_vif(rtwvif); 4329 if (!ieee80211_vif_is_mld(vif)) 4330 continue; 4331 4332 p += scnprintf(p, end - p, 4333 "\t#%u: MLO mode %x, valid 0x%x, active 0x%x\n", 4334 count++, rtwvif->mlo_mode, vif->valid_links, 4335 vif->active_links); 4336 } 4337 4338 if (count == 0) 4339 p += scnprintf(p, end - p, "\t(None)\n"); 4340 4341 return p - buf; 4342 } 4343 4344 static ssize_t 4345 rtw89_debug_priv_mlo_mode_set(struct rtw89_dev *rtwdev, 4346 struct rtw89_debugfs_priv *debugfs_priv, 4347 const char *buf, size_t count) 4348 { 4349 u8 num, mlo_mode; 4350 u32 argv; 4351 4352 num = sscanf(buf, "%hhx %u", &mlo_mode, &argv); 4353 if (num != 2) 4354 return -EINVAL; 4355 4356 rtw89_debug_disable_dm_set_flag(rtwdev, RTW89_DM_MLO); 4357 4358 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Set MLO mode to %x\n", mlo_mode); 4359 4360 switch (mlo_mode) { 4361 case RTW89_MLO_MODE_MLSR: 4362 rtw89_debug_mlo_mode_set_mlsr(rtwdev, argv); 4363 break; 4364 default: 4365 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Unsupported MLO mode\n"); 4366 rtw89_debug_disable_dm_clr_flag(rtwdev, RTW89_DM_MLO); 4367 4368 return -EOPNOTSUPP; 4369 } 4370 4371 return count; 4372 } 4373 4374 enum __diag_mac_cmd { 4375 __CMD_EQUALV, 4376 __CMD_EQUALO, 4377 __CMD_NEQUALV, 4378 __CMD_NEQUALO, 4379 __CMD_SETEQUALV, 4380 __CMD_SETEQUALO, 4381 __CMD_CMPWCR, 4382 __CMD_CMPWWD, 4383 __CMD_NEQ_CMPWCR, 4384 __CMD_NEQ_CMPWWD, 4385 __CMD_INCREMENT, 4386 __CMD_MESSAGE, 4387 }; 4388 4389 enum __diag_mac_io { 4390 __IO_NORMAL, 4391 __IO_NORMAL_PCIE, 4392 __IO_NORMAL_USB, 4393 __IO_NORMAL_SDIO, 4394 __IO_PCIE_CFG, 4395 __IO_SDIO_CCCR, 4396 }; 4397 4398 struct __diag_mac_rule_header { 4399 u8 sheet; 4400 u8 cmd; 4401 u8 seq_major; 4402 u8 seq_minor; 4403 u8 io_band; 4404 #define __DIAG_MAC_IO GENMASK(3, 0) 4405 #define __DIAG_MAC_N_BAND BIT(4) 4406 #define __DIAG_MAC_HAS_BAND BIT(5) 4407 u8 len; /* include header. Unit: 4 bytes */ 4408 u8 rsvd[2]; 4409 } __packed; 4410 4411 struct __diag_mac_rule_equal { 4412 struct __diag_mac_rule_header header; 4413 __le32 addr; 4414 __le32 addr_name_offset; 4415 __le32 mask; 4416 __le32 val; 4417 __le32 msg_offset; 4418 u8 rsvd[4]; 4419 } __packed; 4420 4421 struct __diag_mac_rule_increment { 4422 struct __diag_mac_rule_header header; 4423 __le32 addr; 4424 __le32 addr_name_offset; 4425 __le32 mask; 4426 __le16 sel; 4427 __le16 delay; 4428 __le32 msg_offset; 4429 u8 rsvd[4]; 4430 } __packed; 4431 4432 struct __diag_mac_msg_buf { 4433 __le16 len; 4434 char string[]; 4435 } __packed; 4436 4437 static ssize_t rtw89_mac_diag_do_equalv(struct rtw89_dev *rtwdev, 4438 char *buf, size_t bufsz, 4439 const struct __diag_mac_rule_equal *r, 4440 const void *msg_start, 4441 u64 *positive_bmp) 4442 { 4443 const struct __diag_mac_msg_buf *name = msg_start + 4444 le32_to_cpu(r->addr_name_offset); 4445 const struct __diag_mac_msg_buf *msg = msg_start + 4446 le32_to_cpu(r->msg_offset); 4447 bool want_eq = r->header.cmd == __CMD_EQUALV; 4448 char *p = buf, *end = buf + bufsz; 4449 bool equal = false; 4450 u32 val; 4451 4452 *positive_bmp <<= 1; 4453 4454 if (u8_get_bits(r->header.io_band, __DIAG_MAC_IO) == __IO_PCIE_CFG) 4455 val = rtw89_read32_pci_cfg(rtwdev, le32_to_cpu(r->addr)); 4456 else 4457 val = rtw89_read32(rtwdev, le32_to_cpu(r->addr)); 4458 4459 if ((val & le32_to_cpu(r->mask)) == le32_to_cpu(r->val)) 4460 equal = true; 4461 4462 if (want_eq == equal) { 4463 *positive_bmp |= BIT(0); 4464 return p - buf; 4465 } 4466 4467 p += scnprintf(p, end - p, "sheet: %d, cmd: %d, Reg: %.*s => %x, %.*s\n", 4468 r->header.sheet, r->header.cmd, le16_to_cpu(name->len), 4469 name->string, val, le16_to_cpu(msg->len), msg->string); 4470 4471 return p - buf; 4472 } 4473 4474 static ssize_t rtw89_mac_diag_do_increment(struct rtw89_dev *rtwdev, 4475 char *buf, size_t bufsz, 4476 const struct __diag_mac_rule_increment *r, 4477 const void *msg_start, 4478 u64 *positive_bmp) 4479 { 4480 const struct __diag_mac_msg_buf *name = msg_start + 4481 le32_to_cpu(r->addr_name_offset); 4482 const struct __diag_mac_msg_buf *msg = msg_start + 4483 le32_to_cpu(r->msg_offset); 4484 char *p = buf, *end = buf + bufsz; 4485 u32 addr = le32_to_cpu(r->addr); 4486 u32 mask = le32_to_cpu(r->mask); 4487 u16 sel = le16_to_cpu(r->sel); 4488 u32 val1, val2; 4489 4490 *positive_bmp <<= 1; 4491 4492 rtw89_write32(rtwdev, addr, sel); 4493 4494 if (u8_get_bits(r->header.io_band, __DIAG_MAC_IO) == __IO_PCIE_CFG) 4495 val1 = rtw89_read32_pci_cfg(rtwdev, addr); 4496 else 4497 val1 = rtw89_read32(rtwdev, addr); 4498 4499 mdelay(le16_to_cpu(r->delay)); 4500 4501 if (u8_get_bits(r->header.io_band, __DIAG_MAC_IO) == __IO_PCIE_CFG) 4502 val2 = rtw89_read32_pci_cfg(rtwdev, addr); 4503 else 4504 val2 = rtw89_read32(rtwdev, addr); 4505 4506 if ((val2 & mask) > (val1 & mask)) { 4507 *positive_bmp |= BIT(0); 4508 return p - buf; 4509 } 4510 4511 p += scnprintf(p, end - p, "sheet: %d, cmd: %d, Reg: %.*s [%d]=> %x, %.*s\n", 4512 r->header.sheet, r->header.cmd, le16_to_cpu(name->len), 4513 name->string, le16_to_cpu(r->sel), val1, 4514 le16_to_cpu(msg->len), msg->string); 4515 4516 return p - buf; 4517 } 4518 4519 static bool rtw89_mac_diag_match_hci(struct rtw89_dev *rtwdev, 4520 const struct __diag_mac_rule_header *rh) 4521 { 4522 switch (u8_get_bits(rh->io_band, __DIAG_MAC_IO)) { 4523 case __IO_NORMAL: 4524 default: 4525 return true; 4526 case __IO_NORMAL_PCIE: 4527 case __IO_PCIE_CFG: 4528 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) 4529 return true; 4530 break; 4531 case __IO_NORMAL_USB: 4532 if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) 4533 return true; 4534 break; 4535 case __IO_NORMAL_SDIO: 4536 case __IO_SDIO_CCCR: 4537 if (rtwdev->hci.type == RTW89_HCI_TYPE_SDIO) 4538 return true; 4539 break; 4540 } 4541 4542 return false; 4543 } 4544 4545 static bool rtw89_mac_diag_match_band(struct rtw89_dev *rtwdev, 4546 const struct __diag_mac_rule_header *rh) 4547 { 4548 u8 active_bands; 4549 bool has_band; 4550 u8 band; 4551 4552 has_band = u8_get_bits(rh->io_band, __DIAG_MAC_HAS_BAND); 4553 if (!has_band) 4554 return true; 4555 4556 band = u8_get_bits(rh->io_band, __DIAG_MAC_N_BAND); 4557 active_bands = rtw89_get_active_phy_bitmap(rtwdev); 4558 4559 if (active_bands & BIT(band)) 4560 return true; 4561 4562 return false; 4563 } 4564 4565 static ssize_t rtw89_mac_diag_iter_all(struct rtw89_dev *rtwdev, 4566 char *buf, size_t bufsz) 4567 { 4568 const struct rtw89_fw_element_hdr *elm = rtwdev->fw.elm_info.diag_mac; 4569 u32 n_plains = 0, n_rules = 0, n_positive = 0, n_ignore = 0; 4570 char *p = buf, *end = buf + bufsz, *p_rewind; 4571 const void *rule, *rule_end; 4572 u32 elm_size, rule_size; 4573 const void *msg_start; 4574 u64 positive_bmp = 0; 4575 u8 prev_sheet = 0; 4576 u8 prev_seq = 0; 4577 int limit; 4578 4579 if (!elm) { 4580 p += scnprintf(p, end - p, "No diag_mac entry\n"); 4581 goto out; 4582 } 4583 4584 rule_size = le32_to_cpu(elm->u.diag_mac.rule_size); 4585 elm_size = le32_to_cpu(elm->size); 4586 4587 if (ALIGN(rule_size, 16) > elm_size) { 4588 p += scnprintf(p, end - p, "rule size (%u) exceed elm_size (%u)\n", 4589 ALIGN(rule_size, 16), elm_size); 4590 goto out; 4591 } 4592 4593 rule = &elm->u.diag_mac.rules_and_msgs[0]; 4594 rule_end = &elm->u.diag_mac.rules_and_msgs[rule_size]; 4595 msg_start = &elm->u.diag_mac.rules_and_msgs[ALIGN(rule_size, 16)]; 4596 4597 for (limit = 0; limit < 5000 && rule < rule_end; limit++) { 4598 const struct __diag_mac_rule_header *rh = rule; 4599 u8 sheet = rh->sheet; 4600 u8 seq = rh->seq_major; 4601 4602 if (!rtw89_mac_diag_match_hci(rtwdev, rh) || 4603 !rtw89_mac_diag_match_band(rtwdev, rh)) { 4604 n_ignore++; 4605 goto next; 4606 } 4607 4608 if (!seq || prev_sheet != sheet || prev_seq != seq) { 4609 if (positive_bmp) { 4610 n_positive++; 4611 /* 4612 * discard output for negative results if one in 4613 * a sequence set is positive. 4614 */ 4615 if (p_rewind) 4616 p = p_rewind; 4617 } 4618 p_rewind = seq ? p : NULL; 4619 positive_bmp = 0; 4620 n_rules++; 4621 } 4622 4623 switch (rh->cmd) { 4624 case __CMD_EQUALV: 4625 case __CMD_NEQUALV: 4626 p += rtw89_mac_diag_do_equalv(rtwdev, p, end - p, rule, 4627 msg_start, &positive_bmp); 4628 break; 4629 case __CMD_INCREMENT: 4630 p += rtw89_mac_diag_do_increment(rtwdev, p, end - p, rule, 4631 msg_start, &positive_bmp); 4632 break; 4633 default: 4634 p += scnprintf(p, end - p, "unknown rule cmd %u\n", rh->cmd); 4635 break; 4636 } 4637 4638 next: 4639 n_plains++; 4640 rule += rh->len * 4; 4641 prev_seq = seq; 4642 prev_sheet = sheet; 4643 } 4644 4645 if (positive_bmp) { 4646 n_positive++; 4647 if (p_rewind) 4648 p = p_rewind; 4649 } 4650 4651 p += scnprintf(p, end - p, "\nPlain(Ignore)/Rules/Positive: %u(%u)/%u/%u\n", 4652 n_plains, n_ignore, n_rules, n_positive); 4653 4654 out: 4655 return p - buf; 4656 } 4657 4658 static ssize_t 4659 rtw89_debug_priv_diag_mac_get(struct rtw89_dev *rtwdev, 4660 struct rtw89_debugfs_priv *debugfs_priv, 4661 char *buf, size_t bufsz) 4662 { 4663 lockdep_assert_wiphy(rtwdev->hw->wiphy); 4664 4665 rtw89_leave_lps(rtwdev); 4666 4667 return rtw89_mac_diag_iter_all(rtwdev, buf, bufsz); 4668 } 4669 4670 static ssize_t 4671 rtw89_debug_priv_beacon_info_get(struct rtw89_dev *rtwdev, 4672 struct rtw89_debugfs_priv *debugfs_priv, 4673 char *buf, size_t bufsz) 4674 { 4675 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 4676 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 4677 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 4678 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist; 4679 u16 upper, lower = bcn_stat->tbtt_tu_min; 4680 char *p = buf, *end = buf + bufsz; 4681 u16 *drift = bcn_stat->drift; 4682 u8 bcn_num = bcn_stat->num; 4683 u8 count; 4684 u8 i; 4685 4686 p += scnprintf(p, end - p, "[Beacon info]\n"); 4687 p += scnprintf(p, end - p, "count: %u\n", pkt_stat->beacon_nr); 4688 p += scnprintf(p, end - p, "interval: %u\n", bcn_track->beacon_int); 4689 p += scnprintf(p, end - p, "dtim: %u\n", bcn_track->dtim); 4690 p += scnprintf(p, end - p, "raw rssi: %lu\n", 4691 ewma_rssi_read(&rtwdev->phystat.bcn_rssi)); 4692 p += scnprintf(p, end - p, "hw rate: %u\n", pkt_stat->beacon_rate); 4693 p += scnprintf(p, end - p, "length: %u\n", pkt_stat->beacon_len); 4694 4695 p += scnprintf(p, end - p, "\n[Distribution]\n"); 4696 p += scnprintf(p, end - p, "tbtt\n"); 4697 for (i = 0; i < RTW89_BCN_TRACK_MAX_BIN_NUM; i++) { 4698 upper = lower + RTW89_BCN_TRACK_BIN_WIDTH - 1; 4699 if (i == RTW89_BCN_TRACK_MAX_BIN_NUM - 1) 4700 upper = max(upper, bcn_stat->tbtt_tu_max); 4701 4702 p += scnprintf(p, end - p, "%02u - %02u: %u\n", 4703 lower, upper, bcn_dist->bins[i]); 4704 4705 lower = upper + 1; 4706 } 4707 4708 p += scnprintf(p, end - p, "\ndrift\n"); 4709 4710 for (i = 0; i < bcn_num; i += count) { 4711 count = 1; 4712 while (i + count < bcn_num && drift[i] == drift[i + count]) 4713 count++; 4714 4715 p += scnprintf(p, end - p, "%u: %u\n", drift[i], count); 4716 } 4717 p += scnprintf(p, end - p, "\nlower bound: %u\n", bcn_dist->lower_bound); 4718 p += scnprintf(p, end - p, "upper bound: %u\n", bcn_dist->upper_bound); 4719 p += scnprintf(p, end - p, "outlier count: %u\n", bcn_dist->outlier_count); 4720 4721 p += scnprintf(p, end - p, "\n[Tracking]\n"); 4722 p += scnprintf(p, end - p, "tbtt offset: %u\n", bcn_track->tbtt_offset); 4723 p += scnprintf(p, end - p, "bcn timeout: %u\n", bcn_track->bcn_timeout); 4724 4725 return p - buf; 4726 } 4727 4728 #define rtw89_debug_priv_get(name, opts...) \ 4729 { \ 4730 .cb_read = rtw89_debug_priv_ ##name## _get, \ 4731 .opt = { opts }, \ 4732 } 4733 4734 #define rtw89_debug_priv_set(name, opts...) \ 4735 { \ 4736 .cb_write = rtw89_debug_priv_ ##name## _set, \ 4737 .opt = { opts }, \ 4738 } 4739 4740 #define rtw89_debug_priv_select_and_get(name, opts...) \ 4741 { \ 4742 .cb_write = rtw89_debug_priv_ ##name## _select, \ 4743 .cb_read = rtw89_debug_priv_ ##name## _get, \ 4744 .opt = { opts }, \ 4745 } 4746 4747 #define rtw89_debug_priv_set_and_get(name, opts...) \ 4748 { \ 4749 .cb_write = rtw89_debug_priv_ ##name## _set, \ 4750 .cb_read = rtw89_debug_priv_ ##name## _get, \ 4751 .opt = { opts }, \ 4752 } 4753 4754 #define RSIZE_8K .rsize = 0x2000 4755 #define RSIZE_12K .rsize = 0x3000 4756 #define RSIZE_16K .rsize = 0x4000 4757 #define RSIZE_20K .rsize = 0x5000 4758 #define RSIZE_32K .rsize = 0x8000 4759 #define RSIZE_64K .rsize = 0x10000 4760 #define RSIZE_128K .rsize = 0x20000 4761 #define RSIZE_1M .rsize = 0x100000 4762 #define RLOCK .rlock = 1 4763 #define WLOCK .wlock = 1 4764 #define RWLOCK RLOCK, WLOCK 4765 4766 static const struct rtw89_debugfs rtw89_debugfs_templ = { 4767 .read_reg = rtw89_debug_priv_select_and_get(read_reg), 4768 .write_reg = rtw89_debug_priv_set(write_reg), 4769 .read_rf = rtw89_debug_priv_select_and_get(read_rf), 4770 .write_rf = rtw89_debug_priv_set(write_rf), 4771 .rf_reg_dump = rtw89_debug_priv_get(rf_reg_dump, RSIZE_8K), 4772 .txpwr_table = rtw89_debug_priv_get(txpwr_table, RSIZE_20K, RLOCK), 4773 .mac_reg_dump = rtw89_debug_priv_select_and_get(mac_reg_dump, RSIZE_128K), 4774 .mac_mem_dump = rtw89_debug_priv_select_and_get(mac_mem_dump, RSIZE_16K, RLOCK), 4775 .mac_dbg_port_dump = rtw89_debug_priv_select_and_get(mac_dbg_port_dump, RSIZE_1M), 4776 .send_h2c = rtw89_debug_priv_set(send_h2c), 4777 .early_h2c = rtw89_debug_priv_set_and_get(early_h2c, RWLOCK), 4778 .fw_crash = rtw89_debug_priv_set_and_get(fw_crash, WLOCK), 4779 .btc_info = rtw89_debug_priv_get(btc_info, RSIZE_12K), 4780 .btc_manual = rtw89_debug_priv_set(btc_manual), 4781 .fw_log_manual = rtw89_debug_priv_set(fw_log_manual, WLOCK), 4782 .phy_info = rtw89_debug_priv_get(phy_info), 4783 .stations = rtw89_debug_priv_get(stations, RLOCK), 4784 .disable_dm = rtw89_debug_priv_set_and_get(disable_dm, RWLOCK), 4785 .mlo_mode = rtw89_debug_priv_set_and_get(mlo_mode, RWLOCK), 4786 .beacon_info = rtw89_debug_priv_get(beacon_info), 4787 .diag_mac = rtw89_debug_priv_get(diag_mac, RSIZE_16K, RLOCK), 4788 }; 4789 4790 #define rtw89_debugfs_add(name, mode, fopname, parent) \ 4791 do { \ 4792 struct rtw89_debugfs_priv *priv = &rtwdev->debugfs->name; \ 4793 priv->rtwdev = rtwdev; \ 4794 if (IS_ERR(debugfs_create_file(#name, mode, parent, priv, \ 4795 &file_ops_ ##fopname))) \ 4796 pr_debug("Unable to initialize debugfs:%s\n", #name); \ 4797 } while (0) 4798 4799 #define rtw89_debugfs_add_w(name) \ 4800 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) 4801 #define rtw89_debugfs_add_rw(name) \ 4802 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) 4803 #define rtw89_debugfs_add_r(name) \ 4804 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) 4805 4806 static 4807 void rtw89_debugfs_add_sec0(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir) 4808 { 4809 rtw89_debugfs_add_rw(read_reg); 4810 rtw89_debugfs_add_w(write_reg); 4811 rtw89_debugfs_add_rw(read_rf); 4812 rtw89_debugfs_add_w(write_rf); 4813 rtw89_debugfs_add_r(rf_reg_dump); 4814 rtw89_debugfs_add_r(txpwr_table); 4815 rtw89_debugfs_add_rw(mac_reg_dump); 4816 rtw89_debugfs_add_rw(mac_mem_dump); 4817 rtw89_debugfs_add_rw(mac_dbg_port_dump); 4818 } 4819 4820 static 4821 void rtw89_debugfs_add_sec1(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir) 4822 { 4823 rtw89_debugfs_add_w(send_h2c); 4824 rtw89_debugfs_add_rw(early_h2c); 4825 rtw89_debugfs_add_rw(fw_crash); 4826 rtw89_debugfs_add_r(btc_info); 4827 rtw89_debugfs_add_w(btc_manual); 4828 rtw89_debugfs_add_w(fw_log_manual); 4829 rtw89_debugfs_add_r(phy_info); 4830 rtw89_debugfs_add_r(stations); 4831 rtw89_debugfs_add_rw(disable_dm); 4832 rtw89_debugfs_add_rw(mlo_mode); 4833 rtw89_debugfs_add_r(beacon_info); 4834 rtw89_debugfs_add_r(diag_mac); 4835 } 4836 4837 void rtw89_debugfs_init(struct rtw89_dev *rtwdev) 4838 { 4839 struct dentry *debugfs_topdir; 4840 4841 rtwdev->debugfs = kmemdup(&rtw89_debugfs_templ, 4842 sizeof(rtw89_debugfs_templ), GFP_KERNEL); 4843 if (!rtwdev->debugfs) 4844 return; 4845 4846 #if defined(__linux__) 4847 debugfs_topdir = debugfs_create_dir("rtw89", 4848 #elif defined(__FreeBSD__) 4849 debugfs_topdir = debugfs_create_dir(dev_name(rtwdev->dev), 4850 #endif 4851 rtwdev->hw->wiphy->debugfsdir); 4852 4853 rtw89_debugfs_add_sec0(rtwdev, debugfs_topdir); 4854 rtw89_debugfs_add_sec1(rtwdev, debugfs_topdir); 4855 } 4856 4857 void rtw89_debugfs_deinit(struct rtw89_dev *rtwdev) 4858 { 4859 kfree(rtwdev->debugfs); 4860 } 4861 #endif 4862 4863 #ifdef CONFIG_RTW89_DEBUGMSG 4864 void rtw89_debug(struct rtw89_dev *rtwdev, enum rtw89_debug_mask mask, 4865 const char *fmt, ...) 4866 { 4867 struct va_format vaf = { 4868 .fmt = fmt, 4869 }; 4870 4871 va_list args; 4872 4873 va_start(args, fmt); 4874 vaf.va = &args; 4875 4876 if (rtw89_debug_mask & mask) 4877 #if defined(__linux__) 4878 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); 4879 #elif defined(__FreeBSD__) 4880 { 4881 char *str; 4882 vasprintf(&str, M_KMALLOC, vaf.fmt, args); 4883 dev_printk(KERN_DEBUG, rtwdev->dev, "%s", str); 4884 free(str, M_KMALLOC); 4885 } 4886 #endif 4887 4888 va_end(args); 4889 } 4890 EXPORT_SYMBOL(rtw89_debug); 4891 #endif 4892 #if defined(__FreeBSD__) 4893 #ifdef CONFIG_RTW89_DEBUGFS 4894 MODULE_DEPEND(rtw89, lindebugfs, 1, 1, 1); 4895 #endif 4896 #endif 4897