1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #if defined(__FreeBSD__) 6 #define LINUXKPI_PARAM_PREFIX rtw89_ 7 #endif 8 9 #include <linux/ip.h> 10 #include <linux/udp.h> 11 12 #include "cam.h" 13 #include "chan.h" 14 #include "coex.h" 15 #include "core.h" 16 #include "efuse.h" 17 #include "fw.h" 18 #include "mac.h" 19 #include "phy.h" 20 #include "ps.h" 21 #include "reg.h" 22 #include "sar.h" 23 #include "ser.h" 24 #include "txrx.h" 25 #include "util.h" 26 #include "wow.h" 27 28 static bool rtw89_disable_ps_mode; 29 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); 30 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); 31 32 #if defined(__FreeBSD__) 33 static bool rtw_ht_support = false; 34 module_param_named(support_ht, rtw_ht_support, bool, 0644); 35 MODULE_PARM_DESC(support_ht, "Set to Y to enable HT support"); 36 37 static bool rtw_vht_support = false; 38 module_param_named(support_vht, rtw_vht_support, bool, 0644); 39 MODULE_PARM_DESC(support_vht, "Set to Y to enable VHT support"); 40 41 static bool rtw_eht_support = false; 42 module_param_named(support_eht, rtw_eht_support, bool, 0644); 43 MODULE_PARM_DESC(support_eht, "Set to Y to enable EHT support"); 44 #endif 45 46 47 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \ 48 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, } 49 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \ 50 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ) 51 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \ 52 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ) 53 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \ 54 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ) 55 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \ 56 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ) 57 58 static struct ieee80211_channel rtw89_channels_2ghz[] = { 59 RTW89_DEF_CHAN_2G(2412, 1), 60 RTW89_DEF_CHAN_2G(2417, 2), 61 RTW89_DEF_CHAN_2G(2422, 3), 62 RTW89_DEF_CHAN_2G(2427, 4), 63 RTW89_DEF_CHAN_2G(2432, 5), 64 RTW89_DEF_CHAN_2G(2437, 6), 65 RTW89_DEF_CHAN_2G(2442, 7), 66 RTW89_DEF_CHAN_2G(2447, 8), 67 RTW89_DEF_CHAN_2G(2452, 9), 68 RTW89_DEF_CHAN_2G(2457, 10), 69 RTW89_DEF_CHAN_2G(2462, 11), 70 RTW89_DEF_CHAN_2G(2467, 12), 71 RTW89_DEF_CHAN_2G(2472, 13), 72 RTW89_DEF_CHAN_2G(2484, 14), 73 }; 74 75 static struct ieee80211_channel rtw89_channels_5ghz[] = { 76 RTW89_DEF_CHAN_5G(5180, 36), 77 RTW89_DEF_CHAN_5G(5200, 40), 78 RTW89_DEF_CHAN_5G(5220, 44), 79 RTW89_DEF_CHAN_5G(5240, 48), 80 RTW89_DEF_CHAN_5G(5260, 52), 81 RTW89_DEF_CHAN_5G(5280, 56), 82 RTW89_DEF_CHAN_5G(5300, 60), 83 RTW89_DEF_CHAN_5G(5320, 64), 84 RTW89_DEF_CHAN_5G(5500, 100), 85 RTW89_DEF_CHAN_5G(5520, 104), 86 RTW89_DEF_CHAN_5G(5540, 108), 87 RTW89_DEF_CHAN_5G(5560, 112), 88 RTW89_DEF_CHAN_5G(5580, 116), 89 RTW89_DEF_CHAN_5G(5600, 120), 90 RTW89_DEF_CHAN_5G(5620, 124), 91 RTW89_DEF_CHAN_5G(5640, 128), 92 RTW89_DEF_CHAN_5G(5660, 132), 93 RTW89_DEF_CHAN_5G(5680, 136), 94 RTW89_DEF_CHAN_5G(5700, 140), 95 RTW89_DEF_CHAN_5G(5720, 144), 96 RTW89_DEF_CHAN_5G(5745, 149), 97 RTW89_DEF_CHAN_5G(5765, 153), 98 RTW89_DEF_CHAN_5G(5785, 157), 99 RTW89_DEF_CHAN_5G(5805, 161), 100 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165), 101 RTW89_DEF_CHAN_5G(5845, 169), 102 RTW89_DEF_CHAN_5G(5865, 173), 103 RTW89_DEF_CHAN_5G(5885, 177), 104 }; 105 106 static_assert(RTW89_5GHZ_UNII4_START_INDEX + RTW89_5GHZ_UNII4_CHANNEL_NUM == 107 ARRAY_SIZE(rtw89_channels_5ghz)); 108 109 static struct ieee80211_channel rtw89_channels_6ghz[] = { 110 RTW89_DEF_CHAN_6G(5955, 1), 111 RTW89_DEF_CHAN_6G(5975, 5), 112 RTW89_DEF_CHAN_6G(5995, 9), 113 RTW89_DEF_CHAN_6G(6015, 13), 114 RTW89_DEF_CHAN_6G(6035, 17), 115 RTW89_DEF_CHAN_6G(6055, 21), 116 RTW89_DEF_CHAN_6G(6075, 25), 117 RTW89_DEF_CHAN_6G(6095, 29), 118 RTW89_DEF_CHAN_6G(6115, 33), 119 RTW89_DEF_CHAN_6G(6135, 37), 120 RTW89_DEF_CHAN_6G(6155, 41), 121 RTW89_DEF_CHAN_6G(6175, 45), 122 RTW89_DEF_CHAN_6G(6195, 49), 123 RTW89_DEF_CHAN_6G(6215, 53), 124 RTW89_DEF_CHAN_6G(6235, 57), 125 RTW89_DEF_CHAN_6G(6255, 61), 126 RTW89_DEF_CHAN_6G(6275, 65), 127 RTW89_DEF_CHAN_6G(6295, 69), 128 RTW89_DEF_CHAN_6G(6315, 73), 129 RTW89_DEF_CHAN_6G(6335, 77), 130 RTW89_DEF_CHAN_6G(6355, 81), 131 RTW89_DEF_CHAN_6G(6375, 85), 132 RTW89_DEF_CHAN_6G(6395, 89), 133 RTW89_DEF_CHAN_6G(6415, 93), 134 RTW89_DEF_CHAN_6G(6435, 97), 135 RTW89_DEF_CHAN_6G(6455, 101), 136 RTW89_DEF_CHAN_6G(6475, 105), 137 RTW89_DEF_CHAN_6G(6495, 109), 138 RTW89_DEF_CHAN_6G(6515, 113), 139 RTW89_DEF_CHAN_6G(6535, 117), 140 RTW89_DEF_CHAN_6G(6555, 121), 141 RTW89_DEF_CHAN_6G(6575, 125), 142 RTW89_DEF_CHAN_6G(6595, 129), 143 RTW89_DEF_CHAN_6G(6615, 133), 144 RTW89_DEF_CHAN_6G(6635, 137), 145 RTW89_DEF_CHAN_6G(6655, 141), 146 RTW89_DEF_CHAN_6G(6675, 145), 147 RTW89_DEF_CHAN_6G(6695, 149), 148 RTW89_DEF_CHAN_6G(6715, 153), 149 RTW89_DEF_CHAN_6G(6735, 157), 150 RTW89_DEF_CHAN_6G(6755, 161), 151 RTW89_DEF_CHAN_6G(6775, 165), 152 RTW89_DEF_CHAN_6G(6795, 169), 153 RTW89_DEF_CHAN_6G(6815, 173), 154 RTW89_DEF_CHAN_6G(6835, 177), 155 RTW89_DEF_CHAN_6G(6855, 181), 156 RTW89_DEF_CHAN_6G(6875, 185), 157 RTW89_DEF_CHAN_6G(6895, 189), 158 RTW89_DEF_CHAN_6G(6915, 193), 159 RTW89_DEF_CHAN_6G(6935, 197), 160 RTW89_DEF_CHAN_6G(6955, 201), 161 RTW89_DEF_CHAN_6G(6975, 205), 162 RTW89_DEF_CHAN_6G(6995, 209), 163 RTW89_DEF_CHAN_6G(7015, 213), 164 RTW89_DEF_CHAN_6G(7035, 217), 165 RTW89_DEF_CHAN_6G(7055, 221), 166 RTW89_DEF_CHAN_6G(7075, 225), 167 RTW89_DEF_CHAN_6G(7095, 229), 168 RTW89_DEF_CHAN_6G(7115, 233), 169 }; 170 171 static struct ieee80211_rate rtw89_bitrates[] = { 172 { .bitrate = 10, .hw_value = 0x00, }, 173 { .bitrate = 20, .hw_value = 0x01, }, 174 { .bitrate = 55, .hw_value = 0x02, }, 175 { .bitrate = 110, .hw_value = 0x03, }, 176 { .bitrate = 60, .hw_value = 0x04, }, 177 { .bitrate = 90, .hw_value = 0x05, }, 178 { .bitrate = 120, .hw_value = 0x06, }, 179 { .bitrate = 180, .hw_value = 0x07, }, 180 { .bitrate = 240, .hw_value = 0x08, }, 181 { .bitrate = 360, .hw_value = 0x09, }, 182 { .bitrate = 480, .hw_value = 0x0a, }, 183 { .bitrate = 540, .hw_value = 0x0b, }, 184 }; 185 186 static const struct ieee80211_iface_limit rtw89_iface_limits[] = { 187 { 188 .max = 1, 189 .types = BIT(NL80211_IFTYPE_STATION), 190 }, 191 { 192 .max = 1, 193 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 194 BIT(NL80211_IFTYPE_P2P_GO) | 195 BIT(NL80211_IFTYPE_AP), 196 }, 197 }; 198 199 static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = { 200 { 201 .max = 1, 202 .types = BIT(NL80211_IFTYPE_STATION), 203 }, 204 { 205 .max = 1, 206 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 207 BIT(NL80211_IFTYPE_P2P_GO), 208 }, 209 }; 210 211 static const struct ieee80211_iface_combination rtw89_iface_combs[] = { 212 { 213 .limits = rtw89_iface_limits, 214 .n_limits = ARRAY_SIZE(rtw89_iface_limits), 215 .max_interfaces = RTW89_MAX_INTERFACE_NUM, 216 .num_different_channels = 1, 217 }, 218 { 219 .limits = rtw89_iface_limits_mcc, 220 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc), 221 .max_interfaces = RTW89_MAX_INTERFACE_NUM, 222 .num_different_channels = 2, 223 }, 224 }; 225 226 static const u8 rtw89_ext_capa_sta[] = { 227 [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING, 228 [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT, 229 [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF, 230 }; 231 232 static const struct wiphy_iftype_ext_capab rtw89_iftypes_ext_capa[] = { 233 { 234 .iftype = NL80211_IFTYPE_STATION, 235 .extended_capabilities = rtw89_ext_capa_sta, 236 .extended_capabilities_mask = rtw89_ext_capa_sta, 237 .extended_capabilities_len = sizeof(rtw89_ext_capa_sta), 238 /* relevant only if EHT is supported */ 239 .eml_capabilities = 0, 240 .mld_capa_and_ops = 0, 241 }, 242 }; 243 244 #define RTW89_6GHZ_SPAN_HEAD 6145 245 #define RTW89_6GHZ_SPAN_IDX(center_freq) \ 246 ((((int)(center_freq) - RTW89_6GHZ_SPAN_HEAD) / 5) / 2) 247 248 #define RTW89_DECL_6GHZ_SPAN(center_freq, subband_l, subband_h) \ 249 [RTW89_6GHZ_SPAN_IDX(center_freq)] = { \ 250 .sar_subband_low = RTW89_SAR_6GHZ_ ## subband_l, \ 251 .sar_subband_high = RTW89_SAR_6GHZ_ ## subband_h, \ 252 .acpi_sar_subband_low = RTW89_ACPI_SAR_6GHZ_ ## subband_l, \ 253 .acpi_sar_subband_high = RTW89_ACPI_SAR_6GHZ_ ## subband_h, \ 254 .ant_gain_subband_low = RTW89_ANT_GAIN_6GHZ_ ## subband_l, \ 255 .ant_gain_subband_high = RTW89_ANT_GAIN_6GHZ_ ## subband_h, \ 256 } 257 258 /* Since 6GHz subbands are not edge aligned, some cases span two subbands. 259 * In the following, we describe each of them with rtw89_6ghz_span. 260 */ 261 static const struct rtw89_6ghz_span rtw89_overlapping_6ghz[] = { 262 RTW89_DECL_6GHZ_SPAN(6145, SUBBAND_5_L, SUBBAND_5_H), 263 RTW89_DECL_6GHZ_SPAN(6165, SUBBAND_5_L, SUBBAND_5_H), 264 RTW89_DECL_6GHZ_SPAN(6185, SUBBAND_5_L, SUBBAND_5_H), 265 RTW89_DECL_6GHZ_SPAN(6505, SUBBAND_6, SUBBAND_7_L), 266 RTW89_DECL_6GHZ_SPAN(6525, SUBBAND_6, SUBBAND_7_L), 267 RTW89_DECL_6GHZ_SPAN(6545, SUBBAND_6, SUBBAND_7_L), 268 RTW89_DECL_6GHZ_SPAN(6665, SUBBAND_7_L, SUBBAND_7_H), 269 RTW89_DECL_6GHZ_SPAN(6705, SUBBAND_7_L, SUBBAND_7_H), 270 RTW89_DECL_6GHZ_SPAN(6825, SUBBAND_7_H, SUBBAND_8), 271 RTW89_DECL_6GHZ_SPAN(6865, SUBBAND_7_H, SUBBAND_8), 272 RTW89_DECL_6GHZ_SPAN(6875, SUBBAND_7_H, SUBBAND_8), 273 RTW89_DECL_6GHZ_SPAN(6885, SUBBAND_7_H, SUBBAND_8), 274 }; 275 276 const struct rtw89_6ghz_span * 277 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq) 278 { 279 int idx; 280 281 if (center_freq >= RTW89_6GHZ_SPAN_HEAD) { 282 idx = RTW89_6GHZ_SPAN_IDX(center_freq); 283 /* To decrease size of rtw89_overlapping_6ghz[], 284 * RTW89_6GHZ_SPAN_IDX() truncates the leading NULLs 285 * to make first span as index 0 of the table. So, if center 286 * frequency is less than the first one, it will get netative. 287 */ 288 if (idx >= 0 && idx < ARRAY_SIZE(rtw89_overlapping_6ghz)) 289 return &rtw89_overlapping_6ghz[idx]; 290 } 291 292 return NULL; 293 } 294 295 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate) 296 { 297 struct ieee80211_rate rate; 298 299 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) { 300 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate); 301 return false; 302 } 303 304 rate = rtw89_bitrates[rpt_rate]; 305 *bitrate = rate.bitrate; 306 307 return true; 308 } 309 310 static const struct ieee80211_supported_band rtw89_sband_2ghz = { 311 .band = NL80211_BAND_2GHZ, 312 .channels = rtw89_channels_2ghz, 313 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), 314 .bitrates = rtw89_bitrates, 315 .n_bitrates = ARRAY_SIZE(rtw89_bitrates), 316 .ht_cap = {0}, 317 .vht_cap = {0}, 318 }; 319 320 static const struct ieee80211_supported_band rtw89_sband_5ghz = { 321 .band = NL80211_BAND_5GHZ, 322 .channels = rtw89_channels_5ghz, 323 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), 324 325 /* 5G has no CCK rates, 1M/2M/5.5M/11M */ 326 .bitrates = rtw89_bitrates + 4, 327 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 328 .ht_cap = {0}, 329 .vht_cap = {0}, 330 }; 331 332 static const struct ieee80211_supported_band rtw89_sband_6ghz = { 333 .band = NL80211_BAND_6GHZ, 334 .channels = rtw89_channels_6ghz, 335 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz), 336 337 /* 6G has no CCK rates, 1M/2M/5.5M/11M */ 338 .bitrates = rtw89_bitrates + 4, 339 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 340 }; 341 342 static void __rtw89_traffic_stats_accu(struct rtw89_traffic_stats *stats, 343 struct sk_buff *skb, bool tx) 344 { 345 if (tx) { 346 stats->tx_cnt++; 347 stats->tx_unicast += skb->len; 348 } else { 349 stats->rx_cnt++; 350 stats->rx_unicast += skb->len; 351 } 352 } 353 354 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, 355 struct rtw89_vif *rtwvif, 356 struct sk_buff *skb, 357 bool accu_dev, bool tx) 358 { 359 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 360 361 if (!ieee80211_is_data(hdr->frame_control)) 362 return; 363 364 if (is_broadcast_ether_addr(hdr->addr1) || 365 is_multicast_ether_addr(hdr->addr1)) 366 return; 367 368 if (accu_dev) 369 __rtw89_traffic_stats_accu(&rtwdev->stats, skb, tx); 370 371 if (rtwvif) { 372 __rtw89_traffic_stats_accu(&rtwvif->stats, skb, tx); 373 __rtw89_traffic_stats_accu(&rtwvif->stats_ps, skb, tx); 374 } 375 } 376 377 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef) 378 { 379 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0], 380 NL80211_CHAN_NO_HT); 381 } 382 383 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 384 struct rtw89_chan *chan) 385 { 386 struct ieee80211_channel *channel = chandef->chan; 387 enum nl80211_chan_width width = chandef->width; 388 u32 primary_freq, center_freq; 389 u8 center_chan; 390 u8 bandwidth = RTW89_CHANNEL_WIDTH_20; 391 u32 offset; 392 u8 band; 393 394 center_chan = channel->hw_value; 395 primary_freq = channel->center_freq; 396 center_freq = chandef->center_freq1; 397 398 switch (width) { 399 case NL80211_CHAN_WIDTH_20_NOHT: 400 case NL80211_CHAN_WIDTH_20: 401 bandwidth = RTW89_CHANNEL_WIDTH_20; 402 break; 403 case NL80211_CHAN_WIDTH_40: 404 bandwidth = RTW89_CHANNEL_WIDTH_40; 405 if (primary_freq > center_freq) { 406 center_chan -= 2; 407 } else { 408 center_chan += 2; 409 } 410 break; 411 case NL80211_CHAN_WIDTH_80: 412 case NL80211_CHAN_WIDTH_160: 413 bandwidth = nl_to_rtw89_bandwidth(width); 414 if (primary_freq > center_freq) { 415 offset = (primary_freq - center_freq - 10) / 20; 416 center_chan -= 2 + offset * 4; 417 } else { 418 offset = (center_freq - primary_freq - 10) / 20; 419 center_chan += 2 + offset * 4; 420 } 421 break; 422 default: 423 center_chan = 0; 424 break; 425 } 426 427 switch (channel->band) { 428 default: 429 case NL80211_BAND_2GHZ: 430 band = RTW89_BAND_2G; 431 break; 432 case NL80211_BAND_5GHZ: 433 band = RTW89_BAND_5G; 434 break; 435 case NL80211_BAND_6GHZ: 436 band = RTW89_BAND_6G; 437 break; 438 } 439 440 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth); 441 } 442 443 static void __rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev, 444 const struct rtw89_chan *chan, 445 enum rtw89_phy_idx phy_idx) 446 { 447 const struct rtw89_chip_info *chip = rtwdev->chip; 448 bool entity_active; 449 450 entity_active = rtw89_get_entity_state(rtwdev, phy_idx); 451 if (!entity_active) 452 return; 453 454 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 455 } 456 457 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) 458 { 459 const struct rtw89_chan *chan; 460 461 chan = rtw89_mgnt_chan_get(rtwdev, 0); 462 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_0); 463 464 if (!rtwdev->support_mlo) 465 return; 466 467 chan = rtw89_mgnt_chan_get(rtwdev, 1); 468 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_1); 469 } 470 471 static void __rtw89_set_channel(struct rtw89_dev *rtwdev, 472 const struct rtw89_chan *chan, 473 enum rtw89_mac_idx mac_idx, 474 enum rtw89_phy_idx phy_idx) 475 { 476 const struct rtw89_chip_info *chip = rtwdev->chip; 477 const struct rtw89_chan_rcd *chan_rcd; 478 struct rtw89_channel_help_params bak; 479 bool entity_active; 480 481 entity_active = rtw89_get_entity_state(rtwdev, phy_idx); 482 483 chan_rcd = rtw89_chan_rcd_get_by_chan(chan); 484 485 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx); 486 487 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx); 488 489 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 490 491 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx); 492 493 if (!entity_active || chan_rcd->band_changed) { 494 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type); 495 rtw89_chip_rfk_band_changed(rtwdev, phy_idx, chan); 496 } 497 498 rtw89_set_entity_state(rtwdev, phy_idx, true); 499 } 500 501 int rtw89_set_channel(struct rtw89_dev *rtwdev) 502 { 503 const struct rtw89_chan *chan; 504 enum rtw89_entity_mode mode; 505 506 mode = rtw89_entity_recalc(rtwdev); 507 if (mode < 0 || mode >= NUM_OF_RTW89_ENTITY_MODE) { 508 WARN(1, "Invalid ent mode: %d\n", mode); 509 return -EINVAL; 510 } 511 512 chan = rtw89_mgnt_chan_get(rtwdev, 0); 513 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_0, RTW89_PHY_0); 514 515 if (!rtwdev->support_mlo) 516 return 0; 517 518 chan = rtw89_mgnt_chan_get(rtwdev, 1); 519 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_1, RTW89_PHY_1); 520 521 return 0; 522 } 523 524 static enum rtw89_core_tx_type 525 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, 526 struct sk_buff *skb) 527 { 528 struct ieee80211_hdr *hdr = (void *)skb->data; 529 __le16 fc = hdr->frame_control; 530 531 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc)) 532 return RTW89_CORE_TX_TYPE_MGMT; 533 534 return RTW89_CORE_TX_TYPE_DATA; 535 } 536 537 static void 538 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, 539 struct rtw89_core_tx_request *tx_req, 540 enum btc_pkt_type pkt_type) 541 { 542 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 543 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 544 struct ieee80211_link_sta *link_sta; 545 struct sk_buff *skb = tx_req->skb; 546 struct rtw89_sta *rtwsta; 547 u8 ampdu_num; 548 u8 tid; 549 550 if (pkt_type == PACKET_EAPOL) { 551 desc_info->bk = true; 552 return; 553 } 554 555 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU)) 556 return; 557 558 if (!rtwsta_link) { 559 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); 560 return; 561 } 562 563 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 564 rtwsta = rtwsta_link->rtwsta; 565 566 rcu_read_lock(); 567 568 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 569 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? 570 rtwsta->ampdu_params[tid].agg_num : 571 4 << link_sta->ht_cap.ampdu_factor) - 1); 572 573 desc_info->agg_en = true; 574 desc_info->ampdu_density = link_sta->ht_cap.ampdu_density; 575 desc_info->ampdu_num = ampdu_num; 576 577 rcu_read_unlock(); 578 } 579 580 static void 581 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, 582 struct rtw89_core_tx_request *tx_req) 583 { 584 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 585 const struct rtw89_chip_info *chip = rtwdev->chip; 586 const struct rtw89_sec_cam_entry *sec_cam; 587 struct ieee80211_tx_info *info; 588 struct ieee80211_key_conf *key; 589 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 590 struct sk_buff *skb = tx_req->skb; 591 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; 592 u8 sec_cam_idx; 593 u64 pn64; 594 595 info = IEEE80211_SKB_CB(skb); 596 key = info->control.hw_key; 597 sec_cam_idx = key->hw_key_idx; 598 sec_cam = cam_info->sec_entries[sec_cam_idx]; 599 if (!sec_cam) { 600 rtw89_warn(rtwdev, "sec cam entry is empty\n"); 601 return; 602 } 603 604 switch (key->cipher) { 605 case WLAN_CIPHER_SUITE_WEP40: 606 sec_type = RTW89_SEC_KEY_TYPE_WEP40; 607 break; 608 case WLAN_CIPHER_SUITE_WEP104: 609 sec_type = RTW89_SEC_KEY_TYPE_WEP104; 610 break; 611 case WLAN_CIPHER_SUITE_TKIP: 612 sec_type = RTW89_SEC_KEY_TYPE_TKIP; 613 break; 614 case WLAN_CIPHER_SUITE_CCMP: 615 sec_type = RTW89_SEC_KEY_TYPE_CCMP128; 616 break; 617 case WLAN_CIPHER_SUITE_CCMP_256: 618 sec_type = RTW89_SEC_KEY_TYPE_CCMP256; 619 break; 620 case WLAN_CIPHER_SUITE_GCMP: 621 sec_type = RTW89_SEC_KEY_TYPE_GCMP128; 622 break; 623 case WLAN_CIPHER_SUITE_GCMP_256: 624 sec_type = RTW89_SEC_KEY_TYPE_GCMP256; 625 break; 626 default: 627 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); 628 return; 629 } 630 631 desc_info->sec_en = true; 632 desc_info->sec_keyid = key->keyidx; 633 desc_info->sec_type = sec_type; 634 desc_info->sec_cam_idx = sec_cam->sec_cam_idx; 635 636 if (!chip->hw_sec_hdr) 637 return; 638 639 pn64 = atomic64_inc_return(&key->tx_pn); 640 desc_info->sec_seq[0] = pn64; 641 desc_info->sec_seq[1] = pn64 >> 8; 642 desc_info->sec_seq[2] = pn64 >> 16; 643 desc_info->sec_seq[3] = pn64 >> 24; 644 desc_info->sec_seq[4] = pn64 >> 32; 645 desc_info->sec_seq[5] = pn64 >> 40; 646 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */ 647 } 648 649 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, 650 struct rtw89_core_tx_request *tx_req, 651 const struct rtw89_chan *chan) 652 { 653 struct sk_buff *skb = tx_req->skb; 654 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 655 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 656 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 657 struct ieee80211_vif *vif = tx_info->control.vif; 658 struct ieee80211_bss_conf *bss_conf; 659 u16 lowest_rate; 660 u16 rate; 661 662 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE || 663 (vif && vif->p2p)) 664 lowest_rate = RTW89_HW_RATE_OFDM6; 665 else if (chan->band_type == RTW89_BAND_2G) 666 lowest_rate = RTW89_HW_RATE_CCK1; 667 else 668 lowest_rate = RTW89_HW_RATE_OFDM6; 669 670 if (!rtwvif_link) 671 return lowest_rate; 672 673 rcu_read_lock(); 674 675 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 676 if (!bss_conf->basic_rates || !rtwsta_link) { 677 rate = lowest_rate; 678 goto out; 679 } 680 681 rate = __ffs(bss_conf->basic_rates) + lowest_rate; 682 683 out: 684 rcu_read_unlock(); 685 686 return rate; 687 } 688 689 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev, 690 struct rtw89_core_tx_request *tx_req) 691 { 692 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 693 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 694 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 695 696 if (desc_info->mlo && !desc_info->sw_mld) { 697 if (rtwsta_link) 698 return rtw89_sta_get_main_macid(rtwsta_link->rtwsta); 699 else 700 return rtw89_vif_get_main_macid(rtwvif_link->rtwvif); 701 } 702 703 if (!rtwsta_link) 704 return rtwvif_link->mac_id; 705 706 return rtwsta_link->mac_id; 707 } 708 709 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev, 710 struct rtw89_tx_desc_info *desc_info, 711 struct sk_buff *skb) 712 { 713 struct ieee80211_hdr *hdr = (void *)skb->data; 714 __le16 fc = hdr->frame_control; 715 716 desc_info->hdr_llc_len = ieee80211_hdrlen(fc); 717 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 718 } 719 720 static void 721 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 722 struct rtw89_core_tx_request *tx_req) 723 { 724 const struct rtw89_chip_info *chip = rtwdev->chip; 725 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 726 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 727 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 728 rtwvif_link->chanctx_idx); 729 struct sk_buff *skb = tx_req->skb; 730 u8 qsel, ch_dma; 731 732 qsel = rtw89_core_get_qsel_mgmt(rtwdev, tx_req); 733 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 734 735 desc_info->qsel = qsel; 736 desc_info->ch_dma = ch_dma; 737 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0; 738 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 739 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL; 740 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE; 741 742 /* fixed data rate for mgmt frames */ 743 desc_info->en_wd_info = true; 744 desc_info->use_rate = true; 745 desc_info->dis_data_fb = true; 746 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan); 747 748 if (chip->hw_mgmt_tx_encrypt && IEEE80211_SKB_CB(skb)->control.hw_key) { 749 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 750 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 751 } 752 753 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 754 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n", 755 desc_info->data_rate, chan->channel, chan->band_type, 756 chan->band_width); 757 } 758 759 static void 760 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, 761 struct rtw89_core_tx_request *tx_req) 762 { 763 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 764 765 desc_info->is_bmc = false; 766 desc_info->wd_page = false; 767 desc_info->ch_dma = RTW89_DMA_H2C; 768 } 769 770 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc, 771 const struct rtw89_chan *chan) 772 { 773 static const u8 rtw89_bandwidth_to_om[] = { 774 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, 775 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, 776 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, 777 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 778 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 779 }; 780 const struct rtw89_chip_info *chip = rtwdev->chip; 781 struct rtw89_hal *hal = &rtwdev->hal; 782 u8 om_bandwidth; 783 784 if (!chip->dis_2g_40m_ul_ofdma || 785 chan->band_type != RTW89_BAND_2G || 786 chan->band_width != RTW89_CHANNEL_WIDTH_40) 787 return; 788 789 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? 790 rtw89_bandwidth_to_om[chan->band_width] : 0; 791 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 792 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | 793 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | 794 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | 795 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | 796 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | 797 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | 798 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | 799 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); 800 } 801 802 static bool 803 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, 804 struct rtw89_core_tx_request *tx_req, 805 enum btc_pkt_type pkt_type) 806 { 807 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 808 struct sk_buff *skb = tx_req->skb; 809 struct ieee80211_hdr *hdr = (void *)skb->data; 810 struct ieee80211_link_sta *link_sta; 811 __le16 fc = hdr->frame_control; 812 813 /* AP IOT issue with EAPoL, ARP and DHCP */ 814 if (pkt_type < PACKET_MAX) 815 return false; 816 817 if (!rtwsta_link) 818 return false; 819 820 rcu_read_lock(); 821 822 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 823 if (!link_sta->he_cap.has_he) { 824 rcu_read_unlock(); 825 return false; 826 } 827 828 rcu_read_unlock(); 829 830 if (!ieee80211_is_data_qos(fc)) 831 return false; 832 833 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) 834 return false; 835 836 if (rtwsta_link && rtwsta_link->ra_report.might_fallback_legacy) 837 return false; 838 839 return true; 840 } 841 842 static void 843 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, 844 struct rtw89_core_tx_request *tx_req) 845 { 846 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 847 struct sk_buff *skb = tx_req->skb; 848 struct ieee80211_hdr *hdr = (void *)skb->data; 849 __le16 fc = hdr->frame_control; 850 void *data; 851 __le32 *htc; 852 u8 *qc; 853 int hdr_len; 854 855 hdr_len = ieee80211_has_a4(fc) ? 32 : 26; 856 data = skb_push(skb, IEEE80211_HT_CTL_LEN); 857 #if defined(__linux__) 858 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); 859 #elif defined(__FreeBSD__) 860 memmove(data, (u8 *)data + IEEE80211_HT_CTL_LEN, hdr_len); 861 #endif 862 863 hdr = data; 864 #if defined(__linux__) 865 htc = data + hdr_len; 866 #elif defined(__FreeBSD__) 867 htc = (__le32 *)((u8 *)data + hdr_len); 868 #endif 869 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); 870 *htc = rtwsta_link->htc_template ? rtwsta_link->htc_template : 871 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 872 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); 873 874 #if defined(__linux__) 875 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; 876 #elif defined(__FreeBSD__) 877 qc = (u8 *)data + hdr_len - IEEE80211_QOS_CTL_LEN; 878 #endif 879 qc[0] |= IEEE80211_QOS_CTL_EOSP; 880 } 881 882 static void 883 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, 884 struct rtw89_core_tx_request *tx_req, 885 enum btc_pkt_type pkt_type) 886 { 887 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 888 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 889 890 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) 891 goto desc_bk; 892 893 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); 894 895 desc_info->pkt_size += IEEE80211_HT_CTL_LEN; 896 desc_info->a_ctrl_bsr = true; 897 898 desc_bk: 899 if (!rtwvif_link || rtwvif_link->last_a_ctrl == desc_info->a_ctrl_bsr) 900 return; 901 902 rtwvif_link->last_a_ctrl = desc_info->a_ctrl_bsr; 903 desc_info->bk = true; 904 } 905 906 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev, 907 struct rtw89_core_tx_request *tx_req) 908 { 909 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 910 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 911 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 912 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern; 913 enum rtw89_chanctx_idx idx = rtwvif_link->chanctx_idx; 914 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx); 915 struct ieee80211_link_sta *link_sta; 916 u16 lowest_rate; 917 u16 rate; 918 919 if (rate_pattern->enable) 920 return rate_pattern->rate; 921 922 if (vif->p2p) 923 lowest_rate = RTW89_HW_RATE_OFDM6; 924 else if (chan->band_type == RTW89_BAND_2G) 925 lowest_rate = RTW89_HW_RATE_CCK1; 926 else 927 lowest_rate = RTW89_HW_RATE_OFDM6; 928 929 if (!rtwsta_link) 930 return lowest_rate; 931 932 rcu_read_lock(); 933 934 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 935 if (!link_sta->supp_rates[chan->band_type]) { 936 rate = lowest_rate; 937 goto out; 938 } 939 940 rate = __ffs(link_sta->supp_rates[chan->band_type]) + lowest_rate; 941 942 out: 943 rcu_read_unlock(); 944 945 return rate; 946 } 947 948 static void 949 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, 950 struct rtw89_core_tx_request *tx_req) 951 { 952 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 953 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 954 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 955 struct sk_buff *skb = tx_req->skb; 956 u8 tid, tid_indicate; 957 u8 qsel, ch_dma; 958 959 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 960 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 961 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 962 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 963 964 desc_info->ch_dma = ch_dma; 965 desc_info->tid_indicate = tid_indicate; 966 desc_info->qsel = qsel; 967 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 968 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0; 969 desc_info->er_cap = rtwsta_link ? rtwsta_link->er_cap : false; 970 desc_info->stbc = rtwsta_link ? rtwsta_link->ra.stbc_cap : false; 971 desc_info->ldpc = rtwsta_link ? rtwsta_link->ra.ldpc_cap : false; 972 973 /* enable wd_info for AMPDU */ 974 desc_info->en_wd_info = true; 975 976 if (IEEE80211_SKB_CB(skb)->control.hw_key) 977 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 978 979 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req); 980 } 981 982 static enum btc_pkt_type 983 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, 984 struct rtw89_core_tx_request *tx_req) 985 { 986 struct wiphy *wiphy = rtwdev->hw->wiphy; 987 struct sk_buff *skb = tx_req->skb; 988 struct udphdr *udphdr; 989 990 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { 991 wiphy_work_queue(wiphy, &rtwdev->btc.eapol_notify_work); 992 return PACKET_EAPOL; 993 } 994 995 if (skb->protocol == htons(ETH_P_ARP)) { 996 wiphy_work_queue(wiphy, &rtwdev->btc.arp_notify_work); 997 return PACKET_ARP; 998 } 999 1000 if (skb->protocol == htons(ETH_P_IP) && 1001 ip_hdr(skb)->protocol == IPPROTO_UDP) { 1002 udphdr = udp_hdr(skb); 1003 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || 1004 (udphdr->source == htons(68) && udphdr->dest == htons(67))) && 1005 skb->len > 282) { 1006 wiphy_work_queue(wiphy, &rtwdev->btc.dhcp_notify_work); 1007 return PACKET_DHCP; 1008 } 1009 } 1010 1011 if (skb->protocol == htons(ETH_P_IP) && 1012 ip_hdr(skb)->protocol == IPPROTO_ICMP) { 1013 wiphy_work_queue(wiphy, &rtwdev->btc.icmp_notify_work); 1014 return PACKET_ICMP; 1015 } 1016 1017 return PACKET_MAX; 1018 } 1019 1020 static void 1021 rtw89_core_tx_wake(struct rtw89_dev *rtwdev, 1022 struct rtw89_core_tx_request *tx_req) 1023 { 1024 const struct rtw89_chip_info *chip = rtwdev->chip; 1025 1026 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw)) 1027 return; 1028 1029 switch (chip->chip_id) { 1030 case RTL8852BT: 1031 if (test_bit(RTW89_FLAG_LEISURE_PS, rtwdev->flags)) 1032 goto notify; 1033 break; 1034 case RTL8852C: 1035 if (test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 1036 goto notify; 1037 break; 1038 default: 1039 if (test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags) && 1040 tx_req->tx_type == RTW89_CORE_TX_TYPE_MGMT) 1041 goto notify; 1042 break; 1043 } 1044 1045 return; 1046 1047 notify: 1048 rtw89_mac_notify_wake(rtwdev); 1049 } 1050 1051 static void 1052 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, 1053 struct rtw89_core_tx_request *tx_req) 1054 { 1055 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 1056 struct sk_buff *skb = tx_req->skb; 1057 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1058 struct ieee80211_hdr *hdr = (void *)skb->data; 1059 struct rtw89_addr_cam_entry *addr_cam; 1060 enum rtw89_core_tx_type tx_type; 1061 enum btc_pkt_type pkt_type; 1062 bool upd_wlan_hdr = false; 1063 bool is_bmc; 1064 u16 seq; 1065 1066 if (tx_req->sta) 1067 desc_info->mlo = tx_req->sta->mlo; 1068 else if (tx_req->vif) 1069 desc_info->mlo = ieee80211_vif_is_mld(tx_req->vif); 1070 1071 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 1072 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) { 1073 tx_type = rtw89_core_get_tx_type(rtwdev, skb); 1074 tx_req->tx_type = tx_type; 1075 1076 addr_cam = rtw89_get_addr_cam_of(tx_req->rtwvif_link, 1077 tx_req->rtwsta_link); 1078 if (addr_cam->valid && desc_info->mlo) 1079 upd_wlan_hdr = true; 1080 } 1081 is_bmc = (is_broadcast_ether_addr(hdr->addr1) || 1082 is_multicast_ether_addr(hdr->addr1)); 1083 1084 desc_info->seq = seq; 1085 desc_info->pkt_size = skb->len; 1086 desc_info->is_bmc = is_bmc; 1087 desc_info->wd_page = true; 1088 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM; 1089 desc_info->upd_wlan_hdr = upd_wlan_hdr; 1090 1091 switch (tx_req->tx_type) { 1092 case RTW89_CORE_TX_TYPE_MGMT: 1093 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); 1094 break; 1095 case RTW89_CORE_TX_TYPE_DATA: 1096 rtw89_core_tx_update_data_info(rtwdev, tx_req); 1097 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); 1098 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); 1099 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type); 1100 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 1101 break; 1102 case RTW89_CORE_TX_TYPE_FWCMD: 1103 rtw89_core_tx_update_h2c_info(rtwdev, tx_req); 1104 break; 1105 } 1106 } 1107 1108 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 1109 { 1110 u8 ch_dma; 1111 1112 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 1113 1114 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 1115 } 1116 1117 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1118 int qsel, unsigned int timeout) 1119 { 1120 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 1121 struct rtw89_tx_wait_info *wait; 1122 unsigned long time_left; 1123 int ret = 0; 1124 1125 wait = kzalloc(sizeof(*wait), GFP_KERNEL); 1126 if (!wait) { 1127 rtw89_core_tx_kick_off(rtwdev, qsel); 1128 return 0; 1129 } 1130 1131 init_completion(&wait->completion); 1132 rcu_assign_pointer(skb_data->wait, wait); 1133 1134 rtw89_core_tx_kick_off(rtwdev, qsel); 1135 time_left = wait_for_completion_timeout(&wait->completion, 1136 msecs_to_jiffies(timeout)); 1137 if (time_left == 0) 1138 ret = -ETIMEDOUT; 1139 else if (!wait->tx_done) 1140 ret = -EAGAIN; 1141 1142 rcu_assign_pointer(skb_data->wait, NULL); 1143 kfree_rcu(wait, rcu_head); 1144 1145 return ret; 1146 } 1147 1148 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 1149 struct sk_buff *skb, bool fwdl) 1150 { 1151 struct rtw89_core_tx_request tx_req = {0}; 1152 u32 cnt; 1153 int ret; 1154 1155 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { 1156 rtw89_debug(rtwdev, RTW89_DBG_FW, 1157 "ignore h2c due to power is off with firmware state=%d\n", 1158 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)); 1159 dev_kfree_skb(skb); 1160 return 0; 1161 } 1162 1163 tx_req.skb = skb; 1164 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; 1165 if (fwdl) 1166 tx_req.desc_info.fw_dl = true; 1167 1168 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1169 1170 if (!fwdl) 1171 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); 1172 1173 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); 1174 if (cnt == 0) { 1175 rtw89_err(rtwdev, "no tx fwcmd resource\n"); 1176 return -ENOSPC; 1177 } 1178 1179 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1180 if (ret) { 1181 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1182 return ret; 1183 } 1184 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); 1185 1186 return 0; 1187 } 1188 1189 static int rtw89_core_tx_write_link(struct rtw89_dev *rtwdev, 1190 struct rtw89_vif_link *rtwvif_link, 1191 struct rtw89_sta_link *rtwsta_link, 1192 struct sk_buff *skb, int *qsel, bool sw_mld) 1193 { 1194 struct ieee80211_sta *sta = rtwsta_link_to_sta_safe(rtwsta_link); 1195 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 1196 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 1197 struct rtw89_core_tx_request tx_req = {}; 1198 int ret; 1199 1200 tx_req.skb = skb; 1201 tx_req.vif = vif; 1202 tx_req.sta = sta; 1203 tx_req.rtwvif_link = rtwvif_link; 1204 tx_req.rtwsta_link = rtwsta_link; 1205 tx_req.desc_info.sw_mld = sw_mld; 1206 1207 rtw89_traffic_stats_accu(rtwdev, rtwvif, skb, true, true); 1208 rtw89_wow_parse_akm(rtwdev, skb); 1209 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1210 rtw89_core_tx_wake(rtwdev, &tx_req); 1211 1212 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1213 if (ret) { 1214 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1215 return ret; 1216 } 1217 1218 if (qsel) 1219 *qsel = tx_req.desc_info.qsel; 1220 1221 return 0; 1222 } 1223 1224 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1225 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) 1226 { 1227 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 1228 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 1229 struct rtw89_sta_link *rtwsta_link = NULL; 1230 struct rtw89_vif_link *rtwvif_link; 1231 1232 if (rtwsta) { 1233 rtwsta_link = rtw89_get_designated_link(rtwsta); 1234 if (unlikely(!rtwsta_link)) { 1235 rtw89_err(rtwdev, "tx: find no sta designated link\n"); 1236 return -ENOLINK; 1237 } 1238 1239 rtwvif_link = rtwsta_link->rtwvif_link; 1240 } else { 1241 rtwvif_link = rtw89_get_designated_link(rtwvif); 1242 if (unlikely(!rtwvif_link)) { 1243 rtw89_err(rtwdev, "tx: find no vif designated link\n"); 1244 return -ENOLINK; 1245 } 1246 } 1247 1248 return rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, qsel, false); 1249 } 1250 1251 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) 1252 { 1253 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | 1254 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1255 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1256 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1257 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1258 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | 1259 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | 1260 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); 1261 1262 return cpu_to_le32(dword); 1263 } 1264 1265 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info) 1266 { 1267 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1268 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1269 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1270 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1271 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1272 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); 1273 1274 return cpu_to_le32(dword); 1275 } 1276 1277 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info) 1278 { 1279 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1280 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1281 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type); 1282 1283 return cpu_to_le32(dword); 1284 } 1285 1286 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) 1287 { 1288 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | 1289 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | 1290 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) | 1291 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id); 1292 1293 return cpu_to_le32(dword); 1294 } 1295 1296 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) 1297 { 1298 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | 1299 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | 1300 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); 1301 1302 return cpu_to_le32(dword); 1303 } 1304 1305 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info) 1306 { 1307 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1308 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1309 1310 return cpu_to_le32(dword); 1311 } 1312 1313 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info) 1314 { 1315 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1316 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1317 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1318 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1319 1320 return cpu_to_le32(dword); 1321 } 1322 1323 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info) 1324 { 1325 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) | 1326 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); 1327 1328 return cpu_to_le32(dword); 1329 } 1330 1331 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) 1332 { 1333 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | 1334 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | 1335 FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1336 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1337 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1338 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1339 1340 return cpu_to_le32(dword); 1341 } 1342 1343 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info) 1344 { 1345 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1346 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1347 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1348 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) | 1349 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) | 1350 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0); 1351 1352 return cpu_to_le32(dword); 1353 } 1354 1355 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) 1356 { 1357 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | 1358 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1359 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, 1360 desc_info->data_retry_lowest_rate); 1361 1362 return cpu_to_le32(dword); 1363 } 1364 1365 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) 1366 { 1367 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1368 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | 1369 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | 1370 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1371 1372 return cpu_to_le32(dword); 1373 } 1374 1375 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info) 1376 { 1377 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1378 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1379 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1380 1381 return cpu_to_le32(dword); 1382 } 1383 1384 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) 1385 { 1386 bool rts_en = !desc_info->is_bmc; 1387 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) | 1388 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1); 1389 1390 return cpu_to_le32(dword); 1391 } 1392 1393 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 1394 struct rtw89_tx_desc_info *desc_info, 1395 void *txdesc) 1396 { 1397 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; 1398 struct rtw89_txwd_info *txwd_info; 1399 1400 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); 1401 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1402 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1403 1404 if (!desc_info->en_wd_info) 1405 return; 1406 1407 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1408 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); 1409 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1410 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); 1411 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1412 1413 } 1414 EXPORT_SYMBOL(rtw89_core_fill_txdesc); 1415 1416 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 1417 struct rtw89_tx_desc_info *desc_info, 1418 void *txdesc) 1419 { 1420 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc; 1421 struct rtw89_txwd_info *txwd_info; 1422 1423 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info); 1424 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info); 1425 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1426 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1427 if (desc_info->sec_en) { 1428 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info); 1429 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info); 1430 } 1431 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info); 1432 1433 if (!desc_info->en_wd_info) 1434 return; 1435 1436 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1437 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info); 1438 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1439 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info); 1440 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1441 } 1442 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1); 1443 1444 static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info) 1445 { 1446 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1447 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) | 1448 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) | 1449 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1450 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page); 1451 1452 return cpu_to_le32(dword); 1453 } 1454 1455 static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info) 1456 { 1457 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1458 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1459 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type); 1460 1461 return cpu_to_le32(dword); 1462 } 1463 1464 static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info) 1465 { 1466 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) | 1467 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) | 1468 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) | 1469 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) | 1470 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) | 1471 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id); 1472 1473 return cpu_to_le32(dword); 1474 } 1475 1476 static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info) 1477 { 1478 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq) | 1479 FIELD_PREP(BE_TXD_BODY3_MLO_FLAG, desc_info->mlo) | 1480 FIELD_PREP(BE_TXD_BODY3_IS_MLD_SW_EN, desc_info->sw_mld); 1481 1482 return cpu_to_le32(dword); 1483 } 1484 1485 static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info) 1486 { 1487 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1488 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1489 1490 return cpu_to_le32(dword); 1491 } 1492 1493 static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info) 1494 { 1495 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1496 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1497 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1498 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1499 1500 return cpu_to_le32(dword); 1501 } 1502 1503 static __le32 rtw89_build_txwd_body6_v2(struct rtw89_tx_desc_info *desc_info) 1504 { 1505 u32 dword = FIELD_PREP(BE_TXD_BODY6_UPD_WLAN_HDR, desc_info->upd_wlan_hdr); 1506 1507 return cpu_to_le32(dword); 1508 } 1509 1510 static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info) 1511 { 1512 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) | 1513 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) | 1514 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) | 1515 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate); 1516 1517 return cpu_to_le32(dword); 1518 } 1519 1520 static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info) 1521 { 1522 u32 dword = FIELD_PREP(BE_TXD_INFO0_DATA_STBC, desc_info->stbc) | 1523 FIELD_PREP(BE_TXD_INFO0_DATA_LDPC, desc_info->ldpc) | 1524 FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1525 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port); 1526 1527 return cpu_to_le32(dword); 1528 } 1529 1530 static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info) 1531 { 1532 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) | 1533 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1534 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE, 1535 desc_info->data_retry_lowest_rate); 1536 1537 return cpu_to_le32(dword); 1538 } 1539 1540 static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info) 1541 { 1542 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1543 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1544 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1545 1546 return cpu_to_le32(dword); 1547 } 1548 1549 static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info) 1550 { 1551 bool rts_en = !desc_info->is_bmc; 1552 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, rts_en) | 1553 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1); 1554 1555 return cpu_to_le32(dword); 1556 } 1557 1558 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 1559 struct rtw89_tx_desc_info *desc_info, 1560 void *txdesc) 1561 { 1562 struct rtw89_txwd_body_v2 *txwd_body = txdesc; 1563 struct rtw89_txwd_info_v2 *txwd_info; 1564 1565 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info); 1566 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info); 1567 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info); 1568 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info); 1569 if (desc_info->sec_en) { 1570 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info); 1571 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info); 1572 } 1573 txwd_body->dword6 = rtw89_build_txwd_body6_v2(desc_info); 1574 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info); 1575 1576 if (!desc_info->en_wd_info) 1577 return; 1578 1579 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1); 1580 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info); 1581 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info); 1582 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info); 1583 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info); 1584 } 1585 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2); 1586 1587 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info) 1588 { 1589 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1590 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1591 RTW89_CORE_RX_TYPE_FWDL : 1592 RTW89_CORE_RX_TYPE_H2C); 1593 1594 return cpu_to_le32(dword); 1595 } 1596 1597 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 1598 struct rtw89_tx_desc_info *desc_info, 1599 void *txdesc) 1600 { 1601 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc; 1602 1603 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info); 1604 } 1605 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1); 1606 1607 static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info) 1608 { 1609 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1610 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1611 RTW89_CORE_RX_TYPE_FWDL : 1612 RTW89_CORE_RX_TYPE_H2C); 1613 1614 return cpu_to_le32(dword); 1615 } 1616 1617 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 1618 struct rtw89_tx_desc_info *desc_info, 1619 void *txdesc) 1620 { 1621 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc; 1622 1623 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info); 1624 } 1625 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2); 1626 1627 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, 1628 struct sk_buff *skb, 1629 struct rtw89_rx_phy_ppdu *phy_ppdu) 1630 { 1631 const struct rtw89_chip_info *chip = rtwdev->chip; 1632 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data; 1633 const struct rtw89_rxinfo_user *user; 1634 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 1635 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE; 1636 bool rx_cnt_valid = false; 1637 bool invalid = false; 1638 u8 plcp_size = 0; 1639 u8 *phy_sts; 1640 u8 usr_num; 1641 int i; 1642 1643 if (chip_gen == RTW89_CHIP_BE) { 1644 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1); 1645 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1; 1646 } 1647 1648 if (invalid) 1649 return -EINVAL; 1650 1651 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD); 1652 if (chip_gen == RTW89_CHIP_BE) { 1653 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3; 1654 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1); 1655 } else { 1656 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3; 1657 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM); 1658 } 1659 if (usr_num > chip->ppdu_max_usr) { 1660 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n", 1661 usr_num); 1662 return -EINVAL; 1663 } 1664 1665 for (i = 0; i < usr_num; i++) { 1666 user = &rxinfo->user[i]; 1667 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID)) 1668 continue; 1669 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set 1670 * by hardware, so update mac_id by rxinfo_user[].mac_id. 1671 */ 1672 if (chip_gen == RTW89_CHIP_BE) 1673 phy_ppdu->mac_id = 1674 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID); 1675 phy_ppdu->has_data = 1676 le32_get_bits(user->w0, RTW89_RXINFO_USER_DATA); 1677 phy_ppdu->has_bcn = 1678 le32_get_bits(user->w0, RTW89_RXINFO_USER_BCN); 1679 break; 1680 } 1681 1682 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; 1683 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; 1684 /* 8-byte alignment */ 1685 if (usr_num & BIT(0)) 1686 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; 1687 if (rx_cnt_valid) 1688 phy_sts += rx_cnt_size; 1689 phy_sts += plcp_size; 1690 1691 if (phy_sts > skb->data + skb->len) 1692 return -EINVAL; 1693 1694 phy_ppdu->buf = phy_sts; 1695 phy_ppdu->len = skb->data + skb->len - phy_sts; 1696 1697 return 0; 1698 } 1699 1700 static u8 rtw89_get_data_rate_nss(struct rtw89_dev *rtwdev, u16 data_rate) 1701 { 1702 u8 data_rate_mode; 1703 1704 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 1705 switch (data_rate_mode) { 1706 case DATA_RATE_MODE_NON_HT: 1707 return 1; 1708 case DATA_RATE_MODE_HT: 1709 return rtw89_get_data_ht_nss(rtwdev, data_rate) + 1; 1710 case DATA_RATE_MODE_VHT: 1711 case DATA_RATE_MODE_HE: 1712 case DATA_RATE_MODE_EHT: 1713 return rtw89_get_data_nss(rtwdev, data_rate) + 1; 1714 default: 1715 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1716 return 0; 1717 } 1718 } 1719 1720 static void rtw89_core_rx_process_phy_ppdu_iter(void *data, 1721 struct ieee80211_sta *sta) 1722 { 1723 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; 1724 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 1725 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 1726 struct rtw89_hal *hal = &rtwdev->hal; 1727 struct rtw89_sta_link *rtwsta_link; 1728 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 1729 u8 ant_pos = U8_MAX; 1730 u8 evm_pos = 0; 1731 int i; 1732 1733 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, phy_ppdu->phy_idx); 1734 if (unlikely(!rtwsta_link)) 1735 return; 1736 1737 if (rtwsta_link->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self) 1738 return; 1739 1740 if (hal->ant_diversity && hal->antenna_rx) { 1741 ant_pos = __ffs(hal->antenna_rx); 1742 evm_pos = ant_pos; 1743 } 1744 1745 ewma_rssi_add(&rtwsta_link->avg_rssi, phy_ppdu->rssi_avg); 1746 1747 if (ant_pos < ant_num) { 1748 ewma_rssi_add(&rtwsta_link->rssi[ant_pos], phy_ppdu->rssi[0]); 1749 } else { 1750 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 1751 ewma_rssi_add(&rtwsta_link->rssi[i], phy_ppdu->rssi[i]); 1752 } 1753 1754 if (phy_ppdu->ofdm.has && (phy_ppdu->has_data || phy_ppdu->has_bcn)) { 1755 ewma_snr_add(&rtwsta_link->avg_snr, phy_ppdu->ofdm.avg_snr); 1756 if (rtw89_get_data_rate_nss(rtwdev, phy_ppdu->rate) == 1) { 1757 ewma_evm_add(&rtwsta_link->evm_1ss, phy_ppdu->ofdm.evm_min); 1758 } else { 1759 ewma_evm_add(&rtwsta_link->evm_min[evm_pos], 1760 phy_ppdu->ofdm.evm_min); 1761 ewma_evm_add(&rtwsta_link->evm_max[evm_pos], 1762 phy_ppdu->ofdm.evm_max); 1763 } 1764 } 1765 } 1766 1767 #define VAR_LEN 0xff 1768 #define VAR_LEN_UNIT 8 1769 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, 1770 const struct rtw89_phy_sts_iehdr *iehdr) 1771 { 1772 static const u8 physts_ie_len_tabs[RTW89_CHIP_GEN_NUM][32] = { 1773 [RTW89_CHIP_AX] = { 1774 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1775 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1776 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1777 }, 1778 [RTW89_CHIP_BE] = { 1779 32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1780 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 88, 56, VAR_LEN, 1781 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1782 }, 1783 }; 1784 const u8 *physts_ie_len_tab; 1785 u16 ie_len; 1786 u8 ie; 1787 1788 physts_ie_len_tab = physts_ie_len_tabs[rtwdev->chip->chip_gen]; 1789 1790 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1791 if (physts_ie_len_tab[ie] != VAR_LEN) 1792 ie_len = physts_ie_len_tab[ie]; 1793 else 1794 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT; 1795 1796 return ie_len; 1797 } 1798 1799 static void rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev *rtwdev, 1800 const struct rtw89_phy_sts_iehdr *iehdr, 1801 struct rtw89_rx_phy_ppdu *phy_ppdu) 1802 { 1803 const struct rtw89_phy_sts_ie01_v2 *ie; 1804 u8 *rpl_fd = phy_ppdu->rpl_fd; 1805 1806 ie = (const struct rtw89_phy_sts_ie01_v2 *)iehdr; 1807 rpl_fd[RF_PATH_A] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_A); 1808 rpl_fd[RF_PATH_B] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_B); 1809 rpl_fd[RF_PATH_C] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_C); 1810 rpl_fd[RF_PATH_D] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_D); 1811 1812 phy_ppdu->bw_idx = le32_get_bits(ie->w5, RTW89_PHY_STS_IE01_V2_W5_BW_IDX); 1813 } 1814 1815 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, 1816 const struct rtw89_phy_sts_iehdr *iehdr, 1817 struct rtw89_rx_phy_ppdu *phy_ppdu) 1818 { 1819 const struct rtw89_phy_sts_ie01 *ie = (const struct rtw89_phy_sts_ie01 *)iehdr; 1820 s16 cfo; 1821 u32 t; 1822 1823 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX); 1824 1825 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 1826 phy_ppdu->ldpc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_LDPC); 1827 phy_ppdu->stbc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_STBC); 1828 } 1829 1830 if (!phy_ppdu->hdr_2_en) 1831 phy_ppdu->rx_path_en = 1832 le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RX_PATH_EN); 1833 1834 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) 1835 return; 1836 1837 if (!phy_ppdu->to_self) 1838 return; 1839 1840 phy_ppdu->rpl_avg = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RSSI_AVG_FD); 1841 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR); 1842 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX); 1843 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN); 1844 phy_ppdu->ofdm.has = true; 1845 1846 /* sign conversion for S(12,2) */ 1847 if (rtwdev->chip->cfo_src_fd) { 1848 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO); 1849 cfo = sign_extend32(t, 11); 1850 } else { 1851 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO); 1852 cfo = sign_extend32(t, 11); 1853 } 1854 1855 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); 1856 1857 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1858 rtw89_core_parse_phy_status_ie01_v2(rtwdev, iehdr, phy_ppdu); 1859 } 1860 1861 static void rtw89_core_parse_phy_status_ie00(struct rtw89_dev *rtwdev, 1862 const struct rtw89_phy_sts_iehdr *iehdr, 1863 struct rtw89_rx_phy_ppdu *phy_ppdu) 1864 { 1865 const struct rtw89_phy_sts_ie00 *ie = (const struct rtw89_phy_sts_ie00 *)iehdr; 1866 u16 tmp_rpl; 1867 1868 tmp_rpl = le32_get_bits(ie->w0, RTW89_PHY_STS_IE00_W0_RPL); 1869 phy_ppdu->rpl_avg = tmp_rpl >> 1; 1870 } 1871 1872 static void rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev *rtwdev, 1873 const struct rtw89_phy_sts_iehdr *iehdr, 1874 struct rtw89_rx_phy_ppdu *phy_ppdu) 1875 { 1876 const struct rtw89_phy_sts_ie00_v2 *ie; 1877 u8 *rpl_path = phy_ppdu->rpl_path; 1878 u16 tmp_rpl[RF_PATH_MAX]; 1879 u8 i; 1880 1881 ie = (const struct rtw89_phy_sts_ie00_v2 *)iehdr; 1882 tmp_rpl[RF_PATH_A] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_A); 1883 tmp_rpl[RF_PATH_B] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_B); 1884 tmp_rpl[RF_PATH_C] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_C); 1885 tmp_rpl[RF_PATH_D] = le32_get_bits(ie->w5, RTW89_PHY_STS_IE00_V2_W5_RPL_TD_D); 1886 1887 for (i = 0; i < RF_PATH_MAX; i++) 1888 rpl_path[i] = tmp_rpl[i] >> 1; 1889 } 1890 1891 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, 1892 const struct rtw89_phy_sts_iehdr *iehdr, 1893 struct rtw89_rx_phy_ppdu *phy_ppdu) 1894 { 1895 u8 ie; 1896 1897 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1898 1899 switch (ie) { 1900 case RTW89_PHYSTS_IE00_CMN_CCK: 1901 rtw89_core_parse_phy_status_ie00(rtwdev, iehdr, phy_ppdu); 1902 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1903 rtw89_core_parse_phy_status_ie00_v2(rtwdev, iehdr, phy_ppdu); 1904 break; 1905 case RTW89_PHYSTS_IE01_CMN_OFDM: 1906 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu); 1907 break; 1908 default: 1909 break; 1910 } 1911 1912 return 0; 1913 } 1914 1915 static void rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu *phy_ppdu) 1916 { 1917 #if defined(__linux__) 1918 const struct rtw89_phy_sts_hdr_v2 *hdr = phy_ppdu->buf + PHY_STS_HDR_LEN; 1919 #elif defined(__FreeBSD__) 1920 const struct rtw89_phy_sts_hdr_v2 *hdr = (void *)((u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN); 1921 #endif 1922 1923 phy_ppdu->rx_path_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_V2_W0_PATH_EN); 1924 } 1925 1926 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) 1927 { 1928 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1929 u8 *rssi = phy_ppdu->rssi; 1930 1931 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP); 1932 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG); 1933 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A); 1934 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B); 1935 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C); 1936 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D); 1937 1938 phy_ppdu->hdr_2_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_HDR_2_EN); 1939 if (phy_ppdu->hdr_2_en) 1940 rtw89_core_update_phy_ppdu_hdr_v2(phy_ppdu); 1941 } 1942 1943 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, 1944 struct rtw89_rx_phy_ppdu *phy_ppdu) 1945 { 1946 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1947 u32 len_from_header; 1948 bool physts_valid; 1949 1950 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID); 1951 if (!physts_valid) 1952 return -EINVAL; 1953 1954 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3; 1955 1956 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1957 len_from_header += PHY_STS_HDR_LEN; 1958 1959 if (len_from_header != phy_ppdu->len) { 1960 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n"); 1961 return -EINVAL; 1962 } 1963 rtw89_core_update_phy_ppdu(phy_ppdu); 1964 1965 return 0; 1966 } 1967 1968 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, 1969 struct rtw89_rx_phy_ppdu *phy_ppdu) 1970 { 1971 u16 ie_len; 1972 #if defined(__linux__) 1973 void *pos, *end; 1974 #elif defined(__FreeBSD__) 1975 u8 *pos, *end; 1976 #endif 1977 1978 /* mark invalid reports and bypass them */ 1979 if (phy_ppdu->ie < RTW89_CCK_PKT) 1980 return -EINVAL; 1981 1982 #if defined(__linux__) 1983 pos = phy_ppdu->buf + PHY_STS_HDR_LEN; 1984 if (phy_ppdu->hdr_2_en) 1985 pos += PHY_STS_HDR_LEN; 1986 end = phy_ppdu->buf + phy_ppdu->len; 1987 #elif defined(__FreeBSD__) 1988 pos = (u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN; 1989 end = (u8 *)phy_ppdu->buf + phy_ppdu->len; 1990 #endif 1991 while (pos < end) { 1992 #if defined(__linux__) 1993 const struct rtw89_phy_sts_iehdr *iehdr = pos; 1994 #elif defined(__FreeBSD__) 1995 const struct rtw89_phy_sts_iehdr *iehdr = (void *)pos; 1996 #endif 1997 1998 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr); 1999 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu); 2000 pos += ie_len; 2001 if (pos > end || ie_len == 0) { 2002 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2003 "phy status parse failed\n"); 2004 return -EINVAL; 2005 } 2006 } 2007 2008 rtw89_chip_convert_rpl_to_rssi(rtwdev, phy_ppdu); 2009 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu); 2010 2011 return 0; 2012 } 2013 2014 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, 2015 struct rtw89_rx_phy_ppdu *phy_ppdu) 2016 { 2017 int ret; 2018 2019 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); 2020 if (ret) 2021 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); 2022 else 2023 phy_ppdu->valid = true; 2024 2025 ieee80211_iterate_stations_atomic(rtwdev->hw, 2026 rtw89_core_rx_process_phy_ppdu_iter, 2027 phy_ppdu); 2028 } 2029 2030 static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev, 2031 u8 desc_info_gi, 2032 bool rx_status) 2033 { 2034 switch (desc_info_gi) { 2035 case RTW89_GILTF_SGI_4XHE08: 2036 case RTW89_GILTF_2XHE08: 2037 case RTW89_GILTF_1XHE08: 2038 return NL80211_RATE_INFO_HE_GI_0_8; 2039 case RTW89_GILTF_2XHE16: 2040 case RTW89_GILTF_1XHE16: 2041 return NL80211_RATE_INFO_HE_GI_1_6; 2042 case RTW89_GILTF_LGI_4XHE32: 2043 return NL80211_RATE_INFO_HE_GI_3_2; 2044 default: 2045 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 2046 if (rx_status) 2047 return NL80211_RATE_INFO_HE_GI_3_2; 2048 return U8_MAX; 2049 } 2050 } 2051 2052 static u8 rtw89_rxdesc_to_nl_eht_gi(struct rtw89_dev *rtwdev, 2053 u8 desc_info_gi, 2054 bool rx_status) 2055 { 2056 switch (desc_info_gi) { 2057 case RTW89_GILTF_SGI_4XHE08: 2058 case RTW89_GILTF_2XHE08: 2059 case RTW89_GILTF_1XHE08: 2060 return NL80211_RATE_INFO_EHT_GI_0_8; 2061 case RTW89_GILTF_2XHE16: 2062 case RTW89_GILTF_1XHE16: 2063 return NL80211_RATE_INFO_EHT_GI_1_6; 2064 case RTW89_GILTF_LGI_4XHE32: 2065 return NL80211_RATE_INFO_EHT_GI_3_2; 2066 default: 2067 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 2068 if (rx_status) 2069 return NL80211_RATE_INFO_EHT_GI_3_2; 2070 return U8_MAX; 2071 } 2072 } 2073 2074 static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev, 2075 u8 desc_info_gi, 2076 bool rx_status, bool eht) 2077 { 2078 return eht ? rtw89_rxdesc_to_nl_eht_gi(rtwdev, desc_info_gi, rx_status) : 2079 rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info_gi, rx_status); 2080 } 2081 2082 static 2083 bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf, 2084 bool eht) 2085 { 2086 if (eht) 2087 return status->eht.gi == gi_ltf; 2088 2089 return status->he_gi == gi_ltf; 2090 } 2091 2092 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, 2093 struct rtw89_rx_desc_info *desc_info, 2094 struct ieee80211_rx_status *status) 2095 { 2096 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2097 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; 2098 bool eht = false; 2099 u16 data_rate; 2100 bool ret; 2101 2102 data_rate = desc_info->data_rate; 2103 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 2104 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 2105 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 2106 /* rate_idx is still hardware value here */ 2107 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 2108 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 2109 } else if (data_rate_mode == DATA_RATE_MODE_VHT || 2110 data_rate_mode == DATA_RATE_MODE_HE || 2111 data_rate_mode == DATA_RATE_MODE_EHT) { 2112 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2113 } else { 2114 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 2115 } 2116 2117 eht = data_rate_mode == DATA_RATE_MODE_EHT; 2118 bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 2119 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, false, eht); 2120 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && 2121 status->rate_idx == rate_idx && 2122 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) && 2123 status->bw == bw; 2124 2125 return ret; 2126 } 2127 2128 struct rtw89_vif_rx_stats_iter_data { 2129 struct rtw89_dev *rtwdev; 2130 struct rtw89_rx_phy_ppdu *phy_ppdu; 2131 struct rtw89_rx_desc_info *desc_info; 2132 struct sk_buff *skb; 2133 const u8 *bssid; 2134 }; 2135 2136 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev, 2137 struct rtw89_vif_link *rtwvif_link, 2138 struct ieee80211_bss_conf *bss_conf, 2139 struct sk_buff *skb) 2140 { 2141 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data; 2142 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 2143 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 2144 u8 *pos, *end, type, tf_bw; 2145 u16 aid, tf_rua; 2146 2147 if (!ether_addr_equal(bss_conf->bssid, tf->ta) || 2148 rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION || 2149 rtwvif_link->net_type == RTW89_NET_TYPE_NO_LINK) 2150 return; 2151 2152 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK); 2153 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR) 2154 return; 2155 2156 end = (u8 *)tf + skb->len; 2157 pos = tf->variable; 2158 2159 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) { 2160 aid = RTW89_GET_TF_USER_INFO_AID12(pos); 2161 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos); 2162 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK); 2163 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2164 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n", 2165 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos), 2166 tf_rua, tf_bw); 2167 2168 if (aid == RTW89_TF_PAD) 2169 break; 2170 2171 if (aid == vif->cfg.aid) { 2172 enum nl80211_he_ru_alloc rua; 2173 2174 rtwvif->stats.rx_tf_acc++; 2175 rtwdev->stats.rx_tf_acc++; 2176 2177 /* The following only required for HE trigger frame, but we 2178 * cannot use UL HE-SIG-A2 reserved subfield to identify it 2179 * since some 11ax APs will fill it with all 0s, which will 2180 * be misunderstood as EHT trigger frame. 2181 */ 2182 if (bss_conf->eht_support) 2183 break; 2184 2185 rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1); 2186 2187 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ && 2188 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106) 2189 rtwvif_link->pwr_diff_en = true; 2190 break; 2191 } 2192 2193 pos += RTW89_TF_BASIC_USER_INFO_SZ; 2194 } 2195 } 2196 2197 static void rtw89_cancel_6ghz_probe_work(struct wiphy *wiphy, struct wiphy_work *work) 2198 { 2199 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2200 cancel_6ghz_probe_work); 2201 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 2202 struct rtw89_pktofld_info *info; 2203 2204 lockdep_assert_wiphy(wiphy); 2205 2206 if (!rtwdev->scanning) 2207 return; 2208 2209 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 2210 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload)) 2211 continue; 2212 2213 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id); 2214 2215 /* Don't delete/free info from pkt_list at this moment. Let it 2216 * be deleted/freed in rtw89_release_pkt_list() after scanning, 2217 * since if during scanning, pkt_list is accessed in bottom half. 2218 */ 2219 } 2220 } 2221 2222 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev, 2223 struct sk_buff *skb) 2224 { 2225 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 2226 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 2227 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 2228 struct rtw89_pktofld_info *info; 2229 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie; 2230 bool queue_work = false; 2231 2232 if (rx_status->band != NL80211_BAND_6GHZ) 2233 return; 2234 2235 if (unlikely(!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ)))) { 2236 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rx on unsupported 6 GHz\n"); 2237 return; 2238 } 2239 2240 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len); 2241 2242 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 2243 if (ether_addr_equal(info->bssid, mgmt->bssid)) { 2244 info->cancel = true; 2245 queue_work = true; 2246 continue; 2247 } 2248 2249 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0) 2250 continue; 2251 2252 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) { 2253 info->cancel = true; 2254 queue_work = true; 2255 } 2256 } 2257 2258 if (queue_work) 2259 wiphy_work_queue(rtwdev->hw->wiphy, &rtwdev->cancel_6ghz_probe_work); 2260 } 2261 2262 static void rtw89_vif_sync_bcn_tsf(struct rtw89_vif_link *rtwvif_link, 2263 struct ieee80211_hdr *hdr, size_t len) 2264 { 2265 struct ieee80211_mgmt *mgmt = (typeof(mgmt))hdr; 2266 2267 if (len < offsetof(typeof(*mgmt), u.beacon.variable)) 2268 return; 2269 2270 WRITE_ONCE(rtwvif_link->sync_bcn_tsf, le64_to_cpu(mgmt->u.beacon.timestamp)); 2271 } 2272 2273 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 2274 struct ieee80211_vif *vif) 2275 { 2276 struct rtw89_vif_rx_stats_iter_data *iter_data = data; 2277 struct rtw89_dev *rtwdev = iter_data->rtwdev; 2278 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 2279 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 2280 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 2281 struct sk_buff *skb = iter_data->skb; 2282 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 2283 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2284 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu; 2285 bool is_mld = ieee80211_vif_is_mld(vif); 2286 struct ieee80211_bss_conf *bss_conf; 2287 struct rtw89_vif_link *rtwvif_link; 2288 const u8 *bssid = iter_data->bssid; 2289 2290 if (rtwdev->scanning && 2291 (ieee80211_is_beacon(hdr->frame_control) || 2292 ieee80211_is_probe_resp(hdr->frame_control))) 2293 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb); 2294 2295 rcu_read_lock(); 2296 2297 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, desc_info->bb_sel); 2298 if (unlikely(!rtwvif_link)) 2299 goto out; 2300 2301 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 2302 if (!bss_conf->bssid) 2303 goto out; 2304 2305 if (ieee80211_is_trigger(hdr->frame_control)) { 2306 rtw89_stats_trigger_frame(rtwdev, rtwvif_link, bss_conf, skb); 2307 goto out; 2308 } 2309 2310 if (!ether_addr_equal(bss_conf->bssid, bssid)) 2311 goto out; 2312 2313 if (is_mld) { 2314 rx_status->link_valid = true; 2315 rx_status->link_id = rtwvif_link->link_id; 2316 } 2317 2318 if (ieee80211_is_beacon(hdr->frame_control)) { 2319 if (vif->type == NL80211_IFTYPE_STATION && 2320 !test_bit(RTW89_FLAG_WOWLAN, rtwdev->flags)) { 2321 rtw89_vif_sync_bcn_tsf(rtwvif_link, hdr, skb->len); 2322 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu); 2323 } 2324 pkt_stat->beacon_nr++; 2325 2326 if (phy_ppdu) { 2327 ewma_rssi_add(&rtwdev->phystat.bcn_rssi, phy_ppdu->rssi_avg); 2328 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 2329 rtwvif_link->bcn_bw_idx = phy_ppdu->bw_idx; 2330 } 2331 2332 pkt_stat->beacon_rate = desc_info->data_rate; 2333 } 2334 2335 if (!ether_addr_equal(bss_conf->addr, hdr->addr1)) 2336 goto out; 2337 2338 if (desc_info->data_rate < RTW89_HW_RATE_NR) 2339 pkt_stat->rx_rate_cnt[desc_info->data_rate]++; 2340 2341 rtw89_traffic_stats_accu(rtwdev, rtwvif, skb, false, false); 2342 2343 out: 2344 rcu_read_unlock(); 2345 } 2346 2347 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, 2348 struct rtw89_rx_phy_ppdu *phy_ppdu, 2349 struct rtw89_rx_desc_info *desc_info, 2350 struct sk_buff *skb) 2351 { 2352 struct rtw89_vif_rx_stats_iter_data iter_data; 2353 2354 rtw89_traffic_stats_accu(rtwdev, NULL, skb, true, false); 2355 2356 iter_data.rtwdev = rtwdev; 2357 iter_data.phy_ppdu = phy_ppdu; 2358 iter_data.desc_info = desc_info; 2359 iter_data.skb = skb; 2360 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); 2361 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); 2362 } 2363 2364 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, 2365 struct ieee80211_rx_status *status) 2366 { 2367 const struct rtw89_chan_rcd *rcd = 2368 rtw89_chan_rcd_get(rtwdev, RTW89_CHANCTX_0); 2369 u16 chan = rcd->prev_primary_channel; 2370 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type); 2371 2372 if (status->band != NL80211_BAND_2GHZ && 2373 status->encoding == RX_ENC_LEGACY && 2374 status->rate_idx < RTW89_HW_RATE_OFDM6) { 2375 status->freq = ieee80211_channel_to_frequency(chan, band); 2376 status->band = band; 2377 } 2378 } 2379 2380 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) 2381 { 2382 if (rx_status->band == NL80211_BAND_2GHZ || 2383 rx_status->encoding != RX_ENC_LEGACY) 2384 return; 2385 2386 /* Some control frames' freq(ACKs in this case) are reported wrong due 2387 * to FW notify timing, set to lowest rate to prevent overflow. 2388 */ 2389 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) { 2390 rx_status->rate_idx = 0; 2391 return; 2392 } 2393 2394 /* No 4 CCK rates for non-2G */ 2395 rx_status->rate_idx -= 4; 2396 } 2397 2398 static 2399 void rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev *rtwdev, 2400 struct ieee80211_rx_status *rx_status, 2401 struct rtw89_rx_phy_ppdu *phy_ppdu) 2402 { 2403 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 2404 return; 2405 2406 if (!phy_ppdu) 2407 return; 2408 2409 if (phy_ppdu->ldpc) 2410 rx_status->enc_flags |= RX_ENC_FLAG_LDPC; 2411 if (phy_ppdu->stbc) 2412 rx_status->enc_flags |= u8_encode_bits(1, RX_ENC_FLAG_STBC_MASK); 2413 } 2414 2415 static const u8 rx_status_bw_to_radiotap_eht_usig[] = { 2416 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ, 2417 [RATE_INFO_BW_5] = U8_MAX, 2418 [RATE_INFO_BW_10] = U8_MAX, 2419 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ, 2420 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ, 2421 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ, 2422 [RATE_INFO_BW_HE_RU] = U8_MAX, 2423 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1, 2424 [RATE_INFO_BW_EHT_RU] = U8_MAX, 2425 }; 2426 2427 static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev, 2428 struct sk_buff *skb, 2429 struct ieee80211_rx_status *rx_status) 2430 { 2431 struct ieee80211_radiotap_eht_usig *usig; 2432 struct ieee80211_radiotap_eht *eht; 2433 struct ieee80211_radiotap_tlv *tlv; 2434 int eht_len = struct_size(eht, user_info, 1); 2435 int usig_len = sizeof(*usig); 2436 int len; 2437 u8 bw; 2438 2439 len = sizeof(*tlv) + ALIGN(eht_len, 4) + 2440 sizeof(*tlv) + ALIGN(usig_len, 4); 2441 2442 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END; 2443 skb_reset_mac_header(skb); 2444 2445 /* EHT */ 2446 tlv = skb_push(skb, len); 2447 memset(tlv, 0, len); 2448 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT); 2449 tlv->len = cpu_to_le16(eht_len); 2450 2451 eht = (struct ieee80211_radiotap_eht *)tlv->data; 2452 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI); 2453 eht->data[0] = 2454 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI); 2455 2456 eht->user_info[0] = 2457 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN | 2458 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O | 2459 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN); 2460 eht->user_info[0] |= 2461 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) | 2462 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O); 2463 if (rx_status->enc_flags & RX_ENC_FLAG_LDPC) 2464 eht->user_info[0] |= 2465 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_CODING); 2466 2467 /* U-SIG */ 2468 #if defined(__linux__) 2469 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4); 2470 #elif defined(__FreeBSD__) 2471 tlv = (void *)((u8 *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4)); 2472 #endif 2473 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG); 2474 tlv->len = cpu_to_le16(usig_len); 2475 2476 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig)) 2477 return; 2478 2479 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw]; 2480 if (bw == U8_MAX) 2481 return; 2482 2483 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data; 2484 usig->common = 2485 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) | 2486 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW); 2487 } 2488 2489 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev, 2490 struct sk_buff *skb, 2491 struct ieee80211_rx_status *rx_status) 2492 { 2493 static const struct ieee80211_radiotap_he known_he = { 2494 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 2495 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN | 2496 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN | 2497 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2498 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2499 }; 2500 struct ieee80211_radiotap_he *he; 2501 2502 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 2503 return; 2504 2505 if (rx_status->encoding == RX_ENC_HE) { 2506 rx_status->flag |= RX_FLAG_RADIOTAP_HE; 2507 he = skb_push(skb, sizeof(*he)); 2508 *he = known_he; 2509 } else if (rx_status->encoding == RX_ENC_EHT) { 2510 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status); 2511 } 2512 } 2513 2514 static void rtw89_core_validate_rx_signal(struct ieee80211_rx_status *rx_status) 2515 { 2516 if (!rx_status->signal) 2517 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 2518 } 2519 2520 static void rtw89_core_update_rx_freq_from_ie(struct rtw89_dev *rtwdev, 2521 struct sk_buff *skb, 2522 struct ieee80211_rx_status *rx_status) 2523 { 2524 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 2525 size_t hdr_len, ielen; 2526 u8 *variable; 2527 int chan; 2528 2529 if (!rtwdev->chip->rx_freq_frome_ie) 2530 return; 2531 2532 if (!rtwdev->scanning) 2533 return; 2534 2535 if (ieee80211_is_beacon(mgmt->frame_control)) { 2536 variable = mgmt->u.beacon.variable; 2537 hdr_len = offsetof(struct ieee80211_mgmt, 2538 u.beacon.variable); 2539 } else if (ieee80211_is_probe_resp(mgmt->frame_control)) { 2540 variable = mgmt->u.probe_resp.variable; 2541 hdr_len = offsetof(struct ieee80211_mgmt, 2542 u.probe_resp.variable); 2543 } else { 2544 return; 2545 } 2546 2547 if (skb->len > hdr_len) 2548 ielen = skb->len - hdr_len; 2549 else 2550 return; 2551 2552 /* The parsing code for both 2GHz and 5GHz bands is the same in this 2553 * function. 2554 */ 2555 chan = cfg80211_get_ies_channel_number(variable, ielen, NL80211_BAND_2GHZ); 2556 if (chan == -1) 2557 return; 2558 2559 rx_status->band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 2560 rx_status->freq = ieee80211_channel_to_frequency(chan, rx_status->band); 2561 } 2562 2563 static void rtw89_core_correct_mcc_chan(struct rtw89_dev *rtwdev, 2564 struct rtw89_rx_desc_info *desc_info, 2565 struct ieee80211_rx_status *rx_status, 2566 struct rtw89_rx_phy_ppdu *phy_ppdu) 2567 { 2568 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 2569 struct rtw89_vif_link *rtwvif_link; 2570 struct rtw89_sta_link *rtwsta_link; 2571 const struct rtw89_chan *chan; 2572 u8 mac_id = desc_info->mac_id; 2573 enum rtw89_entity_mode mode; 2574 enum nl80211_band band; 2575 2576 mode = rtw89_get_entity_mode(rtwdev); 2577 if (likely(mode != RTW89_ENTITY_MODE_MCC)) 2578 return; 2579 2580 if (chip_gen == RTW89_CHIP_BE && phy_ppdu) 2581 mac_id = phy_ppdu->mac_id; 2582 2583 rcu_read_lock(); 2584 2585 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, mac_id); 2586 if (!rtwsta_link) 2587 goto out; 2588 2589 rtwvif_link = rtwsta_link->rtwvif_link; 2590 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 2591 band = rtw89_hw_to_nl80211_band(chan->band_type); 2592 rx_status->freq = ieee80211_channel_to_frequency(chan->primary_channel, band); 2593 2594 out: 2595 rcu_read_unlock(); 2596 } 2597 2598 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev, 2599 struct rtw89_rx_phy_ppdu *phy_ppdu, 2600 struct rtw89_rx_desc_info *desc_info, 2601 struct sk_buff *skb_ppdu, 2602 struct ieee80211_rx_status *rx_status) 2603 { 2604 struct napi_struct *napi = &rtwdev->napi; 2605 2606 /* In low power mode, napi isn't scheduled. Receive it to netif. */ 2607 if (unlikely(!napi_is_scheduled(napi))) 2608 napi = NULL; 2609 2610 rtw89_core_hw_to_sband_rate(rx_status); 2611 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); 2612 rtw89_core_update_rx_status_by_ppdu(rtwdev, rx_status, phy_ppdu); 2613 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status); 2614 rtw89_core_validate_rx_signal(rx_status); 2615 rtw89_core_update_rx_freq_from_ie(rtwdev, skb_ppdu, rx_status); 2616 rtw89_core_correct_mcc_chan(rtwdev, desc_info, rx_status, phy_ppdu); 2617 2618 /* In low power mode, it does RX in thread context. */ 2619 local_bh_disable(); 2620 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi); 2621 local_bh_enable(); 2622 rtwdev->napi_budget_countdown--; 2623 } 2624 2625 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, 2626 struct rtw89_rx_phy_ppdu *phy_ppdu, 2627 struct rtw89_rx_desc_info *desc_info, 2628 struct sk_buff *skb) 2629 { 2630 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2631 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; 2632 struct sk_buff *skb_ppdu = NULL, *tmp; 2633 struct ieee80211_rx_status *rx_status; 2634 2635 if (curr > RTW89_MAX_PPDU_CNT) 2636 return; 2637 2638 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { 2639 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); 2640 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2641 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) 2642 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); 2643 rtw89_correct_cck_chan(rtwdev, rx_status); 2644 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status); 2645 } 2646 } 2647 2648 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, 2649 struct rtw89_rx_desc_info *desc_info, 2650 struct sk_buff *skb) 2651 { 2652 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, 2653 .len = skb->len, 2654 .to_self = desc_info->addr1_match, 2655 .rate = desc_info->data_rate, 2656 .mac_id = desc_info->mac_id, 2657 .phy_idx = desc_info->bb_sel}; 2658 int ret; 2659 2660 if (desc_info->mac_info_valid) { 2661 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); 2662 if (ret) 2663 goto out; 2664 } 2665 2666 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); 2667 if (ret) 2668 goto out; 2669 2670 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); 2671 2672 out: 2673 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); 2674 dev_kfree_skb_any(skb); 2675 } 2676 2677 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, 2678 struct rtw89_rx_desc_info *desc_info, 2679 struct sk_buff *skb) 2680 { 2681 switch (desc_info->pkt_type) { 2682 case RTW89_CORE_RX_TYPE_C2H: 2683 rtw89_fw_c2h_irqsafe(rtwdev, skb); 2684 break; 2685 case RTW89_CORE_RX_TYPE_PPDU_STAT: 2686 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); 2687 break; 2688 default: 2689 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", 2690 desc_info->pkt_type); 2691 dev_kfree_skb_any(skb); 2692 break; 2693 } 2694 } 2695 2696 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 2697 struct rtw89_rx_desc_info *desc_info, 2698 u8 *data, u32 data_offset) 2699 { 2700 const struct rtw89_chip_info *chip = rtwdev->chip; 2701 struct rtw89_rxdesc_short *rxd_s; 2702 struct rtw89_rxdesc_long *rxd_l; 2703 u8 shift_len, drv_info_len; 2704 2705 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); 2706 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK); 2707 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK); 2708 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD); 2709 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK); 2710 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD); 2711 if (chip->chip_id == RTL8852C) 2712 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK); 2713 else 2714 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK); 2715 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK); 2716 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK); 2717 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK); 2718 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN); 2719 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK); 2720 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK); 2721 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK); 2722 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR); 2723 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR); 2724 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC); 2725 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC); 2726 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH); 2727 2728 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2729 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2730 desc_info->offset = data_offset + shift_len + drv_info_len; 2731 if (desc_info->long_rxdesc) 2732 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long); 2733 else 2734 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short); 2735 desc_info->ready = true; 2736 2737 if (!desc_info->long_rxdesc) 2738 return; 2739 2740 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); 2741 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK); 2742 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD); 2743 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK); 2744 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK); 2745 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK); 2746 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK); 2747 } 2748 EXPORT_SYMBOL(rtw89_core_query_rxdesc); 2749 2750 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 2751 struct rtw89_rx_desc_info *desc_info, 2752 u8 *data, u32 data_offset) 2753 { 2754 struct rtw89_rxdesc_phy_rpt_v2 *rxd_rpt; 2755 struct rtw89_rxdesc_short_v2 *rxd_s; 2756 struct rtw89_rxdesc_long_v2 *rxd_l; 2757 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len; 2758 2759 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset); 2760 2761 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK); 2762 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK); 2763 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK); 2764 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK); 2765 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK); 2766 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD); 2767 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK); 2768 desc_info->bb_sel = le32_get_bits(rxd_s->dword0, BE_RXD_BB_SEL); 2769 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT) 2770 desc_info->mac_info_valid = true; 2771 2772 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK); 2773 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK); 2774 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD); 2775 2776 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR); 2777 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR); 2778 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC); 2779 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC); 2780 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH); 2781 2782 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK); 2783 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK); 2784 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK); 2785 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK); 2786 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK); 2787 2788 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5); 2789 2790 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2791 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2792 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */ 2793 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */ 2794 desc_info->offset = data_offset + shift_len + drv_info_len + 2795 phy_rtp_len + hdr_cnv_len; 2796 2797 if (desc_info->long_rxdesc) 2798 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2); 2799 else 2800 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2); 2801 desc_info->ready = true; 2802 2803 if (phy_rtp_len == sizeof(*rxd_rpt)) { 2804 rxd_rpt = (struct rtw89_rxdesc_phy_rpt_v2 *)(data + data_offset + 2805 desc_info->rxd_len); 2806 desc_info->rssi = le32_get_bits(rxd_rpt->dword0, BE_RXD_PHY_RSSI); 2807 } 2808 2809 if (!desc_info->long_rxdesc) 2810 return; 2811 2812 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset); 2813 2814 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN); 2815 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK); 2816 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK); 2817 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK); 2818 2819 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK); 2820 } 2821 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2); 2822 2823 struct rtw89_core_iter_rx_status { 2824 struct rtw89_dev *rtwdev; 2825 struct ieee80211_rx_status *rx_status; 2826 struct rtw89_rx_desc_info *desc_info; 2827 u8 mac_id; 2828 }; 2829 2830 static 2831 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) 2832 { 2833 struct rtw89_core_iter_rx_status *iter_data = 2834 (struct rtw89_core_iter_rx_status *)data; 2835 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 2836 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 2837 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 2838 struct rtw89_sta_link *rtwsta_link; 2839 u8 mac_id = iter_data->mac_id; 2840 2841 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, desc_info->bb_sel); 2842 if (unlikely(!rtwsta_link)) 2843 return; 2844 2845 if (mac_id != rtwsta_link->mac_id) 2846 return; 2847 2848 rtwsta_link->rx_status = *rx_status; 2849 rtwsta_link->rx_hw_rate = desc_info->data_rate; 2850 } 2851 2852 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, 2853 struct rtw89_rx_desc_info *desc_info, 2854 struct ieee80211_rx_status *rx_status) 2855 { 2856 struct rtw89_core_iter_rx_status iter_data; 2857 2858 if (!desc_info->addr1_match || !desc_info->long_rxdesc) 2859 return; 2860 2861 if (desc_info->frame_type != RTW89_RX_TYPE_DATA) 2862 return; 2863 2864 iter_data.rtwdev = rtwdev; 2865 iter_data.rx_status = rx_status; 2866 iter_data.desc_info = desc_info; 2867 iter_data.mac_id = desc_info->mac_id; 2868 ieee80211_iterate_stations_atomic(rtwdev->hw, 2869 rtw89_core_stats_sta_rx_status_iter, 2870 &iter_data); 2871 } 2872 2873 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, 2874 struct sk_buff *skb, 2875 struct rtw89_rx_desc_info *desc_info, 2876 struct ieee80211_rx_status *rx_status) 2877 { 2878 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2879 const struct cfg80211_chan_def *chandef = 2880 rtw89_chandef_get(rtwdev, RTW89_CHANCTX_0); 2881 u16 data_rate; 2882 u8 data_rate_mode; 2883 bool eht = false; 2884 u8 gi; 2885 2886 /* currently using single PHY */ 2887 rx_status->freq = chandef->chan->center_freq; 2888 rx_status->band = chandef->chan->band; 2889 2890 if (ieee80211_is_beacon(hdr->frame_control) || 2891 ieee80211_is_probe_resp(hdr->frame_control)) 2892 rx_status->boottime_ns = ktime_get_boottime_ns(); 2893 2894 if (rtwdev->scanning && 2895 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 2896 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev); 2897 u8 chan = cur->primary_channel; 2898 u8 band = cur->band_type; 2899 enum nl80211_band nl_band; 2900 2901 nl_band = rtw89_hw_to_nl80211_band(band); 2902 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band); 2903 rx_status->band = nl_band; 2904 } 2905 2906 if (desc_info->icv_err || desc_info->crc32_err) 2907 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2908 2909 if (desc_info->hw_dec && 2910 !(desc_info->sw_dec || desc_info->icv_err)) 2911 rx_status->flag |= RX_FLAG_DECRYPTED; 2912 2913 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 2914 2915 data_rate = desc_info->data_rate; 2916 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 2917 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 2918 rx_status->encoding = RX_ENC_LEGACY; 2919 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 2920 /* convert rate_idx after we get the correct band */ 2921 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 2922 rx_status->encoding = RX_ENC_HT; 2923 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 2924 if (desc_info->gi_ltf) 2925 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2926 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 2927 rx_status->encoding = RX_ENC_VHT; 2928 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2929 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2930 if (desc_info->gi_ltf) 2931 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2932 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 2933 rx_status->encoding = RX_ENC_HE; 2934 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2935 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2936 } else if (data_rate_mode == DATA_RATE_MODE_EHT) { 2937 rx_status->encoding = RX_ENC_EHT; 2938 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2939 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2940 eht = true; 2941 } else { 2942 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 2943 } 2944 2945 /* he_gi is used to match ppdu, so we always fill it. */ 2946 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht); 2947 if (eht) 2948 rx_status->eht.gi = gi; 2949 else 2950 rx_status->he_gi = gi; 2951 rx_status->flag |= RX_FLAG_MACTIME_START; 2952 rx_status->mactime = desc_info->free_run_cnt; 2953 2954 rtw89_chip_phy_rpt_to_rssi(rtwdev, desc_info, rx_status); 2955 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); 2956 } 2957 2958 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) 2959 { 2960 const struct rtw89_chip_info *chip = rtwdev->chip; 2961 2962 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE) 2963 return RTW89_PS_MODE_NONE; 2964 2965 if (rtw89_disable_ps_mode || !chip->ps_mode_supported || 2966 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw)) 2967 return RTW89_PS_MODE_NONE; 2968 2969 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) && 2970 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw)) 2971 return RTW89_PS_MODE_PWR_GATED; 2972 2973 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) 2974 return RTW89_PS_MODE_CLK_GATED; 2975 2976 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) 2977 return RTW89_PS_MODE_RFOFF; 2978 2979 return RTW89_PS_MODE_NONE; 2980 } 2981 2982 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, 2983 struct rtw89_rx_desc_info *desc_info) 2984 { 2985 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2986 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2987 struct ieee80211_rx_status *rx_status; 2988 struct sk_buff *skb_ppdu, *tmp; 2989 2990 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { 2991 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); 2992 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2993 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status); 2994 } 2995 } 2996 2997 static 2998 void rtw89_core_rx_pkt_hdl(struct rtw89_dev *rtwdev, const struct sk_buff *skb, 2999 const struct rtw89_rx_desc_info *desc) 3000 { 3001 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 3002 struct rtw89_sta_link *rtwsta_link; 3003 struct ieee80211_sta *sta; 3004 struct rtw89_sta *rtwsta; 3005 u8 macid = desc->mac_id; 3006 3007 if (!refcount_read(&rtwdev->refcount_ap_info)) 3008 return; 3009 3010 rcu_read_lock(); 3011 3012 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, macid); 3013 if (!rtwsta_link) 3014 goto out; 3015 3016 rtwsta = rtwsta_link->rtwsta; 3017 if (!test_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags)) 3018 goto out; 3019 3020 sta = rtwsta_to_sta(rtwsta); 3021 if (ieee80211_is_pspoll(hdr->frame_control)) 3022 ieee80211_sta_pspoll(sta); 3023 else if (ieee80211_has_pm(hdr->frame_control) && 3024 (ieee80211_is_data_qos(hdr->frame_control) || 3025 ieee80211_is_qos_nullfunc(hdr->frame_control))) 3026 ieee80211_sta_uapsd_trigger(sta, ieee80211_get_tid(hdr)); 3027 3028 out: 3029 rcu_read_unlock(); 3030 } 3031 3032 void rtw89_core_rx(struct rtw89_dev *rtwdev, 3033 struct rtw89_rx_desc_info *desc_info, 3034 struct sk_buff *skb) 3035 { 3036 struct ieee80211_rx_status *rx_status; 3037 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 3038 u8 ppdu_cnt = desc_info->ppdu_cnt; 3039 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 3040 3041 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { 3042 rtw89_core_rx_process_report(rtwdev, desc_info, skb); 3043 return; 3044 } 3045 3046 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { 3047 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); 3048 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; 3049 } 3050 3051 rx_status = IEEE80211_SKB_RXCB(skb); 3052 memset(rx_status, 0, sizeof(*rx_status)); 3053 rtw89_core_update_rx_status(rtwdev, skb, desc_info, rx_status); 3054 rtw89_core_rx_pkt_hdl(rtwdev, skb, desc_info); 3055 if (desc_info->long_rxdesc && 3056 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) 3057 skb_queue_tail(&ppdu_sts->rx_queue[band], skb); 3058 else 3059 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 3060 } 3061 EXPORT_SYMBOL(rtw89_core_rx); 3062 3063 void rtw89_core_napi_start(struct rtw89_dev *rtwdev) 3064 { 3065 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 3066 return; 3067 3068 napi_enable(&rtwdev->napi); 3069 } 3070 EXPORT_SYMBOL(rtw89_core_napi_start); 3071 3072 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) 3073 { 3074 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 3075 return; 3076 3077 napi_synchronize(&rtwdev->napi); 3078 napi_disable(&rtwdev->napi); 3079 } 3080 EXPORT_SYMBOL(rtw89_core_napi_stop); 3081 3082 int rtw89_core_napi_init(struct rtw89_dev *rtwdev) 3083 { 3084 rtwdev->netdev = alloc_netdev_dummy(0); 3085 if (!rtwdev->netdev) 3086 return -ENOMEM; 3087 3088 netif_napi_add(rtwdev->netdev, &rtwdev->napi, 3089 rtwdev->hci.ops->napi_poll); 3090 return 0; 3091 } 3092 EXPORT_SYMBOL(rtw89_core_napi_init); 3093 3094 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) 3095 { 3096 rtw89_core_napi_stop(rtwdev); 3097 netif_napi_del(&rtwdev->napi); 3098 free_netdev(rtwdev->netdev); 3099 } 3100 EXPORT_SYMBOL(rtw89_core_napi_deinit); 3101 3102 static void rtw89_core_ba_work(struct work_struct *work) 3103 { 3104 struct rtw89_dev *rtwdev = 3105 container_of(work, struct rtw89_dev, ba_work); 3106 struct rtw89_txq *rtwtxq, *tmp; 3107 int ret; 3108 3109 spin_lock_bh(&rtwdev->ba_lock); 3110 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 3111 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3112 struct ieee80211_sta *sta = txq->sta; 3113 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 3114 u8 tid = txq->tid; 3115 3116 if (!sta) { 3117 rtw89_warn(rtwdev, "cannot start BA without sta\n"); 3118 goto skip_ba_work; 3119 } 3120 3121 if (rtwsta->disassoc) { 3122 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 3123 "cannot start BA with disassoc sta\n"); 3124 goto skip_ba_work; 3125 } 3126 3127 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 3128 if (ret) { 3129 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 3130 "failed to setup BA session for %pM:%2d: %d\n", 3131 sta->addr, tid, ret); 3132 if (ret == -EINVAL) 3133 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); 3134 } 3135 skip_ba_work: 3136 list_del_init(&rtwtxq->list); 3137 } 3138 spin_unlock_bh(&rtwdev->ba_lock); 3139 } 3140 3141 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 3142 struct ieee80211_sta *sta) 3143 { 3144 struct rtw89_txq *rtwtxq, *tmp; 3145 3146 spin_lock_bh(&rtwdev->ba_lock); 3147 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 3148 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3149 3150 if (sta == txq->sta) 3151 list_del_init(&rtwtxq->list); 3152 } 3153 spin_unlock_bh(&rtwdev->ba_lock); 3154 } 3155 3156 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 3157 struct ieee80211_sta *sta) 3158 { 3159 struct rtw89_txq *rtwtxq, *tmp; 3160 3161 spin_lock_bh(&rtwdev->ba_lock); 3162 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 3163 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3164 3165 if (sta == txq->sta) { 3166 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3167 list_del_init(&rtwtxq->list); 3168 } 3169 } 3170 spin_unlock_bh(&rtwdev->ba_lock); 3171 } 3172 3173 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 3174 struct ieee80211_sta *sta) 3175 { 3176 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3177 struct sk_buff *skb, *tmp; 3178 3179 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 3180 skb_unlink(skb, &rtwsta->roc_queue); 3181 dev_kfree_skb_any(skb); 3182 } 3183 } 3184 3185 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev, 3186 struct rtw89_txq *rtwtxq) 3187 { 3188 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3189 struct ieee80211_sta *sta = txq->sta; 3190 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 3191 3192 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc)) 3193 return; 3194 3195 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) || 3196 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 3197 return; 3198 3199 spin_lock_bh(&rtwdev->ba_lock); 3200 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 3201 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list); 3202 spin_unlock_bh(&rtwdev->ba_lock); 3203 3204 ieee80211_stop_tx_ba_session(sta, txq->tid); 3205 cancel_delayed_work(&rtwdev->forbid_ba_work); 3206 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work, 3207 RTW89_FORBID_BA_TIMER); 3208 } 3209 3210 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, 3211 struct rtw89_txq *rtwtxq, 3212 struct sk_buff *skb) 3213 { 3214 struct ieee80211_hw *hw = rtwdev->hw; 3215 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3216 struct ieee80211_sta *sta = txq->sta; 3217 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 3218 3219 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 3220 return; 3221 3222 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 3223 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq); 3224 return; 3225 } 3226 3227 if (unlikely(!sta)) 3228 return; 3229 3230 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) 3231 return; 3232 3233 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { 3234 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; 3235 return; 3236 } 3237 3238 spin_lock_bh(&rtwdev->ba_lock); 3239 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { 3240 list_add_tail(&rtwtxq->list, &rtwdev->ba_list); 3241 ieee80211_queue_work(hw, &rtwdev->ba_work); 3242 } 3243 spin_unlock_bh(&rtwdev->ba_lock); 3244 } 3245 3246 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, 3247 struct rtw89_txq *rtwtxq, 3248 unsigned long frame_cnt, 3249 unsigned long byte_cnt) 3250 { 3251 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3252 struct ieee80211_vif *vif = txq->vif; 3253 struct ieee80211_sta *sta = txq->sta; 3254 struct sk_buff *skb; 3255 unsigned long i; 3256 int ret; 3257 3258 rcu_read_lock(); 3259 for (i = 0; i < frame_cnt; i++) { 3260 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); 3261 if (!skb) { 3262 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); 3263 goto out; 3264 } 3265 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); 3266 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); 3267 if (ret) { 3268 rtw89_err(rtwdev, "failed to push txq: %d\n", ret); 3269 ieee80211_free_txskb(rtwdev->hw, skb); 3270 break; 3271 } 3272 } 3273 out: 3274 rcu_read_unlock(); 3275 } 3276 3277 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) 3278 { 3279 u8 qsel, ch_dma; 3280 3281 qsel = rtw89_core_get_qsel(rtwdev, tid); 3282 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 3283 3284 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 3285 } 3286 3287 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, 3288 struct ieee80211_txq *txq, 3289 unsigned long *frame_cnt, 3290 bool *sched_txq, bool *reinvoke) 3291 { 3292 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3293 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(txq->sta); 3294 struct rtw89_sta_link *rtwsta_link; 3295 3296 if (!rtwsta) 3297 return false; 3298 3299 rtwsta_link = rtw89_get_designated_link(rtwsta); 3300 if (unlikely(!rtwsta_link)) { 3301 rtw89_err(rtwdev, "agg wait: find no designated link\n"); 3302 return false; 3303 } 3304 3305 if (rtwsta_link->max_agg_wait <= 0) 3306 return false; 3307 3308 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) 3309 return false; 3310 3311 if (*frame_cnt > 1) { 3312 *frame_cnt -= 1; 3313 *sched_txq = true; 3314 *reinvoke = true; 3315 rtwtxq->wait_cnt = 1; 3316 return false; 3317 } 3318 3319 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta_link->max_agg_wait) { 3320 *reinvoke = true; 3321 rtwtxq->wait_cnt++; 3322 return true; 3323 } 3324 3325 rtwtxq->wait_cnt = 0; 3326 return false; 3327 } 3328 3329 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) 3330 { 3331 struct ieee80211_hw *hw = rtwdev->hw; 3332 struct ieee80211_txq *txq; 3333 struct rtw89_vif *rtwvif; 3334 struct rtw89_txq *rtwtxq; 3335 unsigned long frame_cnt; 3336 unsigned long byte_cnt; 3337 u32 tx_resource; 3338 bool sched_txq; 3339 3340 ieee80211_txq_schedule_start(hw, ac); 3341 while ((txq = ieee80211_next_txq(hw, ac))) { 3342 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3343 rtwvif = vif_to_rtwvif(txq->vif); 3344 3345 if (rtwvif->offchan) { 3346 ieee80211_return_txq(hw, txq, true); 3347 continue; 3348 } 3349 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); 3350 sched_txq = false; 3351 3352 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 3353 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { 3354 ieee80211_return_txq(hw, txq, true); 3355 continue; 3356 } 3357 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); 3358 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); 3359 ieee80211_return_txq(hw, txq, sched_txq); 3360 if (frame_cnt != 0) 3361 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); 3362 3363 /* bound of tx_resource could get stuck due to burst traffic */ 3364 if (frame_cnt == tx_resource) 3365 *reinvoke = true; 3366 } 3367 ieee80211_txq_schedule_end(hw, ac); 3368 } 3369 3370 static void rtw89_ips_work(struct wiphy *wiphy, struct wiphy_work *work) 3371 { 3372 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 3373 ips_work); 3374 3375 lockdep_assert_wiphy(wiphy); 3376 3377 rtw89_enter_ips_by_hwflags(rtwdev); 3378 } 3379 3380 static void rtw89_core_txq_work(struct work_struct *w) 3381 { 3382 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); 3383 bool reinvoke = false; 3384 u8 ac; 3385 3386 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 3387 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); 3388 3389 if (reinvoke) { 3390 /* reinvoke to process the last frame */ 3391 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); 3392 } 3393 } 3394 3395 static void rtw89_core_txq_reinvoke_work(struct work_struct *w) 3396 { 3397 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 3398 txq_reinvoke_work.work); 3399 3400 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 3401 } 3402 3403 static void rtw89_forbid_ba_work(struct work_struct *w) 3404 { 3405 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 3406 forbid_ba_work.work); 3407 struct rtw89_txq *rtwtxq, *tmp; 3408 3409 spin_lock_bh(&rtwdev->ba_lock); 3410 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 3411 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3412 list_del_init(&rtwtxq->list); 3413 } 3414 spin_unlock_bh(&rtwdev->ba_lock); 3415 } 3416 3417 static void rtw89_core_sta_pending_tx_iter(void *data, 3418 struct ieee80211_sta *sta) 3419 { 3420 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3421 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3422 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 3423 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3424 struct rtw89_vif_link *target = data; 3425 struct rtw89_vif_link *rtwvif_link; 3426 struct sk_buff *skb, *tmp; 3427 unsigned int link_id; 3428 int qsel, ret; 3429 3430 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 3431 if (rtwvif_link->chanctx_idx == target->chanctx_idx) 3432 goto bottom; 3433 3434 return; 3435 3436 bottom: 3437 if (skb_queue_len(&rtwsta->roc_queue) == 0) 3438 return; 3439 3440 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 3441 skb_unlink(skb, &rtwsta->roc_queue); 3442 3443 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 3444 if (ret) { 3445 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret); 3446 dev_kfree_skb_any(skb); 3447 } else { 3448 rtw89_core_tx_kick_off(rtwdev, qsel); 3449 } 3450 } 3451 } 3452 3453 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev, 3454 struct rtw89_vif_link *rtwvif_link) 3455 { 3456 ieee80211_iterate_stations_atomic(rtwdev->hw, 3457 rtw89_core_sta_pending_tx_iter, 3458 rtwvif_link); 3459 } 3460 3461 int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 3462 bool qos, bool ps, int timeout) 3463 { 3464 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 3465 int link_id = ieee80211_vif_is_mld(vif) ? rtwvif_link->link_id : -1; 3466 struct rtw89_sta_link *rtwsta_link; 3467 struct ieee80211_sta *sta; 3468 struct ieee80211_hdr *hdr; 3469 struct rtw89_sta *rtwsta; 3470 struct sk_buff *skb; 3471 int ret, qsel; 3472 3473 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 3474 return 0; 3475 3476 rcu_read_lock(); 3477 sta = ieee80211_find_sta(vif, vif->cfg.ap_addr); 3478 if (!sta) { 3479 ret = -EINVAL; 3480 goto out; 3481 } 3482 rtwsta = sta_to_rtwsta(sta); 3483 3484 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, link_id, qos); 3485 if (!skb) { 3486 ret = -ENOMEM; 3487 goto out; 3488 } 3489 3490 hdr = (struct ieee80211_hdr *)skb->data; 3491 if (ps) 3492 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 3493 3494 rtwsta_link = rtwsta->links[rtwvif_link->link_id]; 3495 if (unlikely(!rtwsta_link)) { 3496 ret = -ENOLINK; 3497 goto out; 3498 } 3499 3500 ret = rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, &qsel, true); 3501 if (ret) { 3502 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret); 3503 dev_kfree_skb_any(skb); 3504 goto out; 3505 } 3506 3507 rcu_read_unlock(); 3508 3509 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, qsel, 3510 timeout); 3511 out: 3512 rcu_read_unlock(); 3513 3514 return ret; 3515 } 3516 3517 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3518 { 3519 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3520 struct rtw89_chanctx_pause_parm pause_parm = { 3521 .rsn = RTW89_CHANCTX_PAUSE_REASON_ROC, 3522 }; 3523 struct ieee80211_hw *hw = rtwdev->hw; 3524 struct rtw89_roc *roc = &rtwvif->roc; 3525 struct rtw89_vif_link *rtwvif_link; 3526 struct cfg80211_chan_def roc_chan; 3527 struct rtw89_vif *tmp_vif; 3528 u32 reg; 3529 int ret; 3530 3531 lockdep_assert_wiphy(hw->wiphy); 3532 3533 rtw89_leave_ips_by_hwflags(rtwdev); 3534 rtw89_leave_lps(rtwdev); 3535 3536 rtwvif_link = rtw89_get_designated_link(rtwvif); 3537 if (unlikely(!rtwvif_link)) { 3538 rtw89_err(rtwdev, "roc start: find no designated link\n"); 3539 return; 3540 } 3541 3542 roc->link_id = rtwvif_link->link_id; 3543 3544 pause_parm.trigger = rtwvif_link; 3545 rtw89_chanctx_pause(rtwdev, &pause_parm); 3546 3547 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, true, 3548 RTW89_ROC_TX_TIMEOUT); 3549 if (ret) 3550 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 3551 "roc send null-1 failed: %d\n", ret); 3552 3553 rtw89_for_each_rtwvif(rtwdev, tmp_vif) { 3554 struct rtw89_vif_link *tmp_link; 3555 unsigned int link_id; 3556 3557 rtw89_vif_for_each_link(tmp_vif, tmp_link, link_id) { 3558 if (tmp_link->chanctx_idx == rtwvif_link->chanctx_idx) { 3559 tmp_vif->offchan = true; 3560 break; 3561 } 3562 } 3563 } 3564 3565 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT); 3566 rtw89_config_roc_chandef(rtwdev, rtwvif_link, &roc_chan); 3567 rtw89_set_channel(rtwdev); 3568 3569 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx); 3570 rtw89_write32_clr(rtwdev, reg, B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH); 3571 3572 ieee80211_ready_on_channel(hw); 3573 wiphy_delayed_work_cancel(hw->wiphy, &rtwvif->roc.roc_work); 3574 wiphy_delayed_work_queue(hw->wiphy, &rtwvif->roc.roc_work, 3575 msecs_to_jiffies(rtwvif->roc.duration)); 3576 } 3577 3578 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3579 { 3580 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3581 struct ieee80211_hw *hw = rtwdev->hw; 3582 struct rtw89_roc *roc = &rtwvif->roc; 3583 struct rtw89_vif_link *rtwvif_link; 3584 struct rtw89_vif *tmp_vif; 3585 u32 reg; 3586 int ret; 3587 3588 lockdep_assert_wiphy(hw->wiphy); 3589 3590 ieee80211_remain_on_channel_expired(hw); 3591 3592 rtw89_leave_ips_by_hwflags(rtwdev); 3593 rtw89_leave_lps(rtwdev); 3594 3595 rtwvif_link = rtwvif->links[roc->link_id]; 3596 if (unlikely(!rtwvif_link)) { 3597 rtw89_err(rtwdev, "roc end: find no link (link id %u)\n", 3598 roc->link_id); 3599 return; 3600 } 3601 3602 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx); 3603 rtw89_write32_mask(rtwdev, reg, B_AX_RX_FLTR_CFG_MASK, rtwdev->hal.rx_fltr); 3604 3605 roc->state = RTW89_ROC_IDLE; 3606 rtw89_config_roc_chandef(rtwdev, rtwvif_link, NULL); 3607 rtw89_chanctx_proceed(rtwdev, NULL); 3608 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, false, 3609 RTW89_ROC_TX_TIMEOUT); 3610 if (ret) 3611 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 3612 "roc send null-0 failed: %d\n", ret); 3613 3614 rtw89_for_each_rtwvif(rtwdev, tmp_vif) 3615 tmp_vif->offchan = false; 3616 3617 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif_link); 3618 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 3619 3620 if (hw->conf.flags & IEEE80211_CONF_IDLE) 3621 wiphy_delayed_work_queue(hw->wiphy, &roc->roc_work, 3622 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT)); 3623 } 3624 3625 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work) 3626 { 3627 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 3628 roc.roc_work.work); 3629 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 3630 struct rtw89_roc *roc = &rtwvif->roc; 3631 3632 lockdep_assert_wiphy(wiphy); 3633 3634 switch (roc->state) { 3635 case RTW89_ROC_IDLE: 3636 rtw89_enter_ips_by_hwflags(rtwdev); 3637 break; 3638 case RTW89_ROC_MGMT: 3639 case RTW89_ROC_NORMAL: 3640 rtw89_roc_end(rtwdev, rtwvif); 3641 break; 3642 default: 3643 break; 3644 } 3645 } 3646 3647 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, 3648 u32 throughput, u64 cnt, 3649 enum rtw89_tfc_interval interval) 3650 { 3651 u64 cnt_level; 3652 3653 switch (interval) { 3654 default: 3655 case RTW89_TFC_INTERVAL_100MS: 3656 cnt_level = 5; 3657 break; 3658 case RTW89_TFC_INTERVAL_2SEC: 3659 cnt_level = 100; 3660 break; 3661 } 3662 3663 if (cnt < cnt_level) 3664 return RTW89_TFC_IDLE; 3665 if (throughput > 50) 3666 return RTW89_TFC_HIGH; 3667 if (throughput > 10) 3668 return RTW89_TFC_MID; 3669 if (throughput > 2) 3670 return RTW89_TFC_LOW; 3671 return RTW89_TFC_ULTRA_LOW; 3672 } 3673 3674 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, 3675 struct rtw89_traffic_stats *stats, 3676 enum rtw89_tfc_interval interval) 3677 { 3678 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 3679 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 3680 3681 stats->tx_throughput_raw = rtw89_bytes_to_mbps(stats->tx_unicast, interval); 3682 stats->rx_throughput_raw = rtw89_bytes_to_mbps(stats->rx_unicast, interval); 3683 3684 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); 3685 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); 3686 3687 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 3688 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 3689 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, 3690 stats->tx_cnt, interval); 3691 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, 3692 stats->rx_cnt, interval); 3693 stats->tx_avg_len = stats->tx_cnt ? 3694 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; 3695 stats->rx_avg_len = stats->rx_cnt ? 3696 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; 3697 3698 stats->tx_unicast = 0; 3699 stats->rx_unicast = 0; 3700 stats->tx_cnt = 0; 3701 stats->rx_cnt = 0; 3702 stats->rx_tf_periodic = stats->rx_tf_acc; 3703 stats->rx_tf_acc = 0; 3704 3705 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) 3706 return true; 3707 3708 return false; 3709 } 3710 3711 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) 3712 { 3713 struct rtw89_vif_link *rtwvif_link; 3714 struct rtw89_vif *rtwvif; 3715 unsigned int link_id; 3716 bool tfc_changed; 3717 3718 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats, 3719 RTW89_TFC_INTERVAL_2SEC); 3720 3721 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 3722 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats, 3723 RTW89_TFC_INTERVAL_2SEC); 3724 3725 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 3726 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif_link); 3727 } 3728 3729 return tfc_changed; 3730 } 3731 3732 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) 3733 { 3734 struct ieee80211_vif *vif; 3735 struct rtw89_vif *rtwvif; 3736 3737 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 3738 if (rtwvif->tdls_peer) 3739 continue; 3740 if (rtwvif->offchan) 3741 continue; 3742 3743 if (rtwvif->stats_ps.tx_tfc_lv >= RTW89_TFC_MID || 3744 rtwvif->stats_ps.rx_tfc_lv >= RTW89_TFC_MID) 3745 continue; 3746 3747 vif = rtwvif_to_vif(rtwvif); 3748 3749 if (!(vif->type == NL80211_IFTYPE_STATION || 3750 vif->type == NL80211_IFTYPE_P2P_CLIENT)) 3751 continue; 3752 3753 rtw89_enter_lps(rtwdev, rtwvif, true); 3754 } 3755 } 3756 3757 static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev) 3758 { 3759 enum rtw89_entity_mode mode; 3760 3761 mode = rtw89_get_entity_mode(rtwdev); 3762 if (mode == RTW89_ENTITY_MODE_MCC) 3763 return; 3764 3765 rtw89_chip_rfk_track(rtwdev); 3766 } 3767 3768 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 3769 struct rtw89_vif_link *rtwvif_link, 3770 struct ieee80211_bss_conf *bss_conf) 3771 { 3772 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev); 3773 3774 if (mode == RTW89_ENTITY_MODE_MCC) 3775 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE); 3776 else 3777 rtw89_process_p2p_ps(rtwdev, rtwvif_link, bss_conf); 3778 } 3779 3780 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 3781 struct rtw89_traffic_stats *stats) 3782 { 3783 stats->tx_unicast = 0; 3784 stats->rx_unicast = 0; 3785 stats->tx_cnt = 0; 3786 stats->rx_cnt = 0; 3787 ewma_tp_init(&stats->tx_ewma_tp); 3788 ewma_tp_init(&stats->rx_ewma_tp); 3789 } 3790 3791 #define RTW89_MLSR_GOTO_2GHZ_THRESHOLD -53 3792 #define RTW89_MLSR_EXIT_2GHZ_THRESHOLD -38 3793 static void rtw89_core_mlsr_link_decision(struct rtw89_dev *rtwdev, 3794 struct rtw89_vif *rtwvif) 3795 { 3796 unsigned int sel_link_id = IEEE80211_MLD_MAX_NUM_LINKS; 3797 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3798 struct rtw89_vif_link *rtwvif_link; 3799 const struct rtw89_chan *chan; 3800 unsigned long usable_links; 3801 unsigned int link_id; 3802 u8 decided_bands; 3803 u8 rssi; 3804 3805 rssi = ewma_rssi_read(&rtwdev->phystat.bcn_rssi); 3806 if (unlikely(!rssi)) 3807 return; 3808 3809 if (RTW89_RSSI_RAW_TO_DBM(rssi) >= RTW89_MLSR_EXIT_2GHZ_THRESHOLD) 3810 decided_bands = BIT(RTW89_BAND_5G) | BIT(RTW89_BAND_6G); 3811 else if (RTW89_RSSI_RAW_TO_DBM(rssi) <= RTW89_MLSR_GOTO_2GHZ_THRESHOLD) 3812 decided_bands = BIT(RTW89_BAND_2G); 3813 else 3814 return; 3815 3816 usable_links = ieee80211_vif_usable_links(vif); 3817 3818 rtwvif_link = rtw89_get_designated_link(rtwvif); 3819 if (unlikely(!rtwvif_link)) 3820 goto select; 3821 3822 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 3823 if (decided_bands & BIT(chan->band_type)) 3824 return; 3825 3826 usable_links &= ~BIT(rtwvif_link->link_id); 3827 3828 select: 3829 rcu_read_lock(); 3830 3831 for_each_set_bit(link_id, &usable_links, IEEE80211_MLD_MAX_NUM_LINKS) { 3832 struct ieee80211_bss_conf *link_conf; 3833 struct ieee80211_channel *channel; 3834 enum rtw89_band band; 3835 3836 link_conf = rcu_dereference(vif->link_conf[link_id]); 3837 if (unlikely(!link_conf)) 3838 continue; 3839 3840 channel = link_conf->chanreq.oper.chan; 3841 if (unlikely(!channel)) 3842 continue; 3843 3844 band = rtw89_nl80211_to_hw_band(channel->band); 3845 if (decided_bands & BIT(band)) { 3846 sel_link_id = link_id; 3847 break; 3848 } 3849 } 3850 3851 rcu_read_unlock(); 3852 3853 if (sel_link_id == IEEE80211_MLD_MAX_NUM_LINKS) 3854 return; 3855 3856 rtw89_core_mlsr_switch(rtwdev, rtwvif, sel_link_id); 3857 } 3858 3859 static void rtw89_core_mlo_track(struct rtw89_dev *rtwdev) 3860 { 3861 struct rtw89_hal *hal = &rtwdev->hal; 3862 struct ieee80211_vif *vif; 3863 struct rtw89_vif *rtwvif; 3864 3865 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_MLO)) 3866 return; 3867 3868 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 3869 vif = rtwvif_to_vif(rtwvif); 3870 if (!vif->cfg.assoc || !ieee80211_vif_is_mld(vif)) 3871 continue; 3872 3873 switch (rtwvif->mlo_mode) { 3874 case RTW89_MLO_MODE_MLSR: 3875 rtw89_core_mlsr_link_decision(rtwdev, rtwvif); 3876 break; 3877 default: 3878 break; 3879 } 3880 } 3881 } 3882 3883 static void rtw89_track_ps_work(struct wiphy *wiphy, struct wiphy_work *work) 3884 { 3885 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 3886 track_ps_work.work); 3887 struct rtw89_vif *rtwvif; 3888 3889 lockdep_assert_wiphy(wiphy); 3890 3891 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WORK, rtwdev->flags)) 3892 return; 3893 3894 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 3895 return; 3896 3897 wiphy_delayed_work_queue(wiphy, &rtwdev->track_ps_work, 3898 RTW89_TRACK_PS_WORK_PERIOD); 3899 3900 rtw89_for_each_rtwvif(rtwdev, rtwvif) 3901 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats_ps, 3902 RTW89_TFC_INTERVAL_100MS); 3903 3904 if (rtwdev->scanning) 3905 return; 3906 3907 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 3908 rtw89_enter_lps_track(rtwdev); 3909 } 3910 3911 static void rtw89_track_work(struct wiphy *wiphy, struct wiphy_work *work) 3912 { 3913 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 3914 track_work.work); 3915 bool tfc_changed; 3916 3917 lockdep_assert_wiphy(wiphy); 3918 3919 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WORK, rtwdev->flags)) 3920 return; 3921 3922 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 3923 return; 3924 3925 wiphy_delayed_work_queue(wiphy, &rtwdev->track_work, 3926 RTW89_TRACK_WORK_PERIOD); 3927 3928 tfc_changed = rtw89_traffic_stats_track(rtwdev); 3929 if (rtwdev->scanning) 3930 return; 3931 3932 rtw89_leave_lps(rtwdev); 3933 3934 if (tfc_changed) { 3935 rtw89_hci_recalc_int_mit(rtwdev); 3936 rtw89_btc_ntfy_wl_sta(rtwdev); 3937 } 3938 rtw89_mac_bf_monitor_track(rtwdev); 3939 rtw89_phy_stat_track(rtwdev); 3940 rtw89_phy_env_monitor_track(rtwdev); 3941 rtw89_phy_dig(rtwdev); 3942 rtw89_core_rfk_track(rtwdev); 3943 rtw89_phy_ra_update(rtwdev); 3944 rtw89_phy_cfo_track(rtwdev); 3945 rtw89_phy_tx_path_div_track(rtwdev); 3946 rtw89_phy_antdiv_track(rtwdev); 3947 rtw89_phy_ul_tb_ctrl_track(rtwdev); 3948 rtw89_phy_edcca_track(rtwdev); 3949 rtw89_sar_track(rtwdev); 3950 rtw89_chanctx_track(rtwdev); 3951 rtw89_core_rfkill_poll(rtwdev, false); 3952 rtw89_core_mlo_track(rtwdev); 3953 3954 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 3955 rtw89_enter_lps_track(rtwdev); 3956 } 3957 3958 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) 3959 { 3960 unsigned long bit; 3961 3962 bit = find_first_zero_bit(addr, size); 3963 if (bit < size) 3964 set_bit(bit, addr); 3965 3966 return bit; 3967 } 3968 3969 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) 3970 { 3971 clear_bit(bit, addr); 3972 } 3973 3974 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) 3975 { 3976 bitmap_zero(addr, nbits); 3977 } 3978 3979 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 3980 struct rtw89_sta_link *rtwsta_link, u8 tid, 3981 u8 *cam_idx) 3982 { 3983 const struct rtw89_chip_info *chip = rtwdev->chip; 3984 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3985 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3986 u8 idx; 3987 int i; 3988 3989 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3990 3991 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num); 3992 if (idx == chip->bacam_num) { 3993 /* allocate a static BA CAM to tid=0/5, so replace the existing 3994 * one if BA CAM is full. Hardware will process the original tid 3995 * automatically. 3996 */ 3997 if (tid != 0 && tid != 5) 3998 return -ENOSPC; 3999 4000 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) { 4001 tmp = &cam_info->ba_cam_entry[i]; 4002 if (tmp->tid == 0 || tmp->tid == 5) 4003 continue; 4004 4005 idx = i; 4006 entry = tmp; 4007 list_del(&entry->list); 4008 break; 4009 } 4010 4011 if (!entry) 4012 return -ENOSPC; 4013 } else { 4014 entry = &cam_info->ba_cam_entry[idx]; 4015 } 4016 4017 entry->tid = tid; 4018 list_add_tail(&entry->list, &rtwsta_link->ba_cam_list); 4019 4020 *cam_idx = idx; 4021 4022 return 0; 4023 } 4024 4025 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 4026 struct rtw89_sta_link *rtwsta_link, u8 tid, 4027 u8 *cam_idx) 4028 { 4029 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 4030 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 4031 u8 idx; 4032 4033 lockdep_assert_wiphy(rtwdev->hw->wiphy); 4034 4035 list_for_each_entry_safe(entry, tmp, &rtwsta_link->ba_cam_list, list) { 4036 if (entry->tid != tid) 4037 continue; 4038 4039 idx = entry - cam_info->ba_cam_entry; 4040 list_del(&entry->list); 4041 4042 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx); 4043 *cam_idx = idx; 4044 return 0; 4045 } 4046 4047 return -ENOENT; 4048 } 4049 4050 #define RTW89_TYPE_MAPPING(_type) \ 4051 case NL80211_IFTYPE_ ## _type: \ 4052 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ 4053 break 4054 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc) 4055 { 4056 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4057 const struct ieee80211_bss_conf *bss_conf; 4058 4059 switch (vif->type) { 4060 case NL80211_IFTYPE_STATION: 4061 if (vif->p2p) 4062 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT; 4063 else 4064 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_STATION; 4065 break; 4066 case NL80211_IFTYPE_AP: 4067 if (vif->p2p) 4068 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_GO; 4069 else 4070 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_AP; 4071 break; 4072 RTW89_TYPE_MAPPING(ADHOC); 4073 RTW89_TYPE_MAPPING(MONITOR); 4074 RTW89_TYPE_MAPPING(MESH_POINT); 4075 default: 4076 WARN_ON(1); 4077 break; 4078 } 4079 4080 switch (vif->type) { 4081 case NL80211_IFTYPE_AP: 4082 case NL80211_IFTYPE_MESH_POINT: 4083 rtwvif_link->net_type = RTW89_NET_TYPE_AP_MODE; 4084 rtwvif_link->self_role = RTW89_SELF_ROLE_AP; 4085 break; 4086 case NL80211_IFTYPE_ADHOC: 4087 rtwvif_link->net_type = RTW89_NET_TYPE_AD_HOC; 4088 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT; 4089 break; 4090 case NL80211_IFTYPE_STATION: 4091 if (assoc) { 4092 rtwvif_link->net_type = RTW89_NET_TYPE_INFRA; 4093 4094 rcu_read_lock(); 4095 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 4096 rtwvif_link->trigger = bss_conf->he_support; 4097 rcu_read_unlock(); 4098 } else { 4099 rtwvif_link->net_type = RTW89_NET_TYPE_NO_LINK; 4100 rtwvif_link->trigger = false; 4101 } 4102 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT; 4103 rtwvif_link->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; 4104 break; 4105 case NL80211_IFTYPE_MONITOR: 4106 break; 4107 default: 4108 WARN_ON(1); 4109 break; 4110 } 4111 } 4112 4113 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 4114 struct rtw89_vif_link *rtwvif_link, 4115 struct rtw89_sta_link *rtwsta_link) 4116 { 4117 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4118 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 4119 struct rtw89_hal *hal = &rtwdev->hal; 4120 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 4121 int i; 4122 int ret; 4123 4124 rtwsta_link->prev_rssi = 0; 4125 INIT_LIST_HEAD(&rtwsta_link->ba_cam_list); 4126 ewma_rssi_init(&rtwsta_link->avg_rssi); 4127 ewma_snr_init(&rtwsta_link->avg_snr); 4128 ewma_evm_init(&rtwsta_link->evm_1ss); 4129 for (i = 0; i < ant_num; i++) { 4130 ewma_rssi_init(&rtwsta_link->rssi[i]); 4131 ewma_evm_init(&rtwsta_link->evm_min[i]); 4132 ewma_evm_init(&rtwsta_link->evm_max[i]); 4133 } 4134 4135 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 4136 /* must do rtw89_reg_6ghz_recalc() before rfk channel */ 4137 ret = rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, true); 4138 if (ret) 4139 return ret; 4140 4141 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 4142 BTC_ROLE_MSTS_STA_CONN_START); 4143 rtw89_chip_rfk_channel(rtwdev, rtwvif_link); 4144 4145 if (vif->p2p) { 4146 rtw89_mac_get_tx_retry_limit(rtwdev, rtwsta_link, 4147 &rtwsta_link->tx_retry); 4148 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false, 60); 4149 } 4150 rtw89_phy_dig_suspend(rtwdev); 4151 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 4152 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta_link->mac_id, false); 4153 if (ret) { 4154 rtw89_warn(rtwdev, "failed to send h2c macid pause\n"); 4155 return ret; 4156 } 4157 4158 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link, 4159 RTW89_ROLE_CREATE); 4160 if (ret) { 4161 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 4162 return ret; 4163 } 4164 4165 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 4166 if (ret) 4167 return ret; 4168 4169 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 4170 if (ret) 4171 return ret; 4172 } 4173 4174 return 0; 4175 } 4176 4177 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 4178 struct rtw89_vif_link *rtwvif_link, 4179 struct rtw89_sta_link *rtwsta_link) 4180 { 4181 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4182 4183 rtw89_assoc_link_clr(rtwsta_link); 4184 4185 if (vif->type == NL80211_IFTYPE_STATION) 4186 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, false); 4187 4188 if (rtwvif_link->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT) 4189 rtw89_p2p_noa_once_deinit(rtwvif_link); 4190 4191 return 0; 4192 } 4193 4194 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 4195 struct rtw89_vif_link *rtwvif_link, 4196 struct rtw89_sta_link *rtwsta_link) 4197 { 4198 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4199 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 4200 int ret; 4201 4202 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, true); 4203 rtw89_mac_bf_disassoc(rtwdev, rtwvif_link, rtwsta_link); 4204 4205 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 4206 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta_link->addr_cam); 4207 if (sta->tdls) 4208 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta_link->bssid_cam); 4209 4210 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 4211 rtw89_vif_type_mapping(rtwvif_link, false); 4212 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif_link, true); 4213 } 4214 4215 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 4216 if (ret) { 4217 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 4218 return ret; 4219 } 4220 4221 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, true); 4222 if (ret) { 4223 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 4224 return ret; 4225 } 4226 4227 /* update cam aid mac_id net_type */ 4228 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL); 4229 if (ret) { 4230 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 4231 return ret; 4232 } 4233 4234 return ret; 4235 } 4236 4237 static bool rtw89_sta_link_can_er(struct rtw89_dev *rtwdev, 4238 struct ieee80211_bss_conf *bss_conf, 4239 struct ieee80211_link_sta *link_sta) 4240 { 4241 if (!bss_conf->he_support || 4242 bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE) 4243 return false; 4244 4245 if (rtwdev->chip->chip_id == RTL8852C && 4246 rtw89_sta_link_has_su_mu_4xhe08(link_sta) && 4247 !rtw89_sta_link_has_er_su_4xhe08(link_sta)) 4248 return false; 4249 4250 return true; 4251 } 4252 4253 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 4254 struct rtw89_vif_link *rtwvif_link, 4255 struct rtw89_sta_link *rtwsta_link) 4256 { 4257 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4258 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 4259 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif_link, 4260 rtwsta_link); 4261 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 4262 rtwvif_link->chanctx_idx); 4263 struct ieee80211_link_sta *link_sta; 4264 int ret; 4265 4266 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 4267 if (sta->tdls) { 4268 rcu_read_lock(); 4269 4270 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 4271 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif_link, bssid_cam, 4272 link_sta->addr); 4273 if (ret) { 4274 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n"); 4275 rcu_read_unlock(); 4276 return ret; 4277 } 4278 4279 rcu_read_unlock(); 4280 } 4281 4282 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta_link->addr_cam, bssid_cam); 4283 if (ret) { 4284 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n"); 4285 return ret; 4286 } 4287 } 4288 4289 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 4290 if (ret) { 4291 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 4292 return ret; 4293 } 4294 4295 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, false); 4296 if (ret) { 4297 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 4298 return ret; 4299 } 4300 4301 /* update cam aid mac_id net_type */ 4302 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL); 4303 if (ret) { 4304 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 4305 return ret; 4306 } 4307 4308 rtw89_phy_ra_assoc(rtwdev, rtwsta_link); 4309 rtw89_mac_bf_assoc(rtwdev, rtwvif_link, rtwsta_link); 4310 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, false); 4311 4312 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 4313 struct ieee80211_bss_conf *bss_conf; 4314 4315 rcu_read_lock(); 4316 4317 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4318 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 4319 rtwsta_link->er_cap = rtw89_sta_link_can_er(rtwdev, bss_conf, link_sta); 4320 4321 rcu_read_unlock(); 4322 4323 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 4324 BTC_ROLE_MSTS_STA_CONN_END); 4325 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta_link->htc_template, chan); 4326 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif_link); 4327 4328 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif_link, rtwsta_link->mac_id); 4329 if (ret) { 4330 rtw89_warn(rtwdev, "failed to send h2c general packet\n"); 4331 return ret; 4332 } 4333 4334 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true); 4335 4336 if (vif->p2p) 4337 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false, 4338 rtwsta_link->tx_retry); 4339 rtw89_phy_dig_resume(rtwdev, false); 4340 } 4341 4342 rtw89_assoc_link_set(rtwsta_link); 4343 return ret; 4344 } 4345 4346 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 4347 struct rtw89_vif_link *rtwvif_link, 4348 struct rtw89_sta_link *rtwsta_link) 4349 { 4350 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4351 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 4352 int ret; 4353 4354 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 4355 rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, false); 4356 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 4357 BTC_ROLE_MSTS_STA_DIS_CONN); 4358 4359 if (vif->p2p) 4360 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false, 4361 rtwsta_link->tx_retry); 4362 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 4363 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link, 4364 RTW89_ROLE_REMOVE); 4365 if (ret) { 4366 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 4367 return ret; 4368 } 4369 } 4370 4371 return 0; 4372 } 4373 4374 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 4375 struct ieee80211_sta *sta, 4376 struct cfg80211_tid_cfg *tid_conf) 4377 { 4378 struct ieee80211_txq *txq; 4379 struct rtw89_txq *rtwtxq; 4380 u32 mask = tid_conf->mask; 4381 u8 tids = tid_conf->tids; 4382 int tids_nbit = BITS_PER_BYTE; 4383 int i; 4384 4385 for (i = 0; i < tids_nbit; i++, tids >>= 1) { 4386 if (!tids) 4387 break; 4388 4389 if (!(tids & BIT(0))) 4390 continue; 4391 4392 txq = sta->txq[i]; 4393 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 4394 4395 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) { 4396 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) { 4397 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 4398 } else { 4399 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) 4400 ieee80211_stop_tx_ba_session(sta, txq->tid); 4401 spin_lock_bh(&rtwdev->ba_lock); 4402 list_del_init(&rtwtxq->list); 4403 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 4404 spin_unlock_bh(&rtwdev->ba_lock); 4405 } 4406 } 4407 4408 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) { 4409 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE) 4410 sta->max_amsdu_subframes = 0; 4411 else 4412 sta->max_amsdu_subframes = 1; 4413 } 4414 } 4415 } 4416 4417 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 4418 struct ieee80211_sta *sta, 4419 struct cfg80211_tid_config *tid_config) 4420 { 4421 int i; 4422 4423 for (i = 0; i < tid_config->n_tid_conf; i++) 4424 _rtw89_core_set_tid_config(rtwdev, sta, 4425 &tid_config->tid_conf[i]); 4426 } 4427 4428 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, 4429 struct ieee80211_sta_ht_cap *ht_cap) 4430 { 4431 static const __le16 highest[RF_PATH_MAX] = { 4432 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), 4433 }; 4434 struct rtw89_hal *hal = &rtwdev->hal; 4435 u8 nss = hal->rx_nss; 4436 int i; 4437 4438 ht_cap->ht_supported = true; 4439 ht_cap->cap = 0; 4440 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 4441 IEEE80211_HT_CAP_MAX_AMSDU | 4442 IEEE80211_HT_CAP_TX_STBC | 4443 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 4444 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 4445 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 4446 IEEE80211_HT_CAP_DSSSCCK40 | 4447 IEEE80211_HT_CAP_SGI_40; 4448 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 4449 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; 4450 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 4451 for (i = 0; i < nss; i++) 4452 ht_cap->mcs.rx_mask[i] = 0xFF; 4453 ht_cap->mcs.rx_mask[4] = 0x01; 4454 ht_cap->mcs.rx_highest = highest[nss - 1]; 4455 } 4456 4457 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, 4458 struct ieee80211_sta_vht_cap *vht_cap) 4459 { 4460 static const __le16 highest_bw80[RF_PATH_MAX] = { 4461 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), 4462 }; 4463 static const __le16 highest_bw160[RF_PATH_MAX] = { 4464 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467), 4465 }; 4466 const struct rtw89_chip_info *chip = rtwdev->chip; 4467 const __le16 *highest = chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160) ? 4468 highest_bw160 : highest_bw80; 4469 struct rtw89_hal *hal = &rtwdev->hal; 4470 u16 tx_mcs_map = 0, rx_mcs_map = 0; 4471 u8 sts_cap = 3; 4472 int i; 4473 4474 for (i = 0; i < 8; i++) { 4475 if (i < hal->tx_nss) 4476 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 4477 else 4478 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 4479 if (i < hal->rx_nss) 4480 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 4481 else 4482 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 4483 } 4484 4485 vht_cap->vht_supported = true; 4486 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 4487 IEEE80211_VHT_CAP_SHORT_GI_80 | 4488 IEEE80211_VHT_CAP_RXSTBC_1 | 4489 IEEE80211_VHT_CAP_HTC_VHT | 4490 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 4491 0; 4492 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 4493 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 4494 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 4495 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 4496 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; 4497 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4498 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 4499 IEEE80211_VHT_CAP_SHORT_GI_160; 4500 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); 4501 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); 4502 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; 4503 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; 4504 4505 if (ieee80211_hw_check(rtwdev->hw, SUPPORTS_VHT_EXT_NSS_BW)) 4506 vht_cap->vht_mcs.tx_highest |= 4507 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); 4508 } 4509 4510 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, 4511 enum nl80211_band band, 4512 enum nl80211_iftype iftype, 4513 struct ieee80211_sband_iftype_data *iftype_data) 4514 { 4515 const struct rtw89_chip_info *chip = rtwdev->chip; 4516 struct rtw89_hal *hal = &rtwdev->hal; 4517 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || 4518 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); 4519 struct ieee80211_sta_he_cap *he_cap; 4520 int nss = hal->rx_nss; 4521 u8 *mac_cap_info; 4522 u8 *phy_cap_info; 4523 u16 mcs_map = 0; 4524 int i; 4525 4526 for (i = 0; i < 8; i++) { 4527 if (i < nss) 4528 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); 4529 else 4530 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); 4531 } 4532 4533 he_cap = &iftype_data->he_cap; 4534 mac_cap_info = he_cap->he_cap_elem.mac_cap_info; 4535 phy_cap_info = he_cap->he_cap_elem.phy_cap_info; 4536 4537 he_cap->has_he = true; 4538 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 4539 if (iftype == NL80211_IFTYPE_STATION) 4540 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 4541 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | 4542 IEEE80211_HE_MAC_CAP2_BSR; 4543 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 4544 if (iftype == NL80211_IFTYPE_AP) 4545 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; 4546 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | 4547 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 4548 if (iftype == NL80211_IFTYPE_STATION) 4549 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; 4550 if (band == NL80211_BAND_2GHZ) { 4551 phy_cap_info[0] = 4552 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 4553 } else { 4554 phy_cap_info[0] = 4555 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 4556 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4557 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 4558 } 4559 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 4560 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 4561 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 4562 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 4563 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 4564 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 4565 IEEE80211_HE_PHY_CAP2_DOPPLER_TX; 4566 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; 4567 if (iftype == NL80211_IFTYPE_STATION) 4568 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | 4569 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; 4570 if (iftype == NL80211_IFTYPE_AP) 4571 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; 4572 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 4573 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 4574 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4575 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 4576 phy_cap_info[5] = no_ng16 ? 0 : 4577 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 4578 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; 4579 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 4580 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 4581 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 4582 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; 4583 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 4584 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 4585 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 4586 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 4587 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | 4588 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; 4589 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4590 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 4591 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 4592 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 4593 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 4594 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 4595 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 4596 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 4597 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 4598 if (iftype == NL80211_IFTYPE_STATION) 4599 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 4600 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); 4601 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); 4602 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) { 4603 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map); 4604 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map); 4605 } 4606 4607 if (band == NL80211_BAND_6GHZ) { 4608 __le16 capa; 4609 4610 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE, 4611 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 4612 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 4613 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 4614 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 4615 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 4616 iftype_data->he_6ghz_capa.capa = capa; 4617 } 4618 } 4619 4620 static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev, 4621 enum nl80211_band band, 4622 enum nl80211_iftype iftype, 4623 struct ieee80211_sband_iftype_data *iftype_data) 4624 { 4625 const struct rtw89_chip_info *chip = rtwdev->chip; 4626 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem; 4627 struct ieee80211_eht_mcs_nss_supp *eht_nss; 4628 struct ieee80211_sta_eht_cap *eht_cap; 4629 struct rtw89_hal *hal = &rtwdev->hal; 4630 bool support_mcs_12_13 = true; 4631 bool support_320mhz = false; 4632 u8 val, val_mcs13; 4633 int sts = 8; 4634 4635 if (chip->chip_gen == RTW89_CHIP_AX) 4636 return; 4637 4638 if (hal->no_mcs_12_13) 4639 support_mcs_12_13 = false; 4640 4641 if (band == NL80211_BAND_6GHZ && 4642 chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_320)) 4643 support_320mhz = true; 4644 4645 eht_cap = &iftype_data->eht_cap; 4646 eht_cap_elem = &eht_cap->eht_cap_elem; 4647 eht_nss = &eht_cap->eht_mcs_nss_supp; 4648 4649 eht_cap->has_eht = true; 4650 4651 eht_cap_elem->mac_cap_info[0] = 4652 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991, 4653 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); 4654 eht_cap_elem->mac_cap_info[1] = 0; 4655 4656 eht_cap_elem->phy_cap_info[0] = 4657 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 4658 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 4659 if (support_320mhz) 4660 eht_cap_elem->phy_cap_info[0] |= 4661 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 4662 4663 eht_cap_elem->phy_cap_info[0] |= 4664 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)), 4665 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 4666 eht_cap_elem->phy_cap_info[1] = 4667 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)), 4668 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) | 4669 u8_encode_bits(sts - 1, 4670 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK); 4671 if (support_320mhz) 4672 eht_cap_elem->phy_cap_info[1] |= 4673 u8_encode_bits(sts - 1, 4674 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 4675 4676 eht_cap_elem->phy_cap_info[2] = 0; 4677 4678 eht_cap_elem->phy_cap_info[3] = 4679 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 4680 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 4681 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 4682 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK; 4683 4684 eht_cap_elem->phy_cap_info[4] = 4685 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP | 4686 u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 4687 4688 eht_cap_elem->phy_cap_info[5] = 4689 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US, 4690 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK); 4691 4692 eht_cap_elem->phy_cap_info[6] = 0; 4693 eht_cap_elem->phy_cap_info[7] = 0; 4694 eht_cap_elem->phy_cap_info[8] = 0; 4695 4696 val = u8_encode_bits(hal->rx_nss, IEEE80211_EHT_MCS_NSS_RX) | 4697 u8_encode_bits(hal->tx_nss, IEEE80211_EHT_MCS_NSS_TX); 4698 val_mcs13 = support_mcs_12_13 ? val : 0; 4699 4700 eht_nss->bw._80.rx_tx_mcs9_max_nss = val; 4701 eht_nss->bw._80.rx_tx_mcs11_max_nss = val; 4702 eht_nss->bw._80.rx_tx_mcs13_max_nss = val_mcs13; 4703 eht_nss->bw._160.rx_tx_mcs9_max_nss = val; 4704 eht_nss->bw._160.rx_tx_mcs11_max_nss = val; 4705 eht_nss->bw._160.rx_tx_mcs13_max_nss = val_mcs13; 4706 if (support_320mhz) { 4707 eht_nss->bw._320.rx_tx_mcs9_max_nss = val; 4708 eht_nss->bw._320.rx_tx_mcs11_max_nss = val; 4709 eht_nss->bw._320.rx_tx_mcs13_max_nss = val_mcs13; 4710 } 4711 } 4712 4713 #define RTW89_SBAND_IFTYPES_NR 2 4714 4715 static int rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev, 4716 enum nl80211_band band, 4717 struct ieee80211_supported_band *sband) 4718 { 4719 struct ieee80211_sband_iftype_data *iftype_data; 4720 enum nl80211_iftype iftype; 4721 int idx = 0; 4722 4723 iftype_data = devm_kcalloc(rtwdev->dev, RTW89_SBAND_IFTYPES_NR, 4724 sizeof(*iftype_data), GFP_KERNEL); 4725 if (!iftype_data) 4726 return -ENOMEM; 4727 4728 for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) { 4729 switch (iftype) { 4730 case NL80211_IFTYPE_STATION: 4731 case NL80211_IFTYPE_AP: 4732 break; 4733 default: 4734 continue; 4735 } 4736 4737 if (idx >= RTW89_SBAND_IFTYPES_NR) { 4738 rtw89_warn(rtwdev, "run out of iftype_data\n"); 4739 break; 4740 } 4741 4742 iftype_data[idx].types_mask = BIT(iftype); 4743 4744 rtw89_init_he_cap(rtwdev, band, iftype, &iftype_data[idx]); 4745 rtw89_init_eht_cap(rtwdev, band, iftype, &iftype_data[idx]); 4746 4747 idx++; 4748 } 4749 4750 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx); 4751 return 0; 4752 } 4753 4754 static struct ieee80211_supported_band * 4755 rtw89_core_sband_dup(struct rtw89_dev *rtwdev, 4756 const struct ieee80211_supported_band *sband) 4757 { 4758 struct ieee80211_supported_band *dup; 4759 4760 dup = devm_kmemdup(rtwdev->dev, sband, sizeof(*sband), GFP_KERNEL); 4761 if (!dup) 4762 return NULL; 4763 4764 dup->channels = devm_kmemdup(rtwdev->dev, sband->channels, 4765 sizeof(*sband->channels) * sband->n_channels, 4766 GFP_KERNEL); 4767 if (!dup->channels) 4768 return NULL; 4769 4770 dup->bitrates = devm_kmemdup(rtwdev->dev, sband->bitrates, 4771 sizeof(*sband->bitrates) * sband->n_bitrates, 4772 GFP_KERNEL); 4773 if (!dup->bitrates) 4774 return NULL; 4775 4776 return dup; 4777 } 4778 4779 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) 4780 { 4781 struct ieee80211_hw *hw = rtwdev->hw; 4782 struct ieee80211_supported_band *sband; 4783 u8 support_bands = rtwdev->chip->support_bands; 4784 int ret; 4785 4786 if (support_bands & BIT(NL80211_BAND_2GHZ)) { 4787 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_2ghz); 4788 if (!sband) 4789 return -ENOMEM; 4790 #if defined(__FreeBSD__) 4791 if (rtw_ht_support) 4792 #endif 4793 rtw89_init_ht_cap(rtwdev, &sband->ht_cap); 4794 #if defined(__FreeBSD__) 4795 if (rtw_eht_support) { 4796 #endif 4797 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_2GHZ, sband); 4798 if (ret) 4799 return ret; 4800 #if defined(__FreeBSD__) 4801 } 4802 #endif 4803 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 4804 } 4805 4806 if (support_bands & BIT(NL80211_BAND_5GHZ)) { 4807 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_5ghz); 4808 if (!sband) 4809 return -ENOMEM; 4810 #if defined(__FreeBSD__) 4811 if (rtw_ht_support) 4812 #endif 4813 rtw89_init_ht_cap(rtwdev, &sband->ht_cap); 4814 #if defined(__FreeBSD__) 4815 if (rtw_vht_support) 4816 #endif 4817 rtw89_init_vht_cap(rtwdev, &sband->vht_cap); 4818 #if defined(__FreeBSD__) 4819 if (rtw_eht_support) { 4820 #endif 4821 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_5GHZ, sband); 4822 if (ret) 4823 return ret; 4824 #if defined(__FreeBSD__) 4825 } 4826 #endif 4827 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 4828 } 4829 4830 #if defined(__FreeBSD__) 4831 if (rtw_eht_support) 4832 #endif 4833 if (support_bands & BIT(NL80211_BAND_6GHZ)) { 4834 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_6ghz); 4835 if (!sband) 4836 return -ENOMEM; 4837 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband); 4838 if (ret) 4839 return ret; 4840 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband; 4841 } 4842 4843 return 0; 4844 } 4845 4846 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) 4847 { 4848 int i; 4849 4850 for (i = 0; i < RTW89_PHY_NUM; i++) 4851 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); 4852 for (i = 0; i < RTW89_PHY_NUM; i++) 4853 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; 4854 } 4855 4856 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work) 4857 { 4858 struct rtw89_dev *rtwdev; 4859 struct rtw89_vif_link *rtwvif_link = container_of(work, struct rtw89_vif_link, 4860 update_beacon_work); 4861 4862 lockdep_assert_wiphy(wiphy); 4863 4864 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE) 4865 return; 4866 4867 rtwdev = rtwvif_link->rtwvif->rtwdev; 4868 4869 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link); 4870 } 4871 4872 void rtw89_core_csa_beacon_work(struct wiphy *wiphy, struct wiphy_work *work) 4873 { 4874 struct rtw89_vif_link *rtwvif_link = 4875 container_of(work, struct rtw89_vif_link, csa_beacon_work.work); 4876 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 4877 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4878 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 4879 struct ieee80211_bss_conf *bss_conf; 4880 unsigned int delay; 4881 4882 lockdep_assert_wiphy(wiphy); 4883 4884 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE) 4885 return; 4886 4887 rcu_read_lock(); 4888 4889 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4890 if (!bss_conf->csa_active) { 4891 rcu_read_unlock(); 4892 return; 4893 } 4894 4895 delay = ieee80211_tu_to_usec(bss_conf->beacon_int); 4896 4897 rcu_read_unlock(); 4898 4899 if (!ieee80211_beacon_cntdwn_is_complete(vif, rtwvif_link->link_id)) { 4900 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link); 4901 4902 wiphy_delayed_work_queue(wiphy, &rtwvif_link->csa_beacon_work, 4903 usecs_to_jiffies(delay)); 4904 } else { 4905 ieee80211_csa_finish(vif, rtwvif_link->link_id); 4906 } 4907 } 4908 4909 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond) 4910 { 4911 struct completion *cmpl = &wait->completion; 4912 unsigned long time_left; 4913 unsigned int cur; 4914 4915 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond); 4916 if (cur != RTW89_WAIT_COND_IDLE) 4917 return -EBUSY; 4918 4919 time_left = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT); 4920 if (time_left == 0) { 4921 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4922 return -ETIMEDOUT; 4923 } 4924 4925 if (wait->data.err) 4926 return -EFAULT; 4927 4928 return 0; 4929 } 4930 4931 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 4932 const struct rtw89_completion_data *data) 4933 { 4934 unsigned int cur; 4935 4936 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE); 4937 if (cur != cond) 4938 return; 4939 4940 wait->data = *data; 4941 complete(&wait->completion); 4942 } 4943 4944 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event) 4945 { 4946 u16 bt_req_len; 4947 4948 switch (event) { 4949 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT: 4950 bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0); 4951 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4952 "coex updates BT req len to %d TU\n", bt_req_len); 4953 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE); 4954 break; 4955 default: 4956 if (event < NUM_OF_RTW89_BTC_HMSG) 4957 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4958 "unhandled BTC HMSG event: %d\n", event); 4959 else 4960 rtw89_warn(rtwdev, 4961 "unrecognized BTC HMSG event: %d\n", event); 4962 break; 4963 } 4964 } 4965 4966 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks) 4967 { 4968 const struct dmi_system_id *match; 4969 enum rtw89_quirks quirk; 4970 4971 if (!quirks) 4972 return; 4973 4974 for (match = dmi_first_match(quirks); match; match = dmi_first_match(match + 1)) { 4975 quirk = (uintptr_t)match->driver_data; 4976 if (quirk >= NUM_OF_RTW89_QUIRKS) 4977 continue; 4978 4979 set_bit(quirk, rtwdev->quirks); 4980 } 4981 } 4982 EXPORT_SYMBOL(rtw89_check_quirks); 4983 4984 int rtw89_core_start(struct rtw89_dev *rtwdev) 4985 { 4986 int ret; 4987 4988 ret = rtw89_mac_init(rtwdev); 4989 if (ret) { 4990 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); 4991 return ret; 4992 } 4993 4994 rtw89_btc_ntfy_poweron(rtwdev); 4995 4996 /* efuse process */ 4997 4998 /* pre-config BB/RF, BB reset/RFC reset */ 4999 ret = rtw89_chip_reset_bb_rf(rtwdev); 5000 if (ret) 5001 return ret; 5002 5003 rtw89_phy_init_bb_reg(rtwdev); 5004 rtw89_chip_bb_postinit(rtwdev); 5005 rtw89_phy_init_rf_reg(rtwdev, false); 5006 5007 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); 5008 5009 rtw89_phy_dm_init(rtwdev); 5010 5011 rtw89_mac_cfg_ppdu_status_bands(rtwdev, true); 5012 rtw89_mac_cfg_phy_rpt_bands(rtwdev, true); 5013 rtw89_mac_update_rts_threshold(rtwdev); 5014 5015 ret = rtw89_hci_start(rtwdev); 5016 if (ret) { 5017 rtw89_err(rtwdev, "failed to start hci\n"); 5018 return ret; 5019 } 5020 5021 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->track_work, 5022 RTW89_TRACK_WORK_PERIOD); 5023 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->track_ps_work, 5024 RTW89_TRACK_PS_WORK_PERIOD); 5025 5026 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 5027 5028 rtw89_chip_rfk_init_late(rtwdev); 5029 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 5030 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable); 5031 rtw89_fw_h2c_init_ba_cam(rtwdev); 5032 5033 return 0; 5034 } 5035 5036 void rtw89_core_stop(struct rtw89_dev *rtwdev) 5037 { 5038 struct wiphy *wiphy = rtwdev->hw->wiphy; 5039 struct rtw89_btc *btc = &rtwdev->btc; 5040 5041 lockdep_assert_wiphy(wiphy); 5042 5043 /* Prvent to stop twice; enter_ips and ops_stop */ 5044 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 5045 return; 5046 5047 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 5048 5049 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 5050 5051 wiphy_work_cancel(wiphy, &rtwdev->c2h_work); 5052 wiphy_work_cancel(wiphy, &rtwdev->cancel_6ghz_probe_work); 5053 wiphy_work_cancel(wiphy, &btc->eapol_notify_work); 5054 wiphy_work_cancel(wiphy, &btc->arp_notify_work); 5055 wiphy_work_cancel(wiphy, &btc->dhcp_notify_work); 5056 wiphy_work_cancel(wiphy, &btc->icmp_notify_work); 5057 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 5058 wiphy_delayed_work_cancel(wiphy, &rtwdev->track_work); 5059 wiphy_delayed_work_cancel(wiphy, &rtwdev->track_ps_work); 5060 wiphy_delayed_work_cancel(wiphy, &rtwdev->chanctx_work); 5061 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_act1_work); 5062 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_bt_devinfo_work); 5063 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_rfk_chk_work); 5064 wiphy_delayed_work_cancel(wiphy, &rtwdev->cfo_track_work); 5065 wiphy_delayed_work_cancel(wiphy, &rtwdev->mcc_prepare_done_work); 5066 cancel_delayed_work_sync(&rtwdev->forbid_ba_work); 5067 wiphy_delayed_work_cancel(wiphy, &rtwdev->antdiv_work); 5068 5069 rtw89_btc_ntfy_poweroff(rtwdev); 5070 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 5071 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 5072 rtw89_hci_stop(rtwdev); 5073 rtw89_hci_deinit(rtwdev); 5074 rtw89_mac_pwr_off(rtwdev); 5075 rtw89_hci_reset(rtwdev); 5076 } 5077 5078 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev) 5079 { 5080 const struct rtw89_chip_info *chip = rtwdev->chip; 5081 u8 mac_id_num; 5082 u8 mac_id; 5083 5084 if (rtwdev->support_mlo) 5085 mac_id_num = chip->support_macid_num / chip->support_link_num; 5086 else 5087 mac_id_num = chip->support_macid_num; 5088 5089 mac_id = find_first_zero_bit(rtwdev->mac_id_map, mac_id_num); 5090 if (mac_id == mac_id_num) 5091 return RTW89_MAX_MAC_ID_NUM; 5092 5093 set_bit(mac_id, rtwdev->mac_id_map); 5094 return mac_id; 5095 } 5096 5097 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id) 5098 { 5099 clear_bit(mac_id, rtwdev->mac_id_map); 5100 } 5101 5102 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5103 u8 mac_id, u8 port) 5104 { 5105 const struct rtw89_chip_info *chip = rtwdev->chip; 5106 u8 support_link_num = chip->support_link_num; 5107 u8 support_mld_num = 0; 5108 unsigned int link_id; 5109 u8 index; 5110 5111 bitmap_zero(rtwvif->links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 5112 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) 5113 rtwvif->links[link_id] = NULL; 5114 5115 rtwvif->rtwdev = rtwdev; 5116 5117 if (rtwdev->support_mlo) { 5118 rtwvif->links_inst_valid_num = support_link_num; 5119 support_mld_num = chip->support_macid_num / support_link_num; 5120 } else { 5121 rtwvif->links_inst_valid_num = 1; 5122 } 5123 5124 for (index = 0; index < rtwvif->links_inst_valid_num; index++) { 5125 struct rtw89_vif_link *inst = &rtwvif->links_inst[index]; 5126 5127 inst->rtwvif = rtwvif; 5128 inst->mac_id = mac_id + index * support_mld_num; 5129 inst->mac_idx = RTW89_MAC_0 + index; 5130 inst->phy_idx = RTW89_PHY_0 + index; 5131 5132 /* multi-link use the same port id on different HW bands */ 5133 inst->port = port; 5134 } 5135 } 5136 5137 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5138 struct rtw89_sta *rtwsta, u8 mac_id) 5139 { 5140 const struct rtw89_chip_info *chip = rtwdev->chip; 5141 u8 support_link_num = chip->support_link_num; 5142 u8 support_mld_num = 0; 5143 unsigned int link_id; 5144 u8 index; 5145 5146 bitmap_zero(rtwsta->links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 5147 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) 5148 rtwsta->links[link_id] = NULL; 5149 5150 rtwsta->rtwdev = rtwdev; 5151 rtwsta->rtwvif = rtwvif; 5152 5153 if (rtwdev->support_mlo) { 5154 rtwsta->links_inst_valid_num = support_link_num; 5155 support_mld_num = chip->support_macid_num / support_link_num; 5156 } else { 5157 rtwsta->links_inst_valid_num = 1; 5158 } 5159 5160 for (index = 0; index < rtwsta->links_inst_valid_num; index++) { 5161 struct rtw89_sta_link *inst = &rtwsta->links_inst[index]; 5162 5163 inst->rtwvif_link = &rtwvif->links_inst[index]; 5164 5165 inst->rtwsta = rtwsta; 5166 inst->mac_id = mac_id + index * support_mld_num; 5167 } 5168 } 5169 5170 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 5171 unsigned int link_id) 5172 { 5173 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id]; 5174 u8 index; 5175 int ret; 5176 5177 if (rtwvif_link) 5178 return rtwvif_link; 5179 5180 index = find_first_zero_bit(rtwvif->links_inst_map, 5181 rtwvif->links_inst_valid_num); 5182 if (index == rtwvif->links_inst_valid_num) { 5183 ret = -EBUSY; 5184 goto err; 5185 } 5186 5187 rtwvif_link = &rtwvif->links_inst[index]; 5188 rtwvif_link->link_id = link_id; 5189 5190 set_bit(index, rtwvif->links_inst_map); 5191 rtwvif->links[link_id] = rtwvif_link; 5192 list_add_tail(&rtwvif_link->dlink_schd, &rtwvif->dlink_pool); 5193 return rtwvif_link; 5194 5195 err: 5196 rtw89_err(rtwvif->rtwdev, "vif (link_id %u) failed to set link: %d\n", 5197 link_id, ret); 5198 return NULL; 5199 } 5200 5201 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id) 5202 { 5203 struct rtw89_vif_link **container = &rtwvif->links[link_id]; 5204 struct rtw89_vif_link *link = *container; 5205 u8 index; 5206 5207 if (!link) 5208 return; 5209 5210 index = rtw89_vif_link_inst_get_index(link); 5211 clear_bit(index, rtwvif->links_inst_map); 5212 *container = NULL; 5213 list_del(&link->dlink_schd); 5214 } 5215 5216 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 5217 unsigned int link_id) 5218 { 5219 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 5220 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id]; 5221 struct rtw89_sta_link *rtwsta_link = rtwsta->links[link_id]; 5222 u8 index; 5223 int ret; 5224 5225 if (rtwsta_link) 5226 return rtwsta_link; 5227 5228 if (!rtwvif_link) { 5229 ret = -ENOLINK; 5230 goto err; 5231 } 5232 5233 index = rtw89_vif_link_inst_get_index(rtwvif_link); 5234 if (test_bit(index, rtwsta->links_inst_map)) { 5235 ret = -EBUSY; 5236 goto err; 5237 } 5238 5239 rtwsta_link = &rtwsta->links_inst[index]; 5240 rtwsta_link->link_id = link_id; 5241 5242 set_bit(index, rtwsta->links_inst_map); 5243 rtwsta->links[link_id] = rtwsta_link; 5244 list_add_tail(&rtwsta_link->dlink_schd, &rtwsta->dlink_pool); 5245 return rtwsta_link; 5246 5247 err: 5248 rtw89_err(rtwsta->rtwdev, "sta (link_id %u) failed to set link: %d\n", 5249 link_id, ret); 5250 return NULL; 5251 } 5252 5253 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id) 5254 { 5255 struct rtw89_sta_link **container = &rtwsta->links[link_id]; 5256 struct rtw89_sta_link *link = *container; 5257 u8 index; 5258 5259 if (!link) 5260 return; 5261 5262 index = rtw89_sta_link_inst_get_index(link); 5263 clear_bit(index, rtwsta->links_inst_map); 5264 *container = NULL; 5265 list_del(&link->dlink_schd); 5266 } 5267 5268 int rtw89_core_init(struct rtw89_dev *rtwdev) 5269 { 5270 struct rtw89_btc *btc = &rtwdev->btc; 5271 u8 band; 5272 5273 INIT_LIST_HEAD(&rtwdev->ba_list); 5274 INIT_LIST_HEAD(&rtwdev->forbid_ba_list); 5275 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 5276 INIT_LIST_HEAD(&rtwdev->early_h2c_list); 5277 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 5278 if (!(rtwdev->chip->support_bands & BIT(band))) 5279 continue; 5280 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 5281 } 5282 INIT_LIST_HEAD(&rtwdev->scan_info.chan_list); 5283 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 5284 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 5285 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); 5286 wiphy_delayed_work_init(&rtwdev->track_work, rtw89_track_work); 5287 wiphy_delayed_work_init(&rtwdev->track_ps_work, rtw89_track_ps_work); 5288 wiphy_delayed_work_init(&rtwdev->chanctx_work, rtw89_chanctx_work); 5289 wiphy_delayed_work_init(&rtwdev->coex_act1_work, rtw89_coex_act1_work); 5290 wiphy_delayed_work_init(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); 5291 wiphy_delayed_work_init(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 5292 wiphy_delayed_work_init(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 5293 wiphy_delayed_work_init(&rtwdev->mcc_prepare_done_work, rtw89_mcc_prepare_done_work); 5294 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 5295 wiphy_delayed_work_init(&rtwdev->antdiv_work, rtw89_phy_antdiv_work); 5296 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 5297 if (!rtwdev->txq_wq) 5298 return -ENOMEM; 5299 spin_lock_init(&rtwdev->ba_lock); 5300 spin_lock_init(&rtwdev->rpwm_lock); 5301 mutex_init(&rtwdev->rf_mutex); 5302 rtwdev->total_sta_assoc = 0; 5303 5304 rtw89_init_wait(&rtwdev->mcc.wait); 5305 rtw89_init_wait(&rtwdev->mlo.wait); 5306 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait); 5307 rtw89_init_wait(&rtwdev->wow.wait); 5308 rtw89_init_wait(&rtwdev->mac.ps_wait); 5309 5310 wiphy_work_init(&rtwdev->c2h_work, rtw89_fw_c2h_work); 5311 wiphy_work_init(&rtwdev->ips_work, rtw89_ips_work); 5312 wiphy_work_init(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work); 5313 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work); 5314 5315 skb_queue_head_init(&rtwdev->c2h_queue); 5316 rtw89_core_ppdu_sts_init(rtwdev); 5317 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); 5318 5319 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; 5320 rtwdev->dbcc_en = false; 5321 rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT; 5322 rtwdev->mac.qta_mode = RTW89_QTA_SCC; 5323 5324 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 5325 rtwdev->dbcc_en = true; 5326 rtwdev->mac.qta_mode = RTW89_QTA_DBCC; 5327 rtwdev->mlo_dbcc_mode = MLO_1_PLUS_1_1RF; 5328 } 5329 5330 rtwdev->bbs[RTW89_PHY_0].phy_idx = RTW89_PHY_0; 5331 rtwdev->bbs[RTW89_PHY_1].phy_idx = RTW89_PHY_1; 5332 5333 wiphy_work_init(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); 5334 wiphy_work_init(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); 5335 wiphy_work_init(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); 5336 wiphy_work_init(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); 5337 5338 init_completion(&rtwdev->fw.req.completion); 5339 init_completion(&rtwdev->rfk_wait.completion); 5340 5341 schedule_work(&rtwdev->load_firmware_work); 5342 5343 rtw89_ser_init(rtwdev); 5344 rtw89_entity_init(rtwdev); 5345 rtw89_sar_init(rtwdev); 5346 rtw89_phy_ant_gain_init(rtwdev); 5347 5348 return 0; 5349 } 5350 EXPORT_SYMBOL(rtw89_core_init); 5351 5352 void rtw89_core_deinit(struct rtw89_dev *rtwdev) 5353 { 5354 rtw89_ser_deinit(rtwdev); 5355 rtw89_unload_firmware(rtwdev); 5356 __rtw89_fw_free_all_early_h2c(rtwdev); 5357 5358 destroy_workqueue(rtwdev->txq_wq); 5359 mutex_destroy(&rtwdev->rf_mutex); 5360 } 5361 EXPORT_SYMBOL(rtw89_core_deinit); 5362 5363 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 5364 const u8 *mac_addr, bool hw_scan) 5365 { 5366 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 5367 rtwvif_link->chanctx_idx); 5368 struct rtw89_bb_ctx *bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx); 5369 5370 rtwdev->scanning = true; 5371 5372 ether_addr_copy(rtwvif_link->mac_addr, mac_addr); 5373 rtw89_btc_ntfy_scan_start(rtwdev, rtwvif_link->phy_idx, chan->band_type); 5374 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, true); 5375 rtw89_hci_recalc_int_mit(rtwdev); 5376 rtw89_phy_config_edcca(rtwdev, bb, true); 5377 rtw89_tas_scan(rtwdev, true); 5378 5379 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, mac_addr); 5380 } 5381 5382 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 5383 struct rtw89_vif_link *rtwvif_link, bool hw_scan) 5384 { 5385 struct ieee80211_bss_conf *bss_conf; 5386 struct rtw89_bb_ctx *bb; 5387 int ret; 5388 5389 if (!rtwvif_link) 5390 return; 5391 5392 rcu_read_lock(); 5393 5394 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 5395 ether_addr_copy(rtwvif_link->mac_addr, bss_conf->addr); 5396 5397 rcu_read_unlock(); 5398 5399 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL); 5400 5401 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, false); 5402 rtw89_btc_ntfy_scan_finish(rtwdev, rtwvif_link->phy_idx); 5403 bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx); 5404 rtw89_phy_config_edcca(rtwdev, bb, false); 5405 rtw89_tas_scan(rtwdev, false); 5406 5407 if (hw_scan) { 5408 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, false, false, 5409 RTW89_SCAN_NULL_TIMEOUT); 5410 if (ret) 5411 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 5412 "scan send null-0 failed: %d\n", ret); 5413 } 5414 5415 rtwdev->scanning = false; 5416 rtw89_for_each_active_bb(rtwdev, bb) 5417 bb->dig.bypass_dig = true; 5418 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 5419 wiphy_work_queue(rtwdev->hw->wiphy, &rtwdev->ips_work); 5420 } 5421 5422 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) 5423 { 5424 const struct rtw89_chip_info *chip = rtwdev->chip; 5425 int ret; 5426 u8 val; 5427 u8 cv; 5428 5429 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); 5430 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) { 5431 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) 5432 cv = CHIP_CAV; 5433 else 5434 cv = CHIP_CBV; 5435 } 5436 5437 rtwdev->hal.cv = cv; 5438 5439 if (rtw89_is_rtl885xb(rtwdev)) { 5440 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val); 5441 if (ret) 5442 return; 5443 5444 rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK); 5445 } 5446 } 5447 5448 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev) 5449 { 5450 const struct rtw89_chip_info *chip = rtwdev->chip; 5451 5452 rtwdev->hal.support_cckpd = 5453 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) && 5454 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV); 5455 rtwdev->hal.support_igi = 5456 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV; 5457 5458 if (test_bit(RTW89_QUIRK_THERMAL_PROT_120C, rtwdev->quirks)) 5459 rtwdev->hal.thermal_prot_th = chip->thermal_th[1]; 5460 else if (test_bit(RTW89_QUIRK_THERMAL_PROT_110C, rtwdev->quirks)) 5461 rtwdev->hal.thermal_prot_th = chip->thermal_th[0]; 5462 else 5463 rtwdev->hal.thermal_prot_th = 0; 5464 } 5465 5466 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev) 5467 { 5468 const struct rtw89_chip_info *chip = rtwdev->chip; 5469 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf; 5470 struct rtw89_efuse *efuse = &rtwdev->efuse; 5471 const struct rtw89_rfe_parms *sel; 5472 u8 rfe_type = efuse->rfe_type; 5473 5474 if (!conf) { 5475 sel = chip->dflt_parms; 5476 goto out; 5477 } 5478 5479 while (conf->rfe_parms) { 5480 if (rfe_type == conf->rfe_type) { 5481 sel = conf->rfe_parms; 5482 goto out; 5483 } 5484 conf++; 5485 } 5486 5487 sel = chip->dflt_parms; 5488 5489 out: 5490 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel); 5491 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl); 5492 } 5493 5494 int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5495 unsigned int link_id) 5496 { 5497 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 5498 u16 usable_links = ieee80211_vif_usable_links(vif); 5499 u16 active_links = vif->active_links; 5500 struct rtw89_vif_link *target, *cur; 5501 int ret; 5502 5503 lockdep_assert_wiphy(rtwdev->hw->wiphy); 5504 5505 if (unlikely(!ieee80211_vif_is_mld(vif))) 5506 return -EOPNOTSUPP; 5507 5508 if (unlikely(link_id >= IEEE80211_MLD_MAX_NUM_LINKS || 5509 !(usable_links & BIT(link_id)))) { 5510 rtw89_warn(rtwdev, "%s: link id %u is not usable\n", __func__, 5511 link_id); 5512 return -ENOLINK; 5513 } 5514 5515 if (active_links == BIT(link_id)) 5516 return 0; 5517 5518 rtw89_debug(rtwdev, RTW89_DBG_STATE, "%s: switch to link id %u MLSR\n", 5519 __func__, link_id); 5520 5521 rtw89_leave_lps(rtwdev); 5522 5523 ieee80211_stop_queues(rtwdev->hw); 5524 flush_work(&rtwdev->txq_work); 5525 5526 cur = rtw89_get_designated_link(rtwvif); 5527 5528 ret = ieee80211_set_active_links(vif, active_links | BIT(link_id)); 5529 if (ret) { 5530 rtw89_err(rtwdev, "%s: failed to activate link id %u\n", 5531 __func__, link_id); 5532 goto wake_queue; 5533 } 5534 5535 target = rtwvif->links[link_id]; 5536 if (unlikely(!target)) { 5537 rtw89_err(rtwdev, "%s: failed to confirm link id %u\n", 5538 __func__, link_id); 5539 5540 ieee80211_set_active_links(vif, active_links); 5541 ret = -EFAULT; 5542 goto wake_queue; 5543 } 5544 5545 if (likely(cur)) 5546 rtw89_fw_h2c_mlo_link_cfg(rtwdev, cur, false); 5547 5548 rtw89_fw_h2c_mlo_link_cfg(rtwdev, target, true); 5549 5550 ret = ieee80211_set_active_links(vif, BIT(link_id)); 5551 if (ret) 5552 rtw89_err(rtwdev, "%s: failed to inactivate links 0x%x\n", 5553 __func__, active_links); 5554 5555 rtw89_chip_rfk_channel(rtwdev, target); 5556 5557 rtwvif->mlo_mode = RTW89_MLO_MODE_MLSR; 5558 5559 wake_queue: 5560 ieee80211_wake_queues(rtwdev->hw); 5561 5562 return ret; 5563 } 5564 5565 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) 5566 { 5567 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5568 int ret; 5569 5570 ret = rtw89_mac_partial_init(rtwdev, false); 5571 if (ret) 5572 return ret; 5573 5574 ret = mac->parse_efuse_map(rtwdev); 5575 if (ret) 5576 return ret; 5577 5578 ret = mac->parse_phycap_map(rtwdev); 5579 if (ret) 5580 return ret; 5581 5582 ret = rtw89_mac_setup_phycap(rtwdev); 5583 if (ret) 5584 return ret; 5585 5586 rtw89_core_setup_phycap(rtwdev); 5587 5588 rtw89_hci_mac_pre_deinit(rtwdev); 5589 5590 return 0; 5591 } 5592 5593 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) 5594 { 5595 rtw89_chip_fem_setup(rtwdev); 5596 5597 return 0; 5598 } 5599 5600 static bool rtw89_chip_has_rfkill(struct rtw89_dev *rtwdev) 5601 { 5602 return !!rtwdev->chip->rfkill_init; 5603 } 5604 5605 static void rtw89_core_rfkill_init(struct rtw89_dev *rtwdev) 5606 { 5607 const struct rtw89_rfkill_regs *regs = rtwdev->chip->rfkill_init; 5608 5609 rtw89_write16_mask(rtwdev, regs->pinmux.addr, 5610 regs->pinmux.mask, regs->pinmux.data); 5611 rtw89_write16_mask(rtwdev, regs->mode.addr, 5612 regs->mode.mask, regs->mode.data); 5613 } 5614 5615 static bool rtw89_core_rfkill_get(struct rtw89_dev *rtwdev) 5616 { 5617 const struct rtw89_reg_def *reg = &rtwdev->chip->rfkill_get; 5618 5619 return !rtw89_read8_mask(rtwdev, reg->addr, reg->mask); 5620 } 5621 5622 static void rtw89_rfkill_polling_init(struct rtw89_dev *rtwdev) 5623 { 5624 if (!rtw89_chip_has_rfkill(rtwdev)) 5625 return; 5626 5627 rtw89_core_rfkill_init(rtwdev); 5628 rtw89_core_rfkill_poll(rtwdev, true); 5629 wiphy_rfkill_start_polling(rtwdev->hw->wiphy); 5630 } 5631 5632 static void rtw89_rfkill_polling_deinit(struct rtw89_dev *rtwdev) 5633 { 5634 if (!rtw89_chip_has_rfkill(rtwdev)) 5635 return; 5636 5637 wiphy_rfkill_stop_polling(rtwdev->hw->wiphy); 5638 } 5639 5640 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force) 5641 { 5642 bool prev, blocked; 5643 5644 if (!rtw89_chip_has_rfkill(rtwdev)) 5645 return; 5646 5647 prev = test_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 5648 blocked = rtw89_core_rfkill_get(rtwdev); 5649 5650 if (!force && prev == blocked) 5651 return; 5652 5653 rtw89_info(rtwdev, "rfkill hardware state changed to %s\n", 5654 blocked ? "disable" : "enable"); 5655 5656 if (blocked) 5657 set_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 5658 else 5659 clear_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 5660 5661 wiphy_rfkill_set_hw_state(rtwdev->hw->wiphy, blocked); 5662 } 5663 5664 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) 5665 { 5666 int ret; 5667 5668 rtw89_read_chip_ver(rtwdev); 5669 5670 ret = rtw89_mac_pwr_on(rtwdev); 5671 if (ret) { 5672 rtw89_err(rtwdev, "failed to power on\n"); 5673 return ret; 5674 } 5675 5676 ret = rtw89_wait_firmware_completion(rtwdev); 5677 if (ret) { 5678 rtw89_err(rtwdev, "failed to wait firmware completion\n"); 5679 goto out; 5680 } 5681 5682 ret = rtw89_fw_recognize(rtwdev); 5683 if (ret) { 5684 rtw89_err(rtwdev, "failed to recognize firmware\n"); 5685 goto out; 5686 } 5687 5688 ret = rtw89_chip_efuse_info_setup(rtwdev); 5689 if (ret) 5690 goto out; 5691 5692 ret = rtw89_fw_recognize_elements(rtwdev); 5693 if (ret) { 5694 rtw89_err(rtwdev, "failed to recognize firmware elements\n"); 5695 goto out; 5696 } 5697 5698 ret = rtw89_chip_board_info_setup(rtwdev); 5699 if (ret) 5700 goto out; 5701 5702 rtw89_core_setup_rfe_parms(rtwdev); 5703 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); 5704 5705 out: 5706 rtw89_mac_pwr_off(rtwdev); 5707 5708 return ret; 5709 } 5710 EXPORT_SYMBOL(rtw89_chip_info_setup); 5711 5712 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 5713 struct rtw89_vif_link *rtwvif_link) 5714 { 5715 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5716 const struct rtw89_chip_info *chip = rtwdev->chip; 5717 struct ieee80211_bss_conf *bss_conf; 5718 5719 rcu_read_lock(); 5720 5721 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 5722 if (!bss_conf->he_support || !vif->cfg.assoc) { 5723 rcu_read_unlock(); 5724 return; 5725 } 5726 5727 rcu_read_unlock(); 5728 5729 if (chip->ops->set_txpwr_ul_tb_offset) 5730 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif_link->mac_idx); 5731 } 5732 5733 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) 5734 { 5735 const struct rtw89_chip_info *chip = rtwdev->chip; 5736 u8 n = rtwdev->support_mlo ? chip->support_link_num : 1; 5737 struct ieee80211_hw *hw = rtwdev->hw; 5738 struct rtw89_efuse *efuse = &rtwdev->efuse; 5739 struct rtw89_hal *hal = &rtwdev->hal; 5740 int ret; 5741 int tx_headroom = IEEE80211_HT_CTL_LEN; 5742 5743 if (rtwdev->hci.type == RTW89_HCI_TYPE_USB) 5744 tx_headroom += chip->txwd_body_size + chip->txwd_info_size; 5745 5746 hw->vif_data_size = struct_size_t(struct rtw89_vif, links_inst, n); 5747 hw->sta_data_size = struct_size_t(struct rtw89_sta, links_inst, n); 5748 hw->txq_data_size = sizeof(struct rtw89_txq); 5749 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg); 5750 5751 SET_IEEE80211_PERM_ADDR(hw, efuse->addr); 5752 5753 hw->extra_tx_headroom = tx_headroom; 5754 hw->queues = IEEE80211_NUM_ACS; 5755 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM; 5756 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM; 5757 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL; 5758 5759 hw->radiotap_mcs_details |= IEEE80211_RADIOTAP_MCS_HAVE_FEC | 5760 IEEE80211_RADIOTAP_MCS_HAVE_STBC; 5761 hw->radiotap_vht_details |= IEEE80211_RADIOTAP_VHT_KNOWN_STBC; 5762 5763 ieee80211_hw_set(hw, SIGNAL_DBM); 5764 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 5765 ieee80211_hw_set(hw, MFP_CAPABLE); 5766 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 5767 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 5768 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 5769 ieee80211_hw_set(hw, TX_AMSDU); 5770 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 5771 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 5772 ieee80211_hw_set(hw, SUPPORTS_PS); 5773 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 5774 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 5775 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 5776 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 5777 ieee80211_hw_set(hw, CHANCTX_STA_CSA); 5778 5779 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 5780 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 5781 5782 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw)) 5783 ieee80211_hw_set(hw, CONNECTION_MONITOR); 5784 5785 if (RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &rtwdev->fw)) 5786 ieee80211_hw_set(hw, AP_LINK_PS); 5787 5788 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 5789 BIT(NL80211_IFTYPE_AP) | 5790 BIT(NL80211_IFTYPE_P2P_CLIENT) | 5791 BIT(NL80211_IFTYPE_P2P_GO); 5792 5793 if (hal->ant_diversity) { 5794 hw->wiphy->available_antennas_tx = 0x3; 5795 hw->wiphy->available_antennas_rx = 0x3; 5796 } else { 5797 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; 5798 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; 5799 } 5800 5801 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 5802 WIPHY_FLAG_TDLS_EXTERNAL_SETUP | 5803 WIPHY_FLAG_AP_UAPSD | 5804 WIPHY_FLAG_HAS_CHANNEL_SWITCH | 5805 WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK; 5806 5807 if (!chip->support_rnr) 5808 hw->wiphy->flags |= WIPHY_FLAG_SPLIT_SCAN_6GHZ; 5809 5810 if (chip->chip_gen == RTW89_CHIP_BE) 5811 hw->wiphy->flags |= WIPHY_FLAG_DISABLE_WEXT; 5812 5813 if (rtwdev->support_mlo) { 5814 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_MLO; 5815 hw->wiphy->iftype_ext_capab = rtw89_iftypes_ext_capa; 5816 hw->wiphy->num_iftype_ext_capab = ARRAY_SIZE(rtw89_iftypes_ext_capa); 5817 } 5818 5819 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 5820 5821 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 5822 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN; 5823 5824 #ifdef CONFIG_PM 5825 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 5826 hw->wiphy->max_sched_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 5827 #endif 5828 5829 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 5830 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 5831 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 5832 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 5833 hw->wiphy->max_remain_on_channel_duration = 1000; 5834 5835 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 5836 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 5837 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 5838 5839 ret = rtw89_core_set_supported_band(rtwdev); 5840 if (ret) { 5841 rtw89_err(rtwdev, "failed to set supported band\n"); 5842 return ret; 5843 } 5844 5845 ret = rtw89_regd_setup(rtwdev); 5846 if (ret) { 5847 rtw89_err(rtwdev, "failed to set up regd\n"); 5848 return ret; 5849 } 5850 5851 hw->wiphy->sar_capa = &rtw89_sar_capa; 5852 5853 ret = ieee80211_register_hw(hw); 5854 if (ret) { 5855 rtw89_err(rtwdev, "failed to register hw\n"); 5856 return ret; 5857 } 5858 5859 ret = rtw89_regd_init_hint(rtwdev); 5860 if (ret) { 5861 rtw89_err(rtwdev, "failed to init regd\n"); 5862 goto err_unregister_hw; 5863 } 5864 5865 rtw89_rfkill_polling_init(rtwdev); 5866 5867 return 0; 5868 5869 err_unregister_hw: 5870 ieee80211_unregister_hw(hw); 5871 5872 return ret; 5873 } 5874 5875 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) 5876 { 5877 struct ieee80211_hw *hw = rtwdev->hw; 5878 5879 rtw89_rfkill_polling_deinit(rtwdev); 5880 ieee80211_unregister_hw(hw); 5881 } 5882 5883 int rtw89_core_register(struct rtw89_dev *rtwdev) 5884 { 5885 int ret; 5886 5887 ret = rtw89_core_register_hw(rtwdev); 5888 if (ret) { 5889 rtw89_err(rtwdev, "failed to register core hw\n"); 5890 return ret; 5891 } 5892 5893 rtw89_debugfs_init(rtwdev); 5894 5895 return 0; 5896 } 5897 EXPORT_SYMBOL(rtw89_core_register); 5898 5899 void rtw89_core_unregister(struct rtw89_dev *rtwdev) 5900 { 5901 rtw89_core_unregister_hw(rtwdev); 5902 5903 rtw89_debugfs_deinit(rtwdev); 5904 } 5905 EXPORT_SYMBOL(rtw89_core_unregister); 5906 5907 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 5908 u32 bus_data_size, 5909 const struct rtw89_chip_info *chip, 5910 const struct rtw89_chip_variant *variant) 5911 { 5912 struct rtw89_fw_info early_fw = {}; 5913 const struct firmware *firmware; 5914 struct ieee80211_hw *hw; 5915 struct rtw89_dev *rtwdev; 5916 struct ieee80211_ops *ops; 5917 u32 driver_data_size; 5918 int fw_format = -1; 5919 bool support_mlo; 5920 bool no_chanctx; 5921 5922 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format); 5923 5924 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL); 5925 if (!ops) 5926 goto err; 5927 5928 no_chanctx = chip->support_chanctx_num == 0 || 5929 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) || 5930 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw); 5931 5932 if (no_chanctx) { 5933 ops->add_chanctx = ieee80211_emulate_add_chanctx; 5934 ops->remove_chanctx = ieee80211_emulate_remove_chanctx; 5935 ops->change_chanctx = ieee80211_emulate_change_chanctx; 5936 ops->switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx; 5937 ops->assign_vif_chanctx = NULL; 5938 ops->unassign_vif_chanctx = NULL; 5939 ops->remain_on_channel = NULL; 5940 ops->cancel_remain_on_channel = NULL; 5941 } 5942 5943 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size; 5944 hw = ieee80211_alloc_hw(driver_data_size, ops); 5945 if (!hw) 5946 goto err; 5947 5948 /* Currently, our AP_LINK_PS handling only works for non-MLD softap 5949 * or MLD-single-link softap. If RTW89_MLD_NON_STA_LINK_NUM enlarges, 5950 * please tweak entire AP_LINKS_PS handling before supporting MLO. 5951 */ 5952 support_mlo = !no_chanctx && chip->support_link_num && 5953 RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &early_fw) && 5954 RTW89_MLD_NON_STA_LINK_NUM == 1; 5955 5956 hw->wiphy->iface_combinations = rtw89_iface_combs; 5957 5958 if (no_chanctx || chip->support_chanctx_num == 1) 5959 hw->wiphy->n_iface_combinations = 1; 5960 else 5961 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs); 5962 5963 rtwdev = hw->priv; 5964 rtwdev->hw = hw; 5965 rtwdev->dev = device; 5966 rtwdev->ops = ops; 5967 rtwdev->chip = chip; 5968 rtwdev->variant = variant; 5969 rtwdev->fw.req.firmware = firmware; 5970 rtwdev->fw.fw_format = fw_format; 5971 rtwdev->support_mlo = support_mlo; 5972 5973 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s chanctx\n", 5974 no_chanctx ? "without" : "with"); 5975 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s MLO cap\n", 5976 support_mlo ? "with" : "without"); 5977 5978 return rtwdev; 5979 5980 err: 5981 kfree(ops); 5982 release_firmware(firmware); 5983 return NULL; 5984 } 5985 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw); 5986 5987 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev) 5988 { 5989 kfree(rtwdev->ops); 5990 kfree(rtwdev->rfe_data); 5991 release_firmware(rtwdev->fw.req.firmware); 5992 ieee80211_free_hw(rtwdev->hw); 5993 } 5994 EXPORT_SYMBOL(rtw89_free_ieee80211_hw); 5995 5996 MODULE_AUTHOR("Realtek Corporation"); 5997 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); 5998 MODULE_LICENSE("Dual BSD/GPL"); 5999