1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTW_RX_H_ 6 #define __RTW_RX_H_ 7 8 enum rtw_rx_desc_enc { 9 RX_DESC_ENC_NONE = 0, 10 RX_DESC_ENC_WEP40 = 1, 11 RX_DESC_ENC_TKIP_WO_MIC = 2, 12 RX_DESC_ENC_TKIP_MIC = 3, 13 RX_DESC_ENC_AES = 4, 14 RX_DESC_ENC_WEP104 = 5, 15 }; 16 17 #define GET_RX_DESC_PHYST(rxdesc) \ 18 le32_get_bits(*((__le32 *)(rxdesc) + 0x00), BIT(26)) 19 #define GET_RX_DESC_ICV_ERR(rxdesc) \ 20 le32_get_bits(*((__le32 *)(rxdesc) + 0x00), BIT(15)) 21 #define GET_RX_DESC_CRC32(rxdesc) \ 22 le32_get_bits(*((__le32 *)(rxdesc) + 0x00), BIT(14)) 23 #define GET_RX_DESC_SWDEC(rxdesc) \ 24 le32_get_bits(*((__le32 *)(rxdesc) + 0x00), BIT(27)) 25 #define GET_RX_DESC_C2H(rxdesc) \ 26 le32_get_bits(*((__le32 *)(rxdesc) + 0x02), BIT(28)) 27 #define GET_RX_DESC_PKT_LEN(rxdesc) \ 28 le32_get_bits(*((__le32 *)(rxdesc) + 0x00), GENMASK(13, 0)) 29 #define GET_RX_DESC_DRV_INFO_SIZE(rxdesc) \ 30 le32_get_bits(*((__le32 *)(rxdesc) + 0x00), GENMASK(19, 16)) 31 #define GET_RX_DESC_SHIFT(rxdesc) \ 32 le32_get_bits(*((__le32 *)(rxdesc) + 0x00), GENMASK(25, 24)) 33 #define GET_RX_DESC_ENC_TYPE(rxdesc) \ 34 le32_get_bits(*((__le32 *)(rxdesc) + 0x00), GENMASK(22, 20)) 35 #define GET_RX_DESC_RX_RATE(rxdesc) \ 36 le32_get_bits(*((__le32 *)(rxdesc) + 0x03), GENMASK(6, 0)) 37 #define GET_RX_DESC_MACID(rxdesc) \ 38 le32_get_bits(*((__le32 *)(rxdesc) + 0x01), GENMASK(6, 0)) 39 #define GET_RX_DESC_PPDU_CNT(rxdesc) \ 40 le32_get_bits(*((__le32 *)(rxdesc) + 0x02), GENMASK(30, 29)) 41 #define GET_RX_DESC_TSFL(rxdesc) \ 42 le32_get_bits(*((__le32 *)(rxdesc) + 0x05), GENMASK(31, 0)) 43 44 void rtw_rx_stats(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 45 struct sk_buff *skb); 46 void rtw_rx_fill_rx_status(struct rtw_dev *rtwdev, 47 struct rtw_rx_pkt_stat *pkt_stat, 48 struct ieee80211_hdr *hdr, 49 struct ieee80211_rx_status *rx_status, 50 u8 *phy_status); 51 52 #endif 53