1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/module.h> 6 #include "main.h" 7 #include "coex.h" 8 #include "fw.h" 9 #include "tx.h" 10 #include "rx.h" 11 #include "phy.h" 12 #include "rtw8822c.h" 13 #include "rtw8822c_table.h" 14 #include "mac.h" 15 #include "reg.h" 16 #include "debug.h" 17 #include "util.h" 18 #include "bf.h" 19 #include "efuse.h" 20 21 #define IQK_DONE_8822C 0xaa 22 23 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 24 u8 rx_path, bool is_tx2_path); 25 26 static void rtw8822ce_efuse_parsing(struct rtw_efuse *efuse, 27 struct rtw8822c_efuse *map) 28 { 29 ether_addr_copy(efuse->addr, map->e.mac_addr); 30 } 31 32 static void rtw8822cu_efuse_parsing(struct rtw_efuse *efuse, 33 struct rtw8822c_efuse *map) 34 { 35 ether_addr_copy(efuse->addr, map->u.mac_addr); 36 } 37 38 static void rtw8822cs_efuse_parsing(struct rtw_efuse *efuse, 39 struct rtw8822c_efuse *map) 40 { 41 ether_addr_copy(efuse->addr, map->s.mac_addr); 42 } 43 44 static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 45 { 46 struct rtw_efuse *efuse = &rtwdev->efuse; 47 struct rtw8822c_efuse *map; 48 int i; 49 50 map = (struct rtw8822c_efuse *)log_map; 51 52 efuse->rfe_option = map->rfe_option; 53 efuse->rf_board_option = map->rf_board_option; 54 efuse->crystal_cap = map->xtal_k & XCAP_MASK; 55 efuse->channel_plan = map->channel_plan; 56 efuse->country_code[0] = map->country_code[0]; 57 efuse->country_code[1] = map->country_code[1]; 58 efuse->bt_setting = map->rf_bt_setting; 59 efuse->regd = map->rf_board_option & 0x7; 60 efuse->thermal_meter[RF_PATH_A] = map->path_a_thermal; 61 efuse->thermal_meter[RF_PATH_B] = map->path_b_thermal; 62 efuse->thermal_meter_k = 63 (map->path_a_thermal + map->path_b_thermal) >> 1; 64 efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf; 65 66 for (i = 0; i < 4; i++) 67 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 68 69 switch (rtw_hci_type(rtwdev)) { 70 case RTW_HCI_TYPE_PCIE: 71 rtw8822ce_efuse_parsing(efuse, map); 72 break; 73 case RTW_HCI_TYPE_USB: 74 rtw8822cu_efuse_parsing(efuse, map); 75 break; 76 case RTW_HCI_TYPE_SDIO: 77 rtw8822cs_efuse_parsing(efuse, map); 78 break; 79 default: 80 /* unsupported now */ 81 return -ENOTSUPP; 82 } 83 84 return 0; 85 } 86 87 static void rtw8822c_header_file_init(struct rtw_dev *rtwdev, bool pre) 88 { 89 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN); 90 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_PI_ON); 91 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN); 92 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_PI_ON); 93 94 if (pre) 95 rtw_write32_clr(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN); 96 else 97 rtw_write32_set(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN); 98 } 99 100 static void rtw8822c_bb_reset(struct rtw_dev *rtwdev) 101 { 102 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_BB_RSTB); 103 rtw_write16_clr(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_BB_RSTB); 104 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_BB_RSTB); 105 } 106 107 static void rtw8822c_dac_backup_reg(struct rtw_dev *rtwdev, 108 struct rtw_backup_info *backup, 109 struct rtw_backup_info *backup_rf) 110 { 111 u32 path, i; 112 u32 val; 113 u32 reg; 114 u32 rf_addr[DACK_RF_8822C] = {0x8f}; 115 u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110, 116 0x1c3c, 0x1c24, 0x1d70, 0x9b4, 117 0x1a00, 0x1a14, 0x1d58, 0x1c38, 118 0x1e24, 0x1e28, 0x1860, 0x4160}; 119 120 for (i = 0; i < DACK_REG_8822C; i++) { 121 backup[i].len = 4; 122 backup[i].reg = addrs[i]; 123 backup[i].val = rtw_read32(rtwdev, addrs[i]); 124 } 125 126 for (path = 0; path < DACK_PATH_8822C; path++) { 127 for (i = 0; i < DACK_RF_8822C; i++) { 128 reg = rf_addr[i]; 129 val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK); 130 backup_rf[path * i + i].reg = reg; 131 backup_rf[path * i + i].val = val; 132 } 133 } 134 } 135 136 static void rtw8822c_dac_restore_reg(struct rtw_dev *rtwdev, 137 struct rtw_backup_info *backup, 138 struct rtw_backup_info *backup_rf) 139 { 140 u32 path, i; 141 u32 val; 142 u32 reg; 143 144 rtw_restore_reg(rtwdev, backup, DACK_REG_8822C); 145 146 for (path = 0; path < DACK_PATH_8822C; path++) { 147 for (i = 0; i < DACK_RF_8822C; i++) { 148 val = backup_rf[path * i + i].val; 149 reg = backup_rf[path * i + i].reg; 150 rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val); 151 } 152 } 153 } 154 155 static void rtw8822c_rf_minmax_cmp(struct rtw_dev *rtwdev, u32 value, 156 u32 *min, u32 *max) 157 { 158 if (value >= 0x200) { 159 if (*min >= 0x200) { 160 if (*min > value) 161 *min = value; 162 } else { 163 *min = value; 164 } 165 if (*max >= 0x200) { 166 if (*max < value) 167 *max = value; 168 } 169 } else { 170 if (*min < 0x200) { 171 if (*min > value) 172 *min = value; 173 } 174 175 if (*max >= 0x200) { 176 *max = value; 177 } else { 178 if (*max < value) 179 *max = value; 180 } 181 } 182 } 183 184 static void __rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *v1, u32 *v2) 185 { 186 if (*v1 >= 0x200 && *v2 >= 0x200) { 187 if (*v1 > *v2) 188 swap(*v1, *v2); 189 } else if (*v1 < 0x200 && *v2 < 0x200) { 190 if (*v1 > *v2) 191 swap(*v1, *v2); 192 } else if (*v1 < 0x200 && *v2 >= 0x200) { 193 swap(*v1, *v2); 194 } 195 } 196 197 static void rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *iv, u32 *qv) 198 { 199 u32 i, j; 200 201 for (i = 0; i < DACK_SN_8822C - 1; i++) { 202 for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) { 203 __rtw8822c_dac_iq_sort(rtwdev, &iv[j], &iv[j + 1]); 204 __rtw8822c_dac_iq_sort(rtwdev, &qv[j], &qv[j + 1]); 205 } 206 } 207 } 208 209 static void rtw8822c_dac_iq_offset(struct rtw_dev *rtwdev, u32 *vec, u32 *val) 210 { 211 u32 p, m, t, i; 212 213 m = 0; 214 p = 0; 215 for (i = 10; i < DACK_SN_8822C - 10; i++) { 216 if (vec[i] > 0x200) 217 m = (0x400 - vec[i]) + m; 218 else 219 p = vec[i] + p; 220 } 221 222 if (p > m) { 223 t = p - m; 224 t = t / (DACK_SN_8822C - 20); 225 } else { 226 t = m - p; 227 t = t / (DACK_SN_8822C - 20); 228 if (t != 0x0) 229 t = 0x400 - t; 230 } 231 232 *val = t; 233 } 234 235 static u32 rtw8822c_get_path_write_addr(u8 path) 236 { 237 u32 base_addr; 238 239 switch (path) { 240 case RF_PATH_A: 241 base_addr = 0x1800; 242 break; 243 case RF_PATH_B: 244 base_addr = 0x4100; 245 break; 246 default: 247 WARN_ON(1); 248 return -1; 249 } 250 251 return base_addr; 252 } 253 254 static u32 rtw8822c_get_path_read_addr(u8 path) 255 { 256 u32 base_addr; 257 258 switch (path) { 259 case RF_PATH_A: 260 base_addr = 0x2800; 261 break; 262 case RF_PATH_B: 263 base_addr = 0x4500; 264 break; 265 default: 266 WARN_ON(1); 267 return -1; 268 } 269 270 return base_addr; 271 } 272 273 static bool rtw8822c_dac_iq_check(struct rtw_dev *rtwdev, u32 value) 274 { 275 bool ret = true; 276 277 if ((value >= 0x200 && (0x400 - value) > 0x64) || 278 (value < 0x200 && value > 0x64)) { 279 ret = false; 280 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] Error overflow\n"); 281 } 282 283 return ret; 284 } 285 286 static void rtw8822c_dac_cal_iq_sample(struct rtw_dev *rtwdev, u32 *iv, u32 *qv) 287 { 288 u32 temp; 289 int i = 0, cnt = 0; 290 291 while (i < DACK_SN_8822C && cnt < 10000) { 292 cnt++; 293 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 294 iv[i] = (temp & 0x3ff000) >> 12; 295 qv[i] = temp & 0x3ff; 296 297 if (rtw8822c_dac_iq_check(rtwdev, iv[i]) && 298 rtw8822c_dac_iq_check(rtwdev, qv[i])) 299 i++; 300 } 301 } 302 303 static void rtw8822c_dac_cal_iq_search(struct rtw_dev *rtwdev, 304 u32 *iv, u32 *qv, 305 u32 *i_value, u32 *q_value) 306 { 307 u32 i_max = 0, q_max = 0, i_min = 0, q_min = 0; 308 u32 i_delta, q_delta; 309 u32 temp; 310 int i, cnt = 0; 311 312 do { 313 i_min = iv[0]; 314 i_max = iv[0]; 315 q_min = qv[0]; 316 q_max = qv[0]; 317 for (i = 0; i < DACK_SN_8822C; i++) { 318 rtw8822c_rf_minmax_cmp(rtwdev, iv[i], &i_min, &i_max); 319 rtw8822c_rf_minmax_cmp(rtwdev, qv[i], &q_min, &q_max); 320 } 321 322 if (i_max < 0x200 && i_min < 0x200) 323 i_delta = i_max - i_min; 324 else if (i_max >= 0x200 && i_min >= 0x200) 325 i_delta = i_max - i_min; 326 else 327 i_delta = i_max + (0x400 - i_min); 328 329 if (q_max < 0x200 && q_min < 0x200) 330 q_delta = q_max - q_min; 331 else if (q_max >= 0x200 && q_min >= 0x200) 332 q_delta = q_max - q_min; 333 else 334 q_delta = q_max + (0x400 - q_min); 335 336 rtw_dbg(rtwdev, RTW_DBG_RFK, 337 "[DACK] i: min=0x%08x, max=0x%08x, delta=0x%08x\n", 338 i_min, i_max, i_delta); 339 rtw_dbg(rtwdev, RTW_DBG_RFK, 340 "[DACK] q: min=0x%08x, max=0x%08x, delta=0x%08x\n", 341 q_min, q_max, q_delta); 342 343 rtw8822c_dac_iq_sort(rtwdev, iv, qv); 344 345 if (i_delta > 5 || q_delta > 5) { 346 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 347 iv[0] = (temp & 0x3ff000) >> 12; 348 qv[0] = temp & 0x3ff; 349 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 350 iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12; 351 qv[DACK_SN_8822C - 1] = temp & 0x3ff; 352 } else { 353 break; 354 } 355 } while (cnt++ < 100); 356 357 rtw8822c_dac_iq_offset(rtwdev, iv, i_value); 358 rtw8822c_dac_iq_offset(rtwdev, qv, q_value); 359 } 360 361 static void rtw8822c_dac_cal_rf_mode(struct rtw_dev *rtwdev, 362 u32 *i_value, u32 *q_value) 363 { 364 u32 iv[DACK_SN_8822C], qv[DACK_SN_8822C]; 365 u32 rf_a, rf_b; 366 367 rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK); 368 rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK); 369 370 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a); 371 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b); 372 373 rtw8822c_dac_cal_iq_sample(rtwdev, iv, qv); 374 rtw8822c_dac_cal_iq_search(rtwdev, iv, qv, i_value, q_value); 375 } 376 377 static void rtw8822c_dac_bb_setting(struct rtw_dev *rtwdev) 378 { 379 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff); 380 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2); 381 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3); 382 rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e); 383 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0); 384 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0); 385 rtw_write32(rtwdev, 0x1b00, 0x00000008); 386 rtw_write8(rtwdev, 0x1bcc, 0x3f); 387 rtw_write32(rtwdev, 0x1b00, 0x0000000a); 388 rtw_write8(rtwdev, 0x1bcc, 0x3f); 389 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0); 390 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3); 391 } 392 393 static void rtw8822c_dac_cal_adc(struct rtw_dev *rtwdev, 394 u8 path, u32 *adc_ic, u32 *adc_qc) 395 { 396 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 397 u32 ic = 0, qc = 0, temp = 0; 398 u32 base_addr; 399 u32 path_sel; 400 int i; 401 402 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK path(%d)\n", path); 403 404 base_addr = rtw8822c_get_path_write_addr(path); 405 switch (path) { 406 case RF_PATH_A: 407 path_sel = 0xa0000; 408 break; 409 case RF_PATH_B: 410 path_sel = 0x80000; 411 break; 412 default: 413 WARN_ON(1); 414 return; 415 } 416 417 /* ADCK step1 */ 418 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0); 419 if (path == RF_PATH_B) 420 rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041); 421 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); 422 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 423 rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4); 424 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); 425 rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000); 426 rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000); 427 for (i = 0; i < 10; i++) { 428 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK count=%d\n", i); 429 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003); 430 rtw_write32(rtwdev, 0x1c24, 0x00010002); 431 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 432 rtw_dbg(rtwdev, RTW_DBG_RFK, 433 "[DACK] before: i=0x%x, q=0x%x\n", ic, qc); 434 435 /* compensation value */ 436 if (ic != 0x0) { 437 ic = 0x400 - ic; 438 *adc_ic = ic; 439 } 440 if (qc != 0x0) { 441 qc = 0x400 - qc; 442 *adc_qc = qc; 443 } 444 temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10); 445 rtw_write32(rtwdev, base_addr + 0x68, temp); 446 dm_info->dack_adck[path] = temp; 447 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n", 448 base_addr + 0x68, temp); 449 /* check ADC DC offset */ 450 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103); 451 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 452 rtw_dbg(rtwdev, RTW_DBG_RFK, 453 "[DACK] after: i=0x%08x, q=0x%08x\n", ic, qc); 454 if (ic >= 0x200) 455 ic = 0x400 - ic; 456 if (qc >= 0x200) 457 qc = 0x400 - qc; 458 if (ic < 5 && qc < 5) 459 break; 460 } 461 462 /* ADCK step2 */ 463 rtw_write32(rtwdev, 0x1c3c, 0x00000003); 464 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); 465 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); 466 467 /* release pull low switch on IQ path */ 468 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1); 469 } 470 471 static void rtw8822c_dac_cal_step1(struct rtw_dev *rtwdev, u8 path) 472 { 473 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 474 u32 base_addr; 475 u32 read_addr; 476 477 base_addr = rtw8822c_get_path_write_addr(path); 478 read_addr = rtw8822c_get_path_read_addr(path); 479 480 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]); 481 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 482 if (path == RF_PATH_A) { 483 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); 484 rtw_write32(rtwdev, 0x1c38, 0xffffffff); 485 } 486 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 487 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 488 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); 489 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81); 490 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); 491 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); 492 rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81); 493 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); 494 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); 495 mdelay(2); 496 rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d); 497 mdelay(2); 498 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); 499 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); 500 mdelay(1); 501 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); 502 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); 503 mdelay(20); 504 if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) || 505 !check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff)) 506 rtw_err(rtwdev, "failed to wait for dack ready\n"); 507 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); 508 mdelay(1); 509 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); 510 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); 511 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 512 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); 513 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); 514 } 515 516 static void rtw8822c_dac_cal_step2(struct rtw_dev *rtwdev, 517 u8 path, u32 *ic_out, u32 *qc_out) 518 { 519 u32 base_addr; 520 u32 ic, qc, ic_in, qc_in; 521 522 base_addr = rtw8822c_get_path_write_addr(path); 523 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0); 524 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8); 525 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0); 526 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8); 527 528 rtw_write32(rtwdev, 0x1b00, 0x00000008); 529 rtw_write8(rtwdev, 0x1bcc, 0x03f); 530 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 531 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 532 rtw_write32(rtwdev, 0x1c3c, 0x00088103); 533 534 rtw8822c_dac_cal_rf_mode(rtwdev, &ic_in, &qc_in); 535 ic = ic_in; 536 qc = qc_in; 537 538 /* compensation value */ 539 if (ic != 0x0) 540 ic = 0x400 - ic; 541 if (qc != 0x0) 542 qc = 0x400 - qc; 543 if (ic < 0x300) { 544 ic = ic * 2 * 6 / 5; 545 ic = ic + 0x80; 546 } else { 547 ic = (0x400 - ic) * 2 * 6 / 5; 548 ic = 0x7f - ic; 549 } 550 if (qc < 0x300) { 551 qc = qc * 2 * 6 / 5; 552 qc = qc + 0x80; 553 } else { 554 qc = (0x400 - qc) * 2 * 6 / 5; 555 qc = 0x7f - qc; 556 } 557 558 *ic_out = ic; 559 *qc_out = qc; 560 561 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in); 562 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc); 563 } 564 565 static void rtw8822c_dac_cal_step3(struct rtw_dev *rtwdev, u8 path, 566 u32 adc_ic, u32 adc_qc, 567 u32 *ic_in, u32 *qc_in, 568 u32 *i_out, u32 *q_out) 569 { 570 u32 base_addr; 571 u32 read_addr; 572 u32 ic, qc; 573 u32 temp; 574 575 base_addr = rtw8822c_get_path_write_addr(path); 576 read_addr = rtw8822c_get_path_read_addr(path); 577 ic = *ic_in; 578 qc = *qc_in; 579 580 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 581 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 582 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 583 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); 584 rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81); 585 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); 586 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf); 587 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4); 588 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); 589 rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81); 590 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); 591 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf); 592 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4); 593 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); 594 mdelay(2); 595 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6); 596 mdelay(2); 597 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); 598 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); 599 mdelay(1); 600 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); 601 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); 602 mdelay(20); 603 if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) || 604 !check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc)) 605 rtw_err(rtwdev, "failed to write IQ vector to hardware\n"); 606 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); 607 mdelay(1); 608 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3); 609 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); 610 611 /* check DAC DC offset */ 612 temp = ((adc_ic + 0x10) & 0x3ff) | (((adc_qc + 0x10) & 0x3ff) << 10); 613 rtw_write32(rtwdev, base_addr + 0x68, temp); 614 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 615 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); 616 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 617 if (ic >= 0x10) 618 ic = ic - 0x10; 619 else 620 ic = 0x400 - (0x10 - ic); 621 622 if (qc >= 0x10) 623 qc = qc - 0x10; 624 else 625 qc = 0x400 - (0x10 - qc); 626 627 *i_out = ic; 628 *q_out = qc; 629 630 if (ic >= 0x200) 631 ic = 0x400 - ic; 632 if (qc >= 0x200) 633 qc = 0x400 - qc; 634 635 *ic_in = ic; 636 *qc_in = qc; 637 638 rtw_dbg(rtwdev, RTW_DBG_RFK, 639 "[DACK] after DACK i=0x%x, q=0x%x\n", *i_out, *q_out); 640 } 641 642 static void rtw8822c_dac_cal_step4(struct rtw_dev *rtwdev, u8 path) 643 { 644 u32 base_addr = rtw8822c_get_path_write_addr(path); 645 646 rtw_write32(rtwdev, base_addr + 0x68, 0x0); 647 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); 648 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0); 649 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1); 650 } 651 652 static void rtw8822c_dac_cal_backup_vec(struct rtw_dev *rtwdev, 653 u8 path, u8 vec, u32 w_addr, u32 r_addr) 654 { 655 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 656 u16 val; 657 u32 i; 658 659 if (WARN_ON(vec >= 2)) 660 return; 661 662 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 663 rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i); 664 val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000); 665 dm_info->dack_msbk[path][vec][i] = val; 666 } 667 } 668 669 static void rtw8822c_dac_cal_backup_path(struct rtw_dev *rtwdev, u8 path) 670 { 671 u32 w_off = 0x1c; 672 u32 r_off = 0x2c; 673 u32 w_addr, r_addr; 674 675 if (WARN_ON(path >= 2)) 676 return; 677 678 /* backup I vector */ 679 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0; 680 r_addr = rtw8822c_get_path_read_addr(path) + 0x10; 681 rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr); 682 683 /* backup Q vector */ 684 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; 685 r_addr = rtw8822c_get_path_read_addr(path) + 0x10 + r_off; 686 rtw8822c_dac_cal_backup_vec(rtwdev, path, 1, w_addr, r_addr); 687 } 688 689 static void rtw8822c_dac_cal_backup_dck(struct rtw_dev *rtwdev) 690 { 691 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 692 u8 val; 693 694 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000); 695 dm_info->dack_dck[RF_PATH_A][0][0] = val; 696 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf); 697 dm_info->dack_dck[RF_PATH_A][0][1] = val; 698 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000); 699 dm_info->dack_dck[RF_PATH_A][1][0] = val; 700 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf); 701 dm_info->dack_dck[RF_PATH_A][1][1] = val; 702 703 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000); 704 dm_info->dack_dck[RF_PATH_B][0][0] = val; 705 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf); 706 dm_info->dack_dck[RF_PATH_B][1][0] = val; 707 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000); 708 dm_info->dack_dck[RF_PATH_B][0][1] = val; 709 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf); 710 dm_info->dack_dck[RF_PATH_B][1][1] = val; 711 } 712 713 static void rtw8822c_dac_cal_backup(struct rtw_dev *rtwdev) 714 { 715 u32 temp[3]; 716 717 temp[0] = rtw_read32(rtwdev, 0x1860); 718 temp[1] = rtw_read32(rtwdev, 0x4160); 719 temp[2] = rtw_read32(rtwdev, 0x9b4); 720 721 /* set clock */ 722 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 723 724 /* backup path-A I/Q */ 725 rtw_write32_clr(rtwdev, 0x1830, BIT(30)); 726 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); 727 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_A); 728 729 /* backup path-B I/Q */ 730 rtw_write32_clr(rtwdev, 0x4130, BIT(30)); 731 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); 732 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_B); 733 734 rtw8822c_dac_cal_backup_dck(rtwdev); 735 rtw_write32_set(rtwdev, 0x1830, BIT(30)); 736 rtw_write32_set(rtwdev, 0x4130, BIT(30)); 737 738 rtw_write32(rtwdev, 0x1860, temp[0]); 739 rtw_write32(rtwdev, 0x4160, temp[1]); 740 rtw_write32(rtwdev, 0x9b4, temp[2]); 741 } 742 743 static void rtw8822c_dac_cal_restore_dck(struct rtw_dev *rtwdev) 744 { 745 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 746 u8 val; 747 748 rtw_write32_set(rtwdev, REG_DCKA_I_0, BIT(19)); 749 val = dm_info->dack_dck[RF_PATH_A][0][0]; 750 rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val); 751 val = dm_info->dack_dck[RF_PATH_A][0][1]; 752 rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val); 753 754 rtw_write32_set(rtwdev, REG_DCKA_Q_0, BIT(19)); 755 val = dm_info->dack_dck[RF_PATH_A][1][0]; 756 rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val); 757 val = dm_info->dack_dck[RF_PATH_A][1][1]; 758 rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val); 759 760 rtw_write32_set(rtwdev, REG_DCKB_I_0, BIT(19)); 761 val = dm_info->dack_dck[RF_PATH_B][0][0]; 762 rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val); 763 val = dm_info->dack_dck[RF_PATH_B][0][1]; 764 rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val); 765 766 rtw_write32_set(rtwdev, REG_DCKB_Q_0, BIT(19)); 767 val = dm_info->dack_dck[RF_PATH_B][1][0]; 768 rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val); 769 val = dm_info->dack_dck[RF_PATH_B][1][1]; 770 rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val); 771 } 772 773 static void rtw8822c_dac_cal_restore_prepare(struct rtw_dev *rtwdev) 774 { 775 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 776 777 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0); 778 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0); 779 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0); 780 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0); 781 782 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0); 783 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); 784 rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1); 785 rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1); 786 787 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0); 788 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); 789 rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1); 790 rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1); 791 792 rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0); 793 rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0); 794 rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0); 795 rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0); 796 797 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0); 798 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0); 799 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1); 800 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1); 801 802 rtw8822c_dac_cal_restore_dck(rtwdev); 803 804 rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7); 805 rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7); 806 rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7); 807 rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7); 808 809 rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1); 810 rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1); 811 812 rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0); 813 rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0); 814 rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0); 815 rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0); 816 817 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0); 818 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0); 819 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1); 820 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1); 821 822 rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1); 823 rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1); 824 } 825 826 static bool rtw8822c_dac_cal_restore_wait(struct rtw_dev *rtwdev, 827 u32 target_addr, u32 toggle_addr) 828 { 829 u32 cnt = 0; 830 831 do { 832 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0); 833 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2); 834 835 if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6) 836 return true; 837 838 } while (cnt++ < 100); 839 840 return false; 841 } 842 843 static bool rtw8822c_dac_cal_restore_path(struct rtw_dev *rtwdev, u8 path) 844 { 845 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 846 u32 w_off = 0x1c; 847 u32 r_off = 0x2c; 848 u32 w_i, r_i, w_q, r_q; 849 u32 value; 850 u32 i; 851 852 w_i = rtw8822c_get_path_write_addr(path) + 0xb0; 853 r_i = rtw8822c_get_path_read_addr(path) + 0x08; 854 w_q = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; 855 r_q = rtw8822c_get_path_read_addr(path) + 0x08 + r_off; 856 857 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8)) 858 return false; 859 860 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 861 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); 862 value = dm_info->dack_msbk[path][0][i]; 863 rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value); 864 rtw_write32_mask(rtwdev, w_i, 0xf0000000, i); 865 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1); 866 } 867 868 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); 869 870 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8)) 871 return false; 872 873 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 874 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); 875 value = dm_info->dack_msbk[path][1][i]; 876 rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value); 877 rtw_write32_mask(rtwdev, w_q, 0xf0000000, i); 878 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1); 879 } 880 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); 881 882 rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0); 883 rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0); 884 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0); 885 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0); 886 887 return true; 888 } 889 890 static bool __rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev) 891 { 892 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_A)) 893 return false; 894 895 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_B)) 896 return false; 897 898 return true; 899 } 900 901 static bool rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev) 902 { 903 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 904 u32 temp[3]; 905 906 /* sample the first element for both path's IQ vector */ 907 if (dm_info->dack_msbk[RF_PATH_A][0][0] == 0 && 908 dm_info->dack_msbk[RF_PATH_A][1][0] == 0 && 909 dm_info->dack_msbk[RF_PATH_B][0][0] == 0 && 910 dm_info->dack_msbk[RF_PATH_B][1][0] == 0) 911 return false; 912 913 temp[0] = rtw_read32(rtwdev, 0x1860); 914 temp[1] = rtw_read32(rtwdev, 0x4160); 915 temp[2] = rtw_read32(rtwdev, 0x9b4); 916 917 rtw8822c_dac_cal_restore_prepare(rtwdev); 918 if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) || 919 !check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) || 920 !check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) || 921 !check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff)) 922 return false; 923 924 if (!__rtw8822c_dac_cal_restore(rtwdev)) { 925 rtw_err(rtwdev, "failed to restore dack vectors\n"); 926 return false; 927 } 928 929 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1); 930 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); 931 rtw_write32(rtwdev, 0x1860, temp[0]); 932 rtw_write32(rtwdev, 0x4160, temp[1]); 933 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1); 934 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1); 935 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1); 936 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1); 937 rtw_write32(rtwdev, 0x9b4, temp[2]); 938 939 return true; 940 } 941 942 static void rtw8822c_rf_dac_cal(struct rtw_dev *rtwdev) 943 { 944 struct rtw_backup_info backup_rf[DACK_RF_8822C * DACK_PATH_8822C]; 945 struct rtw_backup_info backup[DACK_REG_8822C]; 946 u32 ic = 0, qc = 0, i; 947 u32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0; 948 u32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0; 949 u32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0; 950 951 if (rtw8822c_dac_cal_restore(rtwdev)) 952 return; 953 954 /* not able to restore, do it */ 955 956 rtw8822c_dac_backup_reg(rtwdev, backup, backup_rf); 957 958 rtw8822c_dac_bb_setting(rtwdev); 959 960 /* path-A */ 961 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_A, &adc_ic_a, &adc_qc_a); 962 for (i = 0; i < 10; i++) { 963 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_A); 964 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_A, &ic, &qc); 965 ic_a = ic; 966 qc_a = qc; 967 968 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_A, adc_ic_a, adc_qc_a, 969 &ic, &qc, &i_a, &q_a); 970 971 if (ic < 5 && qc < 5) 972 break; 973 } 974 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_A); 975 976 /* path-B */ 977 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_B, &adc_ic_b, &adc_qc_b); 978 for (i = 0; i < 10; i++) { 979 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_B); 980 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_B, &ic, &qc); 981 ic_b = ic; 982 qc_b = qc; 983 984 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_B, adc_ic_b, adc_qc_b, 985 &ic, &qc, &i_b, &q_b); 986 987 if (ic < 5 && qc < 5) 988 break; 989 } 990 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_B); 991 992 rtw_write32(rtwdev, 0x1b00, 0x00000008); 993 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); 994 rtw_write8(rtwdev, 0x1bcc, 0x0); 995 rtw_write32(rtwdev, 0x1b00, 0x0000000a); 996 rtw_write8(rtwdev, 0x1bcc, 0x0); 997 998 rtw8822c_dac_restore_reg(rtwdev, backup, backup_rf); 999 1000 /* backup results to restore, saving a lot of time */ 1001 rtw8822c_dac_cal_backup(rtwdev); 1002 1003 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a); 1004 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b); 1005 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a); 1006 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b); 1007 } 1008 1009 static void rtw8822c_rf_x2_check(struct rtw_dev *rtwdev) 1010 { 1011 u8 x2k_busy; 1012 1013 mdelay(1); 1014 x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15)); 1015 if (x2k_busy == 1) { 1016 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440); 1017 rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D); 1018 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440); 1019 mdelay(1); 1020 } 1021 } 1022 1023 static void rtw8822c_set_power_trim(struct rtw_dev *rtwdev, s8 bb_gain[2][8]) 1024 { 1025 #define RF_SET_POWER_TRIM(_path, _seq, _idx) \ 1026 do { \ 1027 rtw_write_rf(rtwdev, _path, 0x33, RFREG_MASK, _seq); \ 1028 rtw_write_rf(rtwdev, _path, 0x3f, RFREG_MASK, \ 1029 bb_gain[_path][_idx]); \ 1030 } while (0) 1031 u8 path; 1032 1033 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1034 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 1); 1035 RF_SET_POWER_TRIM(path, 0x0, 0); 1036 RF_SET_POWER_TRIM(path, 0x1, 1); 1037 RF_SET_POWER_TRIM(path, 0x2, 2); 1038 RF_SET_POWER_TRIM(path, 0x3, 2); 1039 RF_SET_POWER_TRIM(path, 0x4, 3); 1040 RF_SET_POWER_TRIM(path, 0x5, 4); 1041 RF_SET_POWER_TRIM(path, 0x6, 5); 1042 RF_SET_POWER_TRIM(path, 0x7, 6); 1043 RF_SET_POWER_TRIM(path, 0x8, 7); 1044 RF_SET_POWER_TRIM(path, 0x9, 3); 1045 RF_SET_POWER_TRIM(path, 0xa, 4); 1046 RF_SET_POWER_TRIM(path, 0xb, 5); 1047 RF_SET_POWER_TRIM(path, 0xc, 6); 1048 RF_SET_POWER_TRIM(path, 0xd, 7); 1049 RF_SET_POWER_TRIM(path, 0xe, 7); 1050 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 0); 1051 } 1052 #undef RF_SET_POWER_TRIM 1053 } 1054 1055 static void rtw8822c_power_trim(struct rtw_dev *rtwdev) 1056 { 1057 u8 pg_pwr = 0xff, i, path, idx; 1058 s8 bb_gain[2][8] = {}; 1059 u16 rf_efuse_2g[3] = {PPG_2GL_TXAB, PPG_2GM_TXAB, PPG_2GH_TXAB}; 1060 u16 rf_efuse_5g[2][5] = {{PPG_5GL1_TXA, PPG_5GL2_TXA, PPG_5GM1_TXA, 1061 PPG_5GM2_TXA, PPG_5GH1_TXA}, 1062 {PPG_5GL1_TXB, PPG_5GL2_TXB, PPG_5GM1_TXB, 1063 PPG_5GM2_TXB, PPG_5GH1_TXB} }; 1064 bool set = false; 1065 1066 for (i = 0; i < ARRAY_SIZE(rf_efuse_2g); i++) { 1067 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[i], &pg_pwr); 1068 if (pg_pwr == EFUSE_READ_FAIL) 1069 continue; 1070 set = true; 1071 bb_gain[RF_PATH_A][i] = FIELD_GET(PPG_2G_A_MASK, pg_pwr); 1072 bb_gain[RF_PATH_B][i] = FIELD_GET(PPG_2G_B_MASK, pg_pwr); 1073 } 1074 1075 for (i = 0; i < ARRAY_SIZE(rf_efuse_5g[0]); i++) { 1076 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1077 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path][i], 1078 &pg_pwr); 1079 if (pg_pwr == EFUSE_READ_FAIL) 1080 continue; 1081 set = true; 1082 idx = i + ARRAY_SIZE(rf_efuse_2g); 1083 bb_gain[path][idx] = FIELD_GET(PPG_5G_MASK, pg_pwr); 1084 } 1085 } 1086 if (set) 1087 rtw8822c_set_power_trim(rtwdev, bb_gain); 1088 1089 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL); 1090 } 1091 1092 static void rtw8822c_thermal_trim(struct rtw_dev *rtwdev) 1093 { 1094 u16 rf_efuse[2] = {PPG_THERMAL_A, PPG_THERMAL_B}; 1095 u8 pg_therm = 0xff, thermal[2] = {0}, path; 1096 1097 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1098 rtw_read8_physical_efuse(rtwdev, rf_efuse[path], &pg_therm); 1099 if (pg_therm == EFUSE_READ_FAIL) 1100 return; 1101 /* Efuse value of BIT(0) shall be move to BIT(3), and the value 1102 * of BIT(1) to BIT(3) should be right shifted 1 bit. 1103 */ 1104 thermal[path] = FIELD_GET(GENMASK(3, 1), pg_therm); 1105 thermal[path] |= FIELD_PREP(BIT(3), pg_therm & BIT(0)); 1106 rtw_write_rf(rtwdev, path, 0x43, RF_THEMAL_MASK, thermal[path]); 1107 } 1108 } 1109 1110 static void rtw8822c_pa_bias(struct rtw_dev *rtwdev) 1111 { 1112 u16 rf_efuse_2g[2] = {PPG_PABIAS_2GA, PPG_PABIAS_2GB}; 1113 u16 rf_efuse_5g[2] = {PPG_PABIAS_5GA, PPG_PABIAS_5GB}; 1114 u8 pg_pa_bias = 0xff, path; 1115 1116 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1117 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[path], 1118 &pg_pa_bias); 1119 if (pg_pa_bias == EFUSE_READ_FAIL) 1120 return; 1121 pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias); 1122 rtw_write_rf(rtwdev, path, RF_PA, RF_PABIAS_2G_MASK, pg_pa_bias); 1123 } 1124 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1125 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path], 1126 &pg_pa_bias); 1127 pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias); 1128 rtw_write_rf(rtwdev, path, RF_PA, RF_PABIAS_5G_MASK, pg_pa_bias); 1129 } 1130 } 1131 1132 static void rtw8822c_rfk_handshake(struct rtw_dev *rtwdev, bool is_before_k) 1133 { 1134 struct rtw_dm_info *dm = &rtwdev->dm_info; 1135 u8 u1b_tmp; 1136 u8 u4b_tmp; 1137 int ret; 1138 1139 if (is_before_k) { 1140 rtw_dbg(rtwdev, RTW_DBG_RFK, 1141 "[RFK] WiFi / BT RFK handshake start!!\n"); 1142 1143 if (!dm->is_bt_iqk_timeout) { 1144 ret = read_poll_timeout(rtw_read32_mask, u4b_tmp, 1145 u4b_tmp == 0, 20, 600000, false, 1146 rtwdev, REG_PMC_DBG_CTRL1, 1147 BITS_PMC_BT_IQK_STS); 1148 if (ret) { 1149 rtw_dbg(rtwdev, RTW_DBG_RFK, 1150 "[RFK] Wait BT IQK finish timeout!!\n"); 1151 dm->is_bt_iqk_timeout = true; 1152 } 1153 } 1154 1155 rtw_fw_inform_rfk_status(rtwdev, true); 1156 1157 ret = read_poll_timeout(rtw_read8_mask, u1b_tmp, 1158 u1b_tmp == 1, 20, 100000, false, 1159 rtwdev, REG_ARFR4, BIT_WL_RFK); 1160 if (ret) 1161 rtw_dbg(rtwdev, RTW_DBG_RFK, 1162 "[RFK] Send WiFi RFK start H2C cmd FAIL!!\n"); 1163 } else { 1164 rtw_fw_inform_rfk_status(rtwdev, false); 1165 ret = read_poll_timeout(rtw_read8_mask, u1b_tmp, 1166 u1b_tmp == 1, 20, 100000, false, 1167 rtwdev, REG_ARFR4, 1168 BIT_WL_RFK); 1169 if (ret) 1170 rtw_dbg(rtwdev, RTW_DBG_RFK, 1171 "[RFK] Send WiFi RFK finish H2C cmd FAIL!!\n"); 1172 1173 rtw_dbg(rtwdev, RTW_DBG_RFK, 1174 "[RFK] WiFi / BT RFK handshake finish!!\n"); 1175 } 1176 } 1177 1178 static void rtw8822c_rfk_power_save(struct rtw_dev *rtwdev, 1179 bool is_power_save) 1180 { 1181 u8 path; 1182 1183 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1184 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path); 1185 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_PS_EN, 1186 is_power_save ? 0 : 1); 1187 } 1188 } 1189 1190 static void rtw8822c_txgapk_backup_bb_reg(struct rtw_dev *rtwdev, const u32 reg[], 1191 u32 reg_backup[], u32 reg_num) 1192 { 1193 u32 i; 1194 1195 for (i = 0; i < reg_num; i++) { 1196 reg_backup[i] = rtw_read32(rtwdev, reg[i]); 1197 1198 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Backup BB 0x%x = 0x%x\n", 1199 reg[i], reg_backup[i]); 1200 } 1201 } 1202 1203 static void rtw8822c_txgapk_reload_bb_reg(struct rtw_dev *rtwdev, 1204 const u32 reg[], u32 reg_backup[], 1205 u32 reg_num) 1206 { 1207 u32 i; 1208 1209 for (i = 0; i < reg_num; i++) { 1210 rtw_write32(rtwdev, reg[i], reg_backup[i]); 1211 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Reload BB 0x%x = 0x%x\n", 1212 reg[i], reg_backup[i]); 1213 } 1214 } 1215 1216 static bool check_rf_status(struct rtw_dev *rtwdev, u8 status) 1217 { 1218 u8 reg_rf0_a, reg_rf0_b; 1219 1220 reg_rf0_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 1221 RF_MODE_TRXAGC, BIT_RF_MODE); 1222 reg_rf0_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 1223 RF_MODE_TRXAGC, BIT_RF_MODE); 1224 1225 if (reg_rf0_a == status || reg_rf0_b == status) 1226 return false; 1227 1228 return true; 1229 } 1230 1231 static void rtw8822c_txgapk_tx_pause(struct rtw_dev *rtwdev) 1232 { 1233 bool status; 1234 int ret; 1235 1236 rtw_write8(rtwdev, REG_TXPAUSE, BIT_AC_QUEUE); 1237 rtw_write32_mask(rtwdev, REG_TX_FIFO, BIT_STOP_TX, 0x2); 1238 1239 ret = read_poll_timeout_atomic(check_rf_status, status, status, 1240 2, 5000, false, rtwdev, 2); 1241 if (ret) 1242 rtw_warn(rtwdev, "failed to pause TX\n"); 1243 1244 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Tx pause!!\n"); 1245 } 1246 1247 static void rtw8822c_txgapk_bb_dpk(struct rtw_dev *rtwdev, u8 path) 1248 { 1249 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1250 1251 rtw_write32_mask(rtwdev, REG_ENFN, BIT_IQK_DPK_EN, 0x1); 1252 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, 1253 BIT_IQK_DPK_CLOCK_SRC, 0x1); 1254 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, 1255 BIT_IQK_DPK_RESET_SRC, 0x1); 1256 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, BIT_EN_IOQ_IQK_DPK, 0x1); 1257 rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, BIT_TST_IQK2SET_SRC, 0x0); 1258 rtw_write32_mask(rtwdev, REG_CCA_OFF, BIT_CCA_ON_BY_PW, 0x1ff); 1259 1260 if (path == RF_PATH_A) { 1261 rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_A, 1262 BIT_RFTXEN_GCK_FORCE_ON, 0x1); 1263 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_DIS_SHARERX_TXGAT, 0x1); 1264 rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_A, 1265 BIT_TX_SCALE_0DB, 0x1); 1266 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_3WIRE_EN, 0x0); 1267 } else if (path == RF_PATH_B) { 1268 rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_B, 1269 BIT_RFTXEN_GCK_FORCE_ON, 0x1); 1270 rtw_write32_mask(rtwdev, REG_3WIRE2, 1271 BIT_DIS_SHARERX_TXGAT, 0x1); 1272 rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_B, 1273 BIT_TX_SCALE_0DB, 0x1); 1274 rtw_write32_mask(rtwdev, REG_3WIRE2, BIT_3WIRE_EN, 0x0); 1275 } 1276 rtw_write32_mask(rtwdev, REG_CCKSB, BIT_BBMODE, 0x2); 1277 } 1278 1279 static void rtw8822c_txgapk_afe_dpk(struct rtw_dev *rtwdev, u8 path) 1280 { 1281 u32 reg; 1282 1283 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1284 1285 if (path == RF_PATH_A) { 1286 reg = REG_ANAPAR_A; 1287 } else if (path == RF_PATH_B) { 1288 reg = REG_ANAPAR_B; 1289 } else { 1290 rtw_err(rtwdev, "[TXGAPK] unknown path %d!!\n", path); 1291 return; 1292 } 1293 1294 rtw_write32_mask(rtwdev, REG_IQK_CTRL, MASKDWORD, MASKDWORD); 1295 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700f0001); 1296 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700f0001); 1297 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x701f0001); 1298 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x702f0001); 1299 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x703f0001); 1300 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x704f0001); 1301 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x705f0001); 1302 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x706f0001); 1303 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x707f0001); 1304 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x708f0001); 1305 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x709f0001); 1306 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70af0001); 1307 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70bf0001); 1308 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70cf0001); 1309 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70df0001); 1310 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ef0001); 1311 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ff0001); 1312 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ff0001); 1313 } 1314 1315 static void rtw8822c_txgapk_afe_dpk_restore(struct rtw_dev *rtwdev, u8 path) 1316 { 1317 u32 reg; 1318 1319 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1320 1321 if (path == RF_PATH_A) { 1322 reg = REG_ANAPAR_A; 1323 } else if (path == RF_PATH_B) { 1324 reg = REG_ANAPAR_B; 1325 } else { 1326 rtw_err(rtwdev, "[TXGAPK] unknown path %d!!\n", path); 1327 return; 1328 } 1329 rtw_write32_mask(rtwdev, REG_IQK_CTRL, MASKDWORD, 0xffa1005e); 1330 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700b8041); 1331 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70144041); 1332 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70244041); 1333 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70344041); 1334 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70444041); 1335 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x705b8041); 1336 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70644041); 1337 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x707b8041); 1338 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x708b8041); 1339 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x709b8041); 1340 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ab8041); 1341 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70bb8041); 1342 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70cb8041); 1343 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70db8041); 1344 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70eb8041); 1345 rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70fb8041); 1346 } 1347 1348 static void rtw8822c_txgapk_bb_dpk_restore(struct rtw_dev *rtwdev, u8 path) 1349 { 1350 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1351 1352 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x0); 1353 rtw_write_rf(rtwdev, path, RF_DIS_BYPASS_TXBB, BIT_TIA_BYPASS, 0x0); 1354 rtw_write_rf(rtwdev, path, RF_DIS_BYPASS_TXBB, BIT_TXBB, 0x0); 1355 1356 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x0); 1357 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 1358 rtw_write32_mask(rtwdev, REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0); 1359 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, 0x00); 1360 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x1); 1361 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 1362 rtw_write32_mask(rtwdev, REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0); 1363 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, 0x00); 1364 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x0); 1365 rtw_write32_mask(rtwdev, REG_CCA_OFF, BIT_CCA_ON_BY_PW, 0x0); 1366 1367 if (path == RF_PATH_A) { 1368 rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_A, 1369 BIT_RFTXEN_GCK_FORCE_ON, 0x0); 1370 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_DIS_SHARERX_TXGAT, 0x0); 1371 rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_A, 1372 BIT_TX_SCALE_0DB, 0x0); 1373 rtw_write32_mask(rtwdev, REG_3WIRE, BIT_3WIRE_EN, 0x3); 1374 } else if (path == RF_PATH_B) { 1375 rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_B, 1376 BIT_RFTXEN_GCK_FORCE_ON, 0x0); 1377 rtw_write32_mask(rtwdev, REG_3WIRE2, 1378 BIT_DIS_SHARERX_TXGAT, 0x0); 1379 rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_B, 1380 BIT_TX_SCALE_0DB, 0x0); 1381 rtw_write32_mask(rtwdev, REG_3WIRE2, BIT_3WIRE_EN, 0x3); 1382 } 1383 1384 rtw_write32_mask(rtwdev, REG_CCKSB, BIT_BBMODE, 0x0); 1385 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_CFIR_EN, 0x5); 1386 } 1387 1388 static bool _rtw8822c_txgapk_gain_valid(struct rtw_dev *rtwdev, u32 gain) 1389 { 1390 if ((FIELD_GET(BIT_GAIN_TX_PAD_H, gain) >= 0xc) && 1391 (FIELD_GET(BIT_GAIN_TX_PAD_L, gain) >= 0xe)) 1392 return true; 1393 1394 return false; 1395 } 1396 1397 static void _rtw8822c_txgapk_write_gain_bb_table(struct rtw_dev *rtwdev, 1398 u8 band, u8 path) 1399 { 1400 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk; 1401 u32 v, tmp_3f = 0; 1402 u8 gain, check_txgain; 1403 1404 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path); 1405 1406 switch (band) { 1407 case RF_BAND_2G_OFDM: 1408 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x0); 1409 break; 1410 case RF_BAND_5G_L: 1411 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x2); 1412 break; 1413 case RF_BAND_5G_M: 1414 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x3); 1415 break; 1416 case RF_BAND_5G_H: 1417 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x4); 1418 break; 1419 default: 1420 break; 1421 } 1422 1423 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, MASKBYTE0, 0x88); 1424 1425 check_txgain = 0; 1426 for (gain = 0; gain < RF_GAIN_NUM; gain++) { 1427 v = txgapk->rf3f_bp[band][gain][path]; 1428 if (_rtw8822c_txgapk_gain_valid(rtwdev, v)) { 1429 if (!check_txgain) { 1430 tmp_3f = txgapk->rf3f_bp[band][gain][path]; 1431 check_txgain = 1; 1432 } 1433 rtw_dbg(rtwdev, RTW_DBG_RFK, 1434 "[TXGAPK] tx_gain=0x%03X >= 0xCEX\n", 1435 txgapk->rf3f_bp[band][gain][path]); 1436 } else { 1437 tmp_3f = txgapk->rf3f_bp[band][gain][path]; 1438 } 1439 1440 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN, tmp_3f); 1441 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_I_GAIN, gain); 1442 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_GAIN_RST, 0x1); 1443 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_GAIN_RST, 0x0); 1444 1445 rtw_dbg(rtwdev, RTW_DBG_RFK, 1446 "[TXGAPK] Band=%d 0x1b98[11:0]=0x%03X path=%d\n", 1447 band, tmp_3f, path); 1448 } 1449 } 1450 1451 static void rtw8822c_txgapk_write_gain_bb_table(struct rtw_dev *rtwdev) 1452 { 1453 u8 path, band; 1454 1455 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s channel=%d\n", 1456 __func__, rtwdev->dm_info.gapk.channel); 1457 1458 for (band = 0; band < RF_BAND_MAX; band++) { 1459 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1460 _rtw8822c_txgapk_write_gain_bb_table(rtwdev, 1461 band, path); 1462 } 1463 } 1464 } 1465 1466 static void rtw8822c_txgapk_read_offset(struct rtw_dev *rtwdev, u8 path) 1467 { 1468 static const u32 cfg1_1b00[2] = {0x00000d18, 0x00000d2a}; 1469 static const u32 cfg2_1b00[2] = {0x00000d19, 0x00000d2b}; 1470 static const u32 set_pi[2] = {REG_RSV_CTRL, REG_WLRF1}; 1471 static const u32 path_setting[2] = {REG_ORITXCODE, REG_ORITXCODE2}; 1472 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk; 1473 u8 channel = txgapk->channel; 1474 u32 val; 1475 int i; 1476 1477 if (path >= ARRAY_SIZE(cfg1_1b00) || 1478 path >= ARRAY_SIZE(cfg2_1b00) || 1479 path >= ARRAY_SIZE(set_pi) || 1480 path >= ARRAY_SIZE(path_setting)) { 1481 rtw_warn(rtwdev, "[TXGAPK] wrong path %d\n", path); 1482 return; 1483 } 1484 1485 rtw_write32_mask(rtwdev, REG_ANTMAP0, BIT_ANT_PATH, path + 1); 1486 rtw_write32_mask(rtwdev, REG_TXLGMAP, MASKDWORD, 0xe4e40000); 1487 rtw_write32_mask(rtwdev, REG_TXANTSEG, BIT_ANTSEG, 0x3); 1488 rtw_write32_mask(rtwdev, path_setting[path], MASK20BITS, 0x33312); 1489 rtw_write32_mask(rtwdev, path_setting[path], BIT_PATH_EN, 0x1); 1490 rtw_write32_mask(rtwdev, set_pi[path], BITS_RFC_DIRECT, 0x0); 1491 rtw_write_rf(rtwdev, path, RF_LUTDBG, BIT_TXA_TANK, 0x1); 1492 rtw_write_rf(rtwdev, path, RF_IDAC, BIT_TX_MODE, 0x820); 1493 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path); 1494 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x0); 1495 1496 rtw_write32_mask(rtwdev, REG_TX_TONE_IDX, MASKBYTE0, 0x018); 1497 fsleep(1000); 1498 if (channel >= 1 && channel <= 14) 1499 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, BIT_2G_SWING); 1500 else 1501 rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, BIT_5G_SWING); 1502 fsleep(1000); 1503 1504 rtw_write32_mask(rtwdev, REG_NCTL0, MASKDWORD, cfg1_1b00[path]); 1505 rtw_write32_mask(rtwdev, REG_NCTL0, MASKDWORD, cfg2_1b00[path]); 1506 1507 read_poll_timeout(rtw_read32_mask, val, 1508 val == 0x55, 1000, 100000, false, 1509 rtwdev, REG_RPT_CIP, BIT_RPT_CIP_STATUS); 1510 1511 rtw_write32_mask(rtwdev, set_pi[path], BITS_RFC_DIRECT, 0x2); 1512 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path); 1513 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_EN, 0x1); 1514 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x12); 1515 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, BIT_GAPK_RPT_IDX, 0x3); 1516 val = rtw_read32(rtwdev, REG_STAT_RPT); 1517 1518 txgapk->offset[0][path] = (s8)FIELD_GET(BIT_GAPK_RPT0, val); 1519 txgapk->offset[1][path] = (s8)FIELD_GET(BIT_GAPK_RPT1, val); 1520 txgapk->offset[2][path] = (s8)FIELD_GET(BIT_GAPK_RPT2, val); 1521 txgapk->offset[3][path] = (s8)FIELD_GET(BIT_GAPK_RPT3, val); 1522 txgapk->offset[4][path] = (s8)FIELD_GET(BIT_GAPK_RPT4, val); 1523 txgapk->offset[5][path] = (s8)FIELD_GET(BIT_GAPK_RPT5, val); 1524 txgapk->offset[6][path] = (s8)FIELD_GET(BIT_GAPK_RPT6, val); 1525 txgapk->offset[7][path] = (s8)FIELD_GET(BIT_GAPK_RPT7, val); 1526 1527 rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, BIT_GAPK_RPT_IDX, 0x4); 1528 val = rtw_read32(rtwdev, REG_STAT_RPT); 1529 1530 txgapk->offset[8][path] = (s8)FIELD_GET(BIT_GAPK_RPT0, val); 1531 txgapk->offset[9][path] = (s8)FIELD_GET(BIT_GAPK_RPT1, val); 1532 1533 for (i = 0; i < RF_HW_OFFSET_NUM; i++) 1534 if (txgapk->offset[i][path] & BIT(3)) 1535 txgapk->offset[i][path] = txgapk->offset[i][path] | 1536 0xf0; 1537 for (i = 0; i < RF_HW_OFFSET_NUM; i++) 1538 rtw_dbg(rtwdev, RTW_DBG_RFK, 1539 "[TXGAPK] offset %d %d path=%d\n", 1540 txgapk->offset[i][path], i, path); 1541 } 1542 1543 static void rtw8822c_txgapk_calculate_offset(struct rtw_dev *rtwdev, u8 path) 1544 { 1545 static const u32 bb_reg[] = {REG_ANTMAP0, REG_TXLGMAP, REG_TXANTSEG, 1546 REG_ORITXCODE, REG_ORITXCODE2}; 1547 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk; 1548 u8 channel = txgapk->channel; 1549 u32 reg_backup[ARRAY_SIZE(bb_reg)] = {0}; 1550 1551 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s channel=%d\n", 1552 __func__, channel); 1553 1554 rtw8822c_txgapk_backup_bb_reg(rtwdev, bb_reg, 1555 reg_backup, ARRAY_SIZE(bb_reg)); 1556 1557 if (channel >= 1 && channel <= 14) { 1558 rtw_write32_mask(rtwdev, 1559 REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0); 1560 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path); 1561 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x3f); 1562 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 1563 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1); 1564 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x5000f); 1565 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x0); 1566 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x1); 1567 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0f); 1568 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1); 1569 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1); 1570 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0); 1571 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x1); 1572 1573 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x00); 1574 rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x0); 1575 1576 rtw8822c_txgapk_read_offset(rtwdev, path); 1577 rtw_dbg(rtwdev, RTW_DBG_RFK, "=============================\n"); 1578 1579 } else { 1580 rtw_write32_mask(rtwdev, 1581 REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0); 1582 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path); 1583 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x3f); 1584 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 1585 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1); 1586 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50011); 1587 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x3); 1588 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x3); 1589 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1); 1590 rtw_write_rf(rtwdev, path, 1591 RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0x2); 1592 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0x12); 1593 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1); 1594 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0); 1595 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x1); 1596 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RF_MODE, 0x5); 1597 1598 rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x0); 1599 1600 if (channel >= 36 && channel <= 64) 1601 rtw_write32_mask(rtwdev, 1602 REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x2); 1603 else if (channel >= 100 && channel <= 144) 1604 rtw_write32_mask(rtwdev, 1605 REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x3); 1606 else if (channel >= 149 && channel <= 177) 1607 rtw_write32_mask(rtwdev, 1608 REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x4); 1609 1610 rtw8822c_txgapk_read_offset(rtwdev, path); 1611 rtw_dbg(rtwdev, RTW_DBG_RFK, "=============================\n"); 1612 } 1613 rtw8822c_txgapk_reload_bb_reg(rtwdev, bb_reg, 1614 reg_backup, ARRAY_SIZE(bb_reg)); 1615 } 1616 1617 static void rtw8822c_txgapk_rf_restore(struct rtw_dev *rtwdev, u8 path) 1618 { 1619 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1620 1621 if (path >= rtwdev->hal.rf_path_num) 1622 return; 1623 1624 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RF_MODE, 0x3); 1625 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x0); 1626 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x0); 1627 } 1628 1629 static u32 rtw8822c_txgapk_cal_gain(struct rtw_dev *rtwdev, u32 gain, s8 offset) 1630 { 1631 u32 gain_x2, new_gain; 1632 1633 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1634 1635 if (_rtw8822c_txgapk_gain_valid(rtwdev, gain)) { 1636 new_gain = gain; 1637 rtw_dbg(rtwdev, RTW_DBG_RFK, 1638 "[TXGAPK] gain=0x%03X(>=0xCEX) offset=%d new_gain=0x%03X\n", 1639 gain, offset, new_gain); 1640 return new_gain; 1641 } 1642 1643 gain_x2 = (gain << 1) + offset; 1644 new_gain = (gain_x2 >> 1) | (gain_x2 & BIT(0) ? BIT_GAIN_EXT : 0); 1645 1646 rtw_dbg(rtwdev, RTW_DBG_RFK, 1647 "[TXGAPK] gain=0x%X offset=%d new_gain=0x%X\n", 1648 gain, offset, new_gain); 1649 1650 return new_gain; 1651 } 1652 1653 static void rtw8822c_txgapk_write_tx_gain(struct rtw_dev *rtwdev) 1654 { 1655 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk; 1656 u32 i, j, tmp = 0x20, tmp_3f, v; 1657 s8 offset_tmp[RF_GAIN_NUM] = {0}; 1658 u8 path, band = RF_BAND_2G_OFDM, channel = txgapk->channel; 1659 1660 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1661 1662 if (channel >= 1 && channel <= 14) { 1663 tmp = 0x20; 1664 band = RF_BAND_2G_OFDM; 1665 } else if (channel >= 36 && channel <= 64) { 1666 tmp = 0x200; 1667 band = RF_BAND_5G_L; 1668 } else if (channel >= 100 && channel <= 144) { 1669 tmp = 0x280; 1670 band = RF_BAND_5G_M; 1671 } else if (channel >= 149 && channel <= 177) { 1672 tmp = 0x300; 1673 band = RF_BAND_5G_H; 1674 } else { 1675 rtw_err(rtwdev, "[TXGAPK] unknown channel %d!!\n", channel); 1676 return; 1677 } 1678 1679 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1680 for (i = 0; i < RF_GAIN_NUM; i++) { 1681 offset_tmp[i] = 0; 1682 for (j = i; j < RF_GAIN_NUM; j++) { 1683 v = txgapk->rf3f_bp[band][j][path]; 1684 if (_rtw8822c_txgapk_gain_valid(rtwdev, v)) 1685 continue; 1686 1687 offset_tmp[i] += txgapk->offset[j][path]; 1688 txgapk->fianl_offset[i][path] = offset_tmp[i]; 1689 } 1690 1691 v = txgapk->rf3f_bp[band][i][path]; 1692 if (_rtw8822c_txgapk_gain_valid(rtwdev, v)) { 1693 rtw_dbg(rtwdev, RTW_DBG_RFK, 1694 "[TXGAPK] tx_gain=0x%03X >= 0xCEX\n", 1695 txgapk->rf3f_bp[band][i][path]); 1696 } else { 1697 txgapk->rf3f_fs[path][i] = offset_tmp[i]; 1698 rtw_dbg(rtwdev, RTW_DBG_RFK, 1699 "[TXGAPK] offset %d %d\n", 1700 offset_tmp[i], i); 1701 } 1702 } 1703 1704 rtw_write_rf(rtwdev, path, RF_LUTWE2, RFREG_MASK, 0x10000); 1705 for (i = 0; i < RF_GAIN_NUM; i++) { 1706 rtw_write_rf(rtwdev, path, 1707 RF_LUTWA, RFREG_MASK, tmp + i); 1708 1709 tmp_3f = rtw8822c_txgapk_cal_gain(rtwdev, 1710 txgapk->rf3f_bp[band][i][path], 1711 offset_tmp[i]); 1712 rtw_write_rf(rtwdev, path, RF_LUTWD0, 1713 BIT_GAIN_EXT | BIT_DATA_L, tmp_3f); 1714 1715 rtw_dbg(rtwdev, RTW_DBG_RFK, 1716 "[TXGAPK] 0x33=0x%05X 0x3f=0x%04X\n", 1717 tmp + i, tmp_3f); 1718 } 1719 rtw_write_rf(rtwdev, path, RF_LUTWE2, RFREG_MASK, 0x0); 1720 } 1721 } 1722 1723 static void rtw8822c_txgapk_save_all_tx_gain_table(struct rtw_dev *rtwdev) 1724 { 1725 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk; 1726 static const u32 three_wire[2] = {REG_3WIRE, REG_3WIRE2}; 1727 static const u8 ch_num[RF_BAND_MAX] = {1, 1, 36, 100, 149}; 1728 static const u8 band_num[RF_BAND_MAX] = {0x0, 0x0, 0x1, 0x3, 0x5}; 1729 static const u8 cck[RF_BAND_MAX] = {0x1, 0x0, 0x0, 0x0, 0x0}; 1730 u8 path, band, gain, rf0_idx; 1731 u32 rf18, v; 1732 1733 if (rtwdev->dm_info.dm_flags & BIT(RTW_DM_CAP_TXGAPK)) 1734 return; 1735 1736 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1737 1738 if (txgapk->read_txgain == 1) { 1739 rtw_dbg(rtwdev, RTW_DBG_RFK, 1740 "[TXGAPK] Already Read txgapk->read_txgain return!!!\n"); 1741 rtw8822c_txgapk_write_gain_bb_table(rtwdev); 1742 return; 1743 } 1744 1745 for (band = 0; band < RF_BAND_MAX; band++) { 1746 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1747 rf18 = rtw_read_rf(rtwdev, path, RF_CFGCH, RFREG_MASK); 1748 1749 rtw_write32_mask(rtwdev, 1750 three_wire[path], BIT_3WIRE_EN, 0x0); 1751 rtw_write_rf(rtwdev, path, 1752 RF_CFGCH, MASKBYTE0, ch_num[band]); 1753 rtw_write_rf(rtwdev, path, 1754 RF_CFGCH, BIT_BAND, band_num[band]); 1755 rtw_write_rf(rtwdev, path, 1756 RF_BW_TRXBB, BIT_DBG_CCK_CCA, cck[band]); 1757 rtw_write_rf(rtwdev, path, 1758 RF_BW_TRXBB, BIT_TX_CCK_IND, cck[band]); 1759 gain = 0; 1760 for (rf0_idx = 1; rf0_idx < 32; rf0_idx += 3) { 1761 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, 1762 MASKBYTE0, rf0_idx); 1763 v = rtw_read_rf(rtwdev, path, 1764 RF_TX_RESULT, RFREG_MASK); 1765 txgapk->rf3f_bp[band][gain][path] = v & BIT_DATA_L; 1766 1767 rtw_dbg(rtwdev, RTW_DBG_RFK, 1768 "[TXGAPK] 0x5f=0x%03X band=%d path=%d\n", 1769 txgapk->rf3f_bp[band][gain][path], 1770 band, path); 1771 gain++; 1772 } 1773 rtw_write_rf(rtwdev, path, RF_CFGCH, RFREG_MASK, rf18); 1774 rtw_write32_mask(rtwdev, 1775 three_wire[path], BIT_3WIRE_EN, 0x3); 1776 } 1777 } 1778 rtw8822c_txgapk_write_gain_bb_table(rtwdev); 1779 txgapk->read_txgain = 1; 1780 } 1781 1782 static void rtw8822c_txgapk(struct rtw_dev *rtwdev) 1783 { 1784 static const u32 bb_reg[2] = {REG_TX_PTCL_CTRL, REG_TX_FIFO}; 1785 struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk; 1786 u32 bb_reg_backup[2]; 1787 u8 path; 1788 1789 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__); 1790 1791 rtw8822c_txgapk_save_all_tx_gain_table(rtwdev); 1792 1793 if (txgapk->read_txgain == 0) { 1794 rtw_dbg(rtwdev, RTW_DBG_RFK, 1795 "[TXGAPK] txgapk->read_txgain == 0 return!!!\n"); 1796 return; 1797 } 1798 1799 if (rtwdev->efuse.power_track_type >= 4 && 1800 rtwdev->efuse.power_track_type <= 7) { 1801 rtw_dbg(rtwdev, RTW_DBG_RFK, 1802 "[TXGAPK] Normal Mode in TSSI mode. return!!!\n"); 1803 return; 1804 } 1805 1806 rtw8822c_txgapk_backup_bb_reg(rtwdev, bb_reg, 1807 bb_reg_backup, ARRAY_SIZE(bb_reg)); 1808 rtw8822c_txgapk_tx_pause(rtwdev); 1809 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1810 txgapk->channel = rtw_read_rf(rtwdev, path, 1811 RF_CFGCH, RFREG_MASK) & MASKBYTE0; 1812 rtw8822c_txgapk_bb_dpk(rtwdev, path); 1813 rtw8822c_txgapk_afe_dpk(rtwdev, path); 1814 rtw8822c_txgapk_calculate_offset(rtwdev, path); 1815 rtw8822c_txgapk_rf_restore(rtwdev, path); 1816 rtw8822c_txgapk_afe_dpk_restore(rtwdev, path); 1817 rtw8822c_txgapk_bb_dpk_restore(rtwdev, path); 1818 } 1819 rtw8822c_txgapk_write_tx_gain(rtwdev); 1820 rtw8822c_txgapk_reload_bb_reg(rtwdev, bb_reg, 1821 bb_reg_backup, ARRAY_SIZE(bb_reg)); 1822 } 1823 1824 static void rtw8822c_do_gapk(struct rtw_dev *rtwdev) 1825 { 1826 struct rtw_dm_info *dm = &rtwdev->dm_info; 1827 1828 if (dm->dm_flags & BIT(RTW_DM_CAP_TXGAPK)) { 1829 rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] feature disable!!!\n"); 1830 return; 1831 } 1832 rtw8822c_rfk_handshake(rtwdev, true); 1833 rtw8822c_txgapk(rtwdev); 1834 rtw8822c_rfk_handshake(rtwdev, false); 1835 } 1836 1837 static void rtw8822c_rf_init(struct rtw_dev *rtwdev) 1838 { 1839 rtw8822c_rf_dac_cal(rtwdev); 1840 rtw8822c_rf_x2_check(rtwdev); 1841 rtw8822c_thermal_trim(rtwdev); 1842 rtw8822c_power_trim(rtwdev); 1843 rtw8822c_pa_bias(rtwdev); 1844 } 1845 1846 static void rtw8822c_pwrtrack_init(struct rtw_dev *rtwdev) 1847 { 1848 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1849 u8 path; 1850 1851 for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++) { 1852 dm_info->delta_power_index[path] = 0; 1853 ewma_thermal_init(&dm_info->avg_thermal[path]); 1854 dm_info->thermal_avg[path] = 0xff; 1855 } 1856 1857 dm_info->pwr_trk_triggered = false; 1858 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 1859 dm_info->thermal_meter_lck = rtwdev->efuse.thermal_meter_k; 1860 } 1861 1862 static void rtw8822c_phy_set_param(struct rtw_dev *rtwdev) 1863 { 1864 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1865 struct rtw_hal *hal = &rtwdev->hal; 1866 u8 crystal_cap; 1867 u8 cck_gi_u_bnd_msb = 0; 1868 u8 cck_gi_u_bnd_lsb = 0; 1869 u8 cck_gi_l_bnd_msb = 0; 1870 u8 cck_gi_l_bnd_lsb = 0; 1871 bool is_tx2_path; 1872 1873 /* power on BB/RF domain */ 1874 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, 1875 BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB); 1876 rtw_write8_set(rtwdev, REG_RF_CTRL, 1877 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 1878 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN); 1879 1880 /* disable low rate DPD */ 1881 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL); 1882 1883 /* pre init before header files config */ 1884 rtw8822c_header_file_init(rtwdev, true); 1885 1886 rtw_phy_load_tables(rtwdev); 1887 1888 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f; 1889 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00, 1890 crystal_cap | (crystal_cap << 7)); 1891 1892 /* post init after header files config */ 1893 rtw8822c_header_file_init(rtwdev, false); 1894 1895 is_tx2_path = false; 1896 rtw8822c_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx, 1897 is_tx2_path); 1898 rtw_phy_init(rtwdev); 1899 1900 cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000); 1901 cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000); 1902 cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0); 1903 cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000); 1904 1905 dm_info->cck_gi_u_bnd = ((cck_gi_u_bnd_msb << 4) | (cck_gi_u_bnd_lsb)); 1906 dm_info->cck_gi_l_bnd = ((cck_gi_l_bnd_msb << 4) | (cck_gi_l_bnd_lsb)); 1907 1908 rtw8822c_rf_init(rtwdev); 1909 rtw8822c_pwrtrack_init(rtwdev); 1910 1911 rtw_bf_phy_init(rtwdev); 1912 } 1913 1914 #define WLAN_TXQ_RPT_EN 0x1F 1915 #define WLAN_SLOT_TIME 0x09 1916 #define WLAN_PIFS_TIME 0x1C 1917 #define WLAN_SIFS_CCK_CONT_TX 0x0A 1918 #define WLAN_SIFS_OFDM_CONT_TX 0x0E 1919 #define WLAN_SIFS_CCK_TRX 0x0A 1920 #define WLAN_SIFS_OFDM_TRX 0x10 1921 #define WLAN_NAV_MAX 0xC8 1922 #define WLAN_RDG_NAV 0x05 1923 #define WLAN_TXOP_NAV 0x1B 1924 #define WLAN_CCK_RX_TSF 0x30 1925 #define WLAN_OFDM_RX_TSF 0x30 1926 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */ 1927 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */ 1928 #define WLAN_DRV_EARLY_INT 0x04 1929 #define WLAN_BCN_CTRL_CLT0 0x10 1930 #define WLAN_BCN_DMA_TIME 0x02 1931 #define WLAN_BCN_MAX_ERR 0xFF 1932 #define WLAN_SIFS_CCK_DUR_TUNE 0x0A 1933 #define WLAN_SIFS_OFDM_DUR_TUNE 0x10 1934 #define WLAN_SIFS_CCK_CTX 0x0A 1935 #define WLAN_SIFS_CCK_IRX 0x0A 1936 #define WLAN_SIFS_OFDM_CTX 0x0E 1937 #define WLAN_SIFS_OFDM_IRX 0x0E 1938 #define WLAN_EIFS_DUR_TUNE 0x40 1939 #define WLAN_EDCA_VO_PARAM 0x002FA226 1940 #define WLAN_EDCA_VI_PARAM 0x005EA328 1941 #define WLAN_EDCA_BE_PARAM 0x005EA42B 1942 #define WLAN_EDCA_BK_PARAM 0x0000A44F 1943 1944 #define WLAN_RX_FILTER0 0xFFFFFFFF 1945 #define WLAN_RX_FILTER2 0xFFFF 1946 #define WLAN_RCR_CFG 0xE400220E 1947 #define WLAN_RXPKT_MAX_SZ 12288 1948 #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9) 1949 1950 #define WLAN_AMPDU_MAX_TIME 0x70 1951 #define WLAN_RTS_LEN_TH 0xFF 1952 #define WLAN_RTS_TX_TIME_TH 0x08 1953 #define WLAN_MAX_AGG_PKT_LIMIT 0x3f 1954 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x3f 1955 #define WLAN_PRE_TXCNT_TIME_TH 0x1E0 1956 #define FAST_EDCA_VO_TH 0x06 1957 #define FAST_EDCA_VI_TH 0x06 1958 #define FAST_EDCA_BE_TH 0x06 1959 #define FAST_EDCA_BK_TH 0x06 1960 #define WLAN_BAR_RETRY_LIMIT 0x01 1961 #define WLAN_BAR_ACK_TYPE 0x05 1962 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08 1963 #define WLAN_RESP_TXRATE 0x84 1964 #define WLAN_ACK_TO 0x21 1965 #define WLAN_ACK_TO_CCK 0x6A 1966 #define WLAN_DATA_RATE_FB_CNT_1_4 0x01000000 1967 #define WLAN_DATA_RATE_FB_CNT_5_8 0x08070504 1968 #define WLAN_RTS_RATE_FB_CNT_5_8 0x08070504 1969 #define WLAN_DATA_RATE_FB_RATE0 0xFE01F010 1970 #define WLAN_DATA_RATE_FB_RATE0_H 0x40000000 1971 #define WLAN_RTS_RATE_FB_RATE1 0x003FF010 1972 #define WLAN_RTS_RATE_FB_RATE1_H 0x40000000 1973 #define WLAN_RTS_RATE_FB_RATE4 0x0600F010 1974 #define WLAN_RTS_RATE_FB_RATE4_H 0x400003E0 1975 #define WLAN_RTS_RATE_FB_RATE5 0x0600F015 1976 #define WLAN_RTS_RATE_FB_RATE5_H 0x000000E0 1977 #define WLAN_MULTI_ADDR 0xFFFFFFFF 1978 1979 #define WLAN_TX_FUNC_CFG1 0x30 1980 #define WLAN_TX_FUNC_CFG2 0x30 1981 #define WLAN_MAC_OPT_NORM_FUNC1 0x98 1982 #define WLAN_MAC_OPT_LB_FUNC1 0x80 1983 #define WLAN_MAC_OPT_FUNC2 0xb0810041 1984 #define WLAN_MAC_INT_MIG_CFG 0x33330000 1985 1986 #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \ 1987 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \ 1988 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \ 1989 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)) 1990 1991 #define WLAN_SIFS_DUR_TUNE (WLAN_SIFS_CCK_DUR_TUNE | \ 1992 (WLAN_SIFS_OFDM_DUR_TUNE << 8)) 1993 1994 #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\ 1995 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP)) 1996 1997 #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16)) 1998 #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8) 1999 2000 #define MAC_CLK_SPEED 80 /* 80M */ 2001 #define EFUSE_PCB_INFO_OFFSET 0xCA 2002 2003 static int rtw8822c_mac_init(struct rtw_dev *rtwdev) 2004 { 2005 u8 value8; 2006 u16 value16; 2007 u32 value32; 2008 u16 pre_txcnt; 2009 2010 /* txq control */ 2011 value8 = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL); 2012 value8 |= (BIT(7) & ~BIT(1) & ~BIT(2)); 2013 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL, value8); 2014 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); 2015 /* sifs control */ 2016 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SIFS_DUR_TUNE); 2017 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 2018 rtw_write16(rtwdev, REG_RESP_SIFS_CCK, 2019 WLAN_SIFS_CCK_CTX | WLAN_SIFS_CCK_IRX << 8); 2020 rtw_write16(rtwdev, REG_RESP_SIFS_OFDM, 2021 WLAN_SIFS_OFDM_CTX | WLAN_SIFS_OFDM_IRX << 8); 2022 /* rate fallback control */ 2023 rtw_write32(rtwdev, REG_DARFRC, WLAN_DATA_RATE_FB_CNT_1_4); 2024 rtw_write32(rtwdev, REG_DARFRCH, WLAN_DATA_RATE_FB_CNT_5_8); 2025 rtw_write32(rtwdev, REG_RARFRCH, WLAN_RTS_RATE_FB_CNT_5_8); 2026 rtw_write32(rtwdev, REG_ARFR0, WLAN_DATA_RATE_FB_RATE0); 2027 rtw_write32(rtwdev, REG_ARFRH0, WLAN_DATA_RATE_FB_RATE0_H); 2028 rtw_write32(rtwdev, REG_ARFR1_V1, WLAN_RTS_RATE_FB_RATE1); 2029 rtw_write32(rtwdev, REG_ARFRH1_V1, WLAN_RTS_RATE_FB_RATE1_H); 2030 rtw_write32(rtwdev, REG_ARFR4, WLAN_RTS_RATE_FB_RATE4); 2031 rtw_write32(rtwdev, REG_ARFRH4, WLAN_RTS_RATE_FB_RATE4_H); 2032 rtw_write32(rtwdev, REG_ARFR5, WLAN_RTS_RATE_FB_RATE5); 2033 rtw_write32(rtwdev, REG_ARFRH5, WLAN_RTS_RATE_FB_RATE5_H); 2034 /* protocol configuration */ 2035 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 2036 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 2037 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT; 2038 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); 2039 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8)); 2040 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 2041 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 2042 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 2043 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 2044 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 2045 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 2046 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 2047 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 2048 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 2049 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 2050 /* close BA parser */ 2051 rtw_write8_clr(rtwdev, REG_LIFETIME_EN, BIT_BA_PARSER_EN); 2052 rtw_write32_clr(rtwdev, REG_RRSR, BITS_RRSR_RSC); 2053 2054 /* EDCA configuration */ 2055 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, WLAN_EDCA_VO_PARAM); 2056 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, WLAN_EDCA_VI_PARAM); 2057 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, WLAN_EDCA_BE_PARAM); 2058 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, WLAN_EDCA_BK_PARAM); 2059 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 2060 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 2061 rtw_write8_set(rtwdev, REG_RD_CTRL + 1, 2062 (BIT_DIS_TXOP_CFE | BIT_DIS_LSIG_CFE | 2063 BIT_DIS_STBC_CFE) >> 8); 2064 2065 /* MAC clock configuration */ 2066 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BIT_MAC_CLK_SEL); 2067 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED); 2068 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED); 2069 2070 rtw_write8_set(rtwdev, REG_MISC_CTRL, 2071 BIT_EN_FREE_CNT | BIT_DIS_SECOND_CCA); 2072 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 2073 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000); 2074 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 2075 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 2076 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 2077 /* Set beacon cotnrol - enable TSF and other related functions */ 2078 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 2079 /* Set send beacon related registers */ 2080 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 2081 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 2082 rtw_write8(rtwdev, REG_BCN_CTRL_CLINT0, WLAN_BCN_CTRL_CLT0); 2083 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 2084 rtw_write8(rtwdev, REG_BCN_MAX_ERR, WLAN_BCN_MAX_ERR); 2085 2086 /* WMAC configuration */ 2087 rtw_write32(rtwdev, REG_MAR, WLAN_MULTI_ADDR); 2088 rtw_write32(rtwdev, REG_MAR + 4, WLAN_MULTI_ADDR); 2089 rtw_write8(rtwdev, REG_BBPSF_CTRL + 2, WLAN_RESP_TXRATE); 2090 rtw_write8(rtwdev, REG_ACKTO, WLAN_ACK_TO); 2091 rtw_write8(rtwdev, REG_ACKTO_CCK, WLAN_ACK_TO_CCK); 2092 rtw_write16(rtwdev, REG_EIFS, WLAN_EIFS_DUR_TUNE); 2093 rtw_write8(rtwdev, REG_NAV_CTRL + 2, WLAN_NAV_MAX); 2094 rtw_write8(rtwdev, REG_WMAC_TRXPTCL_CTL_H + 2, WLAN_BAR_ACK_TYPE); 2095 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 2096 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 2097 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 2098 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 2099 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 2100 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 2101 rtw_write32_set(rtwdev, REG_GENERAL_OPTION, BIT_DUMMY_FCS_READY_MASK_EN); 2102 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 2103 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION_1, WLAN_MAC_OPT_NORM_FUNC1); 2104 2105 /* init low power */ 2106 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F; 2107 value16 |= (BIT_RXGCK_VHT_FIFOTHR(1) | BIT_RXGCK_HT_FIFOTHR(1) | 2108 BIT_RXGCK_OFDM_FIFOTHR(1) | BIT_RXGCK_CCK_FIFOTHR(1)) >> 16; 2109 rtw_write16(rtwdev, REG_RXPSF_CTRL + 2, value16); 2110 value16 = 0; 2111 value16 = BIT_SET_RXPSF_PKTLENTHR(value16, 1); 2112 value16 |= BIT_RXPSF_CTRLEN | BIT_RXPSF_VHTCHKEN | BIT_RXPSF_HTCHKEN 2113 | BIT_RXPSF_OFDMCHKEN | BIT_RXPSF_CCKCHKEN 2114 | BIT_RXPSF_OFDMRST; 2115 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16); 2116 rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF); 2117 /* rx ignore configuration */ 2118 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL); 2119 value16 &= ~(BIT_RXPSF_MHCHKEN | BIT_RXPSF_CCKRST | 2120 BIT_RXPSF_CONT_ERRCHKEN); 2121 value16 = BIT_SET_RXPSF_ERRTHR(value16, 0x07); 2122 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16); 2123 rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL, 2124 BIT_DIS_CHK_VHTSIGB_CRC); 2125 2126 /* Interrupt migration configuration */ 2127 rtw_write32(rtwdev, REG_INT_MIG, WLAN_MAC_INT_MIG_CFG); 2128 2129 return 0; 2130 } 2131 2132 #define FWCD_SIZE_REG_8822C 0x2000 2133 #define FWCD_SIZE_DMEM_8822C 0x10000 2134 #define FWCD_SIZE_IMEM_8822C 0x10000 2135 #define FWCD_SIZE_EMEM_8822C 0x20000 2136 #define FWCD_SIZE_ROM_8822C 0x10000 2137 2138 static const u32 __fwcd_segs_8822c[] = { 2139 FWCD_SIZE_REG_8822C, 2140 FWCD_SIZE_DMEM_8822C, 2141 FWCD_SIZE_IMEM_8822C, 2142 FWCD_SIZE_EMEM_8822C, 2143 FWCD_SIZE_ROM_8822C, 2144 }; 2145 2146 static const struct rtw_fwcd_segs rtw8822c_fwcd_segs = { 2147 .segs = __fwcd_segs_8822c, 2148 .num = ARRAY_SIZE(__fwcd_segs_8822c), 2149 }; 2150 2151 static int rtw8822c_dump_fw_crash(struct rtw_dev *rtwdev) 2152 { 2153 #define __dump_fw_8822c(_dev, _mem) \ 2154 rtw_dump_fw(_dev, OCPBASE_ ## _mem ## _88XX, \ 2155 FWCD_SIZE_ ## _mem ## _8822C, RTW_FWCD_ ## _mem) 2156 int ret; 2157 2158 ret = rtw_dump_reg(rtwdev, 0x0, FWCD_SIZE_REG_8822C); 2159 if (ret) 2160 return ret; 2161 ret = __dump_fw_8822c(rtwdev, DMEM); 2162 if (ret) 2163 return ret; 2164 ret = __dump_fw_8822c(rtwdev, IMEM); 2165 if (ret) 2166 return ret; 2167 ret = __dump_fw_8822c(rtwdev, EMEM); 2168 if (ret) 2169 return ret; 2170 ret = __dump_fw_8822c(rtwdev, ROM); 2171 if (ret) 2172 return ret; 2173 2174 return 0; 2175 2176 #undef __dump_fw_8822c 2177 } 2178 2179 static void rtw8822c_rstb_3wire(struct rtw_dev *rtwdev, bool enable) 2180 { 2181 if (enable) { 2182 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x1); 2183 rtw_write32_mask(rtwdev, REG_ANAPAR_A, BIT_ANAPAR_UPDATE, 0x1); 2184 rtw_write32_mask(rtwdev, REG_ANAPAR_B, BIT_ANAPAR_UPDATE, 0x1); 2185 } else { 2186 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x0); 2187 } 2188 } 2189 2190 static void rtw8822c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 2191 { 2192 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8)) 2193 #define RF18_BAND_2G (0) 2194 #define RF18_BAND_5G (BIT(16) | BIT(8)) 2195 #define RF18_CHANNEL_MASK (MASKBYTE0) 2196 #define RF18_RFSI_MASK (BIT(18) | BIT(17)) 2197 #define RF18_RFSI_GE_CH80 (BIT(17)) 2198 #define RF18_RFSI_GT_CH140 (BIT(18)) 2199 #define RF18_BW_MASK (BIT(13) | BIT(12)) 2200 #define RF18_BW_20M (BIT(13) | BIT(12)) 2201 #define RF18_BW_40M (BIT(13)) 2202 #define RF18_BW_80M (BIT(12)) 2203 2204 u32 rf_reg18 = 0; 2205 u32 rf_rxbb = 0; 2206 2207 #if defined(__linux__) 2208 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 2209 #elif defined(__FreeBSD__) 2210 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK); 2211 #endif 2212 2213 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 2214 RF18_BW_MASK); 2215 2216 rf_reg18 |= (IS_CH_2G_BAND(channel) ? RF18_BAND_2G : RF18_BAND_5G); 2217 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 2218 if (IS_CH_5G_BAND_4(channel)) 2219 rf_reg18 |= RF18_RFSI_GT_CH140; 2220 else if (IS_CH_5G_BAND_3(channel)) 2221 rf_reg18 |= RF18_RFSI_GE_CH80; 2222 2223 switch (bw) { 2224 case RTW_CHANNEL_WIDTH_5: 2225 case RTW_CHANNEL_WIDTH_10: 2226 case RTW_CHANNEL_WIDTH_20: 2227 default: 2228 rf_reg18 |= RF18_BW_20M; 2229 rf_rxbb = 0x18; 2230 break; 2231 case RTW_CHANNEL_WIDTH_40: 2232 /* RF bandwidth */ 2233 rf_reg18 |= RF18_BW_40M; 2234 rf_rxbb = 0x10; 2235 break; 2236 case RTW_CHANNEL_WIDTH_80: 2237 rf_reg18 |= RF18_BW_80M; 2238 rf_rxbb = 0x8; 2239 break; 2240 } 2241 2242 rtw8822c_rstb_3wire(rtwdev, false); 2243 2244 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01); 2245 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12); 2246 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb); 2247 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00); 2248 2249 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01); 2250 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12); 2251 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb); 2252 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00); 2253 2254 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_reg18); 2255 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_reg18); 2256 2257 rtw8822c_rstb_3wire(rtwdev, true); 2258 } 2259 2260 static void rtw8822c_toggle_igi(struct rtw_dev *rtwdev) 2261 { 2262 u32 igi; 2263 2264 igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f); 2265 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2); 2266 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2); 2267 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi); 2268 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi); 2269 } 2270 2271 static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 2272 u8 primary_ch_idx) 2273 { 2274 if (IS_CH_2G_BAND(channel)) { 2275 rtw_write32_clr(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT); 2276 rtw_write32_set(rtwdev, REG_TXF4, BIT(20)); 2277 rtw_write32_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN); 2278 rtw_write32_clr(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN); 2279 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF); 2280 2281 switch (bw) { 2282 case RTW_CHANNEL_WIDTH_20: 2283 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK, 2284 0x5); 2285 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK, 2286 0x5); 2287 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 2288 0x6); 2289 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 2290 0x6); 2291 break; 2292 case RTW_CHANNEL_WIDTH_40: 2293 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK, 2294 0x4); 2295 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK, 2296 0x4); 2297 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 2298 0x0); 2299 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 2300 0x0); 2301 break; 2302 } 2303 if (channel == 13 || channel == 14) 2304 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969); 2305 else if (channel == 11 || channel == 12) 2306 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a); 2307 else 2308 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa); 2309 if (channel == 14) { 2310 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0); 2311 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD, 2312 0x4962c931); 2313 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3); 2314 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b); 2315 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7); 2316 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0); 2317 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD, 2318 0xff012455); 2319 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff); 2320 } else { 2321 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284); 2322 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD, 2323 0x3e18fec8); 2324 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88); 2325 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4); 2326 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2); 2327 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 2328 0x00faf0de); 2329 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD, 2330 0x00122344); 2331 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 2332 0x0fffffff); 2333 } 2334 if (channel == 13) 2335 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); 2336 else 2337 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1); 2338 } else if (IS_CH_5G_BAND(channel)) { 2339 rtw_write32_set(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN); 2340 rtw_write32_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN); 2341 rtw_write32_set(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT); 2342 rtw_write32_clr(rtwdev, REG_TXF4, BIT(20)); 2343 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22); 2344 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); 2345 if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) { 2346 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 2347 0x1); 2348 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 2349 0x1); 2350 } else if (IS_CH_5G_BAND_3(channel)) { 2351 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 2352 0x2); 2353 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 2354 0x2); 2355 } else if (IS_CH_5G_BAND_4(channel)) { 2356 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 2357 0x3); 2358 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 2359 0x3); 2360 } 2361 2362 if (channel >= 36 && channel <= 51) 2363 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494); 2364 else if (channel >= 52 && channel <= 55) 2365 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493); 2366 else if (channel >= 56 && channel <= 111) 2367 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453); 2368 else if (channel >= 112 && channel <= 119) 2369 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452); 2370 else if (channel >= 120 && channel <= 172) 2371 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412); 2372 else if (channel >= 173 && channel <= 177) 2373 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411); 2374 } 2375 2376 switch (bw) { 2377 case RTW_CHANNEL_WIDTH_20: 2378 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B); 2379 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 2380 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0); 2381 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7); 2382 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6); 2383 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 2384 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 2385 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 2386 break; 2387 case RTW_CHANNEL_WIDTH_40: 2388 rtw_write32_mask(rtwdev, REG_CCKSB, BIT(4), 2389 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0)); 2390 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5); 2391 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); 2392 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, 2393 (primary_ch_idx | (primary_ch_idx << 4))); 2394 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1); 2395 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 2396 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); 2397 break; 2398 case RTW_CHANNEL_WIDTH_80: 2399 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa); 2400 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); 2401 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, 2402 (primary_ch_idx | (primary_ch_idx << 4))); 2403 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6); 2404 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); 2405 break; 2406 case RTW_CHANNEL_WIDTH_5: 2407 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); 2408 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 2409 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1); 2410 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4); 2411 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4); 2412 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 2413 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 2414 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 2415 break; 2416 case RTW_CHANNEL_WIDTH_10: 2417 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); 2418 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 2419 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2); 2420 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6); 2421 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5); 2422 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 2423 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 2424 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 2425 break; 2426 } 2427 } 2428 2429 static void rtw8822c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 2430 u8 primary_chan_idx) 2431 { 2432 rtw8822c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 2433 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 2434 rtw8822c_set_channel_rf(rtwdev, channel, bw); 2435 rtw8822c_toggle_igi(rtwdev); 2436 } 2437 2438 static void rtw8822c_config_cck_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 2439 { 2440 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 2441 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0); 2442 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0); 2443 } else if (rx_path == BB_PATH_AB) { 2444 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1); 2445 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1); 2446 } 2447 2448 if (rx_path == BB_PATH_A) 2449 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0); 2450 else if (rx_path == BB_PATH_B) 2451 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5); 2452 else if (rx_path == BB_PATH_AB) 2453 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1); 2454 } 2455 2456 static void rtw8822c_config_ofdm_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 2457 { 2458 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 2459 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0); 2460 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0); 2461 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0); 2462 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0); 2463 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0); 2464 } else if (rx_path == BB_PATH_AB) { 2465 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1); 2466 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1); 2467 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1); 2468 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1); 2469 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1); 2470 } 2471 2472 rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path); 2473 rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path); 2474 } 2475 2476 static void rtw8822c_config_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 2477 { 2478 rtw8822c_config_cck_rx_path(rtwdev, rx_path); 2479 rtw8822c_config_ofdm_rx_path(rtwdev, rx_path); 2480 } 2481 2482 static void rtw8822c_config_cck_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 2483 bool is_tx2_path) 2484 { 2485 if (tx_path == BB_PATH_A) { 2486 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 2487 } else if (tx_path == BB_PATH_B) { 2488 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4); 2489 } else { 2490 if (is_tx2_path) 2491 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc); 2492 else 2493 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 2494 } 2495 rtw8822c_bb_reset(rtwdev); 2496 } 2497 2498 static void rtw8822c_config_ofdm_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 2499 enum rtw_bb_path tx_path_sel_1ss) 2500 { 2501 if (tx_path == BB_PATH_A) { 2502 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11); 2503 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); 2504 } else if (tx_path == BB_PATH_B) { 2505 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12); 2506 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); 2507 } else { 2508 if (tx_path_sel_1ss == BB_PATH_AB) { 2509 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33); 2510 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404); 2511 } else if (tx_path_sel_1ss == BB_PATH_B) { 2512 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x32); 2513 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400); 2514 } else if (tx_path_sel_1ss == BB_PATH_A) { 2515 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31); 2516 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400); 2517 } 2518 } 2519 rtw8822c_bb_reset(rtwdev); 2520 } 2521 2522 static void rtw8822c_config_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 2523 enum rtw_bb_path tx_path_sel_1ss, 2524 enum rtw_bb_path tx_path_cck, 2525 bool is_tx2_path) 2526 { 2527 rtw8822c_config_cck_tx_path(rtwdev, tx_path_cck, is_tx2_path); 2528 rtw8822c_config_ofdm_tx_path(rtwdev, tx_path, tx_path_sel_1ss); 2529 rtw8822c_bb_reset(rtwdev); 2530 } 2531 2532 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 2533 u8 rx_path, bool is_tx2_path) 2534 { 2535 if ((tx_path | rx_path) & BB_PATH_A) 2536 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312); 2537 else 2538 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111); 2539 if ((tx_path | rx_path) & BB_PATH_B) 2540 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312); 2541 else 2542 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111); 2543 2544 rtw8822c_config_rx_path(rtwdev, rx_path); 2545 rtw8822c_config_tx_path(rtwdev, tx_path, BB_PATH_A, BB_PATH_A, 2546 is_tx2_path); 2547 2548 rtw8822c_toggle_igi(rtwdev); 2549 } 2550 2551 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 2552 struct rtw_rx_pkt_stat *pkt_stat) 2553 { 2554 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2555 u8 l_bnd, u_bnd; 2556 u8 gain_a, gain_b; 2557 s8 rx_power[RTW_RF_PATH_MAX]; 2558 s8 min_rx_power = -120; 2559 u8 rssi; 2560 u8 channel; 2561 int path; 2562 2563 rx_power[RF_PATH_A] = GET_PHY_STAT_P0_PWDB_A(phy_status); 2564 rx_power[RF_PATH_B] = GET_PHY_STAT_P0_PWDB_B(phy_status); 2565 l_bnd = dm_info->cck_gi_l_bnd; 2566 u_bnd = dm_info->cck_gi_u_bnd; 2567 gain_a = GET_PHY_STAT_P0_GAIN_A(phy_status); 2568 gain_b = GET_PHY_STAT_P0_GAIN_B(phy_status); 2569 if (gain_a < l_bnd) 2570 rx_power[RF_PATH_A] += (l_bnd - gain_a) << 1; 2571 else if (gain_a > u_bnd) 2572 rx_power[RF_PATH_A] -= (gain_a - u_bnd) << 1; 2573 if (gain_b < l_bnd) 2574 rx_power[RF_PATH_B] += (l_bnd - gain_b) << 1; 2575 else if (gain_b > u_bnd) 2576 rx_power[RF_PATH_B] -= (gain_b - u_bnd) << 1; 2577 2578 rx_power[RF_PATH_A] -= 110; 2579 rx_power[RF_PATH_B] -= 110; 2580 2581 channel = GET_PHY_STAT_P0_CHANNEL(phy_status); 2582 if (channel == 0) 2583 channel = rtwdev->hal.current_channel; 2584 rtw_set_rx_freq_band(pkt_stat, channel); 2585 2586 pkt_stat->rx_power[RF_PATH_A] = rx_power[RF_PATH_A]; 2587 pkt_stat->rx_power[RF_PATH_B] = rx_power[RF_PATH_B]; 2588 2589 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { 2590 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1); 2591 dm_info->rssi[path] = rssi; 2592 } 2593 2594 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 2595 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 2596 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 2597 min_rx_power); 2598 } 2599 2600 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 2601 struct rtw_rx_pkt_stat *pkt_stat) 2602 { 2603 struct rtw_path_div *p_div = &rtwdev->dm_path_div; 2604 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2605 u8 rxsc, bw; 2606 s8 min_rx_power = -120; 2607 s8 rx_evm; 2608 u8 evm_dbm = 0; 2609 u8 rssi; 2610 int path; 2611 u8 channel; 2612 2613 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 2614 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 2615 else 2616 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 2617 2618 if (rxsc >= 9 && rxsc <= 12) 2619 bw = RTW_CHANNEL_WIDTH_40; 2620 else if (rxsc >= 13) 2621 bw = RTW_CHANNEL_WIDTH_80; 2622 else 2623 bw = RTW_CHANNEL_WIDTH_20; 2624 2625 channel = GET_PHY_STAT_P1_CHANNEL(phy_status); 2626 rtw_set_rx_freq_band(pkt_stat, channel); 2627 2628 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 2629 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110; 2630 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2); 2631 pkt_stat->bw = bw; 2632 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A], 2633 pkt_stat->rx_power[RF_PATH_B], 2634 min_rx_power); 2635 2636 dm_info->curr_rx_rate = pkt_stat->rate; 2637 2638 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status); 2639 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status); 2640 2641 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status); 2642 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status); 2643 2644 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status); 2645 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status); 2646 2647 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { 2648 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1); 2649 dm_info->rssi[path] = rssi; 2650 if (path == RF_PATH_A) { 2651 p_div->path_a_sum += rssi; 2652 p_div->path_a_cnt++; 2653 } else if (path == RF_PATH_B) { 2654 p_div->path_b_sum += rssi; 2655 p_div->path_b_cnt++; 2656 } 2657 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1; 2658 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1; 2659 2660 rx_evm = pkt_stat->rx_evm[path]; 2661 2662 if (rx_evm < 0) { 2663 if (rx_evm == S8_MIN) 2664 evm_dbm = 0; 2665 else 2666 evm_dbm = ((u8)-rx_evm >> 1); 2667 } 2668 dm_info->rx_evm_dbm[path] = evm_dbm; 2669 } 2670 rtw_phy_parsing_cfo(rtwdev, pkt_stat); 2671 } 2672 2673 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 2674 struct rtw_rx_pkt_stat *pkt_stat) 2675 { 2676 u8 page; 2677 2678 page = *phy_status & 0xf; 2679 2680 switch (page) { 2681 case 0: 2682 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 2683 break; 2684 case 1: 2685 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 2686 break; 2687 default: 2688 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 2689 return; 2690 } 2691 } 2692 2693 static void rtw8822c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 2694 struct rtw_rx_pkt_stat *pkt_stat, 2695 struct ieee80211_rx_status *rx_status) 2696 { 2697 struct ieee80211_hdr *hdr; 2698 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 2699 u8 *phy_status = NULL; 2700 2701 memset(pkt_stat, 0, sizeof(*pkt_stat)); 2702 2703 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 2704 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 2705 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 2706 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && 2707 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; 2708 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 2709 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 2710 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 2711 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 2712 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 2713 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 2714 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 2715 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 2716 2717 /* drv_info_sz is in unit of 8-bytes */ 2718 pkt_stat->drv_info_sz *= 8; 2719 2720 /* c2h cmd pkt's rx/phy status is not interested */ 2721 if (pkt_stat->is_c2h) 2722 return; 2723 2724 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 2725 pkt_stat->drv_info_sz); 2726 pkt_stat->hdr = hdr; 2727 if (pkt_stat->phy_status) { 2728 phy_status = rx_desc + desc_sz + pkt_stat->shift; 2729 query_phy_status(rtwdev, phy_status, pkt_stat); 2730 } 2731 2732 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 2733 } 2734 2735 static void 2736 rtw8822c_set_write_tx_power_ref(struct rtw_dev *rtwdev, u8 *tx_pwr_ref_cck, 2737 u8 *tx_pwr_ref_ofdm) 2738 { 2739 struct rtw_hal *hal = &rtwdev->hal; 2740 u32 txref_cck[2] = {0x18a0, 0x41a0}; 2741 u32 txref_ofdm[2] = {0x18e8, 0x41e8}; 2742 u8 path; 2743 2744 for (path = 0; path < hal->rf_path_num; path++) { 2745 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); 2746 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000, 2747 tx_pwr_ref_cck[path]); 2748 } 2749 for (path = 0; path < hal->rf_path_num; path++) { 2750 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); 2751 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00, 2752 tx_pwr_ref_ofdm[path]); 2753 } 2754 } 2755 2756 static void rtw8822c_set_tx_power_diff(struct rtw_dev *rtwdev, u8 rate, 2757 s8 *diff_idx) 2758 { 2759 u32 offset_txagc = 0x3a00; 2760 u8 rate_idx = rate & 0xfc; 2761 u8 pwr_idx[4]; 2762 u32 phy_pwr_idx; 2763 int i; 2764 2765 for (i = 0; i < 4; i++) 2766 pwr_idx[i] = diff_idx[i] & 0x7f; 2767 2768 phy_pwr_idx = pwr_idx[0] | 2769 (pwr_idx[1] << 8) | 2770 (pwr_idx[2] << 16) | 2771 (pwr_idx[3] << 24); 2772 2773 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0); 2774 rtw_write32_mask(rtwdev, offset_txagc + rate_idx, MASKDWORD, 2775 phy_pwr_idx); 2776 } 2777 2778 static void rtw8822c_set_tx_power_index(struct rtw_dev *rtwdev) 2779 { 2780 struct rtw_hal *hal = &rtwdev->hal; 2781 u8 rs, rate, j; 2782 u8 pwr_ref_cck[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATE11M], 2783 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATE11M]}; 2784 u8 pwr_ref_ofdm[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATEMCS7], 2785 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATEMCS7]}; 2786 s8 diff_a, diff_b; 2787 u8 pwr_a, pwr_b; 2788 s8 diff_idx[4]; 2789 2790 rtw8822c_set_write_tx_power_ref(rtwdev, pwr_ref_cck, pwr_ref_ofdm); 2791 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { 2792 for (j = 0; j < rtw_rate_size[rs]; j++) { 2793 rate = rtw_rate_section[rs][j]; 2794 pwr_a = hal->tx_pwr_tbl[RF_PATH_A][rate]; 2795 pwr_b = hal->tx_pwr_tbl[RF_PATH_B][rate]; 2796 if (rs == 0) { 2797 diff_a = (s8)pwr_a - (s8)pwr_ref_cck[0]; 2798 diff_b = (s8)pwr_b - (s8)pwr_ref_cck[1]; 2799 } else { 2800 diff_a = (s8)pwr_a - (s8)pwr_ref_ofdm[0]; 2801 diff_b = (s8)pwr_b - (s8)pwr_ref_ofdm[1]; 2802 } 2803 diff_idx[rate % 4] = min(diff_a, diff_b); 2804 if (rate % 4 == 3) 2805 rtw8822c_set_tx_power_diff(rtwdev, rate - 3, 2806 diff_idx); 2807 } 2808 } 2809 } 2810 2811 static int rtw8822c_set_antenna(struct rtw_dev *rtwdev, 2812 u32 antenna_tx, 2813 u32 antenna_rx) 2814 { 2815 struct rtw_hal *hal = &rtwdev->hal; 2816 2817 switch (antenna_tx) { 2818 case BB_PATH_A: 2819 case BB_PATH_B: 2820 case BB_PATH_AB: 2821 break; 2822 default: 2823 rtw_warn(rtwdev, "unsupported tx path 0x%x\n", antenna_tx); 2824 return -EINVAL; 2825 } 2826 2827 /* path B only is not available for RX */ 2828 switch (antenna_rx) { 2829 case BB_PATH_A: 2830 case BB_PATH_AB: 2831 break; 2832 default: 2833 rtw_warn(rtwdev, "unsupported rx path 0x%x\n", antenna_rx); 2834 return -EINVAL; 2835 } 2836 2837 hal->antenna_tx = antenna_tx; 2838 hal->antenna_rx = antenna_rx; 2839 2840 rtw8822c_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false); 2841 2842 return 0; 2843 } 2844 2845 static void rtw8822c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 2846 { 2847 u8 ldo_pwr; 2848 2849 ldo_pwr = rtw_read8(rtwdev, REG_ANAPARLDO_POW_MAC); 2850 ldo_pwr = enable ? ldo_pwr | BIT_LDOE25_PON : ldo_pwr & ~BIT_LDOE25_PON; 2851 rtw_write8(rtwdev, REG_ANAPARLDO_POW_MAC, ldo_pwr); 2852 } 2853 2854 static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev) 2855 { 2856 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2857 u32 cck_enable; 2858 u32 cck_fa_cnt; 2859 u32 crc32_cnt; 2860 u32 cca32_cnt; 2861 u32 ofdm_fa_cnt; 2862 u32 ofdm_fa_cnt1, ofdm_fa_cnt2, ofdm_fa_cnt3, ofdm_fa_cnt4, ofdm_fa_cnt5; 2863 u16 parity_fail, rate_illegal, crc8_fail, mcs_fail, sb_search_fail, 2864 fast_fsync, crc8_fail_vhta, mcs_fail_vht; 2865 2866 cck_enable = rtw_read32(rtwdev, REG_ENCCK) & BIT_CCK_BLK_EN; 2867 cck_fa_cnt = rtw_read16(rtwdev, REG_CCK_FACNT); 2868 2869 ofdm_fa_cnt1 = rtw_read32(rtwdev, REG_OFDM_FACNT1); 2870 ofdm_fa_cnt2 = rtw_read32(rtwdev, REG_OFDM_FACNT2); 2871 ofdm_fa_cnt3 = rtw_read32(rtwdev, REG_OFDM_FACNT3); 2872 ofdm_fa_cnt4 = rtw_read32(rtwdev, REG_OFDM_FACNT4); 2873 ofdm_fa_cnt5 = rtw_read32(rtwdev, REG_OFDM_FACNT5); 2874 2875 parity_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt1); 2876 rate_illegal = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt2); 2877 crc8_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt2); 2878 crc8_fail_vhta = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt3); 2879 mcs_fail = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt4); 2880 mcs_fail_vht = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt4); 2881 fast_fsync = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt5); 2882 sb_search_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt5); 2883 2884 ofdm_fa_cnt = parity_fail + rate_illegal + crc8_fail + crc8_fail_vhta + 2885 mcs_fail + mcs_fail_vht + fast_fsync + sb_search_fail; 2886 2887 dm_info->cck_fa_cnt = cck_fa_cnt; 2888 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 2889 dm_info->total_fa_cnt = ofdm_fa_cnt; 2890 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; 2891 2892 crc32_cnt = rtw_read32(rtwdev, 0x2c04); 2893 dm_info->cck_ok_cnt = crc32_cnt & 0xffff; 2894 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2895 crc32_cnt = rtw_read32(rtwdev, 0x2c14); 2896 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff; 2897 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2898 crc32_cnt = rtw_read32(rtwdev, 0x2c10); 2899 dm_info->ht_ok_cnt = crc32_cnt & 0xffff; 2900 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2901 crc32_cnt = rtw_read32(rtwdev, 0x2c0c); 2902 dm_info->vht_ok_cnt = crc32_cnt & 0xffff; 2903 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2904 2905 cca32_cnt = rtw_read32(rtwdev, 0x2c08); 2906 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16); 2907 dm_info->cck_cca_cnt = cca32_cnt & 0xffff; 2908 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 2909 if (cck_enable) 2910 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 2911 2912 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0); 2913 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 2); 2914 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0); 2915 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 2); 2916 2917 /* disable rx clk gating to reset counters */ 2918 rtw_write32_clr(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN); 2919 rtw_write32_set(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST); 2920 rtw_write32_clr(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST); 2921 rtw_write32_set(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN); 2922 } 2923 2924 static void rtw8822c_do_lck(struct rtw_dev *rtwdev) 2925 { 2926 u32 val; 2927 2928 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_CTRL, RFREG_MASK, 0x80010); 2929 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0FA); 2930 fsleep(1); 2931 rtw_write_rf(rtwdev, RF_PATH_A, RF_AAC_CTRL, RFREG_MASK, 0x80000); 2932 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_AAC, RFREG_MASK, 0x80001); 2933 read_poll_timeout(rtw_read_rf, val, val != 0x1, 1000, 100000, 2934 true, rtwdev, RF_PATH_A, RF_AAC_CTRL, 0x1000); 2935 rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0F8); 2936 rtw_write_rf(rtwdev, RF_PATH_B, RF_SYN_CTRL, RFREG_MASK, 0x80010); 2937 2938 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000); 2939 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x4f000); 2940 fsleep(1); 2941 rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000); 2942 } 2943 2944 static void rtw8822c_do_iqk(struct rtw_dev *rtwdev) 2945 { 2946 struct rtw_iqk_para para = {0}; 2947 u8 iqk_chk; 2948 int ret; 2949 2950 para.clear = 1; 2951 rtw_fw_do_iqk(rtwdev, ¶); 2952 2953 ret = read_poll_timeout(rtw_read8, iqk_chk, iqk_chk == IQK_DONE_8822C, 2954 20000, 300000, false, rtwdev, REG_RPT_CIP); 2955 if (ret) 2956 rtw_warn(rtwdev, "failed to poll iqk status bit\n"); 2957 2958 rtw_write8(rtwdev, REG_IQKSTAT, 0x0); 2959 } 2960 2961 /* for coex */ 2962 static void rtw8822c_coex_cfg_init(struct rtw_dev *rtwdev) 2963 { 2964 /* enable TBTT nterrupt */ 2965 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 2966 2967 /* BT report packet sample rate */ 2968 /* 0x790[5:0]=0x5 */ 2969 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); 2970 2971 /* enable BT counter statistics */ 2972 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); 2973 2974 /* enable PTA (3-wire function form BT side) */ 2975 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 2976 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); 2977 2978 /* enable PTA (tx/rx signal form WiFi side) */ 2979 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 2980 /* wl tx signal to PTA not case EDCCA */ 2981 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); 2982 /* GNT_BT=1 while select both */ 2983 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); 2984 /* BT_CCA = ~GNT_WL_BB, not or GNT_BT_BB, LTE_Rx */ 2985 rtw_write8_clr(rtwdev, REG_DUMMY_PAGE4_V1, BIT_BTCCA_CTRL); 2986 2987 /* to avoid RF parameter error */ 2988 rtw_write_rf(rtwdev, RF_PATH_B, RF_MODOPT, 0xfffff, 0x40000); 2989 } 2990 2991 static void rtw8822c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 2992 { 2993 struct rtw_coex *coex = &rtwdev->coex; 2994 struct rtw_coex_stat *coex_stat = &coex->stat; 2995 struct rtw_efuse *efuse = &rtwdev->efuse; 2996 u32 rf_0x1; 2997 2998 if (coex_stat->gnt_workaround_state == coex_stat->wl_coex_mode) 2999 return; 3000 3001 coex_stat->gnt_workaround_state = coex_stat->wl_coex_mode; 3002 3003 if ((coex_stat->kt_ver == 0 && coex->under_5g) || coex->freerun) 3004 rf_0x1 = 0x40021; 3005 else 3006 rf_0x1 = 0x40000; 3007 3008 /* BT at S1 for Shared-Ant */ 3009 if (efuse->share_ant) 3010 rf_0x1 |= BIT(13); 3011 3012 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1); 3013 3014 /* WL-S0 2G RF TRX cannot be masked by GNT_BT 3015 * enable "WLS0 BB chage RF mode if GNT_BT = 1" for shared-antenna type 3016 * disable:0x1860[3] = 1, enable:0x1860[3] = 0 3017 * 3018 * enable "DAC off if GNT_WL = 0" for non-shared-antenna 3019 * disable 0x1c30[22] = 0, 3020 * enable: 0x1c30[22] = 1, 0x1c38[12] = 0, 0x1c38[28] = 1 3021 */ 3022 if (coex_stat->wl_coex_mode == COEX_WLINK_2GFREE) { 3023 rtw_write8_mask(rtwdev, REG_ANAPAR + 2, 3024 BIT_ANAPAR_BTPS >> 16, 0); 3025 } else { 3026 rtw_write8_mask(rtwdev, REG_ANAPAR + 2, 3027 BIT_ANAPAR_BTPS >> 16, 1); 3028 rtw_write8_mask(rtwdev, REG_RSTB_SEL + 1, 3029 BIT_DAC_OFF_ENABLE, 0); 3030 rtw_write8_mask(rtwdev, REG_RSTB_SEL + 3, 3031 BIT_DAC_OFF_ENABLE, 1); 3032 } 3033 3034 /* disable WL-S1 BB chage RF mode if GNT_BT 3035 * since RF TRx mask can do it 3036 */ 3037 rtw_write8_mask(rtwdev, REG_IGN_GNTBT4, 3038 BIT_PI_IGNORE_GNT_BT, 1); 3039 3040 /* disable WL-S0 BB chage RF mode if wifi is at 5G, 3041 * or antenna path is separated 3042 */ 3043 if (coex_stat->wl_coex_mode == COEX_WLINK_2GFREE) { 3044 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1, 3045 BIT_PI_IGNORE_GNT_BT, 1); 3046 rtw_write8_mask(rtwdev, REG_NOMASK_TXBT, 3047 BIT_NOMASK_TXBT_ENABLE, 1); 3048 } else if (coex_stat->wl_coex_mode == COEX_WLINK_5G || 3049 coex->under_5g || !efuse->share_ant) { 3050 if (coex_stat->kt_ver >= 3) { 3051 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1, 3052 BIT_PI_IGNORE_GNT_BT, 0); 3053 rtw_write8_mask(rtwdev, REG_NOMASK_TXBT, 3054 BIT_NOMASK_TXBT_ENABLE, 1); 3055 } else { 3056 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1, 3057 BIT_PI_IGNORE_GNT_BT, 1); 3058 } 3059 } else { 3060 /* shared-antenna */ 3061 rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1, 3062 BIT_PI_IGNORE_GNT_BT, 0); 3063 if (coex_stat->kt_ver >= 3) { 3064 rtw_write8_mask(rtwdev, REG_NOMASK_TXBT, 3065 BIT_NOMASK_TXBT_ENABLE, 0); 3066 } 3067 } 3068 } 3069 3070 static void rtw8822c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 3071 { 3072 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0); 3073 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0); 3074 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0); 3075 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0); 3076 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0); 3077 } 3078 3079 static void rtw8822c_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 3080 { 3081 struct rtw_coex *coex = &rtwdev->coex; 3082 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 3083 struct rtw_efuse *efuse = &rtwdev->efuse; 3084 3085 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; 3086 coex_rfe->ant_switch_polarity = 0; 3087 coex_rfe->ant_switch_exist = false; 3088 coex_rfe->ant_switch_with_bt = false; 3089 coex_rfe->ant_switch_diversity = false; 3090 3091 if (efuse->share_ant) 3092 coex_rfe->wlg_at_btg = true; 3093 else 3094 coex_rfe->wlg_at_btg = false; 3095 3096 /* disable LTE coex in wifi side */ 3097 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0); 3098 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); 3099 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); 3100 } 3101 3102 static void rtw8822c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 3103 { 3104 struct rtw_coex *coex = &rtwdev->coex; 3105 struct rtw_coex_dm *coex_dm = &coex->dm; 3106 3107 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 3108 return; 3109 3110 coex_dm->cur_wl_pwr_lvl = wl_pwr; 3111 } 3112 3113 static void rtw8822c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 3114 { 3115 struct rtw_coex *coex = &rtwdev->coex; 3116 struct rtw_coex_dm *coex_dm = &coex->dm; 3117 3118 if (low_gain == coex_dm->cur_wl_rx_low_gain_en) 3119 return; 3120 3121 coex_dm->cur_wl_rx_low_gain_en = low_gain; 3122 3123 if (coex_dm->cur_wl_rx_low_gain_en) { 3124 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table On!\n"); 3125 3126 /* set Rx filter corner RCK offset */ 3127 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x22); 3128 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x36); 3129 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x22); 3130 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x36); 3131 3132 } else { 3133 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table Off!\n"); 3134 3135 /* set Rx filter corner RCK offset */ 3136 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x20); 3137 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x0); 3138 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x20); 3139 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x0); 3140 } 3141 } 3142 3143 static void rtw8822c_bf_enable_bfee_su(struct rtw_dev *rtwdev, 3144 struct rtw_vif *vif, 3145 struct rtw_bfee *bfee) 3146 { 3147 u8 csi_rsc = 0; 3148 u32 tmp6dc; 3149 3150 rtw_bf_enable_bfee_su(rtwdev, vif, bfee); 3151 3152 tmp6dc = rtw_read32(rtwdev, REG_BBPSF_CTRL) | 3153 BIT_WMAC_USE_NDPARATE | 3154 (csi_rsc << 13); 3155 if (vif->net_type == RTW_NET_AP_MODE) 3156 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc | BIT(12)); 3157 else 3158 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc & ~BIT(12)); 3159 3160 rtw_write32(rtwdev, REG_CSI_RRSR, 0x550); 3161 } 3162 3163 static void rtw8822c_bf_config_bfee_su(struct rtw_dev *rtwdev, 3164 struct rtw_vif *vif, 3165 struct rtw_bfee *bfee, bool enable) 3166 { 3167 if (enable) 3168 rtw8822c_bf_enable_bfee_su(rtwdev, vif, bfee); 3169 else 3170 rtw_bf_remove_bfee_su(rtwdev, bfee); 3171 } 3172 3173 static void rtw8822c_bf_config_bfee_mu(struct rtw_dev *rtwdev, 3174 struct rtw_vif *vif, 3175 struct rtw_bfee *bfee, bool enable) 3176 { 3177 if (enable) 3178 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee); 3179 else 3180 rtw_bf_remove_bfee_mu(rtwdev, bfee); 3181 } 3182 3183 static void rtw8822c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif, 3184 struct rtw_bfee *bfee, bool enable) 3185 { 3186 if (bfee->role == RTW_BFEE_SU) 3187 rtw8822c_bf_config_bfee_su(rtwdev, vif, bfee, enable); 3188 else if (bfee->role == RTW_BFEE_MU) 3189 rtw8822c_bf_config_bfee_mu(rtwdev, vif, bfee, enable); 3190 else 3191 rtw_warn(rtwdev, "wrong bfee role\n"); 3192 } 3193 3194 struct dpk_cfg_pair { 3195 u32 addr; 3196 u32 bitmask; 3197 u32 data; 3198 }; 3199 3200 void rtw8822c_parse_tbl_dpk(struct rtw_dev *rtwdev, 3201 const struct rtw_table *tbl) 3202 { 3203 const struct dpk_cfg_pair *p = tbl->data; 3204 const struct dpk_cfg_pair *end = p + tbl->size / 3; 3205 3206 BUILD_BUG_ON(sizeof(struct dpk_cfg_pair) != sizeof(u32) * 3); 3207 3208 for (; p < end; p++) 3209 rtw_write32_mask(rtwdev, p->addr, p->bitmask, p->data); 3210 } 3211 3212 static void rtw8822c_dpk_set_gnt_wl(struct rtw_dev *rtwdev, bool is_before_k) 3213 { 3214 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3215 3216 if (is_before_k) { 3217 dpk_info->gnt_control = rtw_read32(rtwdev, 0x70); 3218 dpk_info->gnt_value = rtw_coex_read_indirect_reg(rtwdev, 0x38); 3219 rtw_write32_mask(rtwdev, 0x70, BIT(26), 0x1); 3220 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKBYTE1, 0x77); 3221 } else { 3222 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKDWORD, 3223 dpk_info->gnt_value); 3224 rtw_write32(rtwdev, 0x70, dpk_info->gnt_control); 3225 } 3226 } 3227 3228 static void 3229 rtw8822c_dpk_restore_registers(struct rtw_dev *rtwdev, u32 reg_num, 3230 struct rtw_backup_info *bckp) 3231 { 3232 rtw_restore_reg(rtwdev, bckp, reg_num); 3233 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3234 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0x4); 3235 } 3236 3237 static void 3238 rtw8822c_dpk_backup_registers(struct rtw_dev *rtwdev, u32 *reg, 3239 u32 reg_num, struct rtw_backup_info *bckp) 3240 { 3241 u32 i; 3242 3243 for (i = 0; i < reg_num; i++) { 3244 bckp[i].len = 4; 3245 bckp[i].reg = reg[i]; 3246 bckp[i].val = rtw_read32(rtwdev, reg[i]); 3247 } 3248 } 3249 3250 static void rtw8822c_dpk_backup_rf_registers(struct rtw_dev *rtwdev, 3251 u32 *rf_reg, 3252 u32 rf_reg_bak[][2]) 3253 { 3254 u32 i; 3255 3256 for (i = 0; i < DPK_RF_REG_NUM; i++) { 3257 rf_reg_bak[i][RF_PATH_A] = rtw_read_rf(rtwdev, RF_PATH_A, 3258 rf_reg[i], RFREG_MASK); 3259 rf_reg_bak[i][RF_PATH_B] = rtw_read_rf(rtwdev, RF_PATH_B, 3260 rf_reg[i], RFREG_MASK); 3261 } 3262 } 3263 3264 static void rtw8822c_dpk_reload_rf_registers(struct rtw_dev *rtwdev, 3265 u32 *rf_reg, 3266 u32 rf_reg_bak[][2]) 3267 { 3268 u32 i; 3269 3270 for (i = 0; i < DPK_RF_REG_NUM; i++) { 3271 rtw_write_rf(rtwdev, RF_PATH_A, rf_reg[i], RFREG_MASK, 3272 rf_reg_bak[i][RF_PATH_A]); 3273 rtw_write_rf(rtwdev, RF_PATH_B, rf_reg[i], RFREG_MASK, 3274 rf_reg_bak[i][RF_PATH_B]); 3275 } 3276 } 3277 3278 static void rtw8822c_dpk_information(struct rtw_dev *rtwdev) 3279 { 3280 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3281 u32 reg; 3282 u8 band_shift; 3283 3284 #if defined(__linux__) 3285 reg = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 3286 #elif defined(__FreeBSD__) 3287 reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK); 3288 #endif 3289 3290 band_shift = FIELD_GET(BIT(16), reg); 3291 dpk_info->dpk_band = 1 << band_shift; 3292 dpk_info->dpk_ch = FIELD_GET(0xff, reg); 3293 dpk_info->dpk_bw = FIELD_GET(0x3000, reg); 3294 } 3295 3296 static void rtw8822c_dpk_rxbb_dc_cal(struct rtw_dev *rtwdev, u8 path) 3297 { 3298 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800); 3299 udelay(5); 3300 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84801); 3301 usleep_range(600, 610); 3302 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800); 3303 } 3304 3305 static u8 rtw8822c_dpk_dc_corr_check(struct rtw_dev *rtwdev, u8 path) 3306 { 3307 u16 dc_i, dc_q; 3308 u8 corr_idx; 3309 3310 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000900f0); 3311 dc_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16)); 3312 dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0)); 3313 3314 if (dc_i & BIT(11)) 3315 dc_i = 0x1000 - dc_i; 3316 if (dc_q & BIT(11)) 3317 dc_q = 0x1000 - dc_q; 3318 3319 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 3320 corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0)); 3321 rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(15, 8)); 3322 3323 if (dc_i > 200 || dc_q > 200 || corr_idx < 40 || corr_idx > 65) 3324 return 1; 3325 else 3326 return 0; 3327 3328 } 3329 3330 static void rtw8822c_dpk_tx_pause(struct rtw_dev *rtwdev) 3331 { 3332 u8 reg_a, reg_b; 3333 u16 count = 0; 3334 3335 rtw_write8(rtwdev, 0x522, 0xff); 3336 rtw_write32_mask(rtwdev, 0x1e70, 0xf, 0x2); 3337 3338 do { 3339 reg_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 0x00, 0xf0000); 3340 reg_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 0x00, 0xf0000); 3341 udelay(2); 3342 count++; 3343 } while ((reg_a == 2 || reg_b == 2) && count < 2500); 3344 } 3345 3346 static void rtw8822c_dpk_mac_bb_setting(struct rtw_dev *rtwdev) 3347 { 3348 rtw8822c_dpk_tx_pause(rtwdev); 3349 rtw_load_table(rtwdev, &rtw8822c_dpk_mac_bb_tbl); 3350 } 3351 3352 static void rtw8822c_dpk_afe_setting(struct rtw_dev *rtwdev, bool is_do_dpk) 3353 { 3354 if (is_do_dpk) 3355 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_is_dpk_tbl); 3356 else 3357 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_no_dpk_tbl); 3358 } 3359 3360 static void rtw8822c_dpk_pre_setting(struct rtw_dev *rtwdev) 3361 { 3362 u8 path; 3363 3364 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 3365 rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0); 3366 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1)); 3367 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) 3368 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000); 3369 else 3370 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000); 3371 rtw_write32_mask(rtwdev, REG_DPD_LUT0, BIT_GLOSS_DB, 0x4); 3372 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x3); 3373 } 3374 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3375 rtw_write32(rtwdev, REG_DPD_CTL11, 0x3b23170b); 3376 rtw_write32(rtwdev, REG_DPD_CTL12, 0x775f5347); 3377 } 3378 3379 static u32 rtw8822c_dpk_rf_setting(struct rtw_dev *rtwdev, u8 path) 3380 { 3381 u32 ori_txbb; 3382 3383 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50017); 3384 ori_txbb = rtw_read_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK); 3385 3386 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1); 3387 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1); 3388 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_BB_GAIN, 0x0); 3389 rtw_write_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK, ori_txbb); 3390 3391 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) { 3392 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x1); 3393 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0); 3394 } else { 3395 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0); 3396 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x6); 3397 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1); 3398 rtw_write_rf(rtwdev, path, RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0); 3399 } 3400 3401 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf); 3402 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1); 3403 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0); 3404 3405 if (rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80) 3406 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x2); 3407 else 3408 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1); 3409 3410 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT(1), 0x1); 3411 3412 usleep_range(100, 110); 3413 3414 return ori_txbb & 0x1f; 3415 } 3416 3417 static u16 rtw8822c_dpk_get_cmd(struct rtw_dev *rtwdev, u8 action, u8 path) 3418 { 3419 u16 cmd; 3420 u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0; 3421 3422 switch (action) { 3423 case RTW_DPK_GAIN_LOSS: 3424 cmd = 0x14 + path; 3425 break; 3426 case RTW_DPK_DO_DPK: 3427 cmd = 0x16 + path + bw; 3428 break; 3429 case RTW_DPK_DPK_ON: 3430 cmd = 0x1a + path; 3431 break; 3432 case RTW_DPK_DAGC: 3433 cmd = 0x1c + path + bw; 3434 break; 3435 default: 3436 return 0; 3437 } 3438 3439 return (cmd << 8) | 0x48; 3440 } 3441 3442 static u8 rtw8822c_dpk_one_shot(struct rtw_dev *rtwdev, u8 path, u8 action) 3443 { 3444 u16 dpk_cmd; 3445 u8 result = 0; 3446 3447 rtw8822c_dpk_set_gnt_wl(rtwdev, true); 3448 3449 if (action == RTW_DPK_CAL_PWR) { 3450 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x1); 3451 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x0); 3452 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0); 3453 msleep(10); 3454 if (!check_hw_ready(rtwdev, REG_STAT_RPT, BIT(31), 0x1)) { 3455 result = 1; 3456 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n"); 3457 } 3458 } else { 3459 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 3460 0x8 | (path << 1)); 3461 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9); 3462 3463 dpk_cmd = rtw8822c_dpk_get_cmd(rtwdev, action, path); 3464 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd); 3465 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd + 1); 3466 msleep(10); 3467 if (!check_hw_ready(rtwdev, 0x2d9c, 0xff, 0x55)) { 3468 result = 1; 3469 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n"); 3470 } 3471 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 3472 0x8 | (path << 1)); 3473 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0); 3474 } 3475 3476 rtw8822c_dpk_set_gnt_wl(rtwdev, false); 3477 3478 rtw_write8(rtwdev, 0x1b10, 0x0); 3479 3480 return result; 3481 } 3482 3483 static u16 rtw8822c_dpk_dgain_read(struct rtw_dev *rtwdev, u8 path) 3484 { 3485 u16 dgain; 3486 3487 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3488 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, 0x00ff0000, 0x0); 3489 3490 dgain = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16)); 3491 3492 return dgain; 3493 } 3494 3495 static u8 rtw8822c_dpk_thermal_read(struct rtw_dev *rtwdev, u8 path) 3496 { 3497 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1); 3498 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x0); 3499 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1); 3500 udelay(15); 3501 3502 return (u8)rtw_read_rf(rtwdev, path, RF_T_METER, 0x0007e); 3503 } 3504 3505 static u32 rtw8822c_dpk_pas_read(struct rtw_dev *rtwdev, u8 path) 3506 { 3507 u32 i_val, q_val; 3508 3509 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1)); 3510 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0); 3511 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060001); 3512 rtw_write32(rtwdev, 0x1b4c, 0x00000000); 3513 rtw_write32(rtwdev, 0x1b4c, 0x00080000); 3514 3515 q_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD); 3516 i_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD); 3517 3518 if (i_val & BIT(15)) 3519 i_val = 0x10000 - i_val; 3520 if (q_val & BIT(15)) 3521 q_val = 0x10000 - q_val; 3522 3523 rtw_write32(rtwdev, 0x1b4c, 0x00000000); 3524 3525 return i_val * i_val + q_val * q_val; 3526 } 3527 3528 static u32 rtw8822c_psd_log2base(u32 val) 3529 { 3530 u32 tmp, val_integerd_b, tindex; 3531 u32 result, val_fractiond_b; 3532 u32 table_fraction[21] = {0, 432, 332, 274, 232, 200, 174, 3533 151, 132, 115, 100, 86, 74, 62, 51, 3534 42, 32, 23, 15, 7, 0}; 3535 3536 if (val == 0) 3537 return 0; 3538 3539 val_integerd_b = __fls(val) + 1; 3540 3541 tmp = (val * 100) / (1 << val_integerd_b); 3542 tindex = tmp / 5; 3543 3544 if (tindex >= ARRAY_SIZE(table_fraction)) 3545 tindex = ARRAY_SIZE(table_fraction) - 1; 3546 3547 val_fractiond_b = table_fraction[tindex]; 3548 3549 result = val_integerd_b * 100 - val_fractiond_b; 3550 3551 return result; 3552 } 3553 3554 static u8 rtw8822c_dpk_gainloss_result(struct rtw_dev *rtwdev, u8 path) 3555 { 3556 u8 result; 3557 3558 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3559 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x1); 3560 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060000); 3561 3562 result = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, 0x000000f0); 3563 3564 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0); 3565 3566 return result; 3567 } 3568 3569 static u8 rtw8822c_dpk_agc_gain_chk(struct rtw_dev *rtwdev, u8 path, 3570 u8 limited_pga) 3571 { 3572 u8 result = 0; 3573 u16 dgain; 3574 3575 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 3576 dgain = rtw8822c_dpk_dgain_read(rtwdev, path); 3577 3578 if (dgain > 1535 && !limited_pga) 3579 return RTW_DPK_GAIN_LESS; 3580 else if (dgain < 768 && !limited_pga) 3581 return RTW_DPK_GAIN_LARGE; 3582 else 3583 return result; 3584 } 3585 3586 static u8 rtw8822c_dpk_agc_loss_chk(struct rtw_dev *rtwdev, u8 path) 3587 { 3588 u32 loss, loss_db; 3589 3590 loss = rtw8822c_dpk_pas_read(rtwdev, path); 3591 if (loss < 0x4000000) 3592 return RTW_DPK_GL_LESS; 3593 loss_db = 3 * rtw8822c_psd_log2base(loss >> 13) - 3870; 3594 3595 if (loss_db > 1000) 3596 return RTW_DPK_GL_LARGE; 3597 else if (loss_db < 250) 3598 return RTW_DPK_GL_LESS; 3599 else 3600 return RTW_DPK_AGC_OUT; 3601 } 3602 3603 struct rtw8822c_dpk_data { 3604 u8 txbb; 3605 u8 pga; 3606 u8 limited_pga; 3607 u8 agc_cnt; 3608 bool loss_only; 3609 bool gain_only; 3610 u8 path; 3611 }; 3612 3613 static u8 rtw8822c_gain_check_state(struct rtw_dev *rtwdev, 3614 struct rtw8822c_dpk_data *data) 3615 { 3616 u8 state; 3617 3618 data->txbb = (u8)rtw_read_rf(rtwdev, data->path, RF_TX_GAIN, 3619 BIT_GAIN_TXBB); 3620 data->pga = (u8)rtw_read_rf(rtwdev, data->path, RF_MODE_TRXAGC, 3621 BIT_RXAGC); 3622 3623 if (data->loss_only) { 3624 state = RTW_DPK_LOSS_CHECK; 3625 goto check_end; 3626 } 3627 3628 state = rtw8822c_dpk_agc_gain_chk(rtwdev, data->path, 3629 data->limited_pga); 3630 if (state == RTW_DPK_GAIN_CHECK && data->gain_only) 3631 state = RTW_DPK_AGC_OUT; 3632 else if (state == RTW_DPK_GAIN_CHECK) 3633 state = RTW_DPK_LOSS_CHECK; 3634 3635 check_end: 3636 data->agc_cnt++; 3637 if (data->agc_cnt >= 6) 3638 state = RTW_DPK_AGC_OUT; 3639 3640 return state; 3641 } 3642 3643 static u8 rtw8822c_gain_large_state(struct rtw_dev *rtwdev, 3644 struct rtw8822c_dpk_data *data) 3645 { 3646 u8 pga = data->pga; 3647 3648 if (pga > 0xe) 3649 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc); 3650 else if (pga > 0xb && pga < 0xf) 3651 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0); 3652 else if (pga < 0xc) 3653 data->limited_pga = 1; 3654 3655 return RTW_DPK_GAIN_CHECK; 3656 } 3657 3658 static u8 rtw8822c_gain_less_state(struct rtw_dev *rtwdev, 3659 struct rtw8822c_dpk_data *data) 3660 { 3661 u8 pga = data->pga; 3662 3663 if (pga < 0xc) 3664 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc); 3665 else if (pga > 0xb && pga < 0xf) 3666 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf); 3667 else if (pga > 0xe) 3668 data->limited_pga = 1; 3669 3670 return RTW_DPK_GAIN_CHECK; 3671 } 3672 3673 static u8 rtw8822c_gl_state(struct rtw_dev *rtwdev, 3674 struct rtw8822c_dpk_data *data, u8 is_large) 3675 { 3676 u8 txbb_bound[] = {0x1f, 0}; 3677 3678 if (data->txbb == txbb_bound[is_large]) 3679 return RTW_DPK_AGC_OUT; 3680 3681 if (is_large == 1) 3682 data->txbb -= 2; 3683 else 3684 data->txbb += 3; 3685 3686 rtw_write_rf(rtwdev, data->path, RF_TX_GAIN, BIT_GAIN_TXBB, data->txbb); 3687 data->limited_pga = 0; 3688 3689 return RTW_DPK_GAIN_CHECK; 3690 } 3691 3692 static u8 rtw8822c_gl_large_state(struct rtw_dev *rtwdev, 3693 struct rtw8822c_dpk_data *data) 3694 { 3695 return rtw8822c_gl_state(rtwdev, data, 1); 3696 } 3697 3698 static u8 rtw8822c_gl_less_state(struct rtw_dev *rtwdev, 3699 struct rtw8822c_dpk_data *data) 3700 { 3701 return rtw8822c_gl_state(rtwdev, data, 0); 3702 } 3703 3704 static u8 rtw8822c_loss_check_state(struct rtw_dev *rtwdev, 3705 struct rtw8822c_dpk_data *data) 3706 { 3707 u8 path = data->path; 3708 u8 state; 3709 3710 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_GAIN_LOSS); 3711 state = rtw8822c_dpk_agc_loss_chk(rtwdev, path); 3712 3713 return state; 3714 } 3715 3716 static u8 (*dpk_state[])(struct rtw_dev *rtwdev, 3717 struct rtw8822c_dpk_data *data) = { 3718 rtw8822c_gain_check_state, rtw8822c_gain_large_state, 3719 rtw8822c_gain_less_state, rtw8822c_gl_large_state, 3720 rtw8822c_gl_less_state, rtw8822c_loss_check_state }; 3721 3722 static u8 rtw8822c_dpk_pas_agc(struct rtw_dev *rtwdev, u8 path, 3723 bool gain_only, bool loss_only) 3724 { 3725 struct rtw8822c_dpk_data data = {0}; 3726 u8 (*func)(struct rtw_dev *rtwdev, struct rtw8822c_dpk_data *data); 3727 u8 state = RTW_DPK_GAIN_CHECK; 3728 3729 data.loss_only = loss_only; 3730 data.gain_only = gain_only; 3731 data.path = path; 3732 3733 for (;;) { 3734 func = dpk_state[state]; 3735 state = func(rtwdev, &data); 3736 if (state == RTW_DPK_AGC_OUT) 3737 break; 3738 } 3739 3740 return data.txbb; 3741 } 3742 3743 static bool rtw8822c_dpk_coef_iq_check(struct rtw_dev *rtwdev, 3744 u16 coef_i, u16 coef_q) 3745 { 3746 if (coef_i == 0x1000 || coef_i == 0x0fff || 3747 coef_q == 0x1000 || coef_q == 0x0fff) 3748 return true; 3749 3750 return false; 3751 } 3752 3753 static u32 rtw8822c_dpk_coef_transfer(struct rtw_dev *rtwdev) 3754 { 3755 u32 reg = 0; 3756 u16 coef_i = 0, coef_q = 0; 3757 3758 reg = rtw_read32(rtwdev, REG_STAT_RPT); 3759 3760 coef_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD) & 0x1fff; 3761 coef_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD) & 0x1fff; 3762 3763 coef_q = ((0x2000 - coef_q) & 0x1fff) - 1; 3764 3765 reg = (coef_i << 16) | coef_q; 3766 3767 return reg; 3768 } 3769 3770 static const u32 rtw8822c_dpk_get_coef_tbl[] = { 3771 0x000400f0, 0x040400f0, 0x080400f0, 0x010400f0, 0x050400f0, 3772 0x090400f0, 0x020400f0, 0x060400f0, 0x0a0400f0, 0x030400f0, 3773 0x070400f0, 0x0b0400f0, 0x0c0400f0, 0x100400f0, 0x0d0400f0, 3774 0x110400f0, 0x0e0400f0, 0x120400f0, 0x0f0400f0, 0x130400f0, 3775 }; 3776 3777 static void rtw8822c_dpk_coef_tbl_apply(struct rtw_dev *rtwdev, u8 path) 3778 { 3779 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3780 int i; 3781 3782 for (i = 0; i < 20; i++) { 3783 rtw_write32(rtwdev, REG_RXSRAM_CTL, 3784 rtw8822c_dpk_get_coef_tbl[i]); 3785 dpk_info->coef[path][i] = rtw8822c_dpk_coef_transfer(rtwdev); 3786 } 3787 } 3788 3789 static void rtw8822c_dpk_get_coef(struct rtw_dev *rtwdev, u8 path) 3790 { 3791 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c); 3792 3793 if (path == RF_PATH_A) { 3794 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x0); 3795 rtw_write32(rtwdev, REG_DPD_CTL0_S0, 0x30000080); 3796 } else if (path == RF_PATH_B) { 3797 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x1); 3798 rtw_write32(rtwdev, REG_DPD_CTL0_S1, 0x30000080); 3799 } 3800 3801 rtw8822c_dpk_coef_tbl_apply(rtwdev, path); 3802 } 3803 3804 static u8 rtw8822c_dpk_coef_read(struct rtw_dev *rtwdev, u8 path) 3805 { 3806 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3807 u8 addr, result = 1; 3808 u16 coef_i, coef_q; 3809 3810 for (addr = 0; addr < 20; addr++) { 3811 coef_i = FIELD_GET(0x1fff0000, dpk_info->coef[path][addr]); 3812 coef_q = FIELD_GET(0x1fff, dpk_info->coef[path][addr]); 3813 3814 if (rtw8822c_dpk_coef_iq_check(rtwdev, coef_i, coef_q)) { 3815 result = 0; 3816 break; 3817 } 3818 } 3819 return result; 3820 } 3821 3822 static void rtw8822c_dpk_coef_write(struct rtw_dev *rtwdev, u8 path, u8 result) 3823 { 3824 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3825 u16 reg[DPK_RF_PATH_NUM] = {0x1b0c, 0x1b64}; 3826 u32 coef; 3827 u8 addr; 3828 3829 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c); 3830 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 3831 3832 for (addr = 0; addr < 20; addr++) { 3833 if (result == 0) { 3834 if (addr == 3) 3835 coef = 0x04001fff; 3836 else 3837 coef = 0x00001fff; 3838 } else { 3839 coef = dpk_info->coef[path][addr]; 3840 } 3841 rtw_write32(rtwdev, reg[path] + addr * 4, coef); 3842 } 3843 } 3844 3845 static void rtw8822c_dpk_fill_result(struct rtw_dev *rtwdev, u32 dpk_txagc, 3846 u8 path, u8 result) 3847 { 3848 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3849 3850 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3851 3852 if (result) 3853 rtw_write8(rtwdev, REG_DPD_AGC, (u8)(dpk_txagc - 6)); 3854 else 3855 rtw_write8(rtwdev, REG_DPD_AGC, 0x00); 3856 3857 dpk_info->result[path] = result; 3858 dpk_info->dpk_txagc[path] = rtw_read8(rtwdev, REG_DPD_AGC); 3859 3860 rtw8822c_dpk_coef_write(rtwdev, path, result); 3861 } 3862 3863 static u32 rtw8822c_dpk_gainloss(struct rtw_dev *rtwdev, u8 path) 3864 { 3865 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3866 u8 tx_agc, tx_bb, ori_txbb, ori_txagc, tx_agc_search, t1, t2; 3867 3868 ori_txbb = rtw8822c_dpk_rf_setting(rtwdev, path); 3869 ori_txagc = (u8)rtw_read_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_TXAGC); 3870 3871 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 3872 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 3873 rtw8822c_dpk_dgain_read(rtwdev, path); 3874 3875 if (rtw8822c_dpk_dc_corr_check(rtwdev, path)) { 3876 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 3877 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 3878 rtw8822c_dpk_dc_corr_check(rtwdev, path); 3879 } 3880 3881 t1 = rtw8822c_dpk_thermal_read(rtwdev, path); 3882 tx_bb = rtw8822c_dpk_pas_agc(rtwdev, path, false, true); 3883 tx_agc_search = rtw8822c_dpk_gainloss_result(rtwdev, path); 3884 3885 if (tx_bb < tx_agc_search) 3886 tx_bb = 0; 3887 else 3888 tx_bb = tx_bb - tx_agc_search; 3889 3890 rtw_write_rf(rtwdev, path, RF_TX_GAIN, BIT_GAIN_TXBB, tx_bb); 3891 3892 tx_agc = ori_txagc - (ori_txbb - tx_bb); 3893 3894 t2 = rtw8822c_dpk_thermal_read(rtwdev, path); 3895 3896 dpk_info->thermal_dpk_delta[path] = abs(t2 - t1); 3897 3898 return tx_agc; 3899 } 3900 3901 static u8 rtw8822c_dpk_by_path(struct rtw_dev *rtwdev, u32 tx_agc, u8 path) 3902 { 3903 u8 result; 3904 3905 result = rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DO_DPK); 3906 3907 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3908 3909 result = result | (u8)rtw_read32_mask(rtwdev, REG_DPD_CTL1_S0, BIT(26)); 3910 3911 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x33e14); 3912 3913 rtw8822c_dpk_get_coef(rtwdev, path); 3914 3915 return result; 3916 } 3917 3918 static void rtw8822c_dpk_cal_gs(struct rtw_dev *rtwdev, u8 path) 3919 { 3920 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3921 u32 tmp_gs = 0; 3922 3923 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3924 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_BYPASS_DPD, 0x0); 3925 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 3926 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9); 3927 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x1); 3928 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3929 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0xf); 3930 3931 if (path == RF_PATH_A) { 3932 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 3933 0x1066680); 3934 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 0x1); 3935 } else { 3936 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 3937 0x1066680); 3938 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 0x1); 3939 } 3940 3941 if (dpk_info->dpk_bw == DPK_CHANNEL_WIDTH_80) { 3942 rtw_write32(rtwdev, REG_DPD_CTL16, 0x80001310); 3943 rtw_write32(rtwdev, REG_DPD_CTL16, 0x00001310); 3944 rtw_write32(rtwdev, REG_DPD_CTL16, 0x810000db); 3945 rtw_write32(rtwdev, REG_DPD_CTL16, 0x010000db); 3946 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428); 3947 rtw_write32(rtwdev, REG_DPD_CTL15, 3948 0x05020000 | (BIT(path) << 28)); 3949 } else { 3950 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8200190c); 3951 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0200190c); 3952 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8301ee14); 3953 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0301ee14); 3954 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428); 3955 rtw_write32(rtwdev, REG_DPD_CTL15, 3956 0x05020008 | (BIT(path) << 28)); 3957 } 3958 3959 rtw_write32_mask(rtwdev, REG_DPD_CTL0, MASKBYTE3, 0x8 | path); 3960 3961 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_CAL_PWR); 3962 3963 rtw_write32_mask(rtwdev, REG_DPD_CTL15, MASKBYTE3, 0x0); 3964 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3965 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0); 3966 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x0); 3967 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3968 3969 if (path == RF_PATH_A) 3970 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 0x5b); 3971 else 3972 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 0x5b); 3973 3974 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0); 3975 3976 tmp_gs = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, BIT_RPT_DGAIN); 3977 tmp_gs = (tmp_gs * 910) >> 10; 3978 tmp_gs = DIV_ROUND_CLOSEST(tmp_gs, 10); 3979 3980 if (path == RF_PATH_A) 3981 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, tmp_gs); 3982 else 3983 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, tmp_gs); 3984 3985 dpk_info->dpk_gs[path] = tmp_gs; 3986 } 3987 3988 static void rtw8822c_dpk_cal_coef1(struct rtw_dev *rtwdev) 3989 { 3990 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3991 u32 offset[DPK_RF_PATH_NUM] = {0, 0x58}; 3992 u32 i_scaling; 3993 u8 path; 3994 3995 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c); 3996 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 3997 rtw_write32(rtwdev, REG_NCTL0, 0x00001148); 3998 rtw_write32(rtwdev, REG_NCTL0, 0x00001149); 3999 4000 check_hw_ready(rtwdev, 0x2d9c, MASKBYTE0, 0x55); 4001 4002 rtw_write8(rtwdev, 0x1b10, 0x0); 4003 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c); 4004 4005 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 4006 i_scaling = 0x16c00 / dpk_info->dpk_gs[path]; 4007 4008 rtw_write32_mask(rtwdev, 0x1b18 + offset[path], MASKHWORD, 4009 i_scaling); 4010 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 4011 GENMASK(31, 28), 0x9); 4012 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 4013 GENMASK(31, 28), 0x1); 4014 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 4015 GENMASK(31, 28), 0x0); 4016 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0 + offset[path], 4017 BIT(14), 0x0); 4018 } 4019 } 4020 4021 static void rtw8822c_dpk_on(struct rtw_dev *rtwdev, u8 path) 4022 { 4023 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 4024 4025 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON); 4026 4027 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 4028 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 4029 4030 if (test_bit(path, dpk_info->dpk_path_ok)) 4031 rtw8822c_dpk_cal_gs(rtwdev, path); 4032 } 4033 4034 static bool rtw8822c_dpk_check_pass(struct rtw_dev *rtwdev, bool is_fail, 4035 u32 dpk_txagc, u8 path) 4036 { 4037 bool result; 4038 4039 if (!is_fail) { 4040 if (rtw8822c_dpk_coef_read(rtwdev, path)) 4041 result = true; 4042 else 4043 result = false; 4044 } else { 4045 result = false; 4046 } 4047 4048 rtw8822c_dpk_fill_result(rtwdev, dpk_txagc, path, result); 4049 4050 return result; 4051 } 4052 4053 static void rtw8822c_dpk_result_reset(struct rtw_dev *rtwdev) 4054 { 4055 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 4056 u8 path; 4057 4058 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 4059 clear_bit(path, dpk_info->dpk_path_ok); 4060 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 4061 0x8 | (path << 1)); 4062 rtw_write32_mask(rtwdev, 0x1b58, 0x0000007f, 0x0); 4063 4064 dpk_info->dpk_txagc[path] = 0; 4065 dpk_info->result[path] = 0; 4066 dpk_info->dpk_gs[path] = 0x5b; 4067 dpk_info->pre_pwsf[path] = 0; 4068 dpk_info->thermal_dpk[path] = rtw8822c_dpk_thermal_read(rtwdev, 4069 path); 4070 } 4071 } 4072 4073 static void rtw8822c_dpk_calibrate(struct rtw_dev *rtwdev, u8 path) 4074 { 4075 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 4076 u32 dpk_txagc; 4077 u8 dpk_fail; 4078 4079 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk start\n", path); 4080 4081 dpk_txagc = rtw8822c_dpk_gainloss(rtwdev, path); 4082 4083 dpk_fail = rtw8822c_dpk_by_path(rtwdev, dpk_txagc, path); 4084 4085 if (!rtw8822c_dpk_check_pass(rtwdev, dpk_fail, dpk_txagc, path)) 4086 rtw_err(rtwdev, "failed to do dpk calibration\n"); 4087 4088 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk finish\n", path); 4089 4090 if (dpk_info->result[path]) 4091 set_bit(path, dpk_info->dpk_path_ok); 4092 } 4093 4094 static void rtw8822c_dpk_path_select(struct rtw_dev *rtwdev) 4095 { 4096 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_A); 4097 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_B); 4098 rtw8822c_dpk_on(rtwdev, RF_PATH_A); 4099 rtw8822c_dpk_on(rtwdev, RF_PATH_B); 4100 rtw8822c_dpk_cal_coef1(rtwdev); 4101 } 4102 4103 static void rtw8822c_dpk_enable_disable(struct rtw_dev *rtwdev) 4104 { 4105 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 4106 u32 mask = BIT(15) | BIT(14); 4107 4108 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 4109 4110 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 4111 dpk_info->is_dpk_pwr_on); 4112 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 4113 dpk_info->is_dpk_pwr_on); 4114 4115 if (test_bit(RF_PATH_A, dpk_info->dpk_path_ok)) { 4116 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, mask, 0x0); 4117 rtw_write8(rtwdev, REG_DPD_CTL0_S0, dpk_info->dpk_gs[RF_PATH_A]); 4118 } 4119 if (test_bit(RF_PATH_B, dpk_info->dpk_path_ok)) { 4120 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, mask, 0x0); 4121 rtw_write8(rtwdev, REG_DPD_CTL0_S1, dpk_info->dpk_gs[RF_PATH_B]); 4122 } 4123 } 4124 4125 static void rtw8822c_dpk_reload_data(struct rtw_dev *rtwdev) 4126 { 4127 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 4128 u8 path; 4129 4130 if (!test_bit(RF_PATH_A, dpk_info->dpk_path_ok) && 4131 !test_bit(RF_PATH_B, dpk_info->dpk_path_ok) && 4132 dpk_info->dpk_ch == 0) 4133 return; 4134 4135 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 4136 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 4137 0x8 | (path << 1)); 4138 if (dpk_info->dpk_band == RTW_BAND_2G) 4139 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000); 4140 else 4141 rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000); 4142 4143 rtw_write8(rtwdev, REG_DPD_AGC, dpk_info->dpk_txagc[path]); 4144 4145 rtw8822c_dpk_coef_write(rtwdev, path, 4146 test_bit(path, dpk_info->dpk_path_ok)); 4147 4148 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON); 4149 4150 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 4151 4152 if (path == RF_PATH_A) 4153 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 4154 dpk_info->dpk_gs[path]); 4155 else 4156 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 4157 dpk_info->dpk_gs[path]); 4158 } 4159 rtw8822c_dpk_cal_coef1(rtwdev); 4160 } 4161 4162 static bool rtw8822c_dpk_reload(struct rtw_dev *rtwdev) 4163 { 4164 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 4165 u8 channel; 4166 4167 dpk_info->is_reload = false; 4168 4169 #if defined(__linux__) 4170 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK) & 0xff); 4171 #elif defined(__FreeBSD__) 4172 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK) & 0xff); 4173 #endif 4174 4175 if (channel == dpk_info->dpk_ch) { 4176 rtw_dbg(rtwdev, RTW_DBG_RFK, 4177 "[DPK] DPK reload for CH%d!!\n", dpk_info->dpk_ch); 4178 rtw8822c_dpk_reload_data(rtwdev); 4179 dpk_info->is_reload = true; 4180 } 4181 4182 return dpk_info->is_reload; 4183 } 4184 4185 static void rtw8822c_do_dpk(struct rtw_dev *rtwdev) 4186 { 4187 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 4188 struct rtw_backup_info bckp[DPK_BB_REG_NUM]; 4189 u32 rf_reg_backup[DPK_RF_REG_NUM][DPK_RF_PATH_NUM]; 4190 u32 bb_reg[DPK_BB_REG_NUM] = { 4191 0x520, 0x820, 0x824, 0x1c3c, 0x1d58, 0x1864, 4192 0x4164, 0x180c, 0x410c, 0x186c, 0x416c, 4193 0x1a14, 0x1e70, 0x80c, 0x1d70, 0x1e7c, 0x18a4, 0x41a4}; 4194 u32 rf_reg[DPK_RF_REG_NUM] = { 4195 0x0, 0x1a, 0x55, 0x63, 0x87, 0x8f, 0xde}; 4196 u8 path; 4197 4198 if (!dpk_info->is_dpk_pwr_on) { 4199 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] Skip DPK due to DPD PWR off\n"); 4200 return; 4201 } else if (rtw8822c_dpk_reload(rtwdev)) { 4202 return; 4203 } 4204 4205 for (path = RF_PATH_A; path < DPK_RF_PATH_NUM; path++) 4206 ewma_thermal_init(&dpk_info->avg_thermal[path]); 4207 4208 rtw8822c_dpk_information(rtwdev); 4209 4210 rtw8822c_dpk_backup_registers(rtwdev, bb_reg, DPK_BB_REG_NUM, bckp); 4211 rtw8822c_dpk_backup_rf_registers(rtwdev, rf_reg, rf_reg_backup); 4212 4213 rtw8822c_dpk_mac_bb_setting(rtwdev); 4214 rtw8822c_dpk_afe_setting(rtwdev, true); 4215 rtw8822c_dpk_pre_setting(rtwdev); 4216 rtw8822c_dpk_result_reset(rtwdev); 4217 rtw8822c_dpk_path_select(rtwdev); 4218 rtw8822c_dpk_afe_setting(rtwdev, false); 4219 rtw8822c_dpk_enable_disable(rtwdev); 4220 4221 rtw8822c_dpk_reload_rf_registers(rtwdev, rf_reg, rf_reg_backup); 4222 for (path = 0; path < rtwdev->hal.rf_path_num; path++) 4223 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 4224 rtw8822c_dpk_restore_registers(rtwdev, DPK_BB_REG_NUM, bckp); 4225 } 4226 4227 static void rtw8822c_phy_calibration(struct rtw_dev *rtwdev) 4228 { 4229 rtw8822c_rfk_power_save(rtwdev, false); 4230 rtw8822c_do_gapk(rtwdev); 4231 rtw8822c_do_iqk(rtwdev); 4232 rtw8822c_do_dpk(rtwdev); 4233 rtw8822c_rfk_power_save(rtwdev, true); 4234 } 4235 4236 static void rtw8822c_dpk_track(struct rtw_dev *rtwdev) 4237 { 4238 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 4239 u8 path; 4240 u8 thermal_value[DPK_RF_PATH_NUM] = {0}; 4241 s8 offset[DPK_RF_PATH_NUM], delta_dpk[DPK_RF_PATH_NUM]; 4242 4243 if (dpk_info->thermal_dpk[0] == 0 && dpk_info->thermal_dpk[1] == 0) 4244 return; 4245 4246 for (path = 0; path < DPK_RF_PATH_NUM; path++) { 4247 thermal_value[path] = rtw8822c_dpk_thermal_read(rtwdev, path); 4248 ewma_thermal_add(&dpk_info->avg_thermal[path], 4249 thermal_value[path]); 4250 thermal_value[path] = 4251 ewma_thermal_read(&dpk_info->avg_thermal[path]); 4252 delta_dpk[path] = dpk_info->thermal_dpk[path] - 4253 thermal_value[path]; 4254 offset[path] = delta_dpk[path] - 4255 dpk_info->thermal_dpk_delta[path]; 4256 offset[path] &= 0x7f; 4257 4258 if (offset[path] != dpk_info->pre_pwsf[path]) { 4259 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 4260 0x8 | (path << 1)); 4261 rtw_write32_mask(rtwdev, 0x1b58, GENMASK(6, 0), 4262 offset[path]); 4263 dpk_info->pre_pwsf[path] = offset[path]; 4264 } 4265 } 4266 } 4267 4268 #define XCAP_EXTEND(val) ({typeof(val) _v = (val); _v | _v << 7; }) 4269 static void rtw8822c_set_crystal_cap_reg(struct rtw_dev *rtwdev, u8 crystal_cap) 4270 { 4271 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4272 struct rtw_cfo_track *cfo = &dm_info->cfo_track; 4273 u32 val = 0; 4274 4275 val = XCAP_EXTEND(crystal_cap); 4276 cfo->crystal_cap = crystal_cap; 4277 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, BIT_XCAP_0, val); 4278 } 4279 4280 static void rtw8822c_set_crystal_cap(struct rtw_dev *rtwdev, u8 crystal_cap) 4281 { 4282 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4283 struct rtw_cfo_track *cfo = &dm_info->cfo_track; 4284 4285 if (cfo->crystal_cap == crystal_cap) 4286 return; 4287 4288 rtw8822c_set_crystal_cap_reg(rtwdev, crystal_cap); 4289 } 4290 4291 static void rtw8822c_cfo_tracking_reset(struct rtw_dev *rtwdev) 4292 { 4293 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4294 struct rtw_cfo_track *cfo = &dm_info->cfo_track; 4295 4296 cfo->is_adjust = true; 4297 4298 if (cfo->crystal_cap > rtwdev->efuse.crystal_cap) 4299 rtw8822c_set_crystal_cap(rtwdev, cfo->crystal_cap - 1); 4300 else if (cfo->crystal_cap < rtwdev->efuse.crystal_cap) 4301 rtw8822c_set_crystal_cap(rtwdev, cfo->crystal_cap + 1); 4302 } 4303 4304 static void rtw8822c_cfo_init(struct rtw_dev *rtwdev) 4305 { 4306 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4307 struct rtw_cfo_track *cfo = &dm_info->cfo_track; 4308 4309 cfo->crystal_cap = rtwdev->efuse.crystal_cap; 4310 cfo->is_adjust = true; 4311 } 4312 4313 #define REPORT_TO_KHZ(val) ({typeof(val) _v = (val); (_v << 1) + (_v >> 1); }) 4314 static s32 rtw8822c_cfo_calc_avg(struct rtw_dev *rtwdev, u8 path_num) 4315 { 4316 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4317 struct rtw_cfo_track *cfo = &dm_info->cfo_track; 4318 s32 cfo_avg, cfo_path_sum = 0, cfo_rpt_sum; 4319 u8 i; 4320 4321 for (i = 0; i < path_num; i++) { 4322 cfo_rpt_sum = REPORT_TO_KHZ(cfo->cfo_tail[i]); 4323 4324 if (cfo->cfo_cnt[i]) 4325 cfo_avg = cfo_rpt_sum / cfo->cfo_cnt[i]; 4326 else 4327 cfo_avg = 0; 4328 4329 cfo_path_sum += cfo_avg; 4330 } 4331 4332 for (i = 0; i < path_num; i++) { 4333 cfo->cfo_tail[i] = 0; 4334 cfo->cfo_cnt[i] = 0; 4335 } 4336 4337 return cfo_path_sum / path_num; 4338 } 4339 4340 static void rtw8822c_cfo_need_adjust(struct rtw_dev *rtwdev, s32 cfo_avg) 4341 { 4342 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4343 struct rtw_cfo_track *cfo = &dm_info->cfo_track; 4344 4345 if (!cfo->is_adjust) { 4346 if (abs(cfo_avg) > CFO_TRK_ENABLE_TH) 4347 cfo->is_adjust = true; 4348 } else { 4349 if (abs(cfo_avg) <= CFO_TRK_STOP_TH) 4350 cfo->is_adjust = false; 4351 } 4352 4353 if (!rtw_coex_disabled(rtwdev)) { 4354 cfo->is_adjust = false; 4355 rtw8822c_set_crystal_cap(rtwdev, rtwdev->efuse.crystal_cap); 4356 } 4357 } 4358 4359 static void rtw8822c_cfo_track(struct rtw_dev *rtwdev) 4360 { 4361 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4362 struct rtw_cfo_track *cfo = &dm_info->cfo_track; 4363 u8 path_num = rtwdev->hal.rf_path_num; 4364 s8 crystal_cap = cfo->crystal_cap; 4365 s32 cfo_avg = 0; 4366 4367 if (rtwdev->sta_cnt != 1) { 4368 rtw8822c_cfo_tracking_reset(rtwdev); 4369 return; 4370 } 4371 4372 if (cfo->packet_count == cfo->packet_count_pre) 4373 return; 4374 4375 cfo->packet_count_pre = cfo->packet_count; 4376 cfo_avg = rtw8822c_cfo_calc_avg(rtwdev, path_num); 4377 rtw8822c_cfo_need_adjust(rtwdev, cfo_avg); 4378 4379 if (cfo->is_adjust) { 4380 if (cfo_avg > CFO_TRK_ADJ_TH) 4381 crystal_cap++; 4382 else if (cfo_avg < -CFO_TRK_ADJ_TH) 4383 crystal_cap--; 4384 4385 crystal_cap = clamp_t(s8, crystal_cap, 0, XCAP_MASK); 4386 rtw8822c_set_crystal_cap(rtwdev, (u8)crystal_cap); 4387 } 4388 } 4389 4390 static const struct rtw_phy_cck_pd_reg 4391 rtw8822c_cck_pd_reg[RTW_CHANNEL_WIDTH_40 + 1][RTW_RF_PATH_MAX] = { 4392 { 4393 {0x1ac8, 0x00ff, 0x1ad0, 0x01f}, 4394 {0x1ac8, 0xff00, 0x1ad0, 0x3e0} 4395 }, 4396 { 4397 {0x1acc, 0x00ff, 0x1ad0, 0x01F00000}, 4398 {0x1acc, 0xff00, 0x1ad0, 0x3E000000} 4399 }, 4400 }; 4401 4402 #define RTW_CCK_PD_MAX 255 4403 #define RTW_CCK_CS_MAX 31 4404 #define RTW_CCK_CS_ERR1 27 4405 #define RTW_CCK_CS_ERR2 29 4406 static void 4407 rtw8822c_phy_cck_pd_set_reg(struct rtw_dev *rtwdev, 4408 s8 pd_diff, s8 cs_diff, u8 bw, u8 nrx) 4409 { 4410 u32 pd, cs; 4411 4412 if (WARN_ON(bw > RTW_CHANNEL_WIDTH_40 || nrx >= RTW_RF_PATH_MAX)) 4413 return; 4414 4415 pd = rtw_read32_mask(rtwdev, 4416 rtw8822c_cck_pd_reg[bw][nrx].reg_pd, 4417 rtw8822c_cck_pd_reg[bw][nrx].mask_pd); 4418 cs = rtw_read32_mask(rtwdev, 4419 rtw8822c_cck_pd_reg[bw][nrx].reg_cs, 4420 rtw8822c_cck_pd_reg[bw][nrx].mask_cs); 4421 pd += pd_diff; 4422 cs += cs_diff; 4423 if (pd > RTW_CCK_PD_MAX) 4424 pd = RTW_CCK_PD_MAX; 4425 if (cs == RTW_CCK_CS_ERR1 || cs == RTW_CCK_CS_ERR2) 4426 cs++; 4427 else if (cs > RTW_CCK_CS_MAX) 4428 cs = RTW_CCK_CS_MAX; 4429 rtw_write32_mask(rtwdev, 4430 rtw8822c_cck_pd_reg[bw][nrx].reg_pd, 4431 rtw8822c_cck_pd_reg[bw][nrx].mask_pd, 4432 pd); 4433 rtw_write32_mask(rtwdev, 4434 rtw8822c_cck_pd_reg[bw][nrx].reg_cs, 4435 rtw8822c_cck_pd_reg[bw][nrx].mask_cs, 4436 cs); 4437 4438 rtw_dbg(rtwdev, RTW_DBG_PHY, 4439 "is_linked=%d, bw=%d, nrx=%d, cs_ratio=0x%x, pd_th=0x%x\n", 4440 rtw_is_assoc(rtwdev), bw, nrx, cs, pd); 4441 } 4442 4443 static void rtw8822c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) 4444 { 4445 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4446 s8 pd_lvl[CCK_PD_LV_MAX] = {0, 2, 4, 6, 8}; 4447 s8 cs_lvl[CCK_PD_LV_MAX] = {0, 2, 2, 2, 4}; 4448 u8 cur_lvl; 4449 u8 nrx, bw; 4450 4451 nrx = (u8)rtw_read32_mask(rtwdev, 0x1a2c, 0x60000); 4452 bw = (u8)rtw_read32_mask(rtwdev, 0x9b0, 0xc); 4453 4454 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d) bw=%d nr=%d cck_fa_avg=%d\n", 4455 dm_info->cck_pd_lv[bw][nrx], new_lvl, bw, nrx, 4456 dm_info->cck_fa_avg); 4457 4458 if (dm_info->cck_pd_lv[bw][nrx] == new_lvl) 4459 return; 4460 4461 cur_lvl = dm_info->cck_pd_lv[bw][nrx]; 4462 4463 /* update cck pd info */ 4464 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 4465 4466 rtw8822c_phy_cck_pd_set_reg(rtwdev, 4467 pd_lvl[new_lvl] - pd_lvl[cur_lvl], 4468 cs_lvl[new_lvl] - cs_lvl[cur_lvl], 4469 bw, nrx); 4470 dm_info->cck_pd_lv[bw][nrx] = new_lvl; 4471 } 4472 4473 #define PWR_TRACK_MASK 0x7f 4474 static void rtw8822c_pwrtrack_set(struct rtw_dev *rtwdev, u8 rf_path) 4475 { 4476 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4477 4478 switch (rf_path) { 4479 case RF_PATH_A: 4480 rtw_write32_mask(rtwdev, 0x18a0, PWR_TRACK_MASK, 4481 dm_info->delta_power_index[rf_path]); 4482 break; 4483 case RF_PATH_B: 4484 rtw_write32_mask(rtwdev, 0x41a0, PWR_TRACK_MASK, 4485 dm_info->delta_power_index[rf_path]); 4486 break; 4487 default: 4488 break; 4489 } 4490 } 4491 4492 static void rtw8822c_pwr_track_stats(struct rtw_dev *rtwdev, u8 path) 4493 { 4494 u8 thermal_value; 4495 4496 if (rtwdev->efuse.thermal_meter[path] == 0xff) 4497 return; 4498 4499 thermal_value = rtw_read_rf(rtwdev, path, RF_T_METER, 0x7e); 4500 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, path); 4501 } 4502 4503 static void rtw8822c_pwr_track_path(struct rtw_dev *rtwdev, 4504 struct rtw_swing_table *swing_table, 4505 u8 path) 4506 { 4507 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4508 u8 delta; 4509 4510 delta = rtw_phy_pwrtrack_get_delta(rtwdev, path); 4511 dm_info->delta_power_index[path] = 4512 rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table, path, path, 4513 delta); 4514 rtw8822c_pwrtrack_set(rtwdev, path); 4515 } 4516 4517 static void __rtw8822c_pwr_track(struct rtw_dev *rtwdev) 4518 { 4519 struct rtw_swing_table swing_table; 4520 u8 i; 4521 4522 rtw_phy_config_swing_table(rtwdev, &swing_table); 4523 4524 for (i = 0; i < rtwdev->hal.rf_path_num; i++) 4525 rtw8822c_pwr_track_stats(rtwdev, i); 4526 if (rtw_phy_pwrtrack_need_lck(rtwdev)) 4527 rtw8822c_do_lck(rtwdev); 4528 for (i = 0; i < rtwdev->hal.rf_path_num; i++) 4529 rtw8822c_pwr_track_path(rtwdev, &swing_table, i); 4530 } 4531 4532 static void rtw8822c_pwr_track(struct rtw_dev *rtwdev) 4533 { 4534 struct rtw_efuse *efuse = &rtwdev->efuse; 4535 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4536 4537 if (efuse->power_track_type != 0) 4538 return; 4539 4540 if (!dm_info->pwr_trk_triggered) { 4541 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01); 4542 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x00); 4543 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01); 4544 4545 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01); 4546 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x00); 4547 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01); 4548 4549 dm_info->pwr_trk_triggered = true; 4550 return; 4551 } 4552 4553 __rtw8822c_pwr_track(rtwdev); 4554 dm_info->pwr_trk_triggered = false; 4555 } 4556 4557 static void rtw8822c_adaptivity_init(struct rtw_dev *rtwdev) 4558 { 4559 rtw_phy_set_edcca_th(rtwdev, RTW8822C_EDCCA_MAX, RTW8822C_EDCCA_MAX); 4560 4561 /* mac edcca state setting */ 4562 rtw_write32_clr(rtwdev, REG_TX_PTCL_CTRL, BIT_DIS_EDCCA); 4563 rtw_write32_set(rtwdev, REG_RD_CTRL, BIT_EDCCA_MSK_CNTDOWN_EN); 4564 4565 /* edcca decistion opt */ 4566 rtw_write32_clr(rtwdev, REG_EDCCA_DECISION, BIT_EDCCA_OPTION); 4567 } 4568 4569 static void rtw8822c_adaptivity(struct rtw_dev *rtwdev) 4570 { 4571 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 4572 s8 l2h, h2l; 4573 u8 igi; 4574 4575 igi = dm_info->igi_history[0]; 4576 if (dm_info->edcca_mode == RTW_EDCCA_NORMAL) { 4577 l2h = max_t(s8, igi + EDCCA_IGI_L2H_DIFF, EDCCA_TH_L2H_LB); 4578 h2l = l2h - EDCCA_L2H_H2L_DIFF_NORMAL; 4579 } else { 4580 if (igi < dm_info->l2h_th_ini - EDCCA_ADC_BACKOFF) 4581 l2h = igi + EDCCA_ADC_BACKOFF; 4582 else 4583 l2h = dm_info->l2h_th_ini; 4584 h2l = l2h - EDCCA_L2H_H2L_DIFF; 4585 } 4586 4587 rtw_phy_set_edcca_th(rtwdev, l2h, h2l); 4588 } 4589 4590 static void rtw8822c_fill_txdesc_checksum(struct rtw_dev *rtwdev, 4591 struct rtw_tx_pkt_info *pkt_info, 4592 u8 *txdesc) 4593 { 4594 const struct rtw_chip_info *chip = rtwdev->chip; 4595 size_t words; 4596 4597 words = (pkt_info->pkt_offset * 8 + chip->tx_pkt_desc_sz) / 2; 4598 4599 fill_txdesc_checksum_common(txdesc, words); 4600 } 4601 4602 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822c[] = { 4603 {0x0086, 4604 RTW_PWR_CUT_ALL_MSK, 4605 RTW_PWR_INTF_SDIO_MSK, 4606 RTW_PWR_ADDR_SDIO, 4607 RTW_PWR_CMD_WRITE, BIT(0), 0}, 4608 {0x0086, 4609 RTW_PWR_CUT_ALL_MSK, 4610 RTW_PWR_INTF_SDIO_MSK, 4611 RTW_PWR_ADDR_SDIO, 4612 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 4613 {0x002E, 4614 RTW_PWR_CUT_ALL_MSK, 4615 RTW_PWR_INTF_ALL_MSK, 4616 RTW_PWR_ADDR_MAC, 4617 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 4618 {0x002D, 4619 RTW_PWR_CUT_ALL_MSK, 4620 RTW_PWR_INTF_ALL_MSK, 4621 RTW_PWR_ADDR_MAC, 4622 RTW_PWR_CMD_WRITE, BIT(0), 0}, 4623 {0x007F, 4624 RTW_PWR_CUT_ALL_MSK, 4625 RTW_PWR_INTF_ALL_MSK, 4626 RTW_PWR_ADDR_MAC, 4627 RTW_PWR_CMD_WRITE, BIT(7), 0}, 4628 {0x004A, 4629 RTW_PWR_CUT_ALL_MSK, 4630 RTW_PWR_INTF_USB_MSK, 4631 RTW_PWR_ADDR_MAC, 4632 RTW_PWR_CMD_WRITE, BIT(0), 0}, 4633 {0x0005, 4634 RTW_PWR_CUT_ALL_MSK, 4635 RTW_PWR_INTF_ALL_MSK, 4636 RTW_PWR_ADDR_MAC, 4637 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 4638 {0xFFFF, 4639 RTW_PWR_CUT_ALL_MSK, 4640 RTW_PWR_INTF_ALL_MSK, 4641 0, 4642 RTW_PWR_CMD_END, 0, 0}, 4643 }; 4644 4645 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822c[] = { 4646 {0x0000, 4647 RTW_PWR_CUT_ALL_MSK, 4648 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 4649 RTW_PWR_ADDR_MAC, 4650 RTW_PWR_CMD_WRITE, BIT(5), 0}, 4651 {0x0005, 4652 RTW_PWR_CUT_ALL_MSK, 4653 RTW_PWR_INTF_ALL_MSK, 4654 RTW_PWR_ADDR_MAC, 4655 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 4656 {0x0075, 4657 RTW_PWR_CUT_ALL_MSK, 4658 RTW_PWR_INTF_PCI_MSK, 4659 RTW_PWR_ADDR_MAC, 4660 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 4661 {0x0006, 4662 RTW_PWR_CUT_ALL_MSK, 4663 RTW_PWR_INTF_ALL_MSK, 4664 RTW_PWR_ADDR_MAC, 4665 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 4666 {0x0075, 4667 RTW_PWR_CUT_ALL_MSK, 4668 RTW_PWR_INTF_PCI_MSK, 4669 RTW_PWR_ADDR_MAC, 4670 RTW_PWR_CMD_WRITE, BIT(0), 0}, 4671 {0xFF1A, 4672 RTW_PWR_CUT_ALL_MSK, 4673 RTW_PWR_INTF_USB_MSK, 4674 RTW_PWR_ADDR_MAC, 4675 RTW_PWR_CMD_WRITE, 0xFF, 0}, 4676 {0x002E, 4677 RTW_PWR_CUT_ALL_MSK, 4678 RTW_PWR_INTF_ALL_MSK, 4679 RTW_PWR_ADDR_MAC, 4680 RTW_PWR_CMD_WRITE, BIT(3), 0}, 4681 {0x0006, 4682 RTW_PWR_CUT_ALL_MSK, 4683 RTW_PWR_INTF_ALL_MSK, 4684 RTW_PWR_ADDR_MAC, 4685 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 4686 {0x0005, 4687 RTW_PWR_CUT_ALL_MSK, 4688 RTW_PWR_INTF_ALL_MSK, 4689 RTW_PWR_ADDR_MAC, 4690 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 4691 {0x1018, 4692 RTW_PWR_CUT_ALL_MSK, 4693 RTW_PWR_INTF_ALL_MSK, 4694 RTW_PWR_ADDR_MAC, 4695 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 4696 {0x0005, 4697 RTW_PWR_CUT_ALL_MSK, 4698 RTW_PWR_INTF_ALL_MSK, 4699 RTW_PWR_ADDR_MAC, 4700 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 4701 {0x0005, 4702 RTW_PWR_CUT_ALL_MSK, 4703 RTW_PWR_INTF_ALL_MSK, 4704 RTW_PWR_ADDR_MAC, 4705 RTW_PWR_CMD_POLLING, BIT(0), 0}, 4706 {0x0074, 4707 RTW_PWR_CUT_ALL_MSK, 4708 RTW_PWR_INTF_PCI_MSK, 4709 RTW_PWR_ADDR_MAC, 4710 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 4711 {0x0071, 4712 RTW_PWR_CUT_ALL_MSK, 4713 RTW_PWR_INTF_PCI_MSK, 4714 RTW_PWR_ADDR_MAC, 4715 RTW_PWR_CMD_WRITE, BIT(4), 0}, 4716 {0x0062, 4717 RTW_PWR_CUT_ALL_MSK, 4718 RTW_PWR_INTF_PCI_MSK, 4719 RTW_PWR_ADDR_MAC, 4720 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 4721 (BIT(7) | BIT(6) | BIT(5))}, 4722 {0x0061, 4723 RTW_PWR_CUT_ALL_MSK, 4724 RTW_PWR_INTF_PCI_MSK, 4725 RTW_PWR_ADDR_MAC, 4726 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, 4727 {0x001F, 4728 RTW_PWR_CUT_ALL_MSK, 4729 RTW_PWR_INTF_ALL_MSK, 4730 RTW_PWR_ADDR_MAC, 4731 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)}, 4732 {0x00EF, 4733 RTW_PWR_CUT_ALL_MSK, 4734 RTW_PWR_INTF_ALL_MSK, 4735 RTW_PWR_ADDR_MAC, 4736 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)}, 4737 {0x1045, 4738 RTW_PWR_CUT_ALL_MSK, 4739 RTW_PWR_INTF_ALL_MSK, 4740 RTW_PWR_ADDR_MAC, 4741 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 4742 {0x0010, 4743 RTW_PWR_CUT_ALL_MSK, 4744 RTW_PWR_INTF_ALL_MSK, 4745 RTW_PWR_ADDR_MAC, 4746 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 4747 {0x1064, 4748 RTW_PWR_CUT_ALL_MSK, 4749 RTW_PWR_INTF_ALL_MSK, 4750 RTW_PWR_ADDR_MAC, 4751 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 4752 {0xFFFF, 4753 RTW_PWR_CUT_ALL_MSK, 4754 RTW_PWR_INTF_ALL_MSK, 4755 0, 4756 RTW_PWR_CMD_END, 0, 0}, 4757 }; 4758 4759 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822c[] = { 4760 {0x0093, 4761 RTW_PWR_CUT_ALL_MSK, 4762 RTW_PWR_INTF_ALL_MSK, 4763 RTW_PWR_ADDR_MAC, 4764 RTW_PWR_CMD_WRITE, BIT(3), 0}, 4765 {0x001F, 4766 RTW_PWR_CUT_ALL_MSK, 4767 RTW_PWR_INTF_ALL_MSK, 4768 RTW_PWR_ADDR_MAC, 4769 RTW_PWR_CMD_WRITE, 0xFF, 0}, 4770 {0x00EF, 4771 RTW_PWR_CUT_ALL_MSK, 4772 RTW_PWR_INTF_ALL_MSK, 4773 RTW_PWR_ADDR_MAC, 4774 RTW_PWR_CMD_WRITE, 0xFF, 0}, 4775 {0x1045, 4776 RTW_PWR_CUT_ALL_MSK, 4777 RTW_PWR_INTF_ALL_MSK, 4778 RTW_PWR_ADDR_MAC, 4779 RTW_PWR_CMD_WRITE, BIT(4), 0}, 4780 {0xFF1A, 4781 RTW_PWR_CUT_ALL_MSK, 4782 RTW_PWR_INTF_USB_MSK, 4783 RTW_PWR_ADDR_MAC, 4784 RTW_PWR_CMD_WRITE, 0xFF, 0x30}, 4785 {0x0049, 4786 RTW_PWR_CUT_ALL_MSK, 4787 RTW_PWR_INTF_ALL_MSK, 4788 RTW_PWR_ADDR_MAC, 4789 RTW_PWR_CMD_WRITE, BIT(1), 0}, 4790 {0x0006, 4791 RTW_PWR_CUT_ALL_MSK, 4792 RTW_PWR_INTF_ALL_MSK, 4793 RTW_PWR_ADDR_MAC, 4794 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 4795 {0x0002, 4796 RTW_PWR_CUT_ALL_MSK, 4797 RTW_PWR_INTF_ALL_MSK, 4798 RTW_PWR_ADDR_MAC, 4799 RTW_PWR_CMD_WRITE, BIT(1), 0}, 4800 {0x0005, 4801 RTW_PWR_CUT_ALL_MSK, 4802 RTW_PWR_INTF_ALL_MSK, 4803 RTW_PWR_ADDR_MAC, 4804 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 4805 {0x0005, 4806 RTW_PWR_CUT_ALL_MSK, 4807 RTW_PWR_INTF_ALL_MSK, 4808 RTW_PWR_ADDR_MAC, 4809 RTW_PWR_CMD_POLLING, BIT(1), 0}, 4810 {0x0000, 4811 RTW_PWR_CUT_ALL_MSK, 4812 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 4813 RTW_PWR_ADDR_MAC, 4814 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 4815 {0xFFFF, 4816 RTW_PWR_CUT_ALL_MSK, 4817 RTW_PWR_INTF_ALL_MSK, 4818 0, 4819 RTW_PWR_CMD_END, 0, 0}, 4820 }; 4821 4822 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822c[] = { 4823 {0x0005, 4824 RTW_PWR_CUT_ALL_MSK, 4825 RTW_PWR_INTF_SDIO_MSK, 4826 RTW_PWR_ADDR_MAC, 4827 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 4828 {0x0007, 4829 RTW_PWR_CUT_ALL_MSK, 4830 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 4831 RTW_PWR_ADDR_MAC, 4832 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 4833 {0x0067, 4834 RTW_PWR_CUT_ALL_MSK, 4835 RTW_PWR_INTF_ALL_MSK, 4836 RTW_PWR_ADDR_MAC, 4837 RTW_PWR_CMD_WRITE, BIT(5), 0}, 4838 {0x004A, 4839 RTW_PWR_CUT_ALL_MSK, 4840 RTW_PWR_INTF_USB_MSK, 4841 RTW_PWR_ADDR_MAC, 4842 RTW_PWR_CMD_WRITE, BIT(0), 0}, 4843 {0x0081, 4844 RTW_PWR_CUT_ALL_MSK, 4845 RTW_PWR_INTF_ALL_MSK, 4846 RTW_PWR_ADDR_MAC, 4847 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 4848 {0x0090, 4849 RTW_PWR_CUT_ALL_MSK, 4850 RTW_PWR_INTF_ALL_MSK, 4851 RTW_PWR_ADDR_MAC, 4852 RTW_PWR_CMD_WRITE, BIT(1), 0}, 4853 {0x0092, 4854 RTW_PWR_CUT_ALL_MSK, 4855 RTW_PWR_INTF_PCI_MSK, 4856 RTW_PWR_ADDR_MAC, 4857 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 4858 {0x0093, 4859 RTW_PWR_CUT_ALL_MSK, 4860 RTW_PWR_INTF_PCI_MSK, 4861 RTW_PWR_ADDR_MAC, 4862 RTW_PWR_CMD_WRITE, 0xFF, 0x04}, 4863 {0x0005, 4864 RTW_PWR_CUT_ALL_MSK, 4865 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 4866 RTW_PWR_ADDR_MAC, 4867 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 4868 {0x0005, 4869 RTW_PWR_CUT_ALL_MSK, 4870 RTW_PWR_INTF_PCI_MSK, 4871 RTW_PWR_ADDR_MAC, 4872 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 4873 {0x0086, 4874 RTW_PWR_CUT_ALL_MSK, 4875 RTW_PWR_INTF_SDIO_MSK, 4876 RTW_PWR_ADDR_SDIO, 4877 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 4878 {0xFFFF, 4879 RTW_PWR_CUT_ALL_MSK, 4880 RTW_PWR_INTF_ALL_MSK, 4881 0, 4882 RTW_PWR_CMD_END, 0, 0}, 4883 }; 4884 4885 static const struct rtw_pwr_seq_cmd *card_enable_flow_8822c[] = { 4886 trans_carddis_to_cardemu_8822c, 4887 trans_cardemu_to_act_8822c, 4888 NULL 4889 }; 4890 4891 static const struct rtw_pwr_seq_cmd *card_disable_flow_8822c[] = { 4892 trans_act_to_cardemu_8822c, 4893 trans_cardemu_to_carddis_8822c, 4894 NULL 4895 }; 4896 4897 static const struct rtw_intf_phy_para usb2_param_8822c[] = { 4898 {0xFFFF, 0x00, 4899 RTW_IP_SEL_PHY, 4900 RTW_INTF_PHY_CUT_ALL, 4901 RTW_INTF_PHY_PLATFORM_ALL}, 4902 }; 4903 4904 static const struct rtw_intf_phy_para usb3_param_8822c[] = { 4905 {0xFFFF, 0x0000, 4906 RTW_IP_SEL_PHY, 4907 RTW_INTF_PHY_CUT_ALL, 4908 RTW_INTF_PHY_PLATFORM_ALL}, 4909 }; 4910 4911 static const struct rtw_intf_phy_para pcie_gen1_param_8822c[] = { 4912 {0xFFFF, 0x0000, 4913 RTW_IP_SEL_PHY, 4914 RTW_INTF_PHY_CUT_ALL, 4915 RTW_INTF_PHY_PLATFORM_ALL}, 4916 }; 4917 4918 static const struct rtw_intf_phy_para pcie_gen2_param_8822c[] = { 4919 {0xFFFF, 0x0000, 4920 RTW_IP_SEL_PHY, 4921 RTW_INTF_PHY_CUT_ALL, 4922 RTW_INTF_PHY_PLATFORM_ALL}, 4923 }; 4924 4925 static const struct rtw_intf_phy_para_table phy_para_table_8822c = { 4926 .usb2_para = usb2_param_8822c, 4927 .usb3_para = usb3_param_8822c, 4928 .gen1_para = pcie_gen1_param_8822c, 4929 .gen2_para = pcie_gen2_param_8822c, 4930 .n_usb2_para = ARRAY_SIZE(usb2_param_8822c), 4931 .n_usb3_para = ARRAY_SIZE(usb2_param_8822c), 4932 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822c), 4933 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822c), 4934 }; 4935 4936 static const struct rtw_rfe_def rtw8822c_rfe_defs[] = { 4937 [0] = RTW_DEF_RFE(8822c, 0, 0), 4938 [1] = RTW_DEF_RFE(8822c, 0, 0), 4939 [2] = RTW_DEF_RFE(8822c, 0, 0), 4940 [3] = RTW_DEF_RFE(8822c, 0, 0), 4941 [4] = RTW_DEF_RFE(8822c, 0, 0), 4942 [5] = RTW_DEF_RFE(8822c, 0, 5), 4943 [6] = RTW_DEF_RFE(8822c, 0, 0), 4944 }; 4945 4946 static const struct rtw_hw_reg rtw8822c_dig[] = { 4947 [0] = { .addr = 0x1d70, .mask = 0x7f }, 4948 [1] = { .addr = 0x1d70, .mask = 0x7f00 }, 4949 }; 4950 4951 static const struct rtw_ltecoex_addr rtw8822c_ltecoex_addr = { 4952 .ctrl = LTECOEX_ACCESS_CTRL, 4953 .wdata = LTECOEX_WRITE_DATA, 4954 .rdata = LTECOEX_READ_DATA, 4955 }; 4956 4957 static const struct rtw_page_table page_table_8822c[] = { 4958 {64, 64, 64, 64, 1}, 4959 {64, 64, 64, 64, 1}, 4960 {64, 64, 0, 0, 1}, 4961 {64, 64, 64, 0, 1}, 4962 {64, 64, 64, 64, 1}, 4963 }; 4964 4965 static const struct rtw_rqpn rqpn_table_8822c[] = { 4966 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 4967 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 4968 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 4969 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 4970 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 4971 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 4972 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 4973 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 4974 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 4975 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 4976 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 4977 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 4978 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 4979 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 4980 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 4981 }; 4982 4983 static struct rtw_prioq_addrs prioq_addrs_8822c = { 4984 .prio[RTW_DMA_MAPPING_EXTRA] = { 4985 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2, 4986 }, 4987 .prio[RTW_DMA_MAPPING_LOW] = { 4988 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2, 4989 }, 4990 .prio[RTW_DMA_MAPPING_NORMAL] = { 4991 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2, 4992 }, 4993 .prio[RTW_DMA_MAPPING_HIGH] = { 4994 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2, 4995 }, 4996 .wsize = true, 4997 }; 4998 4999 static struct rtw_chip_ops rtw8822c_ops = { 5000 .phy_set_param = rtw8822c_phy_set_param, 5001 .read_efuse = rtw8822c_read_efuse, 5002 .query_rx_desc = rtw8822c_query_rx_desc, 5003 .set_channel = rtw8822c_set_channel, 5004 .mac_init = rtw8822c_mac_init, 5005 .dump_fw_crash = rtw8822c_dump_fw_crash, 5006 .read_rf = rtw_phy_read_rf, 5007 .write_rf = rtw_phy_write_rf_reg_mix, 5008 .set_tx_power_index = rtw8822c_set_tx_power_index, 5009 .set_antenna = rtw8822c_set_antenna, 5010 .cfg_ldo25 = rtw8822c_cfg_ldo25, 5011 .false_alarm_statistics = rtw8822c_false_alarm_statistics, 5012 .dpk_track = rtw8822c_dpk_track, 5013 .phy_calibration = rtw8822c_phy_calibration, 5014 .cck_pd_set = rtw8822c_phy_cck_pd_set, 5015 .pwr_track = rtw8822c_pwr_track, 5016 .config_bfee = rtw8822c_bf_config_bfee, 5017 .set_gid_table = rtw_bf_set_gid_table, 5018 .cfg_csi_rate = rtw_bf_cfg_csi_rate, 5019 .adaptivity_init = rtw8822c_adaptivity_init, 5020 .adaptivity = rtw8822c_adaptivity, 5021 .cfo_init = rtw8822c_cfo_init, 5022 .cfo_track = rtw8822c_cfo_track, 5023 .config_tx_path = rtw8822c_config_tx_path, 5024 .config_txrx_mode = rtw8822c_config_trx_mode, 5025 .fill_txdesc_checksum = rtw8822c_fill_txdesc_checksum, 5026 5027 .coex_set_init = rtw8822c_coex_cfg_init, 5028 .coex_set_ant_switch = NULL, 5029 .coex_set_gnt_fix = rtw8822c_coex_cfg_gnt_fix, 5030 .coex_set_gnt_debug = rtw8822c_coex_cfg_gnt_debug, 5031 .coex_set_rfe_type = rtw8822c_coex_cfg_rfe_type, 5032 .coex_set_wl_tx_power = rtw8822c_coex_cfg_wl_tx_power, 5033 .coex_set_wl_rx_gain = rtw8822c_coex_cfg_wl_rx_gain, 5034 }; 5035 5036 /* Shared-Antenna Coex Table */ 5037 static const struct coex_table_para table_sant_8822c[] = { 5038 {0xffffffff, 0xffffffff}, /* case-0 */ 5039 {0x55555555, 0x55555555}, 5040 {0x66555555, 0x66555555}, 5041 {0xaaaaaaaa, 0xaaaaaaaa}, 5042 {0x5a5a5a5a, 0x5a5a5a5a}, 5043 {0xfafafafa, 0xfafafafa}, /* case-5 */ 5044 {0x6a5a5555, 0xaaaaaaaa}, 5045 {0x6a5a56aa, 0x6a5a56aa}, 5046 {0x6a5a5a5a, 0x6a5a5a5a}, 5047 {0x66555555, 0x5a5a5a5a}, 5048 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 5049 {0x66555555, 0x6a5a5aaa}, 5050 {0x66555555, 0x5a5a5aaa}, 5051 {0x66555555, 0x6aaa5aaa}, 5052 {0x66555555, 0xaaaa5aaa}, 5053 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 5054 {0xffff55ff, 0xfafafafa}, 5055 {0xffff55ff, 0x6afa5afa}, 5056 {0xaaffffaa, 0xfafafafa}, 5057 {0xaa5555aa, 0x5a5a5a5a}, 5058 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 5059 {0xaa5555aa, 0xaaaaaaaa}, 5060 {0xffffffff, 0x5a5a5a5a}, 5061 {0xffffffff, 0x5a5a5a5a}, 5062 {0xffffffff, 0x55555555}, 5063 {0xffffffff, 0x5a5a5aaa}, /* case-25 */ 5064 {0x55555555, 0x5a5a5a5a}, 5065 {0x55555555, 0xaaaaaaaa}, 5066 {0x55555555, 0x6a5a6a5a}, 5067 {0x66556655, 0x66556655}, 5068 {0x66556aaa, 0x6a5a6aaa}, /*case-30*/ 5069 {0xffffffff, 0x5aaa5aaa}, 5070 {0x56555555, 0x5a5a5aaa}, 5071 {0xdaffdaff, 0xdaffdaff}, 5072 {0xddffddff, 0xddffddff}, 5073 }; 5074 5075 /* Non-Shared-Antenna Coex Table */ 5076 static const struct coex_table_para table_nsant_8822c[] = { 5077 {0xffffffff, 0xffffffff}, /* case-100 */ 5078 {0x55555555, 0x55555555}, 5079 {0x66555555, 0x66555555}, 5080 {0xaaaaaaaa, 0xaaaaaaaa}, 5081 {0x5a5a5a5a, 0x5a5a5a5a}, 5082 {0xfafafafa, 0xfafafafa}, /* case-105 */ 5083 {0x5afa5afa, 0x5afa5afa}, 5084 {0x55555555, 0xfafafafa}, 5085 {0x66555555, 0xfafafafa}, 5086 {0x66555555, 0x5a5a5a5a}, 5087 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 5088 {0x66555555, 0xaaaaaaaa}, 5089 {0xffff55ff, 0xfafafafa}, 5090 {0xffff55ff, 0x5afa5afa}, 5091 {0xffff55ff, 0xaaaaaaaa}, 5092 {0xffff55ff, 0xffff55ff}, /* case-115 */ 5093 {0xaaffffaa, 0x5afa5afa}, 5094 {0xaaffffaa, 0xaaaaaaaa}, 5095 {0xffffffff, 0xfafafafa}, 5096 {0xffffffff, 0x5afa5afa}, 5097 {0xffffffff, 0xaaaaaaaa}, /* case-120 */ 5098 {0x55ff55ff, 0x5afa5afa}, 5099 {0x55ff55ff, 0xaaaaaaaa}, 5100 {0x55ff55ff, 0x55ff55ff} 5101 }; 5102 5103 /* Shared-Antenna TDMA */ 5104 static const struct coex_tdma_para tdma_sant_8822c[] = { 5105 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 5106 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */ 5107 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 5108 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 5109 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 5110 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ 5111 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 5112 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 5113 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 5114 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 5115 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 5116 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 5117 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 5118 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 5119 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 5120 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 5121 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 5122 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 5123 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 5124 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 5125 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 5126 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 5127 { {0x51, 0x0c, 0x03, 0x10, 0x54} }, 5128 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 5129 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 5130 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 5131 { {0x51, 0x08, 0x03, 0x10, 0x50} }, 5132 { {0x61, 0x08, 0x03, 0x11, 0x11} } 5133 }; 5134 5135 /* Non-Shared-Antenna TDMA */ 5136 static const struct coex_tdma_para tdma_nsant_8822c[] = { 5137 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */ 5138 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 5139 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 5140 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 5141 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 5142 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 5143 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 5144 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 5145 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 5146 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 5147 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 5148 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 5149 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 5150 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 5151 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 5152 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 5153 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 5154 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 5155 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 5156 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 5157 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */ 5158 { {0x51, 0x08, 0x03, 0x10, 0x50} } 5159 }; 5160 5161 /* rssi in percentage % (dbm = % - 100) */ 5162 static const u8 wl_rssi_step_8822c[] = {60, 50, 44, 30}; 5163 static const u8 bt_rssi_step_8822c[] = {8, 15, 20, 25}; 5164 static const struct coex_5g_afh_map afh_5g_8822c[] = { {0, 0, 0} }; 5165 5166 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 5167 static const struct coex_rf_para rf_para_tx_8822c[] = { 5168 {0, 0, false, 7}, /* for normal */ 5169 {0, 16, false, 7}, /* for WL-CPT */ 5170 {8, 17, true, 4}, 5171 {7, 18, true, 4}, 5172 {6, 19, true, 4}, 5173 {5, 20, true, 4}, 5174 {0, 21, true, 4} /* for gamg hid */ 5175 }; 5176 5177 static const struct coex_rf_para rf_para_rx_8822c[] = { 5178 {0, 0, false, 7}, /* for normal */ 5179 {0, 16, false, 7}, /* for WL-CPT */ 5180 {3, 24, true, 5}, 5181 {2, 26, true, 5}, 5182 {1, 27, true, 5}, 5183 {0, 28, true, 5}, 5184 {0, 28, true, 5} /* for gamg hid */ 5185 }; 5186 5187 #if defined(__linux__) 5188 static_assert(ARRAY_SIZE(rf_para_tx_8822c) == ARRAY_SIZE(rf_para_rx_8822c)); 5189 #elif defined(__FreeBSD__) 5190 rtw88_static_assert(ARRAY_SIZE(rf_para_tx_8822c) == ARRAY_SIZE(rf_para_rx_8822c)); 5191 #endif 5192 5193 static const u8 5194 rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 5195 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 5196 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 5197 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 5198 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 5199 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 5200 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 5201 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 5202 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 5203 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 5204 }; 5205 5206 static const u8 5207 rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 5208 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5209 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 5210 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 5211 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5212 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 5213 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 5214 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5215 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 5216 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 5217 }; 5218 5219 static const u8 5220 rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 5221 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 5222 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 5223 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 5224 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 5225 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 5226 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 5227 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 5228 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 5229 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 5230 }; 5231 5232 static const u8 5233 rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 5234 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5235 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 5236 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 5237 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5238 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 5239 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 5240 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5241 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 5242 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 5243 }; 5244 5245 static const u8 rtw8822c_pwrtrk_2gb_n[RTW_PWR_TRK_TBL_SZ] = { 5246 0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 5247 9, 9, 10, 11, 12, 13, 14, 15, 15, 16, 5248 17, 18, 19, 20, 20, 21, 22, 23, 24, 25 5249 }; 5250 5251 static const u8 rtw8822c_pwrtrk_2gb_p[RTW_PWR_TRK_TBL_SZ] = { 5252 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5253 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 5254 19, 20, 21, 22, 23, 24, 25, 26, 27, 28 5255 }; 5256 5257 static const u8 rtw8822c_pwrtrk_2ga_n[RTW_PWR_TRK_TBL_SZ] = { 5258 0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 5259 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 5260 13, 14, 15, 15, 16, 17, 17, 18, 19, 19 5261 }; 5262 5263 static const u8 rtw8822c_pwrtrk_2ga_p[RTW_PWR_TRK_TBL_SZ] = { 5264 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5265 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 5266 19, 20, 21, 22, 23, 24, 25, 25, 26, 27 5267 }; 5268 5269 static const u8 rtw8822c_pwrtrk_2g_cck_b_n[RTW_PWR_TRK_TBL_SZ] = { 5270 0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 5271 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 5272 17, 18, 19, 20, 21, 22, 23, 23, 24, 25 5273 }; 5274 5275 static const u8 rtw8822c_pwrtrk_2g_cck_b_p[RTW_PWR_TRK_TBL_SZ] = { 5276 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 5277 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 5278 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 5279 }; 5280 5281 static const u8 rtw8822c_pwrtrk_2g_cck_a_n[RTW_PWR_TRK_TBL_SZ] = { 5282 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 5283 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 5284 15, 16, 17, 18, 18, 19, 20, 21, 21, 22 5285 }; 5286 5287 static const u8 rtw8822c_pwrtrk_2g_cck_a_p[RTW_PWR_TRK_TBL_SZ] = { 5288 0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 5289 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 5290 18, 18, 19, 20, 21, 22, 23, 24, 24, 25 5291 }; 5292 5293 static const struct rtw_pwr_track_tbl rtw8822c_rtw_pwr_track_tbl = { 5294 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_1], 5295 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_2], 5296 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_3], 5297 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_1], 5298 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_2], 5299 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_3], 5300 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_1], 5301 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_2], 5302 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_3], 5303 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_1], 5304 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_2], 5305 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_3], 5306 .pwrtrk_2gb_n = rtw8822c_pwrtrk_2gb_n, 5307 .pwrtrk_2gb_p = rtw8822c_pwrtrk_2gb_p, 5308 .pwrtrk_2ga_n = rtw8822c_pwrtrk_2ga_n, 5309 .pwrtrk_2ga_p = rtw8822c_pwrtrk_2ga_p, 5310 .pwrtrk_2g_cckb_n = rtw8822c_pwrtrk_2g_cck_b_n, 5311 .pwrtrk_2g_cckb_p = rtw8822c_pwrtrk_2g_cck_b_p, 5312 .pwrtrk_2g_ccka_n = rtw8822c_pwrtrk_2g_cck_a_n, 5313 .pwrtrk_2g_ccka_p = rtw8822c_pwrtrk_2g_cck_a_p, 5314 }; 5315 5316 static struct rtw_hw_reg_offset rtw8822c_edcca_th[] = { 5317 [EDCCA_TH_L2H_IDX] = { 5318 {.addr = 0x84c, .mask = MASKBYTE2}, .offset = 0x80 5319 }, 5320 [EDCCA_TH_H2L_IDX] = { 5321 {.addr = 0x84c, .mask = MASKBYTE3}, .offset = 0x80 5322 }, 5323 }; 5324 5325 #ifdef CONFIG_PM 5326 static const struct wiphy_wowlan_support rtw_wowlan_stub_8822c = { 5327 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_GTK_REKEY_FAILURE | 5328 WIPHY_WOWLAN_DISCONNECT | WIPHY_WOWLAN_SUPPORTS_GTK_REKEY | 5329 WIPHY_WOWLAN_NET_DETECT, 5330 .n_patterns = RTW_MAX_PATTERN_NUM, 5331 .pattern_max_len = RTW_MAX_PATTERN_SIZE, 5332 .pattern_min_len = 1, 5333 .max_nd_match_sets = 4, 5334 }; 5335 #endif 5336 5337 static const struct rtw_reg_domain coex_info_hw_regs_8822c[] = { 5338 {0x1860, BIT(3), RTW_REG_DOMAIN_MAC8}, 5339 {0x4160, BIT(3), RTW_REG_DOMAIN_MAC8}, 5340 {0x1c32, BIT(6), RTW_REG_DOMAIN_MAC8}, 5341 {0x1c38, BIT(28), RTW_REG_DOMAIN_MAC32}, 5342 {0, 0, RTW_REG_DOMAIN_NL}, 5343 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 5344 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 5345 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 5346 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 5347 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 5348 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 5349 {0, 0, RTW_REG_DOMAIN_NL}, 5350 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32}, 5351 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8}, 5352 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 5353 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 5354 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B}, 5355 {0, 0, RTW_REG_DOMAIN_NL}, 5356 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 5357 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 5358 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 5359 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 5360 }; 5361 5362 const struct rtw_chip_info rtw8822c_hw_spec = { 5363 .ops = &rtw8822c_ops, 5364 .id = RTW_CHIP_TYPE_8822C, 5365 .fw_name = "rtw88/rtw8822c_fw.bin", 5366 .wlan_cpu = RTW_WCPU_11AC, 5367 .tx_pkt_desc_sz = 48, 5368 .tx_buf_desc_sz = 16, 5369 .rx_pkt_desc_sz = 24, 5370 .rx_buf_desc_sz = 8, 5371 .phy_efuse_size = 512, 5372 .log_efuse_size = 768, 5373 .ptct_efuse_size = 124, 5374 .txff_size = 262144, 5375 .rxff_size = 24576, 5376 .fw_rxff_size = 12288, 5377 .rsvd_drv_pg_num = 16, 5378 .txgi_factor = 2, 5379 .is_pwr_by_rate_dec = false, 5380 .max_power_index = 0x7f, 5381 .csi_buf_pg_num = 50, 5382 .band = RTW_BAND_2G | RTW_BAND_5G, 5383 .page_size = TX_PAGE_SIZE, 5384 .dig_min = 0x20, 5385 .default_1ss_tx_path = BB_PATH_A, 5386 .path_div_supported = true, 5387 .ht_supported = true, 5388 .vht_supported = true, 5389 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK) | BIT(LPS_DEEP_MODE_PG), 5390 .sys_func_en = 0xD8, 5391 .pwr_on_seq = card_enable_flow_8822c, 5392 .pwr_off_seq = card_disable_flow_8822c, 5393 .page_table = page_table_8822c, 5394 .rqpn_table = rqpn_table_8822c, 5395 .prioq_addrs = &prioq_addrs_8822c, 5396 .intf_table = &phy_para_table_8822c, 5397 .dig = rtw8822c_dig, 5398 .dig_cck = NULL, 5399 .rf_base_addr = {0x3c00, 0x4c00}, 5400 .rf_sipi_addr = {0x1808, 0x4108}, 5401 .ltecoex_addr = &rtw8822c_ltecoex_addr, 5402 .mac_tbl = &rtw8822c_mac_tbl, 5403 .agc_tbl = &rtw8822c_agc_tbl, 5404 .bb_tbl = &rtw8822c_bb_tbl, 5405 .rfk_init_tbl = &rtw8822c_array_mp_cal_init_tbl, 5406 .rf_tbl = {&rtw8822c_rf_b_tbl, &rtw8822c_rf_a_tbl}, 5407 .rfe_defs = rtw8822c_rfe_defs, 5408 .rfe_defs_size = ARRAY_SIZE(rtw8822c_rfe_defs), 5409 .en_dis_dpd = true, 5410 .dpd_ratemask = DIS_DPD_RATEALL, 5411 .pwr_track_tbl = &rtw8822c_rtw_pwr_track_tbl, 5412 .iqk_threshold = 8, 5413 .lck_threshold = 8, 5414 .bfer_su_max_num = 2, 5415 .bfer_mu_max_num = 1, 5416 .rx_ldpc = true, 5417 .tx_stbc = true, 5418 .edcca_th = rtw8822c_edcca_th, 5419 .l2h_th_ini_cs = 60, 5420 .l2h_th_ini_ad = 45, 5421 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_2, 5422 5423 #ifdef CONFIG_PM 5424 .wow_fw_name = "rtw88/rtw8822c_wow_fw.bin", 5425 .wowlan_stub = &rtw_wowlan_stub_8822c, 5426 .max_sched_scan_ssids = 4, 5427 #endif 5428 .max_scan_ie_len = (RTW_PROBE_PG_CNT - 1) * TX_PAGE_SIZE, 5429 .coex_para_ver = 0x22020720, 5430 .bt_desired_ver = 0x20, 5431 .scbd_support = true, 5432 .new_scbd10_def = true, 5433 .ble_hid_profile_support = true, 5434 .wl_mimo_ps_support = true, 5435 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 5436 .bt_rssi_type = COEX_BTRSSI_DBM, 5437 .ant_isolation = 15, 5438 .rssi_tolerance = 2, 5439 .wl_rssi_step = wl_rssi_step_8822c, 5440 .bt_rssi_step = bt_rssi_step_8822c, 5441 .table_sant_num = ARRAY_SIZE(table_sant_8822c), 5442 .table_sant = table_sant_8822c, 5443 .table_nsant_num = ARRAY_SIZE(table_nsant_8822c), 5444 .table_nsant = table_nsant_8822c, 5445 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822c), 5446 .tdma_sant = tdma_sant_8822c, 5447 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822c), 5448 .tdma_nsant = tdma_nsant_8822c, 5449 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822c), 5450 .wl_rf_para_tx = rf_para_tx_8822c, 5451 .wl_rf_para_rx = rf_para_rx_8822c, 5452 .bt_afh_span_bw20 = 0x24, 5453 .bt_afh_span_bw40 = 0x36, 5454 .afh_5g_num = ARRAY_SIZE(afh_5g_8822c), 5455 .afh_5g = afh_5g_8822c, 5456 5457 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8822c), 5458 .coex_info_hw_regs = coex_info_hw_regs_8822c, 5459 5460 .fw_fifo_addr = {0x780, 0x700, 0x780, 0x660, 0x650, 0x680}, 5461 .fwcd_segs = &rtw8822c_fwcd_segs, 5462 }; 5463 EXPORT_SYMBOL(rtw8822c_hw_spec); 5464 5465 MODULE_FIRMWARE("rtw88/rtw8822c_fw.bin"); 5466 MODULE_FIRMWARE("rtw88/rtw8822c_wow_fw.bin"); 5467 5468 MODULE_AUTHOR("Realtek Corporation"); 5469 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8822c driver"); 5470 MODULE_LICENSE("Dual BSD/GPL"); 5471