1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2025 Realtek Corporation 3 */ 4 5 #include <linux/usb.h> 6 #include "main.h" 7 #include "coex.h" 8 #include "tx.h" 9 #include "phy.h" 10 #include "rtw8814a.h" 11 #include "rtw8814a_table.h" 12 #include "rtw88xxa.h" 13 #include "reg.h" 14 #include "debug.h" 15 #include "efuse.h" 16 #include "regd.h" 17 #include "usb.h" 18 19 static void rtw8814a_efuse_grant(struct rtw_dev *rtwdev, bool on) 20 { 21 if (on) { 22 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); 23 24 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_ELDR); 25 rtw_write16_set(rtwdev, REG_SYS_CLKR, 26 BIT_LOADER_CLK_EN | BIT_ANA8M); 27 } else { 28 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF); 29 } 30 } 31 32 static void rtw8814a_read_rfe_type(struct rtw_dev *rtwdev) 33 { 34 struct rtw_efuse *efuse = &rtwdev->efuse; 35 36 if (!(efuse->rfe_option & BIT(7))) 37 return; 38 39 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE) 40 efuse->rfe_option = 0; 41 else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) 42 efuse->rfe_option = 1; 43 } 44 45 static void rtw8814a_read_amplifier_type(struct rtw_dev *rtwdev) 46 { 47 struct rtw_efuse *efuse = &rtwdev->efuse; 48 49 switch (efuse->rfe_option) { 50 case 1: 51 /* Internal 2G */ 52 efuse->pa_type_2g = 0; 53 efuse->lna_type_2g = 0; 54 /* External 5G */ 55 efuse->pa_type_5g = BIT(0); 56 efuse->lna_type_5g = BIT(3); 57 break; 58 case 2 ... 5: 59 /* External everything */ 60 efuse->pa_type_2g = BIT(4); 61 efuse->lna_type_2g = BIT(3); 62 efuse->pa_type_5g = BIT(0); 63 efuse->lna_type_5g = BIT(3); 64 break; 65 case 6: 66 efuse->lna_type_5g = BIT(3); 67 break; 68 default: 69 break; 70 } 71 } 72 73 static void rtw8814a_read_rf_type(struct rtw_dev *rtwdev, 74 struct rtw8814a_efuse *map) 75 { 76 #if IS_ENABLED(CONFIG_RTW88_USB) 77 struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev); 78 #endif 79 struct rtw_hal *hal = &rtwdev->hal; 80 81 switch (map->trx_antenna_option) { 82 case 0xff: /* 4T4R */ 83 case 0xee: /* 3T3R */ 84 #if IS_ENABLED(CONFIG_RTW88_USB) 85 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB && 86 rtwusb->udev->speed != USB_SPEED_SUPER) 87 hal->rf_type = RF_2T2R; 88 else 89 #endif 90 hal->rf_type = RF_3T3R; 91 92 break; 93 case 0x66: /* 2T2R */ 94 case 0x6f: /* 2T4R */ 95 default: 96 hal->rf_type = RF_2T2R; 97 break; 98 } 99 100 hal->rf_path_num = 4; 101 hal->rf_phy_num = 4; 102 103 if (hal->rf_type == RF_3T3R) { 104 hal->antenna_rx = BB_PATH_ABC; 105 hal->antenna_tx = BB_PATH_ABC; 106 } else { 107 hal->antenna_rx = BB_PATH_AB; 108 hal->antenna_tx = BB_PATH_AB; 109 } 110 } 111 112 static void rtw8814a_init_hwcap(struct rtw_dev *rtwdev) 113 { 114 struct rtw_efuse *efuse = &rtwdev->efuse; 115 struct rtw_hal *hal = &rtwdev->hal; 116 117 efuse->hw_cap.bw = BIT(RTW_CHANNEL_WIDTH_20) | 118 BIT(RTW_CHANNEL_WIDTH_40) | 119 BIT(RTW_CHANNEL_WIDTH_80); 120 efuse->hw_cap.ptcl = EFUSE_HW_CAP_PTCL_VHT; 121 122 if (hal->rf_type == RF_3T3R) 123 efuse->hw_cap.nss = 3; 124 else 125 efuse->hw_cap.nss = 2; 126 127 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 128 "hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n", 129 efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl, 130 efuse->hw_cap.ant_num, efuse->hw_cap.nss); 131 } 132 133 static int rtw8814a_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 134 { 135 struct rtw_efuse *efuse = &rtwdev->efuse; 136 struct rtw8814a_efuse *map; 137 int i; 138 139 if (rtw_dbg_is_enabled(rtwdev, RTW_DBG_EFUSE)) 140 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 141 log_map, rtwdev->chip->log_efuse_size, true); 142 143 map = (struct rtw8814a_efuse *)log_map; 144 145 efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(4)); 146 efuse->rfe_option = map->rfe_option; 147 efuse->rf_board_option = map->rf_board_option; 148 efuse->crystal_cap = map->xtal_k; 149 efuse->channel_plan = map->channel_plan; 150 efuse->country_code[0] = map->country_code[0]; 151 efuse->country_code[1] = map->country_code[1]; 152 efuse->bt_setting = map->rf_bt_setting; 153 efuse->regd = map->rf_board_option & 0x7; 154 efuse->thermal_meter[RF_PATH_A] = map->thermal_meter; 155 efuse->thermal_meter_k = map->thermal_meter; 156 efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g; 157 efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g; 158 159 rtw8814a_read_rfe_type(rtwdev); 160 rtw8814a_read_amplifier_type(rtwdev); 161 162 /* Override rtw_chip_parameter_setup() */ 163 rtw8814a_read_rf_type(rtwdev, map); 164 165 rtw8814a_init_hwcap(rtwdev); 166 167 for (i = 0; i < 4; i++) 168 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 169 170 switch (rtw_hci_type(rtwdev)) { 171 case RTW_HCI_TYPE_USB: 172 ether_addr_copy(efuse->addr, map->u.mac_addr); 173 break; 174 case RTW_HCI_TYPE_PCIE: 175 ether_addr_copy(efuse->addr, map->e.mac_addr); 176 break; 177 case RTW_HCI_TYPE_SDIO: 178 default: 179 /* unsupported now */ 180 return -EOPNOTSUPP; 181 } 182 183 return 0; 184 } 185 186 static void rtw8814a_init_rfe_reg(struct rtw_dev *rtwdev) 187 { 188 u8 rfe_option = rtwdev->efuse.rfe_option; 189 190 if (rfe_option == 2 || rfe_option == 1) { 191 rtw_write32_mask(rtwdev, 0x1994, 0xf, 0xf); 192 rtw_write8_set(rtwdev, REG_GPIO_MUXCFG + 2, 0xf0); 193 } else if (rfe_option == 0) { 194 rtw_write32_mask(rtwdev, 0x1994, 0xf, 0xf); 195 rtw_write8_set(rtwdev, REG_GPIO_MUXCFG + 2, 0xc0); 196 } 197 } 198 199 #define RTW_TXSCALE_SIZE 37 200 static const u32 rtw8814a_txscale_tbl[RTW_TXSCALE_SIZE] = { 201 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8, 202 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180, 203 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab, 204 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe 205 }; 206 207 static u32 rtw8814a_get_bb_swing(struct rtw_dev *rtwdev, u8 band, u8 rf_path) 208 { 209 static const u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6}; 210 struct rtw_efuse *efuse = &rtwdev->efuse; 211 u8 tx_bb_swing; 212 213 if (band == RTW_BAND_2G) 214 tx_bb_swing = efuse->tx_bb_swing_setting_2g; 215 else 216 tx_bb_swing = efuse->tx_bb_swing_setting_5g; 217 218 tx_bb_swing >>= 2 * rf_path; 219 tx_bb_swing &= 0x3; 220 221 return swing2setting[tx_bb_swing]; 222 } 223 224 static u8 rtw8814a_get_swing_index(struct rtw_dev *rtwdev) 225 { 226 u32 swing, table_value; 227 u8 i; 228 229 swing = rtw8814a_get_bb_swing(rtwdev, rtwdev->hal.current_band_type, 230 RF_PATH_A); 231 232 for (i = 0; i < ARRAY_SIZE(rtw8814a_txscale_tbl); i++) { 233 table_value = rtw8814a_txscale_tbl[i]; 234 if (swing == table_value) 235 return i; 236 } 237 238 return 24; 239 } 240 241 static void rtw8814a_pwrtrack_init(struct rtw_dev *rtwdev) 242 { 243 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 244 u8 path; 245 246 dm_info->default_ofdm_index = rtw8814a_get_swing_index(rtwdev); 247 248 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) { 249 ewma_thermal_init(&dm_info->avg_thermal[path]); 250 dm_info->delta_power_index[path] = 0; 251 dm_info->delta_power_index_last[path] = 0; 252 } 253 dm_info->pwr_trk_triggered = false; 254 dm_info->pwr_trk_init_trigger = true; 255 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 256 } 257 258 static void rtw8814a_config_trx_path(struct rtw_dev *rtwdev) 259 { 260 /* RX CCK disable 2R CCA */ 261 rtw_write32_clr(rtwdev, REG_CCK0_FAREPORT, 262 BIT_CCK0_2RX | BIT_CCK0_MRC); 263 /* pathB tx on, path A/C/D tx off */ 264 rtw_write32_mask(rtwdev, REG_CCK_RX, 0xf0000000, 0x4); 265 /* pathB rx */ 266 rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0x5); 267 } 268 269 static void rtw8814a_config_cck_rx_antenna_init(struct rtw_dev *rtwdev) 270 { 271 /* CCK 2R CCA parameters */ 272 273 /* Disable Ant diversity */ 274 rtw_write32_mask(rtwdev, REG_RXSB, BIT_RXSB_ANA_DIV, 0x0); 275 /* Concurrent CCA at LSB & USB */ 276 rtw_write32_mask(rtwdev, REG_CCA, BIT_CCA_CO, 0); 277 /* RX path diversity enable */ 278 rtw_write32_mask(rtwdev, REG_ANTSEL, BIT_ANT_BYCO, 0); 279 /* r_en_mrc_antsel */ 280 rtw_write32_mask(rtwdev, REG_PRECTRL, BIT_DIS_CO_PATHSEL, 0); 281 /* MBC weighting */ 282 rtw_write32_mask(rtwdev, REG_CCA_MF, BIT_MBC_WIN, 1); 283 /* 2R CCA only */ 284 rtw_write32_mask(rtwdev, REG_CCKTX, BIT_CMB_CCA_2R, 1); 285 } 286 287 static void rtw8814a_phy_set_param(struct rtw_dev *rtwdev) 288 { 289 u32 crystal_cap, val32; 290 u8 val8, rf_path; 291 292 /* power on BB/RF domain */ 293 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) 294 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_USBA); 295 else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE) 296 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_PCIEA); 297 298 rtw_write8_set(rtwdev, REG_SYS_CFG3_8814A + 2, 299 BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB); 300 301 /* Power on RF paths A..D */ 302 val8 = BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB; 303 rtw_write8(rtwdev, REG_RF_CTRL, val8); 304 rtw_write8(rtwdev, REG_RF_CTRL1, val8); 305 rtw_write8(rtwdev, REG_RF_CTRL2, val8); 306 rtw_write8(rtwdev, REG_RF_CTRL3, val8); 307 308 rtw_load_table(rtwdev, rtwdev->chip->bb_tbl); 309 rtw_load_table(rtwdev, rtwdev->chip->agc_tbl); 310 311 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; 312 crystal_cap |= crystal_cap << 6; 313 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, 0x07ff8000, crystal_cap); 314 315 rtw8814a_config_trx_path(rtwdev); 316 317 for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++) 318 rtw_load_table(rtwdev, rtwdev->chip->rf_tbl[rf_path]); 319 320 val32 = rtw_read_rf(rtwdev, RF_PATH_A, RF_RCK1_V1, RFREG_MASK); 321 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK1_V1, RFREG_MASK, val32); 322 rtw_write_rf(rtwdev, RF_PATH_C, RF_RCK1_V1, RFREG_MASK, val32); 323 rtw_write_rf(rtwdev, RF_PATH_D, RF_RCK1_V1, RFREG_MASK, val32); 324 325 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 326 327 rtw_write8(rtwdev, REG_HWSEQ_CTRL, 0xFF); 328 329 rtw_write32(rtwdev, REG_BAR_MODE_CTRL, 0x0201ffff); 330 331 rtw_write8(rtwdev, REG_MISC_CTRL, BIT_DIS_SECOND_CCA); 332 333 rtw_write8(rtwdev, REG_NAV_CTRL + 2, 0); 334 335 rtw_write8_clr(rtwdev, REG_GPIO_MUXCFG, BIT(5)); 336 337 rtw8814a_config_cck_rx_antenna_init(rtwdev); 338 339 rtw_phy_init(rtwdev); 340 rtw8814a_pwrtrack_init(rtwdev); 341 342 rtw8814a_init_rfe_reg(rtwdev); 343 344 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT(3)); 345 346 rtw_write8(rtwdev, REG_NAV_CTRL + 2, 235); 347 348 /* enable Tx report. */ 349 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, 0x1F); 350 351 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) { 352 /* Reset USB mode switch setting */ 353 rtw_write8(rtwdev, REG_SYS_SDIO_CTRL, 0x0); 354 rtw_write8(rtwdev, REG_ACLK_MON, 0x0); 355 } 356 } 357 358 static void rtw8814ae_enable_rf_1_2v(struct rtw_dev *rtwdev) 359 { 360 /* This is for fullsize card, because GPIO7 there is floating. 361 * We should pull GPIO7 high to enable RF 1.2V Switch Power Supply 362 */ 363 364 /* 1. set 0x40[1:0] to 0, BIT_GPIOSEL=0, select pin as GPIO */ 365 rtw_write8_clr(rtwdev, REG_GPIO_MUXCFG, BIT(1) | BIT(0)); 366 367 /* 2. set 0x44[31] to 0 368 * mode=0: data port; 369 * mode=1 and BIT_GPIO_IO_SEL=0: interrupt mode; 370 */ 371 rtw_write8_clr(rtwdev, REG_GPIO_PIN_CTRL + 3, BIT(7)); 372 373 /* 3. data mode 374 * 3.1 set 0x44[23] to 1 375 * sel=0: input; 376 * sel=1: output; 377 */ 378 rtw_write8_set(rtwdev, REG_GPIO_PIN_CTRL + 2, BIT(7)); 379 380 /* 3.2 set 0x44[15] to 1 381 * output high value; 382 */ 383 rtw_write8_set(rtwdev, REG_GPIO_PIN_CTRL + 1, BIT(7)); 384 } 385 386 static int rtw8814a_mac_init(struct rtw_dev *rtwdev) 387 { 388 #if IS_ENABLED(CONFIG_RTW88_USB) 389 struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev); 390 #endif 391 392 rtw_write16(rtwdev, REG_CR, 393 MAC_TRX_ENABLE | BIT_MAC_SEC_EN | BIT_32K_CAL_TMR_EN); 394 395 rtw_load_table(rtwdev, rtwdev->chip->mac_tbl); 396 397 #if IS_ENABLED(CONFIG_RTW88_USB) 398 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) 399 rtw_write8(rtwdev, REG_AUTO_LLT_V1 + 3, 400 rtwdev->chip->usb_tx_agg_desc_num << 1); 401 #endif 402 403 rtw_write32(rtwdev, REG_HIMR0, 0); 404 rtw_write32(rtwdev, REG_HIMR1, 0); 405 406 rtw_write32_mask(rtwdev, REG_RRSR, 0xfffff, 0xfffff); 407 408 rtw_write16(rtwdev, REG_RETRY_LIMIT, 0x3030); 409 410 rtw_write16(rtwdev, REG_RXFLTMAP0, 0xffff); 411 rtw_write16(rtwdev, REG_RXFLTMAP1, 0x0400); 412 rtw_write16(rtwdev, REG_RXFLTMAP2, 0xffff); 413 414 rtw_write8(rtwdev, REG_MAX_AGGR_NUM, 0x36); 415 rtw_write8(rtwdev, REG_MAX_AGGR_NUM + 1, 0x36); 416 417 /* Set Spec SIFS (used in NAV) */ 418 rtw_write16(rtwdev, REG_SPEC_SIFS, 0x100a); 419 rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, 0x100a); 420 421 /* Set SIFS for CCK */ 422 rtw_write16(rtwdev, REG_SIFS, 0x100a); 423 424 /* Set SIFS for OFDM */ 425 rtw_write16(rtwdev, REG_SIFS + 2, 0x100a); 426 427 /* TXOP */ 428 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, 0x005EA42B); 429 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, 0x0000A44F); 430 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, 0x005EA324); 431 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, 0x002FA226); 432 433 rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL, BIT(7)); 434 435 rtw_write8(rtwdev, REG_ACKTO, 0x80); 436 437 rtw_write16(rtwdev, REG_BCN_CTRL, 438 BIT_DIS_TSF_UDT | (BIT_DIS_TSF_UDT << 8)); 439 rtw_write32_mask(rtwdev, REG_TBTT_PROHIBIT, 0xfffff, WLAN_TBTT_TIME); 440 rtw_write8(rtwdev, REG_DRVERLYINT, 0x05); 441 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 442 rtw_write16(rtwdev, REG_BCNTCFG, 0x4413); 443 rtw_write8(rtwdev, REG_BCN_MAX_ERR, 0xFF); 444 445 rtw_write32(rtwdev, REG_FAST_EDCA_VOVI_SETTING, 0x08070807); 446 rtw_write32(rtwdev, REG_FAST_EDCA_BEBK_SETTING, 0x08070807); 447 448 #if IS_ENABLED(CONFIG_RTW88_USB) 449 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB && 450 rtwusb->udev->speed == USB_SPEED_SUPER) { 451 /* Disable U1/U2 Mode to avoid 2.5G spur in USB3.0. */ 452 rtw_write8_clr(rtwdev, REG_USB_MOD, BIT(4) | BIT(3)); 453 /* To avoid usb 3.0 H2C fail. */ 454 rtw_write16(rtwdev, 0xf002, 0); 455 456 rtw_write8_clr(rtwdev, REG_SW_AMPDU_BURST_MODE_CTRL, 457 BIT_PRE_TX_CMD); 458 } else 459 #endif 460 if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE) { 461 rtw8814ae_enable_rf_1_2v(rtwdev); 462 463 /* Force the antenna b to wifi. */ 464 rtw_write8_set(rtwdev, REG_PAD_CTRL1, BIT(2)); 465 rtw_write8_set(rtwdev, REG_PAD_CTRL1 + 1, BIT(0)); 466 rtw_write8_set(rtwdev, REG_LED_CFG + 3, 467 (BIT(27) | BIT_DPDT_WL_SEL) >> 24); 468 } 469 470 return 0; 471 } 472 473 static void rtw8814a_set_rfe_reg_24g(struct rtw_dev *rtwdev) 474 { 475 switch (rtwdev->efuse.rfe_option) { 476 case 2: 477 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x72707270); 478 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x72707270); 479 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x72707270); 480 rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77707770); 481 482 rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D, 483 BIT_RFE_SELSW0_D, 0x72); 484 485 break; 486 case 1: 487 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777); 488 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777); 489 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x77777777); 490 rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77777777); 491 492 rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D, 493 BIT_RFE_SELSW0_D, 0x77); 494 495 break; 496 case 0: 497 default: 498 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777); 499 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777); 500 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x77777777); 501 /* Is it not necessary to set REG_RFE_PINMUX_D ? */ 502 503 rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D, 504 BIT_RFE_SELSW0_D, 0x77); 505 506 break; 507 } 508 } 509 510 static void rtw8814a_set_rfe_reg_5g(struct rtw_dev *rtwdev) 511 { 512 switch (rtwdev->efuse.rfe_option) { 513 case 2: 514 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x37173717); 515 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x37173717); 516 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x37173717); 517 rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77177717); 518 519 rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D, 520 BIT_RFE_SELSW0_D, 0x37); 521 522 break; 523 case 1: 524 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x33173317); 525 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x33173317); 526 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x33173317); 527 rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77177717); 528 529 rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D, 530 BIT_RFE_SELSW0_D, 0x33); 531 532 break; 533 case 0: 534 default: 535 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x54775477); 536 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x54775477); 537 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x54775477); 538 rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x54775477); 539 540 rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D, 541 BIT_RFE_SELSW0_D, 0x54); 542 543 break; 544 } 545 } 546 547 static void rtw8814a_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 band) 548 { 549 rtw_write32_mask(rtwdev, REG_TXSCALE_A, BB_SWING_MASK, 550 rtw8814a_get_bb_swing(rtwdev, band, RF_PATH_A)); 551 rtw_write32_mask(rtwdev, REG_TXSCALE_B, BB_SWING_MASK, 552 rtw8814a_get_bb_swing(rtwdev, band, RF_PATH_B)); 553 rtw_write32_mask(rtwdev, REG_TXSCALE_C, BB_SWING_MASK, 554 rtw8814a_get_bb_swing(rtwdev, band, RF_PATH_C)); 555 rtw_write32_mask(rtwdev, REG_TXSCALE_D, BB_SWING_MASK, 556 rtw8814a_get_bb_swing(rtwdev, band, RF_PATH_D)); 557 rtw8814a_pwrtrack_init(rtwdev); 558 } 559 560 static void rtw8814a_set_bw_reg_adc(struct rtw_dev *rtwdev, u8 bw) 561 { 562 u32 adc = 0; 563 564 if (bw == RTW_CHANNEL_WIDTH_20) 565 adc = 0; 566 else if (bw == RTW_CHANNEL_WIDTH_40) 567 adc = 1; 568 else if (bw == RTW_CHANNEL_WIDTH_80) 569 adc = 2; 570 571 rtw_write32_mask(rtwdev, REG_ADCCLK, BIT(1) | BIT(0), adc); 572 } 573 574 static void rtw8814a_set_bw_reg_agc(struct rtw_dev *rtwdev, u8 new_band, u8 bw) 575 { 576 u32 agc = 7; 577 578 if (bw == RTW_CHANNEL_WIDTH_20) { 579 agc = 6; 580 } else if (bw == RTW_CHANNEL_WIDTH_40) { 581 if (new_band == RTW_BAND_5G) 582 agc = 8; 583 else 584 agc = 7; 585 } else if (bw == RTW_CHANNEL_WIDTH_80) { 586 agc = 3; 587 } 588 589 rtw_write32_mask(rtwdev, REG_CCASEL, 0xf000, agc); 590 } 591 592 static void rtw8814a_switch_band(struct rtw_dev *rtwdev, u8 new_band, u8 bw) 593 { 594 /* Clear 0x1000[16], When this bit is set to 0, CCK and OFDM 595 * are disabled, and clock are gated. Otherwise, CCK and OFDM 596 * are enabled. 597 */ 598 rtw_write8_clr(rtwdev, REG_SYS_CFG3_8814A + 2, BIT_FEN_BB_RSTB); 599 600 if (new_band == RTW_BAND_2G) { 601 rtw_write32_mask(rtwdev, REG_AGC_TABLE, 0x1f, 0); 602 603 rtw8814a_set_rfe_reg_24g(rtwdev); 604 605 rtw_write32_mask(rtwdev, REG_TXPSEL, 0xf0, 0x2); 606 rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0x5); 607 608 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST, 0x3); 609 610 rtw_write8(rtwdev, REG_CCK_CHECK, 0); 611 612 rtw_write32_mask(rtwdev, 0xa80, BIT(18), 0); 613 } else { 614 rtw_write8(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN); 615 616 /* Enable CCK Tx function, even when CCK is off */ 617 rtw_write32_mask(rtwdev, 0xa80, BIT(18), 1); 618 619 rtw8814a_set_rfe_reg_5g(rtwdev); 620 621 rtw_write32_mask(rtwdev, REG_TXPSEL, 0xf0, 0x0); 622 rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0xf); 623 624 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST, 0x2); 625 } 626 627 rtw8814a_set_channel_bb_swing(rtwdev, new_band); 628 629 rtw8814a_set_bw_reg_adc(rtwdev, bw); 630 rtw8814a_set_bw_reg_agc(rtwdev, new_band, bw); 631 632 rtw_write8_set(rtwdev, REG_SYS_CFG3_8814A + 2, BIT_FEN_BB_RSTB); 633 } 634 635 static void rtw8814a_switch_channel(struct rtw_dev *rtwdev, u8 channel) 636 { 637 struct rtw_hal *hal = &rtwdev->hal; 638 u32 fc_area, rf_mod_ag, cfgch; 639 u8 path; 640 641 switch (channel) { 642 case 36 ... 48: 643 fc_area = 0x494; 644 break; 645 case 50 ... 64: 646 fc_area = 0x453; 647 break; 648 case 100 ... 116: 649 fc_area = 0x452; 650 break; 651 default: 652 if (channel >= 118) 653 fc_area = 0x412; 654 else 655 fc_area = 0x96a; 656 break; 657 } 658 659 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, fc_area); 660 661 for (path = 0; path < hal->rf_path_num; path++) { 662 switch (channel) { 663 case 36 ... 64: 664 rf_mod_ag = 0x101; 665 break; 666 case 100 ... 140: 667 rf_mod_ag = 0x301; 668 break; 669 default: 670 if (channel > 140) 671 rf_mod_ag = 0x501; 672 else 673 rf_mod_ag = 0x000; 674 break; 675 } 676 677 cfgch = (rf_mod_ag << 8) | channel; 678 679 rtw_write_rf(rtwdev, path, RF_CFGCH, 680 RF18_RFSI_MASK | RF18_BAND_MASK | RF18_CHANNEL_MASK, cfgch); 681 } 682 683 switch (channel) { 684 case 36 ... 64: 685 rtw_write32_mask(rtwdev, REG_AGC_TABLE, 0x1f, 1); 686 break; 687 case 100 ... 144: 688 rtw_write32_mask(rtwdev, REG_AGC_TABLE, 0x1f, 2); 689 break; 690 default: 691 if (channel >= 149) 692 rtw_write32_mask(rtwdev, REG_AGC_TABLE, 0x1f, 3); 693 694 break; 695 } 696 } 697 698 static void rtw8814a_24g_cck_tx_dfir(struct rtw_dev *rtwdev, u8 channel) 699 { 700 if (channel >= 1 && channel <= 11) { 701 rtw_write32(rtwdev, REG_CCK0_TX_FILTER1, 0x1a1b0030); 702 rtw_write32(rtwdev, REG_CCK0_TX_FILTER2, 0x090e1317); 703 rtw_write32(rtwdev, REG_CCK0_DEBUG_PORT, 0x00000204); 704 } else if (channel >= 12 && channel <= 13) { 705 rtw_write32(rtwdev, REG_CCK0_TX_FILTER1, 0x1a1b0030); 706 rtw_write32(rtwdev, REG_CCK0_TX_FILTER2, 0x090e1217); 707 rtw_write32(rtwdev, REG_CCK0_DEBUG_PORT, 0x00000305); 708 } else if (channel == 14) { 709 rtw_write32(rtwdev, REG_CCK0_TX_FILTER1, 0x1a1b0030); 710 rtw_write32(rtwdev, REG_CCK0_TX_FILTER2, 0x00000E17); 711 rtw_write32(rtwdev, REG_CCK0_DEBUG_PORT, 0x00000000); 712 } 713 } 714 715 static void rtw8814a_set_bw_reg_mac(struct rtw_dev *rtwdev, u8 bw) 716 { 717 u16 val16 = rtw_read16(rtwdev, REG_WMAC_TRXPTCL_CTL); 718 719 val16 &= ~BIT_RFMOD; 720 if (bw == RTW_CHANNEL_WIDTH_80) 721 val16 |= BIT_RFMOD_80M; 722 else if (bw == RTW_CHANNEL_WIDTH_40) 723 val16 |= BIT_RFMOD_40M; 724 725 rtw_write16(rtwdev, REG_WMAC_TRXPTCL_CTL, val16); 726 } 727 728 static void rtw8814a_set_bw_rf(struct rtw_dev *rtwdev, u8 bw) 729 { 730 u8 path; 731 732 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) { 733 switch (bw) { 734 case RTW_CHANNEL_WIDTH_5: 735 case RTW_CHANNEL_WIDTH_10: 736 case RTW_CHANNEL_WIDTH_20: 737 default: 738 rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_BW_MASK, 3); 739 break; 740 case RTW_CHANNEL_WIDTH_40: 741 rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_BW_MASK, 1); 742 break; 743 case RTW_CHANNEL_WIDTH_80: 744 rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_BW_MASK, 0); 745 break; 746 } 747 } 748 } 749 750 static void rtw8814a_adc_clk(struct rtw_dev *rtwdev) 751 { 752 static const u32 rxiqc_reg[2][4] = { 753 { REG_RX_IQC_AB_A, REG_RX_IQC_AB_B, 754 REG_RX_IQC_AB_C, REG_RX_IQC_AB_D }, 755 { REG_RX_IQC_CD_A, REG_RX_IQC_CD_B, 756 REG_RX_IQC_CD_C, REG_RX_IQC_CD_D } 757 }; 758 u32 bb_reg_8fc, bb_reg_808, rxiqc[4]; 759 u32 i = 0, mac_active = 1; 760 u8 mac_reg_522; 761 762 if (rtwdev->hal.cut_version != RTW_CHIP_VER_CUT_A) 763 return; 764 765 /* 1 Step1. MAC TX pause */ 766 mac_reg_522 = rtw_read8(rtwdev, REG_TXPAUSE); 767 bb_reg_8fc = rtw_read32(rtwdev, REG_DBGSEL); 768 bb_reg_808 = rtw_read32(rtwdev, REG_RXPSEL); 769 rtw_write8(rtwdev, REG_TXPAUSE, 0x3f); 770 771 /* 1 Step 2. Backup rxiqc & rxiqc = 0 */ 772 for (i = 0; i < 4; i++) { 773 rxiqc[i] = rtw_read32(rtwdev, rxiqc_reg[0][i]); 774 rtw_write32(rtwdev, rxiqc_reg[0][i], 0x0); 775 rtw_write32(rtwdev, rxiqc_reg[1][i], 0x0); 776 } 777 rtw_write32_mask(rtwdev, REG_PRECTRL, BIT_IQ_WGT, 0x3); 778 i = 0; 779 780 /* 1 Step 3. Monitor MAC IDLE */ 781 rtw_write32(rtwdev, REG_DBGSEL, 0x0); 782 while (mac_active) { 783 mac_active = rtw_read32(rtwdev, REG_DBGRPT) & 0x803e0008; 784 i++; 785 if (i > 1000) 786 break; 787 } 788 789 /* 1 Step 4. ADC clk flow */ 790 rtw_write8(rtwdev, REG_RXPSEL, 0x11); 791 rtw_write32_mask(rtwdev, REG_DAC_RSTB, BIT(13), 0x1); 792 rtw_write8_mask(rtwdev, REG_GNT_BT, BIT(2) | BIT(1), 0x3); 793 rtw_write32_mask(rtwdev, REG_CCK_RPT_FORMAT, BIT(2), 0x1); 794 795 /* 0xc1c/0xe1c/0x181c/0x1a1c[4] must=1 to ensure table can be 796 * written when bbrstb=0 797 * 0xc60/0xe60/0x1860/0x1a60[15] always = 1 after this line 798 * 0xc60/0xe60/0x1860/0x1a60[14] always = 0 bcz its error in A-cut 799 */ 800 801 /* power_off/clk_off @ anapar_state=idle mode */ 802 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x15800002); 803 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x01808003); 804 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x15800002); 805 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x01808003); 806 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x15800002); 807 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x01808003); 808 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x15800002); 809 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x01808003); 810 811 rtw_write8_mask(rtwdev, REG_GNT_BT, BIT(2), 0x0); 812 rtw_write32_mask(rtwdev, REG_CCK_RPT_FORMAT, BIT(2), 0x0); 813 /* [19] = 1 to turn off ADC */ 814 rtw_write32(rtwdev, REG_CK_MONHA, 0x0D080058); 815 rtw_write32(rtwdev, REG_CK_MONHB, 0x0D080058); 816 rtw_write32(rtwdev, REG_CK_MONHC, 0x0D080058); 817 rtw_write32(rtwdev, REG_CK_MONHD, 0x0D080058); 818 819 /* power_on/clk_off */ 820 /* [19] = 0 to turn on ADC */ 821 rtw_write32(rtwdev, REG_CK_MONHA, 0x0D000058); 822 rtw_write32(rtwdev, REG_CK_MONHB, 0x0D000058); 823 rtw_write32(rtwdev, REG_CK_MONHC, 0x0D000058); 824 rtw_write32(rtwdev, REG_CK_MONHD, 0x0D000058); 825 826 /* power_on/clk_on @ anapar_state=BT mode */ 827 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x05808032); 828 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x05808032); 829 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x05808032); 830 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x05808032); 831 rtw_write8_mask(rtwdev, REG_GNT_BT, BIT(2), 0x1); 832 rtw_write32_mask(rtwdev, REG_CCK_RPT_FORMAT, BIT(2), 0x1); 833 834 /* recover original setting @ anapar_state=BT mode */ 835 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x05808032); 836 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x05808032); 837 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x05808032); 838 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x05808032); 839 840 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x05800002); 841 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x07808003); 842 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x05800002); 843 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x07808003); 844 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x05800002); 845 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x07808003); 846 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x05800002); 847 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x07808003); 848 849 rtw_write8_mask(rtwdev, REG_GNT_BT, BIT(2) | BIT(1), 0x0); 850 rtw_write32_mask(rtwdev, REG_CCK_RPT_FORMAT, BIT(2), 0x0); 851 rtw_write32_mask(rtwdev, REG_DAC_RSTB, BIT(13), 0x0); 852 853 /* 1 Step 5. Recover MAC TX & IQC */ 854 rtw_write8(rtwdev, REG_TXPAUSE, mac_reg_522); 855 rtw_write32(rtwdev, REG_DBGSEL, bb_reg_8fc); 856 rtw_write32(rtwdev, REG_RXPSEL, bb_reg_808); 857 for (i = 0; i < 4; i++) { 858 rtw_write32(rtwdev, rxiqc_reg[0][i], rxiqc[i]); 859 rtw_write32(rtwdev, rxiqc_reg[1][i], 0x01000000); 860 } 861 rtw_write32_mask(rtwdev, REG_PRECTRL, BIT_IQ_WGT, 0x0); 862 } 863 864 static void rtw8814a_spur_calibration_ch140(struct rtw_dev *rtwdev, u8 channel) 865 { 866 struct rtw_hal *hal = &rtwdev->hal; 867 868 /* Add for 8814AE module ch140 MP Rx */ 869 if (channel == 140) { 870 if (hal->ch_param[0] == 0) 871 hal->ch_param[0] = rtw_read32(rtwdev, REG_CCASEL); 872 if (hal->ch_param[1] == 0) 873 hal->ch_param[1] = rtw_read32(rtwdev, REG_PDMFTH); 874 875 rtw_write32(rtwdev, REG_CCASEL, 0x75438170); 876 rtw_write32(rtwdev, REG_PDMFTH, 0x79a18a0a); 877 } else { 878 if (rtw_read32(rtwdev, REG_CCASEL) == 0x75438170 && 879 hal->ch_param[0] != 0) 880 rtw_write32(rtwdev, REG_CCASEL, hal->ch_param[0]); 881 882 if (rtw_read32(rtwdev, REG_PDMFTH) == 0x79a18a0a && 883 hal->ch_param[1] != 0) 884 rtw_write32(rtwdev, REG_PDMFTH, hal->ch_param[1]); 885 886 hal->ch_param[0] = rtw_read32(rtwdev, REG_CCASEL); 887 hal->ch_param[1] = rtw_read32(rtwdev, REG_PDMFTH); 888 } 889 } 890 891 static void rtw8814a_set_nbi_reg(struct rtw_dev *rtwdev, u32 tone_idx) 892 { 893 /* tone_idx X 10 */ 894 static const u32 nbi_128[] = { 895 25, 55, 85, 115, 135, 896 155, 185, 205, 225, 245, 897 265, 285, 305, 335, 355, 898 375, 395, 415, 435, 455, 899 485, 505, 525, 555, 585, 615, 635 900 }; 901 u32 reg_idx = 0; 902 u32 i; 903 904 for (i = 0; i < ARRAY_SIZE(nbi_128); i++) { 905 if (tone_idx < nbi_128[i]) { 906 reg_idx = i + 1; 907 break; 908 } 909 } 910 911 rtw_write32_mask(rtwdev, REG_NBI_SETTING, 0xfc000, reg_idx); 912 } 913 914 static void rtw8814a_nbi_setting(struct rtw_dev *rtwdev, u32 ch, u32 f_intf) 915 { 916 u32 fc, int_distance, tone_idx; 917 918 fc = 2412 + (ch - 1) * 5; 919 int_distance = abs_diff(fc, f_intf); 920 921 /* 10 * (int_distance / 0.3125) */ 922 tone_idx = int_distance << 5; 923 924 rtw8814a_set_nbi_reg(rtwdev, tone_idx); 925 926 rtw_write32_mask(rtwdev, REG_NBI_SETTING, BIT_NBI_ENABLE, 1); 927 } 928 929 static void rtw8814a_spur_nbi_setting(struct rtw_dev *rtwdev) 930 { 931 u8 primary_channel = rtwdev->hal.primary_channel; 932 u8 rfe_type = rtwdev->efuse.rfe_option; 933 934 if (rfe_type != 0 && rfe_type != 1 && rfe_type != 6 && rfe_type != 7) 935 return; 936 937 if (primary_channel == 14) 938 rtw8814a_nbi_setting(rtwdev, primary_channel, 2480); 939 else if (primary_channel >= 4 && primary_channel <= 8) 940 rtw8814a_nbi_setting(rtwdev, primary_channel, 2440); 941 else 942 rtw_write32_mask(rtwdev, REG_NBI_SETTING, BIT_NBI_ENABLE, 0); 943 } 944 945 /* A workaround to eliminate the 5280 MHz & 5600 MHz & 5760 MHz spur of 8814A */ 946 static void rtw8814a_spur_calibration(struct rtw_dev *rtwdev, u8 channel, u8 bw) 947 { 948 u8 rfe_type = rtwdev->efuse.rfe_option; 949 bool reset_nbi_csi = true; 950 951 if (rfe_type == 0) { 952 switch (bw) { 953 case RTW_CHANNEL_WIDTH_40: 954 if (channel == 54 || channel == 118) { 955 rtw_write32_mask(rtwdev, REG_NBI_SETTING, 956 0x000fe000, 0x3e >> 1); 957 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1, 958 BIT(0), 1); 959 rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0); 960 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK1, 961 BIT(0), 1); 962 rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0); 963 rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0); 964 965 reset_nbi_csi = false; 966 } else if (channel == 151) { 967 rtw_write32_mask(rtwdev, REG_NBI_SETTING, 968 0x000fe000, 0x1e >> 1); 969 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1, 970 BIT(0), 1); 971 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK0, 972 BIT(16), 1); 973 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0); 974 rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0); 975 rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0); 976 977 reset_nbi_csi = false; 978 } 979 break; 980 case RTW_CHANNEL_WIDTH_80: 981 if (channel == 58 || channel == 122) { 982 rtw_write32_mask(rtwdev, REG_NBI_SETTING, 983 0x000fe000, 0x3a >> 1); 984 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1, 985 BIT(0), 1); 986 rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0); 987 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0); 988 rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0); 989 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK7, 990 BIT(0), 1); 991 992 reset_nbi_csi = false; 993 } else if (channel == 155) { 994 rtw_write32_mask(rtwdev, REG_NBI_SETTING, 995 0x000fe000, 0x5a >> 1); 996 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1, 997 BIT(0), 1); 998 rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0); 999 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0); 1000 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK6, 1001 BIT(16), 1); 1002 rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0); 1003 1004 reset_nbi_csi = false; 1005 } 1006 break; 1007 case RTW_CHANNEL_WIDTH_20: 1008 if (channel == 153) { 1009 rtw_write32_mask(rtwdev, REG_NBI_SETTING, 1010 0x000fe000, 0x1e >> 1); 1011 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1, 1012 BIT(0), 1); 1013 rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0); 1014 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0); 1015 rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0); 1016 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK7, 1017 BIT(16), 1); 1018 1019 reset_nbi_csi = false; 1020 } 1021 1022 rtw8814a_spur_calibration_ch140(rtwdev, channel); 1023 break; 1024 default: 1025 break; 1026 } 1027 } else if (rfe_type == 1 || rfe_type == 2) { 1028 switch (bw) { 1029 case RTW_CHANNEL_WIDTH_20: 1030 if (channel == 153) { 1031 rtw_write32_mask(rtwdev, REG_NBI_SETTING, 1032 0x000fe000, 0x1E >> 1); 1033 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1, 1034 BIT(0), 1); 1035 rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0); 1036 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0); 1037 rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0); 1038 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK7, 1039 BIT(16), 1); 1040 1041 reset_nbi_csi = false; 1042 } 1043 break; 1044 case RTW_CHANNEL_WIDTH_40: 1045 if (channel == 151) { 1046 rtw_write32_mask(rtwdev, REG_NBI_SETTING, 1047 0x000fe000, 0x1e >> 1); 1048 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1, 1049 BIT(0), 1); 1050 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK0, 1051 BIT(16), 1); 1052 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0); 1053 rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0); 1054 rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0); 1055 1056 reset_nbi_csi = false; 1057 } 1058 break; 1059 case RTW_CHANNEL_WIDTH_80: 1060 if (channel == 155) { 1061 rtw_write32_mask(rtwdev, REG_NBI_SETTING, 1062 0x000fe000, 0x5a >> 1); 1063 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1, 1064 BIT(0), 1); 1065 rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0); 1066 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0); 1067 rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK6, 1068 BIT(16), 1); 1069 rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0); 1070 1071 reset_nbi_csi = false; 1072 } 1073 break; 1074 default: 1075 break; 1076 } 1077 } 1078 1079 if (reset_nbi_csi) { 1080 rtw_write32_mask(rtwdev, REG_NBI_SETTING, 1081 0x000fe000, 0xfc >> 1); 1082 rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1, BIT(0), 0); 1083 rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0); 1084 rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0); 1085 rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0); 1086 rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0); 1087 } 1088 1089 rtw8814a_spur_nbi_setting(rtwdev); 1090 } 1091 1092 static void rtw8814a_set_bw_mode(struct rtw_dev *rtwdev, u8 new_band, 1093 u8 channel, u8 bw, u8 primary_chan_idx) 1094 { 1095 u8 txsc40 = 0, txsc20, txsc; 1096 1097 rtw8814a_set_bw_reg_mac(rtwdev, bw); 1098 1099 txsc20 = primary_chan_idx; 1100 if (bw == RTW_CHANNEL_WIDTH_80) { 1101 if (txsc20 == RTW_SC_20_UPPER || txsc20 == RTW_SC_20_UPMOST) 1102 txsc40 = RTW_SC_40_UPPER; 1103 else 1104 txsc40 = RTW_SC_40_LOWER; 1105 } 1106 1107 txsc = BIT_TXSC_20M(txsc20) | BIT_TXSC_40M(txsc40); 1108 rtw_write8(rtwdev, REG_DATA_SC, txsc); 1109 1110 rtw8814a_set_bw_reg_adc(rtwdev, bw); 1111 rtw8814a_set_bw_reg_agc(rtwdev, new_band, bw); 1112 1113 if (bw == RTW_CHANNEL_WIDTH_80) { 1114 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x3c, txsc); 1115 } else if (bw == RTW_CHANNEL_WIDTH_40) { 1116 rtw_write32_mask(rtwdev, REG_ADCCLK, 0x3c, txsc); 1117 1118 if (txsc == RTW_SC_20_UPPER) 1119 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); 1120 else 1121 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); 1122 } 1123 1124 rtw8814a_set_bw_rf(rtwdev, bw); 1125 1126 rtw8814a_adc_clk(rtwdev); 1127 1128 rtw8814a_spur_calibration(rtwdev, channel, bw); 1129 } 1130 1131 static void rtw8814a_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 1132 u8 primary_chan_idx) 1133 { 1134 u8 old_band, new_band; 1135 1136 if (rtw_read8(rtwdev, REG_CCK_CHECK) & BIT_CHECK_CCK_EN) 1137 old_band = RTW_BAND_5G; 1138 else 1139 old_band = RTW_BAND_2G; 1140 1141 if (channel > 14) 1142 new_band = RTW_BAND_5G; 1143 else 1144 new_band = RTW_BAND_2G; 1145 1146 if (new_band != old_band) 1147 rtw8814a_switch_band(rtwdev, new_band, bw); 1148 1149 rtw8814a_switch_channel(rtwdev, channel); 1150 1151 rtw8814a_24g_cck_tx_dfir(rtwdev, channel); 1152 1153 rtw8814a_set_bw_mode(rtwdev, new_band, channel, bw, primary_chan_idx); 1154 } 1155 1156 static s8 rtw8814a_cck_rx_pwr(u8 lna_idx, u8 vga_idx) 1157 { 1158 s8 rx_pwr_all = 0; 1159 1160 switch (lna_idx) { 1161 case 7: 1162 rx_pwr_all = -38 - 2 * vga_idx; 1163 break; 1164 case 5: 1165 rx_pwr_all = -28 - 2 * vga_idx; 1166 break; 1167 case 3: 1168 rx_pwr_all = -8 - 2 * vga_idx; 1169 break; 1170 case 2: 1171 rx_pwr_all = -1 - 2 * vga_idx; 1172 break; 1173 default: 1174 break; 1175 } 1176 1177 return rx_pwr_all; 1178 } 1179 1180 static void rtw8814a_query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 1181 struct rtw_rx_pkt_stat *pkt_stat) 1182 { 1183 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1184 struct rtw_jaguar_phy_status_rpt *rpt; 1185 u8 gain[RTW_RF_PATH_MAX], rssi, i; 1186 s8 rx_pwr_db, middle1, middle2; 1187 s8 snr[RTW_RF_PATH_MAX]; 1188 s8 evm[RTW_RF_PATH_MAX]; 1189 u8 rfmode, subchannel; 1190 u8 lna, vga; 1191 s8 cfo[2]; 1192 1193 rpt = (struct rtw_jaguar_phy_status_rpt *)phy_status; 1194 1195 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 1196 1197 if (pkt_stat->rate <= DESC_RATE11M) { 1198 lna = le32_get_bits(rpt->w1, RTW_JGRPHY_W1_AGC_RPT_LNA_IDX); 1199 vga = le32_get_bits(rpt->w1, RTW_JGRPHY_W1_AGC_RPT_VGA_IDX); 1200 1201 rx_pwr_db = rtw8814a_cck_rx_pwr(lna, vga); 1202 1203 pkt_stat->rx_power[RF_PATH_A] = rx_pwr_db; 1204 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 1205 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 1206 pkt_stat->signal_power = rx_pwr_db; 1207 } else { /* OFDM rate */ 1208 gain[RF_PATH_A] = le32_get_bits(rpt->w0, RTW_JGRPHY_W0_GAIN_A); 1209 gain[RF_PATH_B] = le32_get_bits(rpt->w0, RTW_JGRPHY_W0_GAIN_B); 1210 gain[RF_PATH_C] = le32_get_bits(rpt->w5, RTW_JGRPHY_W5_GAIN_C); 1211 gain[RF_PATH_D] = le32_get_bits(rpt->w6, RTW_JGRPHY_W6_GAIN_D); 1212 1213 snr[RF_PATH_A] = le32_get_bits(rpt->w3, RTW_JGRPHY_W3_RXSNR_A); 1214 snr[RF_PATH_B] = le32_get_bits(rpt->w4, RTW_JGRPHY_W4_RXSNR_B); 1215 snr[RF_PATH_C] = le32_get_bits(rpt->w5, RTW_JGRPHY_W5_RXSNR_C); 1216 snr[RF_PATH_D] = le32_get_bits(rpt->w5, RTW_JGRPHY_W5_RXSNR_D); 1217 1218 evm[RF_PATH_A] = le32_get_bits(rpt->w3, RTW_JGRPHY_W3_RXEVM_1); 1219 evm[RF_PATH_B] = le32_get_bits(rpt->w3, RTW_JGRPHY_W3_RXEVM_2); 1220 evm[RF_PATH_C] = le32_get_bits(rpt->w4, RTW_JGRPHY_W4_RXEVM_3); 1221 evm[RF_PATH_D] = le32_get_bits(rpt->w5, RTW_JGRPHY_W5_RXEVM_4); 1222 1223 if (pkt_stat->rate <= DESC_RATE54M) 1224 evm[RF_PATH_A] = le32_get_bits(rpt->w6, 1225 RTW_JGRPHY_W6_SIGEVM); 1226 1227 for (i = RF_PATH_A; i < RTW_RF_PATH_MAX; i++) { 1228 pkt_stat->rx_power[i] = gain[i] - 110; 1229 1230 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[i], 1); 1231 dm_info->rssi[i] = rssi; 1232 1233 pkt_stat->rx_snr[i] = snr[i]; 1234 dm_info->rx_snr[i] = snr[i] >> 1; 1235 1236 pkt_stat->rx_evm[i] = evm[i]; 1237 evm[i] = max_t(s8, -127, evm[i]); 1238 dm_info->rx_evm_dbm[i] = abs(evm[i]) >> 1; 1239 } 1240 1241 rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1242 RTW_RF_PATH_MAX); 1243 pkt_stat->rssi = rssi; 1244 1245 /* When power saving is enabled the hardware sometimes 1246 * reports unbelievably high gain for paths A and C 1247 * (e.g. one frame 64 68 68 72, the next frame 106 66 88 72, 1248 * the next 66 66 68 72), so use the second lowest gain 1249 * instead of the highest. 1250 */ 1251 middle1 = max(min(gain[RF_PATH_A], gain[RF_PATH_B]), 1252 min(gain[RF_PATH_C], gain[RF_PATH_D])); 1253 middle2 = min(max(gain[RF_PATH_A], gain[RF_PATH_B]), 1254 max(gain[RF_PATH_C], gain[RF_PATH_D])); 1255 rx_pwr_db = min(middle1, middle2); 1256 rx_pwr_db -= 110; 1257 pkt_stat->signal_power = rx_pwr_db; 1258 1259 rfmode = le32_get_bits(rpt->w0, RTW_JGRPHY_W0_R_RFMOD); 1260 subchannel = le32_get_bits(rpt->w0, RTW_JGRPHY_W0_SUB_CHNL); 1261 1262 if (rfmode == 1 && subchannel == 0) { 1263 pkt_stat->bw = RTW_CHANNEL_WIDTH_40; 1264 } else if (rfmode == 2) { 1265 if (subchannel == 0) 1266 pkt_stat->bw = RTW_CHANNEL_WIDTH_80; 1267 else if (subchannel == 9 || subchannel == 10) 1268 pkt_stat->bw = RTW_CHANNEL_WIDTH_40; 1269 } 1270 1271 cfo[RF_PATH_A] = le32_get_bits(rpt->w2, RTW_JGRPHY_W2_CFO_TAIL_A); 1272 cfo[RF_PATH_B] = le32_get_bits(rpt->w2, RTW_JGRPHY_W2_CFO_TAIL_B); 1273 1274 for (i = RF_PATH_A; i < 2; i++) { 1275 pkt_stat->cfo_tail[i] = cfo[i]; 1276 dm_info->cfo_tail[i] = (cfo[i] * 5) >> 1; 1277 } 1278 } 1279 } 1280 1281 static void 1282 rtw8814a_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) 1283 { 1284 struct rtw_hal *hal = &rtwdev->hal; 1285 u32 txagc_table_wd; 1286 u8 rate, pwr_index; 1287 int j; 1288 1289 for (j = 0; j < rtw_rate_size[rs]; j++) { 1290 rate = rtw_rate_section[rs][j]; 1291 1292 pwr_index = hal->tx_pwr_tbl[path][rate] + 2; 1293 if (pwr_index > rtwdev->chip->max_power_index) 1294 pwr_index = rtwdev->chip->max_power_index; 1295 1296 txagc_table_wd = 0x00801000; 1297 txagc_table_wd |= (pwr_index << 24) | (path << 8) | rate; 1298 1299 rtw_write32(rtwdev, REG_AGC_TBL, txagc_table_wd); 1300 1301 /* first time to turn on the txagc table 1302 * second to write the addr0 1303 */ 1304 if (rate == DESC_RATE1M) 1305 rtw_write32(rtwdev, REG_AGC_TBL, txagc_table_wd); 1306 } 1307 } 1308 1309 static void rtw8814a_set_tx_power_index(struct rtw_dev *rtwdev) 1310 { 1311 struct rtw_hal *hal = &rtwdev->hal; 1312 int path; 1313 1314 for (path = 0; path < hal->rf_path_num; path++) { 1315 if (hal->current_band_type == RTW_BAND_2G) 1316 rtw8814a_set_tx_power_index_by_rate(rtwdev, path, 1317 RTW_RATE_SECTION_CCK); 1318 1319 rtw8814a_set_tx_power_index_by_rate(rtwdev, path, 1320 RTW_RATE_SECTION_OFDM); 1321 1322 if (test_bit(RTW_FLAG_SCANNING, rtwdev->flags)) 1323 continue; 1324 1325 rtw8814a_set_tx_power_index_by_rate(rtwdev, path, 1326 RTW_RATE_SECTION_HT_1S); 1327 rtw8814a_set_tx_power_index_by_rate(rtwdev, path, 1328 RTW_RATE_SECTION_VHT_1S); 1329 1330 rtw8814a_set_tx_power_index_by_rate(rtwdev, path, 1331 RTW_RATE_SECTION_HT_2S); 1332 rtw8814a_set_tx_power_index_by_rate(rtwdev, path, 1333 RTW_RATE_SECTION_VHT_2S); 1334 1335 rtw8814a_set_tx_power_index_by_rate(rtwdev, path, 1336 RTW_RATE_SECTION_HT_3S); 1337 rtw8814a_set_tx_power_index_by_rate(rtwdev, path, 1338 RTW_RATE_SECTION_VHT_3S); 1339 } 1340 } 1341 1342 static void rtw8814a_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 1343 { 1344 } 1345 1346 /* Without this RTL8814A sends too many frames and (some?) 11n AP 1347 * can't handle it, resulting in low TX speed. Other chips seem fine. 1348 */ 1349 static void rtw8814a_set_ampdu_factor(struct rtw_dev *rtwdev, u8 factor) 1350 { 1351 factor = min_t(u8, factor, IEEE80211_VHT_MAX_AMPDU_256K); 1352 1353 rtw_write32(rtwdev, REG_AMPDU_MAX_LENGTH, (8192 << factor) - 1); 1354 } 1355 1356 static void rtw8814a_false_alarm_statistics(struct rtw_dev *rtwdev) 1357 { 1358 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1359 u32 cck_fa_cnt, ofdm_fa_cnt; 1360 u32 crc32_cnt, cca32_cnt; 1361 u32 cck_enable; 1362 1363 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28); 1364 cck_fa_cnt = rtw_read16(rtwdev, REG_FA_CCK); 1365 ofdm_fa_cnt = rtw_read16(rtwdev, REG_FA_OFDM); 1366 1367 dm_info->cck_fa_cnt = cck_fa_cnt; 1368 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 1369 dm_info->total_fa_cnt = ofdm_fa_cnt; 1370 if (cck_enable) 1371 dm_info->total_fa_cnt += cck_fa_cnt; 1372 1373 crc32_cnt = rtw_read32(rtwdev, REG_CRC_CCK); 1374 dm_info->cck_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD); 1375 dm_info->cck_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD); 1376 1377 crc32_cnt = rtw_read32(rtwdev, REG_CRC_OFDM); 1378 dm_info->ofdm_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD); 1379 dm_info->ofdm_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD); 1380 1381 crc32_cnt = rtw_read32(rtwdev, REG_CRC_HT); 1382 dm_info->ht_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD); 1383 dm_info->ht_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD); 1384 1385 crc32_cnt = rtw_read32(rtwdev, REG_CRC_VHT); 1386 dm_info->vht_ok_cnt = u32_get_bits(crc32_cnt, MASKLWORD); 1387 dm_info->vht_err_cnt = u32_get_bits(crc32_cnt, MASKHWORD); 1388 1389 cca32_cnt = rtw_read32(rtwdev, REG_CCA_OFDM); 1390 dm_info->ofdm_cca_cnt = u32_get_bits(cca32_cnt, MASKHWORD); 1391 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 1392 if (cck_enable) { 1393 cca32_cnt = rtw_read32(rtwdev, REG_CCA_CCK); 1394 dm_info->cck_cca_cnt = u32_get_bits(cca32_cnt, MASKLWORD); 1395 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 1396 } 1397 1398 rtw_write32_set(rtwdev, REG_FAS, BIT(17)); 1399 rtw_write32_clr(rtwdev, REG_FAS, BIT(17)); 1400 rtw_write32_clr(rtwdev, REG_CCK0_FAREPORT, BIT(15)); 1401 rtw_write32_set(rtwdev, REG_CCK0_FAREPORT, BIT(15)); 1402 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); 1403 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0)); 1404 } 1405 1406 #define MAC_REG_NUM_8814 2 1407 #define BB_REG_NUM_8814 14 1408 #define RF_REG_NUM_8814 1 1409 1410 static void rtw8814a_iqk_backup_mac_bb(struct rtw_dev *rtwdev, 1411 u32 *mac_backup, u32 *bb_backup, 1412 const u32 *mac_regs, 1413 const u32 *bb_regs) 1414 { 1415 u32 i; 1416 1417 /* save MACBB default value */ 1418 for (i = 0; i < MAC_REG_NUM_8814; i++) 1419 mac_backup[i] = rtw_read32(rtwdev, mac_regs[i]); 1420 1421 for (i = 0; i < BB_REG_NUM_8814; i++) 1422 bb_backup[i] = rtw_read32(rtwdev, bb_regs[i]); 1423 } 1424 1425 static void rtw8814a_iqk_backup_rf(struct rtw_dev *rtwdev, 1426 u32 rf_backup[][4], const u32 *rf_regs) 1427 { 1428 u32 i; 1429 1430 /* Save RF Parameters */ 1431 for (i = 0; i < RF_REG_NUM_8814; i++) { 1432 rf_backup[i][RF_PATH_A] = rtw_read_rf(rtwdev, RF_PATH_A, 1433 rf_regs[i], RFREG_MASK); 1434 rf_backup[i][RF_PATH_B] = rtw_read_rf(rtwdev, RF_PATH_B, 1435 rf_regs[i], RFREG_MASK); 1436 rf_backup[i][RF_PATH_C] = rtw_read_rf(rtwdev, RF_PATH_C, 1437 rf_regs[i], RFREG_MASK); 1438 rf_backup[i][RF_PATH_D] = rtw_read_rf(rtwdev, RF_PATH_D, 1439 rf_regs[i], RFREG_MASK); 1440 } 1441 } 1442 1443 static void rtw8814a_iqk_afe_setting(struct rtw_dev *rtwdev, bool do_iqk) 1444 { 1445 if (do_iqk) { 1446 /* IQK AFE setting RX_WAIT_CCA mode */ 1447 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x0e808003); 1448 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x0e808003); 1449 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x0e808003); 1450 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x0e808003); 1451 } else { 1452 rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x07808003); 1453 rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x07808003); 1454 rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x07808003); 1455 rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x07808003); 1456 } 1457 1458 rtw_write32_mask(rtwdev, REG_DAC_RSTB, BIT(13), 0x1); 1459 1460 rtw_write8_set(rtwdev, REG_GNT_BT, BIT(2) | BIT(1)); 1461 rtw_write8_clr(rtwdev, REG_GNT_BT, BIT(2) | BIT(1)); 1462 1463 rtw_write32_set(rtwdev, REG_CCK_RPT_FORMAT, BIT(2)); 1464 rtw_write32_clr(rtwdev, REG_CCK_RPT_FORMAT, BIT(2)); 1465 } 1466 1467 static void rtw8814a_iqk_restore_mac_bb(struct rtw_dev *rtwdev, 1468 u32 *mac_backup, u32 *bb_backup, 1469 const u32 *mac_regs, 1470 const u32 *bb_regs) 1471 { 1472 u32 i; 1473 1474 /* Reload MacBB Parameters */ 1475 for (i = 0; i < MAC_REG_NUM_8814; i++) 1476 rtw_write32(rtwdev, mac_regs[i], mac_backup[i]); 1477 1478 for (i = 0; i < BB_REG_NUM_8814; i++) 1479 rtw_write32(rtwdev, bb_regs[i], bb_backup[i]); 1480 } 1481 1482 static void rtw8814a_iqk_restore_rf(struct rtw_dev *rtwdev, 1483 const u32 rf_backup[][4], 1484 const u32 *rf_regs) 1485 { 1486 u32 i; 1487 1488 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x0); 1489 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE, RFREG_MASK, 0x0); 1490 rtw_write_rf(rtwdev, RF_PATH_C, RF_LUTWE, RFREG_MASK, 0x0); 1491 rtw_write_rf(rtwdev, RF_PATH_D, RF_LUTWE, RFREG_MASK, 0x0); 1492 1493 rtw_write_rf(rtwdev, RF_PATH_A, RF_RXBB2, RFREG_MASK, 0x88001); 1494 rtw_write_rf(rtwdev, RF_PATH_B, RF_RXBB2, RFREG_MASK, 0x88001); 1495 rtw_write_rf(rtwdev, RF_PATH_C, RF_RXBB2, RFREG_MASK, 0x88001); 1496 rtw_write_rf(rtwdev, RF_PATH_D, RF_RXBB2, RFREG_MASK, 0x88001); 1497 1498 for (i = 0; i < RF_REG_NUM_8814; i++) { 1499 rtw_write_rf(rtwdev, RF_PATH_A, rf_regs[i], 1500 RFREG_MASK, rf_backup[i][RF_PATH_A]); 1501 rtw_write_rf(rtwdev, RF_PATH_B, rf_regs[i], 1502 RFREG_MASK, rf_backup[i][RF_PATH_B]); 1503 rtw_write_rf(rtwdev, RF_PATH_C, rf_regs[i], 1504 RFREG_MASK, rf_backup[i][RF_PATH_C]); 1505 rtw_write_rf(rtwdev, RF_PATH_D, rf_regs[i], 1506 RFREG_MASK, rf_backup[i][RF_PATH_D]); 1507 } 1508 } 1509 1510 static void rtw8814a_iqk_reset_nctl(struct rtw_dev *rtwdev) 1511 { 1512 rtw_write32(rtwdev, 0x1b00, 0xf8000000); 1513 rtw_write32(rtwdev, 0x1b80, 0x00000006); 1514 1515 rtw_write32(rtwdev, 0x1b00, 0xf8000000); 1516 rtw_write32(rtwdev, 0x1b80, 0x00000002); 1517 } 1518 1519 static void rtw8814a_iqk_configure_mac(struct rtw_dev *rtwdev) 1520 { 1521 rtw_write8(rtwdev, REG_TXPAUSE, 0x3f); 1522 rtw_write32_clr(rtwdev, REG_BCN_CTRL, 1523 (BIT_EN_BCN_FUNCTION << 8) | BIT_EN_BCN_FUNCTION); 1524 1525 /* RX ante off */ 1526 rtw_write8(rtwdev, REG_RXPSEL, 0x00); 1527 /* CCA off */ 1528 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf, 0xe); 1529 /* CCK RX path off */ 1530 rtw_write32_set(rtwdev, REG_PRECTRL, BIT_IQ_WGT); 1531 rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777); 1532 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777); 1533 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x77777777); 1534 rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77777777); 1535 rtw_write32_mask(rtwdev, REG_RFE_INVSEL_D, BIT_RFE_SELSW0_D, 0x77); 1536 rtw_write32_mask(rtwdev, REG_PSD, BIT_PSD_INI, 0x0); 1537 1538 rtw_write32_mask(rtwdev, REG_RFE_INV0, 0xf, 0x0); 1539 } 1540 1541 static void rtw8814a_lok_one_shot(struct rtw_dev *rtwdev, u8 path) 1542 { 1543 u32 lok_temp1, lok_temp2; 1544 bool lok_ready; 1545 u8 ii; 1546 1547 /* ADC Clock source */ 1548 rtw_write32_mask(rtwdev, REG_FAS, BIT(21) | BIT(20), path); 1549 /* LOK: CMD ID = 0 1550 * {0xf8000011, 0xf8000021, 0xf8000041, 0xf8000081} 1551 */ 1552 rtw_write32(rtwdev, 0x1b00, 0xf8000001 | (BIT(path) << 4)); 1553 1554 usleep_range(1000, 1100); 1555 1556 if (read_poll_timeout(!rtw_read32_mask, lok_ready, lok_ready, 1557 1000, 10000, false, 1558 rtwdev, 0x1b00, BIT(0))) { 1559 rtw_dbg(rtwdev, RTW_DBG_RFK, "==>S%d LOK timed out\n", path); 1560 1561 rtw8814a_iqk_reset_nctl(rtwdev); 1562 1563 rtw_write_rf(rtwdev, path, RF_DTXLOK, RFREG_MASK, 0x08400); 1564 1565 return; 1566 } 1567 1568 rtw_write32(rtwdev, 0x1b00, 0xf8000000 | (path << 1)); 1569 rtw_write32(rtwdev, 0x1bd4, 0x003f0001); 1570 1571 lok_temp2 = rtw_read32_mask(rtwdev, 0x1bfc, 0x003e0000); 1572 lok_temp2 = (lok_temp2 + 0x10) & 0x1f; 1573 1574 lok_temp1 = rtw_read32_mask(rtwdev, 0x1bfc, 0x0000003e); 1575 lok_temp1 = (lok_temp1 + 0x10) & 0x1f; 1576 1577 for (ii = 1; ii < 5; ii++) { 1578 lok_temp1 += (lok_temp1 & BIT(4 - ii)) << (ii * 2); 1579 lok_temp2 += (lok_temp2 & BIT(4 - ii)) << (ii * 2); 1580 } 1581 1582 rtw_dbg(rtwdev, RTW_DBG_RFK, 1583 "path %d lok_temp1 = %#x, lok_temp2 = %#x\n", 1584 path, lok_temp1 >> 4, lok_temp2 >> 4); 1585 1586 rtw_write_rf(rtwdev, path, RF_DTXLOK, 0x07c00, lok_temp1 >> 4); 1587 rtw_write_rf(rtwdev, path, RF_DTXLOK, 0xf8000, lok_temp2 >> 4); 1588 } 1589 1590 static void rtw8814a_iqk_tx_one_shot(struct rtw_dev *rtwdev, u8 path, 1591 u32 *tx_matrix, bool *tx_ok) 1592 { 1593 u8 bw = rtwdev->hal.current_band_width; 1594 u8 cal_retry; 1595 u32 iqk_cmd; 1596 1597 for (cal_retry = 0; cal_retry < 4; cal_retry++) { 1598 rtw_write32_mask(rtwdev, REG_FAS, BIT(21) | BIT(20), path); 1599 1600 iqk_cmd = 0xf8000001 | ((bw + 3) << 8) | (BIT(path) << 4); 1601 1602 rtw_dbg(rtwdev, RTW_DBG_RFK, "TXK_Trigger = %#x\n", iqk_cmd); 1603 1604 rtw_write32(rtwdev, 0x1b00, iqk_cmd); 1605 1606 usleep_range(10000, 11000); 1607 1608 if (read_poll_timeout(!rtw_read32_mask, *tx_ok, *tx_ok, 1609 1000, 20000, false, 1610 rtwdev, 0x1b00, BIT(0))) { 1611 rtw_dbg(rtwdev, RTW_DBG_RFK, 1612 "tx iqk S%d timed out\n", path); 1613 1614 rtw8814a_iqk_reset_nctl(rtwdev); 1615 } else { 1616 *tx_ok = !rtw_read32_mask(rtwdev, 0x1b08, BIT(26)); 1617 1618 if (*tx_ok) 1619 break; 1620 } 1621 } 1622 1623 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d tx ==> 0x1b00 = 0x%x\n", 1624 path, rtw_read32(rtwdev, 0x1b00)); 1625 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d tx ==> 0x1b08 = 0x%x\n", 1626 path, rtw_read32(rtwdev, 0x1b08)); 1627 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d tx ==> cal_retry = %x\n", 1628 path, cal_retry); 1629 1630 rtw_write32(rtwdev, 0x1b00, 0xf8000000 | (path << 1)); 1631 1632 if (*tx_ok) { 1633 *tx_matrix = rtw_read32(rtwdev, 0x1b38); 1634 1635 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d_IQC = 0x%x\n", 1636 path, *tx_matrix); 1637 } 1638 } 1639 1640 static void rtw8814a_iqk_rx_one_shot(struct rtw_dev *rtwdev, u8 path, 1641 u32 *tx_matrix, bool *tx_ok) 1642 { 1643 static const u16 iqk_apply[RTW_RF_PATH_MAX] = { 1644 REG_TXAGCIDX, REG_TX_AGC_B, REG_TX_AGC_C, REG_TX_AGC_D 1645 }; 1646 u8 band = rtwdev->hal.current_band_type; 1647 u8 bw = rtwdev->hal.current_band_width; 1648 u32 rx_matrix; 1649 u8 cal_retry; 1650 u32 iqk_cmd; 1651 bool rx_ok; 1652 1653 for (cal_retry = 0; cal_retry < 4; cal_retry++) { 1654 rtw_write32_mask(rtwdev, REG_FAS, BIT(21) | BIT(20), path); 1655 1656 if (band == RTW_BAND_2G) { 1657 rtw_write_rf(rtwdev, path, RF_LUTDBG, BIT(11), 0x1); 1658 rtw_write_rf(rtwdev, path, RF_GAINTX, 0xfffff, 0x51ce1); 1659 1660 switch (path) { 1661 case 0: 1662 case 1: 1663 rtw_write32(rtwdev, REG_RFE_PINMUX_B, 1664 0x54775477); 1665 break; 1666 case 2: 1667 rtw_write32(rtwdev, REG_RFE_PINMUX_C, 1668 0x54775477); 1669 break; 1670 case 3: 1671 rtw_write32(rtwdev, REG_RFE_INVSEL_D, 0x75400000); 1672 rtw_write32(rtwdev, REG_RFE_PINMUX_D, 1673 0x77777777); 1674 break; 1675 } 1676 } 1677 1678 iqk_cmd = 0xf8000001 | ((9 - bw) << 8) | (BIT(path) << 4); 1679 1680 rtw_dbg(rtwdev, RTW_DBG_RFK, "RXK_Trigger = 0x%x\n", iqk_cmd); 1681 1682 rtw_write32(rtwdev, 0x1b00, iqk_cmd); 1683 1684 usleep_range(10000, 11000); 1685 1686 if (read_poll_timeout(!rtw_read32_mask, rx_ok, rx_ok, 1687 1000, 20000, false, 1688 rtwdev, 0x1b00, BIT(0))) { 1689 rtw_dbg(rtwdev, RTW_DBG_RFK, 1690 "rx iqk S%d timed out\n", path); 1691 1692 rtw8814a_iqk_reset_nctl(rtwdev); 1693 } else { 1694 rx_ok = !rtw_read32_mask(rtwdev, 0x1b08, BIT(26)); 1695 1696 if (rx_ok) 1697 break; 1698 } 1699 } 1700 1701 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d rx ==> 0x1b00 = 0x%x\n", 1702 path, rtw_read32(rtwdev, 0x1b00)); 1703 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d rx ==> 0x1b08 = 0x%x\n", 1704 path, rtw_read32(rtwdev, 0x1b08)); 1705 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d rx ==> cal_retry = %x\n", 1706 path, cal_retry); 1707 1708 rtw_write32(rtwdev, 0x1b00, 0xf8000000 | (path << 1)); 1709 1710 if (rx_ok) { 1711 rtw_write32(rtwdev, 0x1b3c, 0x20000000); 1712 rx_matrix = rtw_read32(rtwdev, 0x1b3c); 1713 1714 rtw_dbg(rtwdev, RTW_DBG_RFK, "S%d_IQC = 0x%x\n", 1715 path, rx_matrix); 1716 } 1717 1718 if (*tx_ok) 1719 rtw_write32(rtwdev, 0x1b38, *tx_matrix); 1720 else 1721 rtw_write32_mask(rtwdev, iqk_apply[path], BIT(0), 0x0); 1722 1723 if (!rx_ok) 1724 rtw_write32_mask(rtwdev, iqk_apply[path], 1725 BIT(11) | BIT(10), 0x0); 1726 1727 if (band == RTW_BAND_2G) 1728 rtw_write_rf(rtwdev, path, RF_LUTDBG, BIT(11), 0x0); 1729 } 1730 1731 static void rtw8814a_iqk(struct rtw_dev *rtwdev) 1732 { 1733 u8 band = rtwdev->hal.current_band_type; 1734 u8 bw = rtwdev->hal.current_band_width; 1735 u32 tx_matrix[RTW_RF_PATH_MAX]; 1736 bool tx_ok[RTW_RF_PATH_MAX]; 1737 u8 path; 1738 1739 rtw_dbg(rtwdev, RTW_DBG_RFK, "IQK band = %d GHz bw = %d MHz\n", 1740 band == RTW_BAND_2G ? 2 : 5, (1 << (bw + 1)) * 10); 1741 1742 rtw_write_rf(rtwdev, RF_PATH_A, RF_TXMOD, BIT(19), 0x1); 1743 rtw_write_rf(rtwdev, RF_PATH_B, RF_TXMOD, BIT(19), 0x1); 1744 rtw_write_rf(rtwdev, RF_PATH_C, RF_TXMOD, BIT(19), 0x1); 1745 rtw_write_rf(rtwdev, RF_PATH_D, RF_TXMOD, BIT(19), 0x1); 1746 1747 rtw_write32_mask(rtwdev, REG_TXAGCIDX, 1748 (BIT(11) | BIT(10) | BIT(0)), 0x401); 1749 rtw_write32_mask(rtwdev, REG_TX_AGC_B, 1750 (BIT(11) | BIT(10) | BIT(0)), 0x401); 1751 rtw_write32_mask(rtwdev, REG_TX_AGC_C, 1752 (BIT(11) | BIT(10) | BIT(0)), 0x401); 1753 rtw_write32_mask(rtwdev, REG_TX_AGC_D, 1754 (BIT(11) | BIT(10) | BIT(0)), 0x401); 1755 1756 if (band == RTW_BAND_5G) 1757 rtw_write32(rtwdev, 0x1b00, 0xf8000ff1); 1758 else 1759 rtw_write32(rtwdev, 0x1b00, 0xf8000ef1); 1760 1761 usleep_range(1000, 1100); 1762 1763 rtw_write32(rtwdev, 0x810, 0x20101063); 1764 rtw_write32(rtwdev, REG_DAC_RSTB, 0x0B00C000); 1765 1766 for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++) 1767 rtw8814a_lok_one_shot(rtwdev, path); 1768 1769 for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++) 1770 rtw8814a_iqk_tx_one_shot(rtwdev, path, 1771 &tx_matrix[path], &tx_ok[path]); 1772 1773 for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++) 1774 rtw8814a_iqk_rx_one_shot(rtwdev, path, 1775 &tx_matrix[path], &tx_ok[path]); 1776 } 1777 1778 static void rtw8814a_do_iqk(struct rtw_dev *rtwdev) 1779 { 1780 static const u32 backup_mac_reg[MAC_REG_NUM_8814] = {0x520, 0x550}; 1781 static const u32 backup_bb_reg[BB_REG_NUM_8814] = { 1782 0xa14, 0x808, 0x838, 0x90c, 0x810, 0xcb0, 0xeb0, 1783 0x18b4, 0x1ab4, 0x1abc, 0x9a4, 0x764, 0xcbc, 0x910 1784 }; 1785 static const u32 backup_rf_reg[RF_REG_NUM_8814] = {0x0}; 1786 u32 rf_backup[RF_REG_NUM_8814][RTW_RF_PATH_MAX]; 1787 u32 mac_backup[MAC_REG_NUM_8814]; 1788 u32 bb_backup[BB_REG_NUM_8814]; 1789 1790 rtw8814a_iqk_backup_mac_bb(rtwdev, mac_backup, bb_backup, 1791 backup_mac_reg, backup_bb_reg); 1792 rtw8814a_iqk_afe_setting(rtwdev, true); 1793 rtw8814a_iqk_backup_rf(rtwdev, rf_backup, backup_rf_reg); 1794 rtw8814a_iqk_configure_mac(rtwdev); 1795 rtw8814a_iqk(rtwdev); 1796 rtw8814a_iqk_reset_nctl(rtwdev); /* for 3-wire to BB use */ 1797 rtw8814a_iqk_afe_setting(rtwdev, false); 1798 rtw8814a_iqk_restore_mac_bb(rtwdev, mac_backup, bb_backup, 1799 backup_mac_reg, backup_bb_reg); 1800 rtw8814a_iqk_restore_rf(rtwdev, rf_backup, backup_rf_reg); 1801 } 1802 1803 static void rtw8814a_phy_calibration(struct rtw_dev *rtwdev) 1804 { 1805 rtw8814a_do_iqk(rtwdev); 1806 } 1807 1808 static void rtw8814a_coex_cfg_init(struct rtw_dev *rtwdev) 1809 { 1810 } 1811 1812 static void rtw8814a_coex_cfg_ant_switch(struct rtw_dev *rtwdev, u8 ctrl_type, 1813 u8 pos_type) 1814 { 1815 /* Override rtw_coex_coex_ctrl_owner(). RF path C does not 1816 * function when BIT_LTE_MUX_CTRL_PATH is set. 1817 */ 1818 rtw_write8_clr(rtwdev, REG_SYS_SDIO_CTRL + 3, 1819 BIT_LTE_MUX_CTRL_PATH >> 24); 1820 } 1821 1822 static void rtw8814a_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 1823 { 1824 } 1825 1826 static void rtw8814a_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 1827 { 1828 } 1829 1830 static void rtw8814a_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 1831 { 1832 struct rtw_coex *coex = &rtwdev->coex; 1833 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 1834 1835 /* Only needed to make rtw8814a_coex_cfg_ant_switch() run. */ 1836 coex_rfe->ant_switch_exist = true; 1837 } 1838 1839 static void rtw8814a_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 1840 { 1841 } 1842 1843 static void rtw8814a_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 1844 { 1845 } 1846 1847 static void rtw8814a_txagc_swing_offset(struct rtw_dev *rtwdev, u8 path, 1848 u8 tx_pwr_idx_offset, 1849 s8 *txagc_idx, u8 *swing_idx) 1850 { 1851 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1852 u8 swing_upper_bound = dm_info->default_ofdm_index + 10; 1853 s8 delta_pwr_idx = dm_info->delta_power_index[path]; 1854 u8 swing_index = dm_info->default_ofdm_index; 1855 u8 max_tx_pwr_idx_offset = 0xf; 1856 u8 swing_lower_bound = 0; 1857 s8 agc_index = 0; 1858 1859 tx_pwr_idx_offset = min_t(u8, tx_pwr_idx_offset, max_tx_pwr_idx_offset); 1860 1861 if (delta_pwr_idx >= 0) { 1862 if (delta_pwr_idx <= tx_pwr_idx_offset) { 1863 agc_index = delta_pwr_idx; 1864 swing_index = dm_info->default_ofdm_index; 1865 } else if (delta_pwr_idx > tx_pwr_idx_offset) { 1866 agc_index = tx_pwr_idx_offset; 1867 swing_index = dm_info->default_ofdm_index + 1868 delta_pwr_idx - tx_pwr_idx_offset; 1869 swing_index = min_t(u8, swing_index, swing_upper_bound); 1870 } 1871 } else { 1872 if (dm_info->default_ofdm_index > abs(delta_pwr_idx)) 1873 swing_index = 1874 dm_info->default_ofdm_index + delta_pwr_idx; 1875 else 1876 swing_index = swing_lower_bound; 1877 swing_index = max_t(u8, swing_index, swing_lower_bound); 1878 1879 agc_index = 0; 1880 } 1881 1882 if (swing_index >= RTW_TXSCALE_SIZE) { 1883 rtw_warn(rtwdev, "swing index overflow\n"); 1884 swing_index = RTW_TXSCALE_SIZE - 1; 1885 } 1886 *txagc_idx = agc_index; 1887 *swing_idx = swing_index; 1888 } 1889 1890 static void rtw8814a_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 path, 1891 u8 pwr_idx_offset) 1892 { 1893 static const u32 txagc_reg[RTW_RF_PATH_MAX] = { 1894 REG_TX_AGC_A, REG_TX_AGC_B, REG_TX_AGC_C, REG_TX_AGC_D 1895 }; 1896 static const u32 txscale_reg[RTW_RF_PATH_MAX] = { 1897 REG_TXSCALE_A, REG_TXSCALE_B, REG_TXSCALE_C, REG_TXSCALE_D 1898 }; 1899 s8 txagc_idx; 1900 u8 swing_idx; 1901 1902 rtw8814a_txagc_swing_offset(rtwdev, path, pwr_idx_offset, 1903 &txagc_idx, &swing_idx); 1904 rtw_write32_mask(rtwdev, txagc_reg[path], GENMASK(29, 25), 1905 txagc_idx); 1906 rtw_write32_mask(rtwdev, txscale_reg[path], BB_SWING_MASK, 1907 rtw8814a_txscale_tbl[swing_idx]); 1908 } 1909 1910 static void rtw8814a_pwrtrack_set(struct rtw_dev *rtwdev, u8 path) 1911 { 1912 u8 max_pwr_idx = rtwdev->chip->max_power_index; 1913 u8 band_width = rtwdev->hal.current_band_width; 1914 u8 channel = rtwdev->hal.current_channel; 1915 u8 tx_rate = rtwdev->dm_info.tx_rate; 1916 u8 regd = rtw_regd_get(rtwdev); 1917 u8 pwr_idx_offset, tx_pwr_idx; 1918 1919 tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, path, tx_rate, 1920 band_width, channel, regd); 1921 1922 tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx); 1923 1924 pwr_idx_offset = max_pwr_idx - tx_pwr_idx; 1925 1926 rtw8814a_pwrtrack_set_pwr(rtwdev, path, pwr_idx_offset); 1927 } 1928 1929 static void rtw8814a_phy_pwrtrack_path(struct rtw_dev *rtwdev, 1930 struct rtw_swing_table *swing_table, 1931 u8 path) 1932 { 1933 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1934 u8 power_idx_cur, power_idx_last; 1935 u8 delta; 1936 1937 /* 8814A only has one thermal meter at PATH A */ 1938 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 1939 1940 power_idx_last = dm_info->delta_power_index[path]; 1941 power_idx_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table, 1942 path, RF_PATH_A, delta); 1943 1944 /* if delta of power indexes are the same, just skip */ 1945 if (power_idx_cur == power_idx_last) 1946 return; 1947 1948 dm_info->delta_power_index[path] = power_idx_cur; 1949 rtw8814a_pwrtrack_set(rtwdev, path); 1950 } 1951 1952 static void rtw8814a_phy_pwrtrack(struct rtw_dev *rtwdev) 1953 { 1954 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1955 struct rtw_swing_table swing_table; 1956 u8 thermal_value, path; 1957 1958 rtw_phy_config_swing_table(rtwdev, &swing_table); 1959 1960 if (rtwdev->efuse.thermal_meter[RF_PATH_A] == 0xff) 1961 return; 1962 1963 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 1964 1965 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 1966 1967 if (dm_info->pwr_trk_init_trigger) 1968 dm_info->pwr_trk_init_trigger = false; 1969 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 1970 RF_PATH_A)) 1971 goto iqk; 1972 1973 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) 1974 rtw8814a_phy_pwrtrack_path(rtwdev, &swing_table, path); 1975 1976 iqk: 1977 if (rtw_phy_pwrtrack_need_iqk(rtwdev)) 1978 rtw8814a_do_iqk(rtwdev); 1979 } 1980 1981 static void rtw8814a_pwr_track(struct rtw_dev *rtwdev) 1982 { 1983 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1984 1985 if (!dm_info->pwr_trk_triggered) { 1986 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 1987 GENMASK(17, 16), 0x03); 1988 dm_info->pwr_trk_triggered = true; 1989 return; 1990 } 1991 1992 rtw8814a_phy_pwrtrack(rtwdev); 1993 dm_info->pwr_trk_triggered = false; 1994 } 1995 1996 static void rtw8814a_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) 1997 { 1998 static const u8 pd[CCK_PD_LV_MAX] = {0x40, 0x83, 0xcd, 0xdd, 0xed}; 1999 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2000 2001 /* Override rtw_phy_cck_pd_lv_link(). It implements something 2002 * like type 2/3/4. We need type 1 here. 2003 */ 2004 if (rtw_is_assoc(rtwdev)) { 2005 if (dm_info->min_rssi > 60) { 2006 new_lvl = CCK_PD_LV3; 2007 } else if (dm_info->min_rssi > 35) { 2008 new_lvl = CCK_PD_LV2; 2009 } else if (dm_info->min_rssi > 20) { 2010 if (dm_info->cck_fa_avg > 500) 2011 new_lvl = CCK_PD_LV2; 2012 else if (dm_info->cck_fa_avg < 250) 2013 new_lvl = CCK_PD_LV1; 2014 else 2015 return; 2016 } else { 2017 new_lvl = CCK_PD_LV1; 2018 } 2019 } 2020 2021 rtw_dbg(rtwdev, RTW_DBG_PHY, "lv: (%d) -> (%d)\n", 2022 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A], new_lvl); 2023 2024 if (dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] == new_lvl) 2025 return; 2026 2027 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 2028 dm_info->cck_pd_lv[RTW_CHANNEL_WIDTH_20][RF_PATH_A] = new_lvl; 2029 2030 rtw_write8(rtwdev, REG_CCK_PD_TH, pd[new_lvl]); 2031 } 2032 2033 static void rtw8814a_led_set(struct led_classdev *led, 2034 enum led_brightness brightness) 2035 { 2036 struct rtw_dev *rtwdev = container_of(led, struct rtw_dev, led_cdev); 2037 u32 led_gpio_cfg; 2038 2039 led_gpio_cfg = rtw_read32(rtwdev, REG_GPIO_PIN_CTRL_2); 2040 led_gpio_cfg |= BIT(16) | BIT(17) | BIT(21) | BIT(22); 2041 2042 if (brightness == LED_OFF) { 2043 led_gpio_cfg |= BIT(8) | BIT(9) | BIT(13) | BIT(14); 2044 } else { 2045 led_gpio_cfg &= ~(BIT(8) | BIT(9) | BIT(13) | BIT(14)); 2046 led_gpio_cfg &= ~(BIT(0) | BIT(1) | BIT(5) | BIT(6)); 2047 } 2048 2049 rtw_write32(rtwdev, REG_GPIO_PIN_CTRL_2, led_gpio_cfg); 2050 } 2051 2052 static void rtw8814a_fill_txdesc_checksum(struct rtw_dev *rtwdev, 2053 struct rtw_tx_pkt_info *pkt_info, 2054 u8 *txdesc) 2055 { 2056 size_t words = 32 / 2; /* calculate the first 32 bytes (16 words) */ 2057 2058 fill_txdesc_checksum_common(txdesc, words); 2059 } 2060 2061 static const struct rtw_chip_ops rtw8814a_ops = { 2062 .power_on = rtw_power_on, 2063 .power_off = rtw_power_off, 2064 .phy_set_param = rtw8814a_phy_set_param, 2065 .read_efuse = rtw8814a_read_efuse, 2066 .query_phy_status = rtw8814a_query_phy_status, 2067 .set_channel = rtw8814a_set_channel, 2068 .mac_init = rtw8814a_mac_init, 2069 .mac_postinit = NULL, 2070 .read_rf = rtw_phy_read_rf, 2071 .write_rf = rtw_phy_write_rf_reg_sipi, 2072 .set_tx_power_index = rtw8814a_set_tx_power_index, 2073 .set_antenna = NULL, 2074 .cfg_ldo25 = rtw8814a_cfg_ldo25, 2075 .efuse_grant = rtw8814a_efuse_grant, 2076 .set_ampdu_factor = rtw8814a_set_ampdu_factor, 2077 .false_alarm_statistics = rtw8814a_false_alarm_statistics, 2078 .phy_calibration = rtw8814a_phy_calibration, 2079 .cck_pd_set = rtw8814a_phy_cck_pd_set, 2080 .pwr_track = rtw8814a_pwr_track, 2081 .config_bfee = NULL, 2082 .set_gid_table = NULL, 2083 .cfg_csi_rate = NULL, 2084 .led_set = rtw8814a_led_set, 2085 .fill_txdesc_checksum = rtw8814a_fill_txdesc_checksum, 2086 2087 .coex_set_init = rtw8814a_coex_cfg_init, 2088 .coex_set_ant_switch = rtw8814a_coex_cfg_ant_switch, 2089 .coex_set_gnt_fix = rtw8814a_coex_cfg_gnt_fix, 2090 .coex_set_gnt_debug = rtw8814a_coex_cfg_gnt_debug, 2091 .coex_set_rfe_type = rtw8814a_coex_cfg_rfe_type, 2092 .coex_set_wl_tx_power = rtw8814a_coex_cfg_wl_tx_power, 2093 .coex_set_wl_rx_gain = rtw8814a_coex_cfg_wl_rx_gain, 2094 }; 2095 2096 static const struct rtw_rqpn rqpn_table_8814a[] = { 2097 /* SDIO */ 2098 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, /* vo vi */ 2099 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, /* be bk */ 2100 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, /* mg hi */ 2101 /* PCIE */ 2102 {RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_NORMAL, 2103 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2104 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2105 /* USB, 2 bulk out */ 2106 {RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH, 2107 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2108 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2109 /* USB, 3 bulk out */ 2110 {RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_NORMAL, 2111 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2112 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2113 /* USB, 4 bulk out */ 2114 {RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_NORMAL, 2115 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2116 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2117 }; 2118 2119 static const struct rtw_prioq_addrs prioq_addrs_8814a = { 2120 .prio[RTW_DMA_MAPPING_EXTRA] = { 2121 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2, 2122 }, 2123 .prio[RTW_DMA_MAPPING_LOW] = { 2124 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2, 2125 }, 2126 .prio[RTW_DMA_MAPPING_NORMAL] = { 2127 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2, 2128 }, 2129 .prio[RTW_DMA_MAPPING_HIGH] = { 2130 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2, 2131 }, 2132 .wsize = true, 2133 }; 2134 2135 static const struct rtw_page_table page_table_8814a[] = { 2136 /* SDIO */ 2137 {0, 0, 0, 0, 0}, /* hq nq lq exq gapq */ 2138 /* PCIE */ 2139 {32, 32, 32, 32, 0}, 2140 /* USB, 2 bulk out */ 2141 {32, 32, 32, 32, 0}, 2142 /* USB, 3 bulk out */ 2143 {32, 32, 32, 32, 0}, 2144 /* USB, 4 bulk out */ 2145 {32, 32, 32, 32, 0}, 2146 }; 2147 2148 static const struct rtw_intf_phy_para_table phy_para_table_8814a = {}; 2149 2150 static const struct rtw_hw_reg rtw8814a_dig[] = { 2151 [0] = { .addr = 0xc50, .mask = 0x7f }, 2152 [1] = { .addr = 0xe50, .mask = 0x7f }, 2153 [2] = { .addr = 0x1850, .mask = 0x7f }, 2154 [3] = { .addr = 0x1a50, .mask = 0x7f }, 2155 }; 2156 2157 static const struct rtw_rfe_def rtw8814a_rfe_defs[] = { 2158 [0] = { .phy_pg_tbl = &rtw8814a_bb_pg_type0_tbl, 2159 .txpwr_lmt_tbl = &rtw8814a_txpwr_lmt_type0_tbl, 2160 .pwr_track_tbl = &rtw8814a_rtw_pwrtrk_type0_tbl }, 2161 [1] = { .phy_pg_tbl = &rtw8814a_bb_pg_tbl, 2162 .txpwr_lmt_tbl = &rtw8814a_txpwr_lmt_type1_tbl, 2163 .pwr_track_tbl = &rtw8814a_rtw_pwrtrk_tbl }, 2164 }; 2165 2166 /* rssi in percentage % (dbm = % - 100) */ 2167 static const u8 wl_rssi_step_8814a[] = {60, 50, 44, 30}; 2168 static const u8 bt_rssi_step_8814a[] = {30, 30, 30, 30}; 2169 2170 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 2171 static const struct coex_rf_para rf_para_tx_8814a[] = { 2172 {0, 0, false, 7}, /* for normal */ 2173 {0, 16, false, 7}, /* for WL-CPT */ 2174 {4, 0, true, 1}, 2175 {3, 6, true, 1}, 2176 {2, 9, true, 1}, 2177 {1, 13, true, 1} 2178 }; 2179 2180 static const struct coex_rf_para rf_para_rx_8814a[] = { 2181 {0, 0, false, 7}, /* for normal */ 2182 {0, 16, false, 7}, /* for WL-CPT */ 2183 {4, 0, true, 1}, 2184 {3, 6, true, 1}, 2185 {2, 9, true, 1}, 2186 {1, 13, true, 1} 2187 }; 2188 2189 static_assert(ARRAY_SIZE(rf_para_tx_8814a) == ARRAY_SIZE(rf_para_rx_8814a)); 2190 2191 const struct rtw_chip_info rtw8814a_hw_spec = { 2192 .ops = &rtw8814a_ops, 2193 .id = RTW_CHIP_TYPE_8814A, 2194 .fw_name = "rtw88/rtw8814a_fw.bin", 2195 .wlan_cpu = RTW_WCPU_3081, 2196 .tx_pkt_desc_sz = 40, 2197 .tx_buf_desc_sz = 16, 2198 .rx_pkt_desc_sz = 24, 2199 .rx_buf_desc_sz = 8, 2200 .phy_efuse_size = 1024, 2201 .log_efuse_size = 512, 2202 .ptct_efuse_size = 0, 2203 .txff_size = (2048 - 10) * TX_PAGE_SIZE, 2204 .rxff_size = 23552, 2205 .rsvd_drv_pg_num = 8, 2206 .band = RTW_BAND_2G | RTW_BAND_5G, 2207 .page_size = TX_PAGE_SIZE, 2208 .csi_buf_pg_num = 0, 2209 .dig_min = 0x1c, 2210 .txgi_factor = 1, 2211 .is_pwr_by_rate_dec = true, 2212 .rx_ldpc = true, 2213 .max_power_index = 0x3f, 2214 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_2, 2215 .amsdu_in_ampdu = false, /* RX speed is better without AMSDU */ 2216 .usb_tx_agg_desc_num = 3, 2217 .hw_feature_report = false, 2218 .c2h_ra_report_size = 6, 2219 .old_datarate_fb_limit = false, 2220 .ht_supported = true, 2221 .vht_supported = true, 2222 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK), 2223 .sys_func_en = 0xDC, 2224 .pwr_on_seq = card_enable_flow_8814a, 2225 .pwr_off_seq = card_disable_flow_8814a, 2226 .rqpn_table = rqpn_table_8814a, 2227 .prioq_addrs = &prioq_addrs_8814a, 2228 .page_table = page_table_8814a, 2229 .intf_table = &phy_para_table_8814a, 2230 .dig = rtw8814a_dig, 2231 .dig_cck = NULL, 2232 .rf_base_addr = {0x2800, 0x2c00, 0x3800, 0x3c00}, 2233 .rf_sipi_addr = {0xc90, 0xe90, 0x1890, 0x1a90}, 2234 .ltecoex_addr = NULL, 2235 .mac_tbl = &rtw8814a_mac_tbl, 2236 .agc_tbl = &rtw8814a_agc_tbl, 2237 .bb_tbl = &rtw8814a_bb_tbl, 2238 .rf_tbl = {&rtw8814a_rf_a_tbl, &rtw8814a_rf_b_tbl, 2239 &rtw8814a_rf_c_tbl, &rtw8814a_rf_d_tbl}, 2240 .rfe_defs = rtw8814a_rfe_defs, 2241 .rfe_defs_size = ARRAY_SIZE(rtw8814a_rfe_defs), 2242 .iqk_threshold = 8, 2243 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN, 2244 2245 .coex_para_ver = 0, 2246 .bt_desired_ver = 0, 2247 .scbd_support = false, 2248 .new_scbd10_def = false, 2249 .ble_hid_profile_support = false, 2250 .wl_mimo_ps_support = false, 2251 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 2252 .bt_rssi_type = COEX_BTRSSI_RATIO, 2253 .ant_isolation = 15, 2254 .rssi_tolerance = 2, 2255 .wl_rssi_step = wl_rssi_step_8814a, 2256 .bt_rssi_step = bt_rssi_step_8814a, 2257 .table_sant_num = 0, 2258 .table_sant = NULL, 2259 .table_nsant_num = 0, 2260 .table_nsant = NULL, 2261 .tdma_sant_num = 0, 2262 .tdma_sant = NULL, 2263 .tdma_nsant_num = 0, 2264 .tdma_nsant = NULL, 2265 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8814a), 2266 .wl_rf_para_tx = rf_para_tx_8814a, 2267 .wl_rf_para_rx = rf_para_rx_8814a, 2268 .bt_afh_span_bw20 = 0x24, 2269 .bt_afh_span_bw40 = 0x36, 2270 .afh_5g_num = 0, 2271 .afh_5g = NULL, 2272 .coex_info_hw_regs_num = 0, 2273 .coex_info_hw_regs = NULL, 2274 }; 2275 EXPORT_SYMBOL(rtw8814a_hw_spec); 2276 2277 MODULE_FIRMWARE("rtw88/rtw8814a_fw.bin"); 2278 2279 MODULE_AUTHOR("Bitterblue Smith <rtl8821cerfe2@gmail.com>"); 2280 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8814a driver"); 2281 MODULE_LICENSE("Dual BSD/GPL"); 2282