1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright 2024 Fiona Klute 3 * 4 * Based on code originally in rtw8723d.[ch], 5 * Copyright(c) 2018-2019 Realtek Corporation 6 */ 7 8 #include "main.h" 9 #include "debug.h" 10 #include "phy.h" 11 #include "reg.h" 12 #include "tx.h" 13 #include "rtw8723x.h" 14 #if defined(__FreeBSD__) 15 #include <linux/printk.h> 16 #endif 17 18 static const struct rtw_hw_reg rtw8723x_txagc[] = { 19 [DESC_RATE1M] = { .addr = 0xe08, .mask = 0x0000ff00 }, 20 [DESC_RATE2M] = { .addr = 0x86c, .mask = 0x0000ff00 }, 21 [DESC_RATE5_5M] = { .addr = 0x86c, .mask = 0x00ff0000 }, 22 [DESC_RATE11M] = { .addr = 0x86c, .mask = 0xff000000 }, 23 [DESC_RATE6M] = { .addr = 0xe00, .mask = 0x000000ff }, 24 [DESC_RATE9M] = { .addr = 0xe00, .mask = 0x0000ff00 }, 25 [DESC_RATE12M] = { .addr = 0xe00, .mask = 0x00ff0000 }, 26 [DESC_RATE18M] = { .addr = 0xe00, .mask = 0xff000000 }, 27 [DESC_RATE24M] = { .addr = 0xe04, .mask = 0x000000ff }, 28 [DESC_RATE36M] = { .addr = 0xe04, .mask = 0x0000ff00 }, 29 [DESC_RATE48M] = { .addr = 0xe04, .mask = 0x00ff0000 }, 30 [DESC_RATE54M] = { .addr = 0xe04, .mask = 0xff000000 }, 31 [DESC_RATEMCS0] = { .addr = 0xe10, .mask = 0x000000ff }, 32 [DESC_RATEMCS1] = { .addr = 0xe10, .mask = 0x0000ff00 }, 33 [DESC_RATEMCS2] = { .addr = 0xe10, .mask = 0x00ff0000 }, 34 [DESC_RATEMCS3] = { .addr = 0xe10, .mask = 0xff000000 }, 35 [DESC_RATEMCS4] = { .addr = 0xe14, .mask = 0x000000ff }, 36 [DESC_RATEMCS5] = { .addr = 0xe14, .mask = 0x0000ff00 }, 37 [DESC_RATEMCS6] = { .addr = 0xe14, .mask = 0x00ff0000 }, 38 [DESC_RATEMCS7] = { .addr = 0xe14, .mask = 0xff000000 }, 39 }; 40 41 static void __rtw8723x_lck(struct rtw_dev *rtwdev) 42 { 43 u32 lc_cal; 44 u8 val_ctx, rf_val; 45 int ret; 46 47 val_ctx = rtw_read8(rtwdev, REG_CTX); 48 if ((val_ctx & BIT_MASK_CTX_TYPE) != 0) 49 rtw_write8(rtwdev, REG_CTX, val_ctx & ~BIT_MASK_CTX_TYPE); 50 else 51 rtw_write8(rtwdev, REG_TXPAUSE, 0xFF); 52 lc_cal = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK); 53 54 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal | BIT_LCK); 55 56 ret = read_poll_timeout(rtw_read_rf, rf_val, rf_val != 0x1, 57 10000, 1000000, false, 58 rtwdev, RF_PATH_A, RF_CFGCH, BIT_LCK); 59 if (ret) 60 rtw_warn(rtwdev, "failed to poll LCK status bit\n"); 61 62 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal); 63 if ((val_ctx & BIT_MASK_CTX_TYPE) != 0) 64 rtw_write8(rtwdev, REG_CTX, val_ctx); 65 else 66 rtw_write8(rtwdev, REG_TXPAUSE, 0x00); 67 } 68 69 #define DBG_EFUSE_VAL(rtwdev, map, name) \ 70 rtw_dbg(rtwdev, RTW_DBG_EFUSE, # name "=0x%02x\n", \ 71 (map)->name) 72 #define DBG_EFUSE_2BYTE(rtwdev, map, name) \ 73 rtw_dbg(rtwdev, RTW_DBG_EFUSE, # name "=0x%02x%02x\n", \ 74 (map)->name[0], (map)->name[1]) 75 #define DBG_EFUSE_FIX(rtwdev, name) \ 76 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "Fixed invalid EFUSE value: " \ 77 # name "=0x%x\n", rtwdev->efuse.name) 78 79 static void rtw8723xe_efuse_debug(struct rtw_dev *rtwdev, 80 struct rtw8723x_efuse *map) 81 { 82 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "mac_addr=%pM\n", map->e.mac_addr); 83 DBG_EFUSE_2BYTE(rtwdev, map, e.vendor_id); 84 DBG_EFUSE_2BYTE(rtwdev, map, e.device_id); 85 DBG_EFUSE_2BYTE(rtwdev, map, e.sub_vendor_id); 86 DBG_EFUSE_2BYTE(rtwdev, map, e.sub_device_id); 87 } 88 89 static void rtw8723xu_efuse_debug(struct rtw_dev *rtwdev, 90 struct rtw8723x_efuse *map) 91 { 92 DBG_EFUSE_2BYTE(rtwdev, map, u.vendor_id); 93 DBG_EFUSE_2BYTE(rtwdev, map, u.product_id); 94 DBG_EFUSE_VAL(rtwdev, map, u.usb_option); 95 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "mac_addr=%pM\n", map->u.mac_addr); 96 } 97 98 static void rtw8723xs_efuse_debug(struct rtw_dev *rtwdev, 99 struct rtw8723x_efuse *map) 100 { 101 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "mac_addr=%pM\n", map->s.mac_addr); 102 } 103 104 static void __rtw8723x_debug_txpwr_limit(struct rtw_dev *rtwdev, 105 struct rtw_txpwr_idx *table, 106 int tx_path_count) 107 { 108 if (!rtw_dbg_is_enabled(rtwdev, RTW_DBG_EFUSE)) 109 return; 110 111 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 112 "Power index table (2.4G):\n"); 113 /* CCK base */ 114 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "CCK base\n"); 115 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF G0 G1 G2 G3 G4 G5\n"); 116 for (int i = 0; i < tx_path_count; i++) 117 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 118 "[%c]: %3u %3u %3u %3u %3u %3u\n", 119 'A' + i, 120 table[i].pwr_idx_2g.cck_base[0], 121 table[i].pwr_idx_2g.cck_base[1], 122 table[i].pwr_idx_2g.cck_base[2], 123 table[i].pwr_idx_2g.cck_base[3], 124 table[i].pwr_idx_2g.cck_base[4], 125 table[i].pwr_idx_2g.cck_base[5]); 126 /* CCK diff */ 127 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "CCK diff\n"); 128 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF 1S 2S 3S 4S\n"); 129 for (int i = 0; i < tx_path_count; i++) 130 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 131 "[%c]: %2d %2d %2d %2d\n", 132 'A' + i, 0 /* no diff for 1S */, 133 table[i].pwr_idx_2g.ht_2s_diff.cck, 134 table[i].pwr_idx_2g.ht_3s_diff.cck, 135 table[i].pwr_idx_2g.ht_4s_diff.cck); 136 /* BW40-1S base */ 137 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "BW40-1S base\n"); 138 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF G0 G1 G2 G3 G4\n"); 139 for (int i = 0; i < tx_path_count; i++) 140 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 141 "[%c]: %3u %3u %3u %3u %3u\n", 142 'A' + i, 143 table[i].pwr_idx_2g.bw40_base[0], 144 table[i].pwr_idx_2g.bw40_base[1], 145 table[i].pwr_idx_2g.bw40_base[2], 146 table[i].pwr_idx_2g.bw40_base[3], 147 table[i].pwr_idx_2g.bw40_base[4]); 148 /* OFDM diff */ 149 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "OFDM diff\n"); 150 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF 1S 2S 3S 4S\n"); 151 for (int i = 0; i < tx_path_count; i++) 152 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 153 "[%c]: %2d %2d %2d %2d\n", 154 'A' + i, 155 table[i].pwr_idx_2g.ht_1s_diff.ofdm, 156 table[i].pwr_idx_2g.ht_2s_diff.ofdm, 157 table[i].pwr_idx_2g.ht_3s_diff.ofdm, 158 table[i].pwr_idx_2g.ht_4s_diff.ofdm); 159 /* BW20 diff */ 160 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "BW20 diff\n"); 161 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF 1S 2S 3S 4S\n"); 162 for (int i = 0; i < tx_path_count; i++) 163 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 164 "[%c]: %2d %2d %2d %2d\n", 165 'A' + i, 166 table[i].pwr_idx_2g.ht_1s_diff.bw20, 167 table[i].pwr_idx_2g.ht_2s_diff.bw20, 168 table[i].pwr_idx_2g.ht_3s_diff.bw20, 169 table[i].pwr_idx_2g.ht_4s_diff.bw20); 170 /* BW40 diff */ 171 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "BW40 diff\n"); 172 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF 1S 2S 3S 4S\n"); 173 for (int i = 0; i < tx_path_count; i++) 174 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 175 "[%c]: %2d %2d %2d %2d\n", 176 'A' + i, 0 /* no diff for 1S */, 177 table[i].pwr_idx_2g.ht_2s_diff.bw40, 178 table[i].pwr_idx_2g.ht_3s_diff.bw40, 179 table[i].pwr_idx_2g.ht_4s_diff.bw40); 180 } 181 182 static void efuse_debug_dump(struct rtw_dev *rtwdev, 183 struct rtw8723x_efuse *map) 184 { 185 if (!rtw_dbg_is_enabled(rtwdev, RTW_DBG_EFUSE)) 186 return; 187 188 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "EFUSE raw logical map:\n"); 189 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1, 190 (u8 *)map, sizeof(struct rtw8723x_efuse), false); 191 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "Parsed rtw8723x EFUSE data:\n"); 192 DBG_EFUSE_VAL(rtwdev, map, rtl_id); 193 DBG_EFUSE_VAL(rtwdev, map, afe); 194 rtw8723x_debug_txpwr_limit(rtwdev, map->txpwr_idx_table, 4); 195 DBG_EFUSE_VAL(rtwdev, map, channel_plan); 196 DBG_EFUSE_VAL(rtwdev, map, xtal_k); 197 DBG_EFUSE_VAL(rtwdev, map, thermal_meter); 198 DBG_EFUSE_VAL(rtwdev, map, iqk_lck); 199 DBG_EFUSE_VAL(rtwdev, map, pa_type); 200 DBG_EFUSE_2BYTE(rtwdev, map, lna_type_2g); 201 DBG_EFUSE_2BYTE(rtwdev, map, lna_type_5g); 202 DBG_EFUSE_VAL(rtwdev, map, rf_board_option); 203 DBG_EFUSE_VAL(rtwdev, map, rf_feature_option); 204 DBG_EFUSE_VAL(rtwdev, map, rf_bt_setting); 205 DBG_EFUSE_VAL(rtwdev, map, eeprom_version); 206 DBG_EFUSE_VAL(rtwdev, map, eeprom_customer_id); 207 DBG_EFUSE_VAL(rtwdev, map, tx_bb_swing_setting_2g); 208 DBG_EFUSE_VAL(rtwdev, map, tx_pwr_calibrate_rate); 209 DBG_EFUSE_VAL(rtwdev, map, rf_antenna_option); 210 DBG_EFUSE_VAL(rtwdev, map, rfe_option); 211 DBG_EFUSE_2BYTE(rtwdev, map, country_code); 212 213 switch (rtw_hci_type(rtwdev)) { 214 case RTW_HCI_TYPE_PCIE: 215 rtw8723xe_efuse_debug(rtwdev, map); 216 break; 217 case RTW_HCI_TYPE_USB: 218 rtw8723xu_efuse_debug(rtwdev, map); 219 break; 220 case RTW_HCI_TYPE_SDIO: 221 rtw8723xs_efuse_debug(rtwdev, map); 222 break; 223 default: 224 /* unsupported now */ 225 break; 226 } 227 } 228 229 static void rtw8723xe_efuse_parsing(struct rtw_efuse *efuse, 230 struct rtw8723x_efuse *map) 231 { 232 ether_addr_copy(efuse->addr, map->e.mac_addr); 233 } 234 235 static void rtw8723xu_efuse_parsing(struct rtw_efuse *efuse, 236 struct rtw8723x_efuse *map) 237 { 238 ether_addr_copy(efuse->addr, map->u.mac_addr); 239 } 240 241 static void rtw8723xs_efuse_parsing(struct rtw_efuse *efuse, 242 struct rtw8723x_efuse *map) 243 { 244 ether_addr_copy(efuse->addr, map->s.mac_addr); 245 } 246 247 /* Default power index table for RTL8703B/RTL8723D, used if EFUSE does 248 * not contain valid data. Replaces EFUSE data from offset 0x10 (start 249 * of txpwr_idx_table). 250 */ 251 static const u8 rtw8723x_txpwr_idx_table[] = { 252 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 253 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02 254 }; 255 256 static int __rtw8723x_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 257 { 258 struct rtw_efuse *efuse = &rtwdev->efuse; 259 u8 *pwr = (u8 *)efuse->txpwr_idx_table; 260 struct rtw8723x_efuse *map; 261 bool valid = false; 262 int i; 263 264 map = (struct rtw8723x_efuse *)log_map; 265 efuse_debug_dump(rtwdev, map); 266 267 efuse->rfe_option = 0; 268 efuse->rf_board_option = map->rf_board_option; 269 efuse->crystal_cap = map->xtal_k; 270 efuse->pa_type_2g = map->pa_type; 271 efuse->lna_type_2g = map->lna_type_2g[0]; 272 efuse->channel_plan = map->channel_plan; 273 efuse->country_code[0] = map->country_code[0]; 274 efuse->country_code[1] = map->country_code[1]; 275 efuse->bt_setting = map->rf_bt_setting; 276 efuse->regd = map->rf_board_option & 0x7; 277 efuse->thermal_meter[0] = map->thermal_meter; 278 efuse->thermal_meter_k = map->thermal_meter; 279 efuse->afe = map->afe; 280 281 for (i = 0; i < 4; i++) 282 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 283 284 switch (rtw_hci_type(rtwdev)) { 285 case RTW_HCI_TYPE_PCIE: 286 rtw8723xe_efuse_parsing(efuse, map); 287 break; 288 case RTW_HCI_TYPE_USB: 289 rtw8723xu_efuse_parsing(efuse, map); 290 break; 291 case RTW_HCI_TYPE_SDIO: 292 rtw8723xs_efuse_parsing(efuse, map); 293 break; 294 default: 295 /* unsupported now */ 296 return -EOPNOTSUPP; 297 } 298 299 /* If TX power index table in EFUSE is invalid, fall back to 300 * built-in table. 301 */ 302 for (i = 0; i < ARRAY_SIZE(rtw8723x_txpwr_idx_table); i++) 303 if (pwr[i] != 0xff) { 304 valid = true; 305 break; 306 } 307 if (!valid) { 308 for (i = 0; i < ARRAY_SIZE(rtw8723x_txpwr_idx_table); i++) 309 pwr[i] = rtw8723x_txpwr_idx_table[i]; 310 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 311 "Replaced invalid EFUSE TX power index table."); 312 rtw8723x_debug_txpwr_limit(rtwdev, 313 efuse->txpwr_idx_table, 2); 314 } 315 316 /* Override invalid antenna settings. */ 317 if (efuse->bt_setting == 0xff) { 318 /* shared antenna */ 319 efuse->bt_setting |= BIT(0); 320 /* RF path A */ 321 efuse->bt_setting &= ~BIT(6); 322 DBG_EFUSE_FIX(rtwdev, bt_setting); 323 } 324 325 /* Override invalid board options: The coex code incorrectly 326 * assumes that if bits 6 & 7 are set the board doesn't 327 * support coex. Regd is also derived from rf_board_option and 328 * should be 0 if there's no valid data. 329 */ 330 if (efuse->rf_board_option == 0xff) { 331 efuse->regd = 0; 332 efuse->rf_board_option &= GENMASK(5, 0); 333 DBG_EFUSE_FIX(rtwdev, rf_board_option); 334 } 335 336 /* Override invalid crystal cap setting, default comes from 337 * vendor driver. Chip specific. 338 */ 339 if (efuse->crystal_cap == 0xff) { 340 efuse->crystal_cap = 0x20; 341 DBG_EFUSE_FIX(rtwdev, crystal_cap); 342 } 343 344 return 0; 345 } 346 347 #define BIT_CFENDFORM BIT(9) 348 #define BIT_WMAC_TCR_ERR0 BIT(12) 349 #define BIT_WMAC_TCR_ERR1 BIT(13) 350 #define BIT_TCR_CFG (BIT_CFENDFORM | BIT_WMAC_TCR_ERR0 | \ 351 BIT_WMAC_TCR_ERR1) 352 #define WLAN_RX_FILTER0 0xFFFF 353 #define WLAN_RX_FILTER1 0x400 354 #define WLAN_RX_FILTER2 0xFFFF 355 #define WLAN_RCR_CFG 0x700060CE 356 357 static int __rtw8723x_mac_init(struct rtw_dev *rtwdev) 358 { 359 rtw_write32(rtwdev, REG_TCR, BIT_TCR_CFG); 360 361 rtw_write16(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 362 rtw_write16(rtwdev, REG_RXFLTMAP1, WLAN_RX_FILTER1); 363 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 364 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 365 366 rtw_write32(rtwdev, REG_INT_MIG, 0); 367 rtw_write32(rtwdev, REG_MCUTST_1, 0x0); 368 369 rtw_write8(rtwdev, REG_MISC_CTRL, BIT_DIS_SECOND_CCA); 370 rtw_write8(rtwdev, REG_2ND_CCA_CTRL, 0); 371 372 return 0; 373 } 374 375 static int __rtw8723x_mac_postinit(struct rtw_dev *rtwdev) 376 { 377 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); 378 379 return 0; 380 } 381 382 static void __rtw8723x_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 383 { 384 u8 ldo_pwr; 385 386 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); 387 if (enable) { 388 ldo_pwr &= ~BIT_MASK_LDO25_VOLTAGE; 389 ldo_pwr |= (BIT_LDO25_VOLTAGE_V25 << 4) | BIT_LDO25_EN; 390 } else { 391 ldo_pwr &= ~BIT_LDO25_EN; 392 } 393 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); 394 } 395 396 static void 397 rtw8723x_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) 398 { 399 struct rtw_hal *hal = &rtwdev->hal; 400 const struct rtw_hw_reg *txagc; 401 u8 rate, pwr_index; 402 int j; 403 404 for (j = 0; j < rtw_rate_size[rs]; j++) { 405 rate = rtw_rate_section[rs][j]; 406 pwr_index = hal->tx_pwr_tbl[path][rate]; 407 408 if (rate >= ARRAY_SIZE(rtw8723x_txagc)) { 409 rtw_warn(rtwdev, "rate 0x%x isn't supported\n", rate); 410 continue; 411 } 412 txagc = &rtw8723x_txagc[rate]; 413 if (!txagc->addr) { 414 rtw_warn(rtwdev, "rate 0x%x isn't defined\n", rate); 415 continue; 416 } 417 418 rtw_write32_mask(rtwdev, txagc->addr, txagc->mask, pwr_index); 419 } 420 } 421 422 static void __rtw8723x_set_tx_power_index(struct rtw_dev *rtwdev) 423 { 424 struct rtw_hal *hal = &rtwdev->hal; 425 int rs, path; 426 427 for (path = 0; path < hal->rf_path_num; path++) { 428 for (rs = 0; rs <= RTW_RATE_SECTION_HT_1S; rs++) 429 rtw8723x_set_tx_power_index_by_rate(rtwdev, path, rs); 430 } 431 } 432 433 static void __rtw8723x_efuse_grant(struct rtw_dev *rtwdev, bool on) 434 { 435 if (on) { 436 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); 437 438 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_ELDR); 439 rtw_write16_set(rtwdev, REG_SYS_CLKR, BIT_LOADER_CLK_EN | BIT_ANA8M); 440 } else { 441 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF); 442 } 443 } 444 445 static void __rtw8723x_false_alarm_statistics(struct rtw_dev *rtwdev) 446 { 447 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 448 u32 cck_fa_cnt; 449 u32 ofdm_fa_cnt; 450 u32 crc32_cnt; 451 u32 val32; 452 453 /* hold counter */ 454 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 1); 455 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 1); 456 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KEEP, 1); 457 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KEEP, 1); 458 459 cck_fa_cnt = rtw_read32_mask(rtwdev, REG_CCK_FA_LSB_11N, MASKBYTE0); 460 cck_fa_cnt += rtw_read32_mask(rtwdev, REG_CCK_FA_MSB_11N, MASKBYTE3) << 8; 461 462 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE1_11N); 463 ofdm_fa_cnt = u32_get_bits(val32, BIT_MASK_OFDM_FF_CNT); 464 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_SF_CNT); 465 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE2_11N); 466 dm_info->ofdm_cca_cnt = u32_get_bits(val32, BIT_MASK_OFDM_CCA_CNT); 467 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_PF_CNT); 468 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE3_11N); 469 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_RI_CNT); 470 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_CRC_CNT); 471 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE4_11N); 472 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_MNS_CNT); 473 474 dm_info->cck_fa_cnt = cck_fa_cnt; 475 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 476 dm_info->total_fa_cnt = cck_fa_cnt + ofdm_fa_cnt; 477 478 dm_info->cck_err_cnt = rtw_read32(rtwdev, REG_IGI_C_11N); 479 dm_info->cck_ok_cnt = rtw_read32(rtwdev, REG_IGI_D_11N); 480 crc32_cnt = rtw_read32(rtwdev, REG_OFDM_CRC32_CNT_11N); 481 dm_info->ofdm_err_cnt = u32_get_bits(crc32_cnt, BIT_MASK_OFDM_LCRC_ERR); 482 dm_info->ofdm_ok_cnt = u32_get_bits(crc32_cnt, BIT_MASK_OFDM_LCRC_OK); 483 crc32_cnt = rtw_read32(rtwdev, REG_HT_CRC32_CNT_11N); 484 dm_info->ht_err_cnt = u32_get_bits(crc32_cnt, BIT_MASK_HT_CRC_ERR); 485 dm_info->ht_ok_cnt = u32_get_bits(crc32_cnt, BIT_MASK_HT_CRC_OK); 486 dm_info->vht_err_cnt = 0; 487 dm_info->vht_ok_cnt = 0; 488 489 val32 = rtw_read32(rtwdev, REG_CCK_CCA_CNT_11N); 490 dm_info->cck_cca_cnt = (u32_get_bits(val32, BIT_MASK_CCK_FA_MSB) << 8) | 491 u32_get_bits(val32, BIT_MASK_CCK_FA_LSB); 492 dm_info->total_cca_cnt = dm_info->cck_cca_cnt + dm_info->ofdm_cca_cnt; 493 494 /* reset counter */ 495 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 1); 496 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 0); 497 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 1); 498 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 0); 499 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 0); 500 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 0); 501 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 0); 502 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 2); 503 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 0); 504 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 2); 505 rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 1); 506 rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 0); 507 } 508 509 /* IQK (IQ calibration) */ 510 511 static 512 void __rtw8723x_iqk_backup_regs(struct rtw_dev *rtwdev, 513 struct rtw8723x_iqk_backup_regs *backup) 514 { 515 int i; 516 517 for (i = 0; i < RTW8723X_IQK_ADDA_REG_NUM; i++) 518 backup->adda[i] = rtw_read32(rtwdev, 519 rtw8723x_common.iqk_adda_regs[i]); 520 521 for (i = 0; i < RTW8723X_IQK_MAC8_REG_NUM; i++) 522 backup->mac8[i] = rtw_read8(rtwdev, 523 rtw8723x_common.iqk_mac8_regs[i]); 524 for (i = 0; i < RTW8723X_IQK_MAC32_REG_NUM; i++) 525 backup->mac32[i] = rtw_read32(rtwdev, 526 rtw8723x_common.iqk_mac32_regs[i]); 527 528 for (i = 0; i < RTW8723X_IQK_BB_REG_NUM; i++) 529 backup->bb[i] = rtw_read32(rtwdev, 530 rtw8723x_common.iqk_bb_regs[i]); 531 532 backup->igia = rtw_read32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0); 533 backup->igib = rtw_read32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0); 534 535 backup->bb_sel_btg = rtw_read32(rtwdev, REG_BB_SEL_BTG); 536 } 537 538 static 539 void __rtw8723x_iqk_restore_regs(struct rtw_dev *rtwdev, 540 const struct rtw8723x_iqk_backup_regs *backup) 541 { 542 int i; 543 544 for (i = 0; i < RTW8723X_IQK_ADDA_REG_NUM; i++) 545 rtw_write32(rtwdev, rtw8723x_common.iqk_adda_regs[i], 546 backup->adda[i]); 547 548 for (i = 0; i < RTW8723X_IQK_MAC8_REG_NUM; i++) 549 rtw_write8(rtwdev, rtw8723x_common.iqk_mac8_regs[i], 550 backup->mac8[i]); 551 for (i = 0; i < RTW8723X_IQK_MAC32_REG_NUM; i++) 552 rtw_write32(rtwdev, rtw8723x_common.iqk_mac32_regs[i], 553 backup->mac32[i]); 554 555 for (i = 0; i < RTW8723X_IQK_BB_REG_NUM; i++) 556 rtw_write32(rtwdev, rtw8723x_common.iqk_bb_regs[i], 557 backup->bb[i]); 558 559 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); 560 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, backup->igia); 561 562 rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, 0x50); 563 rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, backup->igib); 564 565 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x01008c00); 566 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x01008c00); 567 } 568 569 static 570 bool __rtw8723x_iqk_similarity_cmp(struct rtw_dev *rtwdev, 571 s32 result[][IQK_NR], 572 u8 c1, u8 c2) 573 { 574 u32 i, j, diff; 575 u32 bitmap = 0; 576 u8 candidate[PATH_NR] = {IQK_ROUND_INVALID, IQK_ROUND_INVALID}; 577 bool ret = true; 578 579 s32 tmp1, tmp2; 580 581 for (i = 0; i < IQK_NR; i++) { 582 tmp1 = iqkxy_to_s32(result[c1][i]); 583 tmp2 = iqkxy_to_s32(result[c2][i]); 584 585 diff = abs(tmp1 - tmp2); 586 587 if (diff <= MAX_TOLERANCE) 588 continue; 589 590 if ((i == IQK_S1_RX_X || i == IQK_S0_RX_X) && !bitmap) { 591 if (result[c1][i] + result[c1][i + 1] == 0) 592 candidate[i / IQK_SX_NR] = c2; 593 else if (result[c2][i] + result[c2][i + 1] == 0) 594 candidate[i / IQK_SX_NR] = c1; 595 else 596 bitmap |= BIT(i); 597 } else { 598 bitmap |= BIT(i); 599 } 600 } 601 602 if (bitmap != 0) 603 goto check_sim; 604 605 for (i = 0; i < PATH_NR; i++) { 606 if (candidate[i] == IQK_ROUND_INVALID) 607 continue; 608 609 for (j = i * IQK_SX_NR; j < i * IQK_SX_NR + 2; j++) 610 result[IQK_ROUND_HYBRID][j] = result[candidate[i]][j]; 611 ret = false; 612 } 613 614 return ret; 615 616 check_sim: 617 for (i = 0; i < IQK_NR; i++) { 618 j = i & ~1; /* 2 bits are a pair for IQ[X, Y] */ 619 if (bitmap & GENMASK(j + 1, j)) 620 continue; 621 622 result[IQK_ROUND_HYBRID][i] = result[c1][i]; 623 } 624 625 return false; 626 } 627 628 static u8 __rtw8723x_pwrtrack_get_limit_ofdm(struct rtw_dev *rtwdev) 629 { 630 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 631 u8 tx_rate = dm_info->tx_rate; 632 u8 limit_ofdm = 30; 633 634 switch (tx_rate) { 635 case DESC_RATE1M...DESC_RATE5_5M: 636 case DESC_RATE11M: 637 break; 638 case DESC_RATE6M...DESC_RATE48M: 639 limit_ofdm = 36; 640 break; 641 case DESC_RATE54M: 642 limit_ofdm = 34; 643 break; 644 case DESC_RATEMCS0...DESC_RATEMCS2: 645 limit_ofdm = 38; 646 break; 647 case DESC_RATEMCS3...DESC_RATEMCS4: 648 limit_ofdm = 36; 649 break; 650 case DESC_RATEMCS5...DESC_RATEMCS7: 651 limit_ofdm = 34; 652 break; 653 default: 654 rtw_warn(rtwdev, "pwrtrack unhandled tx_rate 0x%x\n", tx_rate); 655 break; 656 } 657 658 return limit_ofdm; 659 } 660 661 static 662 void __rtw8723x_pwrtrack_set_xtal(struct rtw_dev *rtwdev, u8 therm_path, 663 u8 delta) 664 { 665 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 666 const struct rtw_rfe_def *rfe_def = rtw_get_rfe_def(rtwdev); 667 const struct rtw_pwr_track_tbl *tbl = rfe_def->pwr_track_tbl; 668 const s8 *pwrtrk_xtal; 669 s8 xtal_cap; 670 671 if (dm_info->thermal_avg[therm_path] > 672 rtwdev->efuse.thermal_meter[therm_path]) 673 pwrtrk_xtal = tbl->pwrtrk_xtal_p; 674 else 675 pwrtrk_xtal = tbl->pwrtrk_xtal_n; 676 677 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F; 678 xtal_cap = clamp_t(s8, xtal_cap + pwrtrk_xtal[delta], 0, 0x3F); 679 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, 680 xtal_cap | (xtal_cap << 6)); 681 } 682 683 static 684 void __rtw8723x_fill_txdesc_checksum(struct rtw_dev *rtwdev, 685 struct rtw_tx_pkt_info *pkt_info, 686 u8 *txdesc) 687 { 688 size_t words = 32 / 2; /* calculate the first 32 bytes (16 words) */ 689 __le16 chksum = 0; 690 __le16 *data = (__le16 *)(txdesc); 691 struct rtw_tx_desc *tx_desc = (struct rtw_tx_desc *)txdesc; 692 693 le32p_replace_bits(&tx_desc->w7, 0, RTW_TX_DESC_W7_TXDESC_CHECKSUM); 694 695 while (words--) 696 chksum ^= *data++; 697 698 chksum = ~chksum; 699 700 le32p_replace_bits(&tx_desc->w7, __le16_to_cpu(chksum), 701 RTW_TX_DESC_W7_TXDESC_CHECKSUM); 702 } 703 704 static void __rtw8723x_coex_cfg_init(struct rtw_dev *rtwdev) 705 { 706 /* enable TBTT nterrupt */ 707 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 708 709 /* BT report packet sample rate */ 710 /* 0x790[5:0]=0x5 */ 711 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); 712 713 /* enable BT counter statistics */ 714 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); 715 716 /* enable PTA (3-wire function form BT side) */ 717 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 718 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); 719 720 /* enable PTA (tx/rx signal form WiFi side) */ 721 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 722 } 723 724 const struct rtw8723x_common rtw8723x_common = { 725 .iqk_adda_regs = { 726 0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 727 0xe88, 0xe8c, 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xeec 728 }, 729 .iqk_mac8_regs = {0x522, 0x550, 0x551}, 730 .iqk_mac32_regs = {0x40}, 731 .iqk_bb_regs = { 732 0xc04, 0xc08, 0x874, 0xb68, 0xb6c, 0x870, 0x860, 0x864, 0xa04 733 }, 734 735 .ltecoex_addr = { 736 .ctrl = REG_LTECOEX_CTRL, 737 .wdata = REG_LTECOEX_WRITE_DATA, 738 .rdata = REG_LTECOEX_READ_DATA, 739 }, 740 .rf_sipi_addr = { 741 [RF_PATH_A] = { .hssi_1 = 0x820, .lssi_read = 0x8a0, 742 .hssi_2 = 0x824, .lssi_read_pi = 0x8b8}, 743 [RF_PATH_B] = { .hssi_1 = 0x828, .lssi_read = 0x8a4, 744 .hssi_2 = 0x82c, .lssi_read_pi = 0x8bc}, 745 }, 746 .dig = { 747 [0] = { .addr = 0xc50, .mask = 0x7f }, 748 [1] = { .addr = 0xc50, .mask = 0x7f }, 749 }, 750 .dig_cck = { 751 [0] = { .addr = 0xa0c, .mask = 0x3f00 }, 752 }, 753 .prioq_addrs = { 754 .prio[RTW_DMA_MAPPING_EXTRA] = { 755 .rsvd = REG_RQPN_NPQ + 2, .avail = REG_RQPN_NPQ + 3, 756 }, 757 .prio[RTW_DMA_MAPPING_LOW] = { 758 .rsvd = REG_RQPN + 1, .avail = REG_FIFOPAGE_CTRL_2 + 1, 759 }, 760 .prio[RTW_DMA_MAPPING_NORMAL] = { 761 .rsvd = REG_RQPN_NPQ, .avail = REG_RQPN_NPQ + 1, 762 }, 763 .prio[RTW_DMA_MAPPING_HIGH] = { 764 .rsvd = REG_RQPN, .avail = REG_FIFOPAGE_CTRL_2, 765 }, 766 .wsize = false, 767 }, 768 769 .lck = __rtw8723x_lck, 770 .read_efuse = __rtw8723x_read_efuse, 771 .mac_init = __rtw8723x_mac_init, 772 .mac_postinit = __rtw8723x_mac_postinit, 773 .cfg_ldo25 = __rtw8723x_cfg_ldo25, 774 .set_tx_power_index = __rtw8723x_set_tx_power_index, 775 .efuse_grant = __rtw8723x_efuse_grant, 776 .false_alarm_statistics = __rtw8723x_false_alarm_statistics, 777 .iqk_backup_regs = __rtw8723x_iqk_backup_regs, 778 .iqk_restore_regs = __rtw8723x_iqk_restore_regs, 779 .iqk_similarity_cmp = __rtw8723x_iqk_similarity_cmp, 780 .pwrtrack_get_limit_ofdm = __rtw8723x_pwrtrack_get_limit_ofdm, 781 .pwrtrack_set_xtal = __rtw8723x_pwrtrack_set_xtal, 782 .coex_cfg_init = __rtw8723x_coex_cfg_init, 783 .fill_txdesc_checksum = __rtw8723x_fill_txdesc_checksum, 784 .debug_txpwr_limit = __rtw8723x_debug_txpwr_limit, 785 }; 786 EXPORT_SYMBOL(rtw8723x_common); 787 788 MODULE_AUTHOR("Realtek Corporation"); 789 MODULE_AUTHOR("Fiona Klute <fiona.klute@gmx.de>"); 790 MODULE_DESCRIPTION("Common functions for Realtek 802.11n wireless 8723x drivers"); 791 MODULE_LICENSE("Dual BSD/GPL"); 792