1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright 2024 Fiona Klute 3 * 4 * Based on code originally in rtw8723d.[ch], 5 * Copyright(c) 2018-2019 Realtek Corporation 6 */ 7 8 #include "main.h" 9 #include "debug.h" 10 #include "phy.h" 11 #include "reg.h" 12 #include "tx.h" 13 #include "rtw8723x.h" 14 #if defined(__FreeBSD__) 15 #include <linux/printk.h> 16 #endif 17 18 static const struct rtw_hw_reg rtw8723x_txagc[] = { 19 [DESC_RATE1M] = { .addr = 0xe08, .mask = 0x0000ff00 }, 20 [DESC_RATE2M] = { .addr = 0x86c, .mask = 0x0000ff00 }, 21 [DESC_RATE5_5M] = { .addr = 0x86c, .mask = 0x00ff0000 }, 22 [DESC_RATE11M] = { .addr = 0x86c, .mask = 0xff000000 }, 23 [DESC_RATE6M] = { .addr = 0xe00, .mask = 0x000000ff }, 24 [DESC_RATE9M] = { .addr = 0xe00, .mask = 0x0000ff00 }, 25 [DESC_RATE12M] = { .addr = 0xe00, .mask = 0x00ff0000 }, 26 [DESC_RATE18M] = { .addr = 0xe00, .mask = 0xff000000 }, 27 [DESC_RATE24M] = { .addr = 0xe04, .mask = 0x000000ff }, 28 [DESC_RATE36M] = { .addr = 0xe04, .mask = 0x0000ff00 }, 29 [DESC_RATE48M] = { .addr = 0xe04, .mask = 0x00ff0000 }, 30 [DESC_RATE54M] = { .addr = 0xe04, .mask = 0xff000000 }, 31 [DESC_RATEMCS0] = { .addr = 0xe10, .mask = 0x000000ff }, 32 [DESC_RATEMCS1] = { .addr = 0xe10, .mask = 0x0000ff00 }, 33 [DESC_RATEMCS2] = { .addr = 0xe10, .mask = 0x00ff0000 }, 34 [DESC_RATEMCS3] = { .addr = 0xe10, .mask = 0xff000000 }, 35 [DESC_RATEMCS4] = { .addr = 0xe14, .mask = 0x000000ff }, 36 [DESC_RATEMCS5] = { .addr = 0xe14, .mask = 0x0000ff00 }, 37 [DESC_RATEMCS6] = { .addr = 0xe14, .mask = 0x00ff0000 }, 38 [DESC_RATEMCS7] = { .addr = 0xe14, .mask = 0xff000000 }, 39 }; 40 41 static void __rtw8723x_lck(struct rtw_dev *rtwdev) 42 { 43 u32 lc_cal; 44 u8 val_ctx, rf_val; 45 int ret; 46 47 val_ctx = rtw_read8(rtwdev, REG_CTX); 48 if ((val_ctx & BIT_MASK_CTX_TYPE) != 0) 49 rtw_write8(rtwdev, REG_CTX, val_ctx & ~BIT_MASK_CTX_TYPE); 50 else 51 rtw_write8(rtwdev, REG_TXPAUSE, 0xFF); 52 lc_cal = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK); 53 54 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal | BIT_LCK); 55 56 ret = read_poll_timeout(rtw_read_rf, rf_val, rf_val != 0x1, 57 10000, 1000000, false, 58 rtwdev, RF_PATH_A, RF_CFGCH, BIT_LCK); 59 if (ret) 60 rtw_warn(rtwdev, "failed to poll LCK status bit\n"); 61 62 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, lc_cal); 63 if ((val_ctx & BIT_MASK_CTX_TYPE) != 0) 64 rtw_write8(rtwdev, REG_CTX, val_ctx); 65 else 66 rtw_write8(rtwdev, REG_TXPAUSE, 0x00); 67 } 68 69 #define DBG_EFUSE_VAL(rtwdev, map, name) \ 70 rtw_dbg(rtwdev, RTW_DBG_EFUSE, # name "=0x%02x\n", \ 71 (map)->name) 72 #define DBG_EFUSE_2BYTE(rtwdev, map, name) \ 73 rtw_dbg(rtwdev, RTW_DBG_EFUSE, # name "=0x%02x%02x\n", \ 74 (map)->name[0], (map)->name[1]) 75 76 static void rtw8723xe_efuse_debug(struct rtw_dev *rtwdev, 77 struct rtw8723x_efuse *map) 78 { 79 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "mac_addr=%pM\n", map->e.mac_addr); 80 DBG_EFUSE_2BYTE(rtwdev, map, e.vendor_id); 81 DBG_EFUSE_2BYTE(rtwdev, map, e.device_id); 82 DBG_EFUSE_2BYTE(rtwdev, map, e.sub_vendor_id); 83 DBG_EFUSE_2BYTE(rtwdev, map, e.sub_device_id); 84 } 85 86 static void rtw8723xu_efuse_debug(struct rtw_dev *rtwdev, 87 struct rtw8723x_efuse *map) 88 { 89 DBG_EFUSE_2BYTE(rtwdev, map, u.vendor_id); 90 DBG_EFUSE_2BYTE(rtwdev, map, u.product_id); 91 DBG_EFUSE_VAL(rtwdev, map, u.usb_option); 92 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "mac_addr=%pM\n", map->u.mac_addr); 93 } 94 95 static void rtw8723xs_efuse_debug(struct rtw_dev *rtwdev, 96 struct rtw8723x_efuse *map) 97 { 98 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "mac_addr=%pM\n", map->s.mac_addr); 99 } 100 101 static void __rtw8723x_debug_txpwr_limit(struct rtw_dev *rtwdev, 102 struct rtw_txpwr_idx *table, 103 int tx_path_count) 104 { 105 if (!rtw_dbg_is_enabled(rtwdev, RTW_DBG_EFUSE)) 106 return; 107 108 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 109 "Power index table (2.4G):\n"); 110 /* CCK base */ 111 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "CCK base\n"); 112 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF G0 G1 G2 G3 G4 G5\n"); 113 for (int i = 0; i < tx_path_count; i++) 114 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 115 "[%c]: %3u %3u %3u %3u %3u %3u\n", 116 'A' + i, 117 table[i].pwr_idx_2g.cck_base[0], 118 table[i].pwr_idx_2g.cck_base[1], 119 table[i].pwr_idx_2g.cck_base[2], 120 table[i].pwr_idx_2g.cck_base[3], 121 table[i].pwr_idx_2g.cck_base[4], 122 table[i].pwr_idx_2g.cck_base[5]); 123 /* CCK diff */ 124 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "CCK diff\n"); 125 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF 1S 2S 3S 4S\n"); 126 for (int i = 0; i < tx_path_count; i++) 127 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 128 "[%c]: %2d %2d %2d %2d\n", 129 'A' + i, 0 /* no diff for 1S */, 130 table[i].pwr_idx_2g.ht_2s_diff.cck, 131 table[i].pwr_idx_2g.ht_3s_diff.cck, 132 table[i].pwr_idx_2g.ht_4s_diff.cck); 133 /* BW40-1S base */ 134 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "BW40-1S base\n"); 135 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF G0 G1 G2 G3 G4\n"); 136 for (int i = 0; i < tx_path_count; i++) 137 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 138 "[%c]: %3u %3u %3u %3u %3u\n", 139 'A' + i, 140 table[i].pwr_idx_2g.bw40_base[0], 141 table[i].pwr_idx_2g.bw40_base[1], 142 table[i].pwr_idx_2g.bw40_base[2], 143 table[i].pwr_idx_2g.bw40_base[3], 144 table[i].pwr_idx_2g.bw40_base[4]); 145 /* OFDM diff */ 146 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "OFDM diff\n"); 147 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF 1S 2S 3S 4S\n"); 148 for (int i = 0; i < tx_path_count; i++) 149 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 150 "[%c]: %2d %2d %2d %2d\n", 151 'A' + i, 152 table[i].pwr_idx_2g.ht_1s_diff.ofdm, 153 table[i].pwr_idx_2g.ht_2s_diff.ofdm, 154 table[i].pwr_idx_2g.ht_3s_diff.ofdm, 155 table[i].pwr_idx_2g.ht_4s_diff.ofdm); 156 /* BW20 diff */ 157 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "BW20 diff\n"); 158 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF 1S 2S 3S 4S\n"); 159 for (int i = 0; i < tx_path_count; i++) 160 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 161 "[%c]: %2d %2d %2d %2d\n", 162 'A' + i, 163 table[i].pwr_idx_2g.ht_1s_diff.bw20, 164 table[i].pwr_idx_2g.ht_2s_diff.bw20, 165 table[i].pwr_idx_2g.ht_3s_diff.bw20, 166 table[i].pwr_idx_2g.ht_4s_diff.bw20); 167 /* BW40 diff */ 168 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "BW40 diff\n"); 169 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "RF 1S 2S 3S 4S\n"); 170 for (int i = 0; i < tx_path_count; i++) 171 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 172 "[%c]: %2d %2d %2d %2d\n", 173 'A' + i, 0 /* no diff for 1S */, 174 table[i].pwr_idx_2g.ht_2s_diff.bw40, 175 table[i].pwr_idx_2g.ht_3s_diff.bw40, 176 table[i].pwr_idx_2g.ht_4s_diff.bw40); 177 } 178 179 static void efuse_debug_dump(struct rtw_dev *rtwdev, 180 struct rtw8723x_efuse *map) 181 { 182 if (!rtw_dbg_is_enabled(rtwdev, RTW_DBG_EFUSE)) 183 return; 184 185 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "EFUSE raw logical map:\n"); 186 print_hex_dump(KERN_DEBUG, "", DUMP_PREFIX_OFFSET, 16, 1, 187 (u8 *)map, sizeof(struct rtw8723x_efuse), false); 188 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "Parsed rtw8723x EFUSE data:\n"); 189 DBG_EFUSE_VAL(rtwdev, map, rtl_id); 190 DBG_EFUSE_VAL(rtwdev, map, afe); 191 rtw8723x_debug_txpwr_limit(rtwdev, map->txpwr_idx_table, 4); 192 DBG_EFUSE_VAL(rtwdev, map, channel_plan); 193 DBG_EFUSE_VAL(rtwdev, map, xtal_k); 194 DBG_EFUSE_VAL(rtwdev, map, thermal_meter); 195 DBG_EFUSE_VAL(rtwdev, map, iqk_lck); 196 DBG_EFUSE_VAL(rtwdev, map, pa_type); 197 DBG_EFUSE_2BYTE(rtwdev, map, lna_type_2g); 198 DBG_EFUSE_2BYTE(rtwdev, map, lna_type_5g); 199 DBG_EFUSE_VAL(rtwdev, map, rf_board_option); 200 DBG_EFUSE_VAL(rtwdev, map, rf_feature_option); 201 DBG_EFUSE_VAL(rtwdev, map, rf_bt_setting); 202 DBG_EFUSE_VAL(rtwdev, map, eeprom_version); 203 DBG_EFUSE_VAL(rtwdev, map, eeprom_customer_id); 204 DBG_EFUSE_VAL(rtwdev, map, tx_bb_swing_setting_2g); 205 DBG_EFUSE_VAL(rtwdev, map, tx_pwr_calibrate_rate); 206 DBG_EFUSE_VAL(rtwdev, map, rf_antenna_option); 207 DBG_EFUSE_VAL(rtwdev, map, rfe_option); 208 DBG_EFUSE_2BYTE(rtwdev, map, country_code); 209 210 switch (rtw_hci_type(rtwdev)) { 211 case RTW_HCI_TYPE_PCIE: 212 rtw8723xe_efuse_debug(rtwdev, map); 213 break; 214 case RTW_HCI_TYPE_USB: 215 rtw8723xu_efuse_debug(rtwdev, map); 216 break; 217 case RTW_HCI_TYPE_SDIO: 218 rtw8723xs_efuse_debug(rtwdev, map); 219 break; 220 default: 221 /* unsupported now */ 222 break; 223 } 224 } 225 226 static void rtw8723xe_efuse_parsing(struct rtw_efuse *efuse, 227 struct rtw8723x_efuse *map) 228 { 229 ether_addr_copy(efuse->addr, map->e.mac_addr); 230 } 231 232 static void rtw8723xu_efuse_parsing(struct rtw_efuse *efuse, 233 struct rtw8723x_efuse *map) 234 { 235 ether_addr_copy(efuse->addr, map->u.mac_addr); 236 } 237 238 static void rtw8723xs_efuse_parsing(struct rtw_efuse *efuse, 239 struct rtw8723x_efuse *map) 240 { 241 ether_addr_copy(efuse->addr, map->s.mac_addr); 242 } 243 244 static int __rtw8723x_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 245 { 246 struct rtw_efuse *efuse = &rtwdev->efuse; 247 struct rtw8723x_efuse *map; 248 int i; 249 250 map = (struct rtw8723x_efuse *)log_map; 251 efuse_debug_dump(rtwdev, map); 252 253 efuse->rfe_option = 0; 254 efuse->rf_board_option = map->rf_board_option; 255 efuse->crystal_cap = map->xtal_k; 256 efuse->pa_type_2g = map->pa_type; 257 efuse->lna_type_2g = map->lna_type_2g[0]; 258 efuse->channel_plan = map->channel_plan; 259 efuse->country_code[0] = map->country_code[0]; 260 efuse->country_code[1] = map->country_code[1]; 261 efuse->bt_setting = map->rf_bt_setting; 262 efuse->regd = map->rf_board_option & 0x7; 263 efuse->thermal_meter[0] = map->thermal_meter; 264 efuse->thermal_meter_k = map->thermal_meter; 265 efuse->afe = map->afe; 266 267 for (i = 0; i < 4; i++) 268 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 269 270 switch (rtw_hci_type(rtwdev)) { 271 case RTW_HCI_TYPE_PCIE: 272 rtw8723xe_efuse_parsing(efuse, map); 273 break; 274 case RTW_HCI_TYPE_USB: 275 rtw8723xu_efuse_parsing(efuse, map); 276 break; 277 case RTW_HCI_TYPE_SDIO: 278 rtw8723xs_efuse_parsing(efuse, map); 279 break; 280 default: 281 /* unsupported now */ 282 return -EOPNOTSUPP; 283 } 284 285 return 0; 286 } 287 288 #define BIT_CFENDFORM BIT(9) 289 #define BIT_WMAC_TCR_ERR0 BIT(12) 290 #define BIT_WMAC_TCR_ERR1 BIT(13) 291 #define BIT_TCR_CFG (BIT_CFENDFORM | BIT_WMAC_TCR_ERR0 | \ 292 BIT_WMAC_TCR_ERR1) 293 #define WLAN_RX_FILTER0 0xFFFF 294 #define WLAN_RX_FILTER1 0x400 295 #define WLAN_RX_FILTER2 0xFFFF 296 #define WLAN_RCR_CFG 0x700060CE 297 298 static int __rtw8723x_mac_init(struct rtw_dev *rtwdev) 299 { 300 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); 301 rtw_write32(rtwdev, REG_TCR, BIT_TCR_CFG); 302 303 rtw_write16(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 304 rtw_write16(rtwdev, REG_RXFLTMAP1, WLAN_RX_FILTER1); 305 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 306 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 307 308 rtw_write32(rtwdev, REG_INT_MIG, 0); 309 rtw_write32(rtwdev, REG_MCUTST_1, 0x0); 310 311 rtw_write8(rtwdev, REG_MISC_CTRL, BIT_DIS_SECOND_CCA); 312 rtw_write8(rtwdev, REG_2ND_CCA_CTRL, 0); 313 314 return 0; 315 } 316 317 static void __rtw8723x_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 318 { 319 u8 ldo_pwr; 320 321 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); 322 if (enable) { 323 ldo_pwr &= ~BIT_MASK_LDO25_VOLTAGE; 324 ldo_pwr |= (BIT_LDO25_VOLTAGE_V25 << 4) | BIT_LDO25_EN; 325 } else { 326 ldo_pwr &= ~BIT_LDO25_EN; 327 } 328 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); 329 } 330 331 static void 332 rtw8723x_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) 333 { 334 struct rtw_hal *hal = &rtwdev->hal; 335 const struct rtw_hw_reg *txagc; 336 u8 rate, pwr_index; 337 int j; 338 339 for (j = 0; j < rtw_rate_size[rs]; j++) { 340 rate = rtw_rate_section[rs][j]; 341 pwr_index = hal->tx_pwr_tbl[path][rate]; 342 343 if (rate >= ARRAY_SIZE(rtw8723x_txagc)) { 344 rtw_warn(rtwdev, "rate 0x%x isn't supported\n", rate); 345 continue; 346 } 347 txagc = &rtw8723x_txagc[rate]; 348 if (!txagc->addr) { 349 rtw_warn(rtwdev, "rate 0x%x isn't defined\n", rate); 350 continue; 351 } 352 353 rtw_write32_mask(rtwdev, txagc->addr, txagc->mask, pwr_index); 354 } 355 } 356 357 static void __rtw8723x_set_tx_power_index(struct rtw_dev *rtwdev) 358 { 359 struct rtw_hal *hal = &rtwdev->hal; 360 int rs, path; 361 362 for (path = 0; path < hal->rf_path_num; path++) { 363 for (rs = 0; rs <= RTW_RATE_SECTION_HT_1S; rs++) 364 rtw8723x_set_tx_power_index_by_rate(rtwdev, path, rs); 365 } 366 } 367 368 static void __rtw8723x_efuse_grant(struct rtw_dev *rtwdev, bool on) 369 { 370 if (on) { 371 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); 372 373 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_ELDR); 374 rtw_write16_set(rtwdev, REG_SYS_CLKR, BIT_LOADER_CLK_EN | BIT_ANA8M); 375 } else { 376 rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF); 377 } 378 } 379 380 static void __rtw8723x_false_alarm_statistics(struct rtw_dev *rtwdev) 381 { 382 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 383 u32 cck_fa_cnt; 384 u32 ofdm_fa_cnt; 385 u32 crc32_cnt; 386 u32 val32; 387 388 /* hold counter */ 389 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 1); 390 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 1); 391 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KEEP, 1); 392 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KEEP, 1); 393 394 cck_fa_cnt = rtw_read32_mask(rtwdev, REG_CCK_FA_LSB_11N, MASKBYTE0); 395 cck_fa_cnt += rtw_read32_mask(rtwdev, REG_CCK_FA_MSB_11N, MASKBYTE3) << 8; 396 397 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE1_11N); 398 ofdm_fa_cnt = u32_get_bits(val32, BIT_MASK_OFDM_FF_CNT); 399 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_SF_CNT); 400 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE2_11N); 401 dm_info->ofdm_cca_cnt = u32_get_bits(val32, BIT_MASK_OFDM_CCA_CNT); 402 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_PF_CNT); 403 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE3_11N); 404 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_RI_CNT); 405 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_CRC_CNT); 406 val32 = rtw_read32(rtwdev, REG_OFDM_FA_TYPE4_11N); 407 ofdm_fa_cnt += u32_get_bits(val32, BIT_MASK_OFDM_MNS_CNT); 408 409 dm_info->cck_fa_cnt = cck_fa_cnt; 410 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 411 dm_info->total_fa_cnt = cck_fa_cnt + ofdm_fa_cnt; 412 413 dm_info->cck_err_cnt = rtw_read32(rtwdev, REG_IGI_C_11N); 414 dm_info->cck_ok_cnt = rtw_read32(rtwdev, REG_IGI_D_11N); 415 crc32_cnt = rtw_read32(rtwdev, REG_OFDM_CRC32_CNT_11N); 416 dm_info->ofdm_err_cnt = u32_get_bits(crc32_cnt, BIT_MASK_OFDM_LCRC_ERR); 417 dm_info->ofdm_ok_cnt = u32_get_bits(crc32_cnt, BIT_MASK_OFDM_LCRC_OK); 418 crc32_cnt = rtw_read32(rtwdev, REG_HT_CRC32_CNT_11N); 419 dm_info->ht_err_cnt = u32_get_bits(crc32_cnt, BIT_MASK_HT_CRC_ERR); 420 dm_info->ht_ok_cnt = u32_get_bits(crc32_cnt, BIT_MASK_HT_CRC_OK); 421 dm_info->vht_err_cnt = 0; 422 dm_info->vht_ok_cnt = 0; 423 424 val32 = rtw_read32(rtwdev, REG_CCK_CCA_CNT_11N); 425 dm_info->cck_cca_cnt = (u32_get_bits(val32, BIT_MASK_CCK_FA_MSB) << 8) | 426 u32_get_bits(val32, BIT_MASK_CCK_FA_LSB); 427 dm_info->total_cca_cnt = dm_info->cck_cca_cnt + dm_info->ofdm_cca_cnt; 428 429 /* reset counter */ 430 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 1); 431 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTC_11N, BIT_MASK_OFDM_FA_RST, 0); 432 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 1); 433 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_RST1, 0); 434 rtw_write32_mask(rtwdev, REG_OFDM_FA_HOLDC_11N, BIT_MASK_OFDM_FA_KEEP, 0); 435 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, BIT_MASK_OFDM_FA_KEEP1, 0); 436 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 0); 437 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_CNT_KPEN, 2); 438 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 0); 439 rtw_write32_mask(rtwdev, REG_CCK_FA_RST_11N, BIT_MASK_CCK_FA_KPEN, 2); 440 rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 1); 441 rtw_write32_mask(rtwdev, REG_PAGE_F_RST_11N, BIT_MASK_F_RST_ALL, 0); 442 } 443 444 /* IQK (IQ calibration) */ 445 446 static 447 void __rtw8723x_iqk_backup_regs(struct rtw_dev *rtwdev, 448 struct rtw8723x_iqk_backup_regs *backup) 449 { 450 int i; 451 452 for (i = 0; i < RTW8723X_IQK_ADDA_REG_NUM; i++) 453 backup->adda[i] = rtw_read32(rtwdev, 454 rtw8723x_common.iqk_adda_regs[i]); 455 456 for (i = 0; i < RTW8723X_IQK_MAC8_REG_NUM; i++) 457 backup->mac8[i] = rtw_read8(rtwdev, 458 rtw8723x_common.iqk_mac8_regs[i]); 459 for (i = 0; i < RTW8723X_IQK_MAC32_REG_NUM; i++) 460 backup->mac32[i] = rtw_read32(rtwdev, 461 rtw8723x_common.iqk_mac32_regs[i]); 462 463 for (i = 0; i < RTW8723X_IQK_BB_REG_NUM; i++) 464 backup->bb[i] = rtw_read32(rtwdev, 465 rtw8723x_common.iqk_bb_regs[i]); 466 467 backup->igia = rtw_read32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0); 468 backup->igib = rtw_read32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0); 469 470 backup->bb_sel_btg = rtw_read32(rtwdev, REG_BB_SEL_BTG); 471 } 472 473 static 474 void __rtw8723x_iqk_restore_regs(struct rtw_dev *rtwdev, 475 const struct rtw8723x_iqk_backup_regs *backup) 476 { 477 int i; 478 479 for (i = 0; i < RTW8723X_IQK_ADDA_REG_NUM; i++) 480 rtw_write32(rtwdev, rtw8723x_common.iqk_adda_regs[i], 481 backup->adda[i]); 482 483 for (i = 0; i < RTW8723X_IQK_MAC8_REG_NUM; i++) 484 rtw_write8(rtwdev, rtw8723x_common.iqk_mac8_regs[i], 485 backup->mac8[i]); 486 for (i = 0; i < RTW8723X_IQK_MAC32_REG_NUM; i++) 487 rtw_write32(rtwdev, rtw8723x_common.iqk_mac32_regs[i], 488 backup->mac32[i]); 489 490 for (i = 0; i < RTW8723X_IQK_BB_REG_NUM; i++) 491 rtw_write32(rtwdev, rtw8723x_common.iqk_bb_regs[i], 492 backup->bb[i]); 493 494 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); 495 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, backup->igia); 496 497 rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, 0x50); 498 rtw_write32_mask(rtwdev, REG_OFDM0_XBAGC1, MASKBYTE0, backup->igib); 499 500 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x01008c00); 501 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x01008c00); 502 } 503 504 static 505 bool __rtw8723x_iqk_similarity_cmp(struct rtw_dev *rtwdev, 506 s32 result[][IQK_NR], 507 u8 c1, u8 c2) 508 { 509 u32 i, j, diff; 510 u32 bitmap = 0; 511 u8 candidate[PATH_NR] = {IQK_ROUND_INVALID, IQK_ROUND_INVALID}; 512 bool ret = true; 513 514 s32 tmp1, tmp2; 515 516 for (i = 0; i < IQK_NR; i++) { 517 tmp1 = iqkxy_to_s32(result[c1][i]); 518 tmp2 = iqkxy_to_s32(result[c2][i]); 519 520 diff = abs(tmp1 - tmp2); 521 522 if (diff <= MAX_TOLERANCE) 523 continue; 524 525 if ((i == IQK_S1_RX_X || i == IQK_S0_RX_X) && !bitmap) { 526 if (result[c1][i] + result[c1][i + 1] == 0) 527 candidate[i / IQK_SX_NR] = c2; 528 else if (result[c2][i] + result[c2][i + 1] == 0) 529 candidate[i / IQK_SX_NR] = c1; 530 else 531 bitmap |= BIT(i); 532 } else { 533 bitmap |= BIT(i); 534 } 535 } 536 537 if (bitmap != 0) 538 goto check_sim; 539 540 for (i = 0; i < PATH_NR; i++) { 541 if (candidate[i] == IQK_ROUND_INVALID) 542 continue; 543 544 for (j = i * IQK_SX_NR; j < i * IQK_SX_NR + 2; j++) 545 result[IQK_ROUND_HYBRID][j] = result[candidate[i]][j]; 546 ret = false; 547 } 548 549 return ret; 550 551 check_sim: 552 for (i = 0; i < IQK_NR; i++) { 553 j = i & ~1; /* 2 bits are a pair for IQ[X, Y] */ 554 if (bitmap & GENMASK(j + 1, j)) 555 continue; 556 557 result[IQK_ROUND_HYBRID][i] = result[c1][i]; 558 } 559 560 return false; 561 } 562 563 static u8 __rtw8723x_pwrtrack_get_limit_ofdm(struct rtw_dev *rtwdev) 564 { 565 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 566 u8 tx_rate = dm_info->tx_rate; 567 u8 limit_ofdm = 30; 568 569 switch (tx_rate) { 570 case DESC_RATE1M...DESC_RATE5_5M: 571 case DESC_RATE11M: 572 break; 573 case DESC_RATE6M...DESC_RATE48M: 574 limit_ofdm = 36; 575 break; 576 case DESC_RATE54M: 577 limit_ofdm = 34; 578 break; 579 case DESC_RATEMCS0...DESC_RATEMCS2: 580 limit_ofdm = 38; 581 break; 582 case DESC_RATEMCS3...DESC_RATEMCS4: 583 limit_ofdm = 36; 584 break; 585 case DESC_RATEMCS5...DESC_RATEMCS7: 586 limit_ofdm = 34; 587 break; 588 default: 589 rtw_warn(rtwdev, "pwrtrack unhandled tx_rate 0x%x\n", tx_rate); 590 break; 591 } 592 593 return limit_ofdm; 594 } 595 596 static 597 void __rtw8723x_pwrtrack_set_xtal(struct rtw_dev *rtwdev, u8 therm_path, 598 u8 delta) 599 { 600 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 601 const struct rtw_pwr_track_tbl *tbl = rtwdev->chip->pwr_track_tbl; 602 const s8 *pwrtrk_xtal; 603 s8 xtal_cap; 604 605 if (dm_info->thermal_avg[therm_path] > 606 rtwdev->efuse.thermal_meter[therm_path]) 607 pwrtrk_xtal = tbl->pwrtrk_xtal_p; 608 else 609 pwrtrk_xtal = tbl->pwrtrk_xtal_n; 610 611 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F; 612 xtal_cap = clamp_t(s8, xtal_cap + pwrtrk_xtal[delta], 0, 0x3F); 613 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, 614 xtal_cap | (xtal_cap << 6)); 615 } 616 617 static 618 void __rtw8723x_fill_txdesc_checksum(struct rtw_dev *rtwdev, 619 struct rtw_tx_pkt_info *pkt_info, 620 u8 *txdesc) 621 { 622 size_t words = 32 / 2; /* calculate the first 32 bytes (16 words) */ 623 __le16 chksum = 0; 624 __le16 *data = (__le16 *)(txdesc); 625 struct rtw_tx_desc *tx_desc = (struct rtw_tx_desc *)txdesc; 626 627 le32p_replace_bits(&tx_desc->w7, 0, RTW_TX_DESC_W7_TXDESC_CHECKSUM); 628 629 while (words--) 630 chksum ^= *data++; 631 632 chksum = ~chksum; 633 634 le32p_replace_bits(&tx_desc->w7, __le16_to_cpu(chksum), 635 RTW_TX_DESC_W7_TXDESC_CHECKSUM); 636 } 637 638 static void __rtw8723x_coex_cfg_init(struct rtw_dev *rtwdev) 639 { 640 /* enable TBTT nterrupt */ 641 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 642 643 /* BT report packet sample rate */ 644 /* 0x790[5:0]=0x5 */ 645 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); 646 647 /* enable BT counter statistics */ 648 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); 649 650 /* enable PTA (3-wire function form BT side) */ 651 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 652 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); 653 654 /* enable PTA (tx/rx signal form WiFi side) */ 655 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 656 } 657 658 const struct rtw8723x_common rtw8723x_common = { 659 .iqk_adda_regs = { 660 0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, 0xe7c, 0xe80, 0xe84, 661 0xe88, 0xe8c, 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, 0xeec 662 }, 663 .iqk_mac8_regs = {0x522, 0x550, 0x551}, 664 .iqk_mac32_regs = {0x40}, 665 .iqk_bb_regs = { 666 0xc04, 0xc08, 0x874, 0xb68, 0xb6c, 0x870, 0x860, 0x864, 0xa04 667 }, 668 669 .ltecoex_addr = { 670 .ctrl = REG_LTECOEX_CTRL, 671 .wdata = REG_LTECOEX_WRITE_DATA, 672 .rdata = REG_LTECOEX_READ_DATA, 673 }, 674 .rf_sipi_addr = { 675 [RF_PATH_A] = { .hssi_1 = 0x820, .lssi_read = 0x8a0, 676 .hssi_2 = 0x824, .lssi_read_pi = 0x8b8}, 677 [RF_PATH_B] = { .hssi_1 = 0x828, .lssi_read = 0x8a4, 678 .hssi_2 = 0x82c, .lssi_read_pi = 0x8bc}, 679 }, 680 .dig = { 681 [0] = { .addr = 0xc50, .mask = 0x7f }, 682 [1] = { .addr = 0xc50, .mask = 0x7f }, 683 }, 684 .dig_cck = { 685 [0] = { .addr = 0xa0c, .mask = 0x3f00 }, 686 }, 687 .prioq_addrs = { 688 .prio[RTW_DMA_MAPPING_EXTRA] = { 689 .rsvd = REG_RQPN_NPQ + 2, .avail = REG_RQPN_NPQ + 3, 690 }, 691 .prio[RTW_DMA_MAPPING_LOW] = { 692 .rsvd = REG_RQPN + 1, .avail = REG_FIFOPAGE_CTRL_2 + 1, 693 }, 694 .prio[RTW_DMA_MAPPING_NORMAL] = { 695 .rsvd = REG_RQPN_NPQ, .avail = REG_RQPN_NPQ + 1, 696 }, 697 .prio[RTW_DMA_MAPPING_HIGH] = { 698 .rsvd = REG_RQPN, .avail = REG_FIFOPAGE_CTRL_2, 699 }, 700 .wsize = false, 701 }, 702 703 .lck = __rtw8723x_lck, 704 .read_efuse = __rtw8723x_read_efuse, 705 .mac_init = __rtw8723x_mac_init, 706 .cfg_ldo25 = __rtw8723x_cfg_ldo25, 707 .set_tx_power_index = __rtw8723x_set_tx_power_index, 708 .efuse_grant = __rtw8723x_efuse_grant, 709 .false_alarm_statistics = __rtw8723x_false_alarm_statistics, 710 .iqk_backup_regs = __rtw8723x_iqk_backup_regs, 711 .iqk_restore_regs = __rtw8723x_iqk_restore_regs, 712 .iqk_similarity_cmp = __rtw8723x_iqk_similarity_cmp, 713 .pwrtrack_get_limit_ofdm = __rtw8723x_pwrtrack_get_limit_ofdm, 714 .pwrtrack_set_xtal = __rtw8723x_pwrtrack_set_xtal, 715 .coex_cfg_init = __rtw8723x_coex_cfg_init, 716 .fill_txdesc_checksum = __rtw8723x_fill_txdesc_checksum, 717 .debug_txpwr_limit = __rtw8723x_debug_txpwr_limit, 718 }; 719 EXPORT_SYMBOL(rtw8723x_common); 720 721 MODULE_AUTHOR("Realtek Corporation"); 722 MODULE_AUTHOR("Fiona Klute <fiona.klute@gmx.de>"); 723 MODULE_DESCRIPTION("Common functions for Realtek 802.11n wireless 8723x drivers"); 724 MODULE_LICENSE("Dual BSD/GPL"); 725