1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright Fiona Klute <fiona.klute@gmx.de> */ 3 4 #include <linux/of_net.h> 5 #include "main.h" 6 #include "coex.h" 7 #include "debug.h" 8 #include "mac.h" 9 #include "phy.h" 10 #include "reg.h" 11 #include "rx.h" 12 #include "rtw8703b.h" 13 #include "rtw8703b_tables.h" 14 #include "rtw8723x.h" 15 16 #define BIT_MASK_TXQ_INIT (BIT(7)) 17 #define WLAN_RL_VAL 0x3030 18 /* disable BAR */ 19 #define WLAN_BAR_VAL 0x0201ffff 20 #define WLAN_PIFS_VAL 0 21 #define WLAN_RX_PKT_LIMIT 0x18 22 #define WLAN_SLOT_TIME 0x09 23 #define WLAN_SPEC_SIFS 0x100a 24 #define WLAN_MAX_AGG_NR 0x1f 25 #define WLAN_AMPDU_MAX_TIME 0x70 26 27 /* unit is 32us */ 28 #define TBTT_PROHIBIT_SETUP_TIME 0x04 29 #define TBTT_PROHIBIT_HOLD_TIME 0x80 30 #define TBTT_PROHIBIT_HOLD_TIME_STOP_BCN 0x64 31 32 /* raw pkt_stat->drv_info_sz is in unit of 8-bytes */ 33 #define RX_DRV_INFO_SZ_UNIT_8703B 8 34 35 #define TRANS_SEQ_END \ 36 0xFFFF, \ 37 RTW_PWR_CUT_ALL_MSK, \ 38 RTW_PWR_INTF_ALL_MSK, \ 39 0, \ 40 RTW_PWR_CMD_END, 0, 0 41 42 /* rssi in percentage % (dbm = % - 100) */ 43 /* These are used to select simple signal quality levels, might need 44 * tweaking. Same for rf_para tables below. 45 */ 46 static const u8 wl_rssi_step_8703b[] = {60, 50, 44, 30}; 47 static const u8 bt_rssi_step_8703b[] = {30, 30, 30, 30}; 48 static const struct coex_5g_afh_map afh_5g_8703b[] = { {0, 0, 0} }; 49 50 /* Actually decreasing wifi TX power/RX gain isn't implemented in 51 * rtw8703b, but hopefully adjusting the BT side helps. 52 */ 53 static const struct coex_rf_para rf_para_tx_8703b[] = { 54 {0, 0, false, 7}, /* for normal */ 55 {0, 10, false, 7}, /* for WL-CPT */ 56 {1, 0, true, 4}, 57 {1, 2, true, 4}, 58 {1, 10, true, 4}, 59 {1, 15, true, 4} 60 }; 61 62 static const struct coex_rf_para rf_para_rx_8703b[] = { 63 {0, 0, false, 7}, /* for normal */ 64 {0, 10, false, 7}, /* for WL-CPT */ 65 {1, 0, true, 5}, 66 {1, 2, true, 5}, 67 {1, 10, true, 5}, 68 {1, 15, true, 5} 69 }; 70 71 static const u32 rtw8703b_ofdm_swing_table[] = { 72 0x0b40002d, /* 0, -15.0dB */ 73 0x0c000030, /* 1, -14.5dB */ 74 0x0cc00033, /* 2, -14.0dB */ 75 0x0d800036, /* 3, -13.5dB */ 76 0x0e400039, /* 4, -13.0dB */ 77 0x0f00003c, /* 5, -12.5dB */ 78 0x10000040, /* 6, -12.0dB */ 79 0x11000044, /* 7, -11.5dB */ 80 0x12000048, /* 8, -11.0dB */ 81 0x1300004c, /* 9, -10.5dB */ 82 0x14400051, /* 10, -10.0dB */ 83 0x15800056, /* 11, -9.5dB */ 84 0x16c0005b, /* 12, -9.0dB */ 85 0x18000060, /* 13, -8.5dB */ 86 0x19800066, /* 14, -8.0dB */ 87 0x1b00006c, /* 15, -7.5dB */ 88 0x1c800072, /* 16, -7.0dB */ 89 0x1e400079, /* 17, -6.5dB */ 90 0x20000080, /* 18, -6.0dB */ 91 0x22000088, /* 19, -5.5dB */ 92 0x24000090, /* 20, -5.0dB */ 93 0x26000098, /* 21, -4.5dB */ 94 0x288000a2, /* 22, -4.0dB */ 95 0x2ac000ab, /* 23, -3.5dB */ 96 0x2d4000b5, /* 24, -3.0dB */ 97 0x300000c0, /* 25, -2.5dB */ 98 0x32c000cb, /* 26, -2.0dB */ 99 0x35c000d7, /* 27, -1.5dB */ 100 0x390000e4, /* 28, -1.0dB */ 101 0x3c8000f2, /* 29, -0.5dB */ 102 0x40000100, /* 30, +0dB */ 103 0x43c0010f, /* 31, +0.5dB */ 104 0x47c0011f, /* 32, +1.0dB */ 105 0x4c000130, /* 33, +1.5dB */ 106 0x50800142, /* 34, +2.0dB */ 107 0x55400155, /* 35, +2.5dB */ 108 0x5a400169, /* 36, +3.0dB */ 109 0x5fc0017f, /* 37, +3.5dB */ 110 0x65400195, /* 38, +4.0dB */ 111 0x6b8001ae, /* 39, +4.5dB */ 112 0x71c001c7, /* 40, +5.0dB */ 113 0x788001e2, /* 41, +5.5dB */ 114 0x7f8001fe /* 42, +6.0dB */ 115 }; 116 117 static const u32 rtw8703b_cck_pwr_regs[] = { 118 0x0a22, 0x0a23, 0x0a24, 0x0a25, 0x0a26, 0x0a27, 0x0a28, 0x0a29, 119 0x0a9a, 0x0a9b, 0x0a9c, 0x0a9d, 0x0aa0, 0x0aa1, 0x0aa2, 0x0aa3, 120 }; 121 122 static const u8 rtw8703b_cck_swing_table[][16] = { 123 {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 124 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ 125 {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 126 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ 127 {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 128 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ 129 {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 130 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ 131 {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 132 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ 133 {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 134 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ 135 {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 136 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ 137 {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 138 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ 139 {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 140 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ 141 {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 142 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ 143 {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 144 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ 145 {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 146 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ 147 {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 148 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ 149 {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 150 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ 151 {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 152 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ 153 {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 154 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ 155 {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 156 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ 157 {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 158 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ 159 {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 160 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ 161 {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 162 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ 163 {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 164 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ 165 }; 166 167 #define RTW_OFDM_SWING_TABLE_SIZE ARRAY_SIZE(rtw8703b_ofdm_swing_table) 168 #define RTW_CCK_SWING_TABLE_SIZE ARRAY_SIZE(rtw8703b_cck_swing_table) 169 170 static const struct rtw_pwr_seq_cmd trans_pre_enable_8703b[] = { 171 /* set up external crystal (XTAL) */ 172 {REG_PAD_CTRL1 + 2, 173 RTW_PWR_CUT_ALL_MSK, 174 RTW_PWR_INTF_ALL_MSK, 175 RTW_PWR_ADDR_MAC, 176 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 177 /* set CLK_REQ to high active */ 178 {0x0069, 179 RTW_PWR_CUT_ALL_MSK, 180 RTW_PWR_INTF_ALL_MSK, 181 RTW_PWR_ADDR_MAC, 182 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 183 /* unlock ISO/CLK/power control register */ 184 {REG_RSV_CTRL, 185 RTW_PWR_CUT_ALL_MSK, 186 RTW_PWR_INTF_ALL_MSK, 187 RTW_PWR_ADDR_MAC, 188 RTW_PWR_CMD_WRITE, 0xff, 0}, 189 {TRANS_SEQ_END}, 190 }; 191 192 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8703b[] = { 193 {0x0005, 194 RTW_PWR_CUT_ALL_MSK, 195 RTW_PWR_INTF_ALL_MSK, 196 RTW_PWR_ADDR_MAC, 197 RTW_PWR_CMD_WRITE, BIT(7), 0}, 198 {TRANS_SEQ_END}, 199 }; 200 201 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8703b[] = { 202 {0x0023, 203 RTW_PWR_CUT_ALL_MSK, 204 RTW_PWR_INTF_SDIO_MSK, 205 RTW_PWR_ADDR_MAC, 206 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 207 {0x0007, 208 RTW_PWR_CUT_ALL_MSK, 209 RTW_PWR_INTF_SDIO_MSK | RTW_PWR_INTF_USB_MSK, 210 RTW_PWR_ADDR_MAC, 211 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 212 {0x0006, 213 RTW_PWR_CUT_ALL_MSK, 214 RTW_PWR_INTF_ALL_MSK, 215 RTW_PWR_ADDR_MAC, 216 RTW_PWR_CMD_WRITE, BIT(0), 0}, 217 {0x0005, 218 RTW_PWR_CUT_ALL_MSK, 219 RTW_PWR_INTF_ALL_MSK, 220 RTW_PWR_ADDR_MAC, 221 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 222 {TRANS_SEQ_END}, 223 }; 224 225 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8703b[] = { 226 {0x0020, 227 RTW_PWR_CUT_ALL_MSK, 228 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 229 RTW_PWR_ADDR_MAC, 230 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 231 {0x0067, 232 RTW_PWR_CUT_ALL_MSK, 233 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 234 RTW_PWR_ADDR_MAC, 235 RTW_PWR_CMD_WRITE, BIT(4), 0}, 236 {0x0001, 237 RTW_PWR_CUT_ALL_MSK, 238 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 239 RTW_PWR_ADDR_MAC, 240 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 241 {0x0000, 242 RTW_PWR_CUT_ALL_MSK, 243 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 244 RTW_PWR_ADDR_MAC, 245 RTW_PWR_CMD_WRITE, BIT(5), 0}, 246 {0x0005, 247 RTW_PWR_CUT_ALL_MSK, 248 RTW_PWR_INTF_ALL_MSK, 249 RTW_PWR_ADDR_MAC, 250 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 251 {0x0075, 252 RTW_PWR_CUT_ALL_MSK, 253 RTW_PWR_INTF_PCI_MSK, 254 RTW_PWR_ADDR_MAC, 255 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 256 {0x0004, 257 RTW_PWR_CUT_ALL_MSK, 258 RTW_PWR_INTF_PCI_MSK, 259 RTW_PWR_ADDR_MAC, 260 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 261 {0x0004, 262 RTW_PWR_CUT_ALL_MSK, 263 RTW_PWR_INTF_PCI_MSK, 264 RTW_PWR_ADDR_MAC, 265 RTW_PWR_CMD_WRITE, BIT(3), 0}, 266 /* wait for power ready */ 267 {0x0006, 268 RTW_PWR_CUT_ALL_MSK, 269 RTW_PWR_INTF_ALL_MSK, 270 RTW_PWR_ADDR_MAC, 271 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 272 {0x0075, 273 RTW_PWR_CUT_ALL_MSK, 274 RTW_PWR_INTF_PCI_MSK, 275 RTW_PWR_ADDR_MAC, 276 RTW_PWR_CMD_WRITE, BIT(0), 0}, 277 {0x0006, 278 RTW_PWR_CUT_ALL_MSK, 279 RTW_PWR_INTF_ALL_MSK, 280 RTW_PWR_ADDR_MAC, 281 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 282 {0x0005, 283 RTW_PWR_CUT_ALL_MSK, 284 RTW_PWR_INTF_ALL_MSK, 285 RTW_PWR_ADDR_MAC, 286 RTW_PWR_CMD_WRITE, BIT(7), 0}, 287 {0x0005, 288 RTW_PWR_CUT_ALL_MSK, 289 RTW_PWR_INTF_ALL_MSK, 290 RTW_PWR_ADDR_MAC, 291 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 292 {0x0005, 293 RTW_PWR_CUT_ALL_MSK, 294 RTW_PWR_INTF_ALL_MSK, 295 RTW_PWR_ADDR_MAC, 296 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 297 {0x0005, 298 RTW_PWR_CUT_ALL_MSK, 299 RTW_PWR_INTF_ALL_MSK, 300 RTW_PWR_ADDR_MAC, 301 RTW_PWR_CMD_POLLING, BIT(0), 0}, 302 {0x0010, 303 RTW_PWR_CUT_ALL_MSK, 304 RTW_PWR_INTF_ALL_MSK, 305 RTW_PWR_ADDR_MAC, 306 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 307 {0x0049, 308 RTW_PWR_CUT_ALL_MSK, 309 RTW_PWR_INTF_ALL_MSK, 310 RTW_PWR_ADDR_MAC, 311 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 312 {0x0063, 313 RTW_PWR_CUT_ALL_MSK, 314 RTW_PWR_INTF_ALL_MSK, 315 RTW_PWR_ADDR_MAC, 316 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 317 {0x0062, 318 RTW_PWR_CUT_ALL_MSK, 319 RTW_PWR_INTF_ALL_MSK, 320 RTW_PWR_ADDR_MAC, 321 RTW_PWR_CMD_WRITE, BIT(1), 0}, 322 {0x0058, 323 RTW_PWR_CUT_ALL_MSK, 324 RTW_PWR_INTF_ALL_MSK, 325 RTW_PWR_ADDR_MAC, 326 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 327 {0x005A, 328 RTW_PWR_CUT_ALL_MSK, 329 RTW_PWR_INTF_ALL_MSK, 330 RTW_PWR_ADDR_MAC, 331 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 332 {0x0068, 333 RTW_PWR_CUT_TEST_MSK, 334 RTW_PWR_INTF_ALL_MSK, 335 RTW_PWR_ADDR_MAC, 336 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 337 {0x0069, 338 RTW_PWR_CUT_ALL_MSK, 339 RTW_PWR_INTF_ALL_MSK, 340 RTW_PWR_ADDR_MAC, 341 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 342 {TRANS_SEQ_END}, 343 }; 344 345 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8703b[] = { 346 {0x001f, 347 RTW_PWR_CUT_ALL_MSK, 348 RTW_PWR_INTF_ALL_MSK, 349 RTW_PWR_ADDR_MAC, 350 RTW_PWR_CMD_WRITE, 0xff, 0}, 351 {0x0049, 352 RTW_PWR_CUT_ALL_MSK, 353 RTW_PWR_INTF_ALL_MSK, 354 RTW_PWR_ADDR_MAC, 355 RTW_PWR_CMD_WRITE, BIT(1), 0}, 356 {0x0006, 357 RTW_PWR_CUT_ALL_MSK, 358 RTW_PWR_INTF_ALL_MSK, 359 RTW_PWR_ADDR_MAC, 360 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 361 {0x0005, 362 RTW_PWR_CUT_ALL_MSK, 363 RTW_PWR_INTF_ALL_MSK, 364 RTW_PWR_ADDR_MAC, 365 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 366 {0x0005, 367 RTW_PWR_CUT_ALL_MSK, 368 RTW_PWR_INTF_ALL_MSK, 369 RTW_PWR_ADDR_MAC, 370 RTW_PWR_CMD_POLLING, BIT(1), 0}, 371 {0x0010, 372 RTW_PWR_CUT_ALL_MSK, 373 RTW_PWR_INTF_ALL_MSK, 374 RTW_PWR_ADDR_MAC, 375 RTW_PWR_CMD_WRITE, BIT(6), 0}, 376 {0x0000, 377 RTW_PWR_CUT_ALL_MSK, 378 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 379 RTW_PWR_ADDR_MAC, 380 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 381 {0x0020, 382 RTW_PWR_CUT_ALL_MSK, 383 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 384 RTW_PWR_ADDR_MAC, 385 RTW_PWR_CMD_WRITE, BIT(0), 0}, 386 {TRANS_SEQ_END}, 387 }; 388 389 static const struct rtw_pwr_seq_cmd trans_act_to_reset_mcu_8703b[] = { 390 {REG_SYS_FUNC_EN + 1, 391 RTW_PWR_CUT_ALL_MSK, 392 RTW_PWR_INTF_SDIO_MSK, 393 RTW_PWR_ADDR_MAC, 394 RTW_PWR_CMD_WRITE, BIT_FEN_CPUEN, 0}, 395 /* reset MCU ready */ 396 {REG_MCUFW_CTRL, 397 RTW_PWR_CUT_ALL_MSK, 398 RTW_PWR_INTF_SDIO_MSK, 399 RTW_PWR_ADDR_MAC, 400 RTW_PWR_CMD_WRITE, 0xff, 0}, 401 /* reset MCU IO wrapper */ 402 {REG_RSV_CTRL + 1, 403 RTW_PWR_CUT_ALL_MSK, 404 RTW_PWR_INTF_SDIO_MSK, 405 RTW_PWR_ADDR_MAC, 406 RTW_PWR_CMD_WRITE, BIT(0), 0}, 407 {REG_RSV_CTRL + 1, 408 RTW_PWR_CUT_ALL_MSK, 409 RTW_PWR_INTF_SDIO_MSK, 410 RTW_PWR_ADDR_MAC, 411 RTW_PWR_CMD_WRITE, BIT(0), 1}, 412 {TRANS_SEQ_END}, 413 }; 414 415 static const struct rtw_pwr_seq_cmd trans_act_to_lps_8703b[] = { 416 {0x0301, 417 RTW_PWR_CUT_ALL_MSK, 418 RTW_PWR_INTF_ALL_MSK, 419 RTW_PWR_ADDR_MAC, 420 RTW_PWR_CMD_WRITE, 0xff, 0xff}, 421 {0x0522, 422 RTW_PWR_CUT_ALL_MSK, 423 RTW_PWR_INTF_ALL_MSK, 424 RTW_PWR_ADDR_MAC, 425 RTW_PWR_CMD_WRITE, 0xff, 0xff}, 426 {0x05f8, 427 RTW_PWR_CUT_ALL_MSK, 428 RTW_PWR_INTF_ALL_MSK, 429 RTW_PWR_ADDR_MAC, 430 RTW_PWR_CMD_POLLING, 0xff, 0}, 431 {0x05f9, 432 RTW_PWR_CUT_ALL_MSK, 433 RTW_PWR_INTF_ALL_MSK, 434 RTW_PWR_ADDR_MAC, 435 RTW_PWR_CMD_POLLING, 0xff, 0}, 436 {0x05fa, 437 RTW_PWR_CUT_ALL_MSK, 438 RTW_PWR_INTF_ALL_MSK, 439 RTW_PWR_ADDR_MAC, 440 RTW_PWR_CMD_POLLING, 0xff, 0}, 441 {0x05fb, 442 RTW_PWR_CUT_ALL_MSK, 443 RTW_PWR_INTF_ALL_MSK, 444 RTW_PWR_ADDR_MAC, 445 RTW_PWR_CMD_POLLING, 0xff, 0}, 446 {0x0002, 447 RTW_PWR_CUT_ALL_MSK, 448 RTW_PWR_INTF_ALL_MSK, 449 RTW_PWR_ADDR_MAC, 450 RTW_PWR_CMD_WRITE, BIT(0), 0}, 451 {0x0002, 452 RTW_PWR_CUT_ALL_MSK, 453 RTW_PWR_INTF_ALL_MSK, 454 RTW_PWR_ADDR_MAC, 455 RTW_PWR_CMD_DELAY, 0, RTW_PWR_DELAY_US}, 456 {0x0002, 457 RTW_PWR_CUT_ALL_MSK, 458 RTW_PWR_INTF_ALL_MSK, 459 RTW_PWR_ADDR_MAC, 460 RTW_PWR_CMD_WRITE, BIT(1), 0}, 461 {0x0100, 462 RTW_PWR_CUT_ALL_MSK, 463 RTW_PWR_INTF_ALL_MSK, 464 RTW_PWR_ADDR_MAC, 465 RTW_PWR_CMD_WRITE, 0xff, 0x03}, 466 {0x0101, 467 RTW_PWR_CUT_ALL_MSK, 468 RTW_PWR_INTF_ALL_MSK, 469 RTW_PWR_ADDR_MAC, 470 RTW_PWR_CMD_WRITE, BIT(1), 0}, 471 {0x0093, 472 RTW_PWR_CUT_ALL_MSK, 473 RTW_PWR_INTF_SDIO_MSK, 474 RTW_PWR_ADDR_MAC, 475 RTW_PWR_CMD_WRITE, 0xff, 0}, 476 {0x0553, 477 RTW_PWR_CUT_ALL_MSK, 478 RTW_PWR_INTF_ALL_MSK, 479 RTW_PWR_ADDR_MAC, 480 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 481 {TRANS_SEQ_END}, 482 }; 483 484 static const struct rtw_pwr_seq_cmd *card_enable_flow_8703b[] = { 485 trans_pre_enable_8703b, 486 trans_carddis_to_cardemu_8703b, 487 trans_cardemu_to_act_8703b, 488 NULL 489 }; 490 491 static const struct rtw_pwr_seq_cmd *card_disable_flow_8703b[] = { 492 trans_act_to_lps_8703b, 493 trans_act_to_reset_mcu_8703b, 494 trans_act_to_cardemu_8703b, 495 trans_cardemu_to_carddis_8703b, 496 NULL 497 }; 498 499 static const struct rtw_rfe_def rtw8703b_rfe_defs[] = { 500 [0] = { .phy_pg_tbl = &rtw8703b_bb_pg_tbl, 501 .txpwr_lmt_tbl = &rtw8703b_txpwr_lmt_tbl,}, 502 }; 503 504 static const struct rtw_page_table page_table_8703b[] = { 505 {12, 2, 2, 0, 1}, 506 {12, 2, 2, 0, 1}, 507 {12, 2, 2, 0, 1}, 508 {12, 2, 2, 0, 1}, 509 {12, 2, 2, 0, 1}, 510 }; 511 512 static const struct rtw_rqpn rqpn_table_8703b[] = { 513 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 514 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 515 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 516 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 517 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 518 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 519 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 520 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 521 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 522 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 523 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 524 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 525 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 526 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 527 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 528 }; 529 530 /* Default power index table for RTL8703B, used if EFUSE does not 531 * contain valid data. Replaces EFUSE data from offset 0x10 (start of 532 * txpwr_idx_table). 533 */ 534 static const u8 rtw8703b_txpwr_idx_table[] = { 535 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 536 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02 537 }; 538 539 static void try_mac_from_devicetree(struct rtw_dev *rtwdev) 540 { 541 #if defined(CONFIG_OF) 542 struct device_node *node = rtwdev->dev->of_node; 543 struct rtw_efuse *efuse = &rtwdev->efuse; 544 int ret; 545 546 if (node) { 547 ret = of_get_mac_address(node, efuse->addr); 548 if (ret == 0) { 549 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 550 "got wifi mac address from DT: %pM\n", 551 efuse->addr); 552 } 553 } 554 #endif 555 } 556 557 #define DBG_EFUSE_FIX(rtwdev, name) \ 558 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "Fixed invalid EFUSE value: " \ 559 # name "=0x%x\n", rtwdev->efuse.name) 560 561 static int rtw8703b_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 562 { 563 struct rtw_efuse *efuse = &rtwdev->efuse; 564 u8 *pwr = (u8 *)efuse->txpwr_idx_table; 565 bool valid = false; 566 int ret; 567 568 ret = rtw8723x_read_efuse(rtwdev, log_map); 569 if (ret != 0) 570 return ret; 571 572 if (!is_valid_ether_addr(efuse->addr)) 573 try_mac_from_devicetree(rtwdev); 574 575 /* If TX power index table in EFUSE is invalid, fall back to 576 * built-in table. 577 */ 578 for (int i = 0; i < ARRAY_SIZE(rtw8703b_txpwr_idx_table); i++) 579 if (pwr[i] != 0xff) { 580 valid = true; 581 break; 582 } 583 if (!valid) { 584 for (int i = 0; i < ARRAY_SIZE(rtw8703b_txpwr_idx_table); i++) 585 pwr[i] = rtw8703b_txpwr_idx_table[i]; 586 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 587 "Replaced invalid EFUSE TX power index table."); 588 rtw8723x_debug_txpwr_limit(rtwdev, 589 efuse->txpwr_idx_table, 2); 590 } 591 592 /* Override invalid antenna settings. */ 593 if (efuse->bt_setting == 0xff) { 594 /* shared antenna */ 595 efuse->bt_setting |= BIT(0); 596 /* RF path A */ 597 efuse->bt_setting &= ~BIT(6); 598 DBG_EFUSE_FIX(rtwdev, bt_setting); 599 } 600 601 /* Override invalid board options: The coex code incorrectly 602 * assumes that if bits 6 & 7 are set the board doesn't 603 * support coex. Regd is also derived from rf_board_option and 604 * should be 0 if there's no valid data. 605 */ 606 if (efuse->rf_board_option == 0xff) { 607 efuse->regd = 0; 608 efuse->rf_board_option &= GENMASK(5, 0); 609 DBG_EFUSE_FIX(rtwdev, rf_board_option); 610 } 611 612 /* Override invalid crystal cap setting, default comes from 613 * vendor driver. Chip specific. 614 */ 615 if (efuse->crystal_cap == 0xff) { 616 efuse->crystal_cap = 0x20; 617 DBG_EFUSE_FIX(rtwdev, crystal_cap); 618 } 619 620 return 0; 621 } 622 623 static void rtw8703b_pwrtrack_init(struct rtw_dev *rtwdev) 624 { 625 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 626 u8 path; 627 628 /* TODO: The vendor driver selects these using tables in 629 * halrf_powertracking_ce.c, functions are called 630 * get_swing_index and get_cck_swing_index. There the current 631 * fixed values are only the defaults in case no match is 632 * found. 633 */ 634 dm_info->default_ofdm_index = 30; 635 dm_info->default_cck_index = 20; 636 637 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) { 638 ewma_thermal_init(&dm_info->avg_thermal[path]); 639 dm_info->delta_power_index[path] = 0; 640 } 641 dm_info->pwr_trk_triggered = false; 642 dm_info->pwr_trk_init_trigger = true; 643 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 644 dm_info->txagc_remnant_cck = 0; 645 dm_info->txagc_remnant_ofdm = 0; 646 } 647 648 static void rtw8703b_phy_set_param(struct rtw_dev *rtwdev) 649 { 650 u8 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F; 651 652 /* power on BB/RF domain */ 653 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, 654 BIT_FEN_EN_25_1 | BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB); 655 rtw_write8_set(rtwdev, REG_RF_CTRL, 656 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 657 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, 0x0780); 658 rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80); 659 660 rtw_phy_load_tables(rtwdev); 661 662 rtw_write32_clr(rtwdev, REG_RCR, BIT_RCR_ADF); 663 /* 0xff is from vendor driver, rtw8723d uses 664 * BIT_HIQ_NO_LMT_EN_ROOT. Comment in vendor driver: "Packet 665 * in Hi Queue Tx immediately". I wonder if setting all bits 666 * is really necessary. 667 */ 668 rtw_write8_set(rtwdev, REG_HIQ_NO_LMT_EN, 0xff); 669 rtw_write16_set(rtwdev, REG_AFE_CTRL_4, BIT_CK320M_AFE_EN | BIT_EN_SYN); 670 671 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, 672 xtal_cap | (xtal_cap << 6)); 673 rtw_write32_set(rtwdev, REG_FPGA0_RFMOD, BIT_CCKEN | BIT_OFDMEN); 674 675 /* Init EDCA */ 676 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SPEC_SIFS); 677 rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, WLAN_SPEC_SIFS); 678 rtw_write16(rtwdev, REG_SIFS, WLAN_SPEC_SIFS); /* CCK */ 679 rtw_write16(rtwdev, REG_SIFS + 2, WLAN_SPEC_SIFS); /* OFDM */ 680 /* TXOP */ 681 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, 0x002FA226); 682 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, 0x005EA324); 683 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, 0x005EA42B); 684 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, 0x0000A44F); 685 686 /* Init retry */ 687 rtw_write8(rtwdev, REG_ACKTO, 0x40); 688 689 /* Set up RX aggregation. sdio.c also sets DMA mode, but not 690 * the burst parameters. 691 */ 692 rtw_write8(rtwdev, REG_RXDMA_MODE, 693 BIT_DMA_MODE | 694 FIELD_PREP_CONST(BIT_MASK_AGG_BURST_NUM, AGG_BURST_NUM) | 695 FIELD_PREP_CONST(BIT_MASK_AGG_BURST_SIZE, AGG_BURST_SIZE)); 696 697 /* Init beacon parameters */ 698 rtw_write8(rtwdev, REG_BCN_CTRL, 699 BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION | BIT_EN_TXBCN_RPT); 700 rtw_write8(rtwdev, REG_TBTT_PROHIBIT, TBTT_PROHIBIT_SETUP_TIME); 701 rtw_write8(rtwdev, REG_TBTT_PROHIBIT + 1, 702 TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF); 703 rtw_write8(rtwdev, REG_TBTT_PROHIBIT + 2, 704 (rtw_read8(rtwdev, REG_TBTT_PROHIBIT + 2) & 0xF0) 705 | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8)); 706 707 /* configure packet burst */ 708 rtw_write8_set(rtwdev, REG_SINGLE_AMPDU_CTRL, BIT_EN_SINGLE_APMDU); 709 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RX_PKT_LIMIT); 710 rtw_write8(rtwdev, REG_MAX_AGGR_NUM, WLAN_MAX_AGG_NR); 711 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_VAL); 712 rtw_write8_clr(rtwdev, REG_FWHW_TXQ_CTRL, BIT_MASK_TXQ_INIT); 713 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, WLAN_AMPDU_MAX_TIME); 714 715 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 716 rtw_write16(rtwdev, REG_RETRY_LIMIT, WLAN_RL_VAL); 717 rtw_write32(rtwdev, REG_BAR_MODE_CTRL, WLAN_BAR_VAL); 718 rtw_write16(rtwdev, REG_ATIMWND, 0x2); 719 720 rtw_phy_init(rtwdev); 721 722 if (rtw_read32_mask(rtwdev, REG_BB_AMP, BIT_MASK_RX_LNA) != 0) { 723 rtwdev->dm_info.rx_cck_agc_report_type = 1; 724 } else { 725 rtwdev->dm_info.rx_cck_agc_report_type = 0; 726 rtw_warn(rtwdev, "unexpected cck agc report type"); 727 } 728 729 rtw8723x_lck(rtwdev); 730 731 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); 732 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20); 733 734 rtw8703b_pwrtrack_init(rtwdev); 735 } 736 737 static bool rtw8703b_check_spur_ov_thres(struct rtw_dev *rtwdev, 738 u32 freq, u32 thres) 739 { 740 bool ret = false; 741 742 rtw_write32(rtwdev, REG_ANALOG_P4, DIS_3WIRE); 743 rtw_write32(rtwdev, REG_PSDFN, freq); 744 rtw_write32(rtwdev, REG_PSDFN, START_PSD | freq); 745 746 msleep(30); 747 if (rtw_read32(rtwdev, REG_PSDRPT) >= thres) 748 ret = true; 749 750 rtw_write32(rtwdev, REG_PSDFN, freq); 751 rtw_write32(rtwdev, REG_ANALOG_P4, EN_3WIRE); 752 753 return ret; 754 } 755 756 static void rtw8703b_cfg_notch(struct rtw_dev *rtwdev, u8 channel, bool notch) 757 { 758 if (!notch) { 759 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f); 760 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); 761 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 762 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 763 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 764 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); 765 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); 766 return; 767 } 768 769 switch (channel) { 770 case 5: 771 fallthrough; 772 case 13: 773 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb); 774 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 775 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x06000000); 776 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 777 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 778 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); 779 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 780 break; 781 case 6: 782 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x4); 783 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 784 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000600); 785 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 786 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 787 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); 788 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 789 break; 790 case 7: 791 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x3); 792 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 793 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 794 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 795 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 796 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x06000000); 797 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 798 break; 799 case 8: 800 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xa); 801 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 802 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 803 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 804 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 805 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000380); 806 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 807 break; 808 case 14: 809 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5); 810 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 811 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 812 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 813 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 814 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00180000); 815 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 816 break; 817 default: 818 rtw_warn(rtwdev, 819 "Bug: Notch filter enable called for channel %u!", 820 channel); 821 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); 822 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); 823 break; 824 } 825 } 826 827 static void rtw8703b_spur_cal(struct rtw_dev *rtwdev, u8 channel) 828 { 829 bool notch; 830 u32 freq; 831 832 if (channel == 5) { 833 freq = FREQ_CH5; 834 } else if (channel == 6) { 835 freq = FREQ_CH6; 836 } else if (channel == 7) { 837 freq = FREQ_CH7; 838 } else if (channel == 8) { 839 freq = FREQ_CH8; 840 } else if (channel == 13) { 841 freq = FREQ_CH13; 842 } else if (channel == 14) { 843 freq = FREQ_CH14; 844 } else { 845 rtw8703b_cfg_notch(rtwdev, channel, false); 846 return; 847 } 848 849 notch = rtw8703b_check_spur_ov_thres(rtwdev, freq, SPUR_THRES); 850 rtw8703b_cfg_notch(rtwdev, channel, notch); 851 } 852 853 static void rtw8703b_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 854 { 855 u32 rf_cfgch_a; 856 u32 rf_cfgch_b; 857 /* default value for 20M */ 858 u32 rf_rck = 0x00000C08; 859 860 rf_cfgch_a = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK); 861 rf_cfgch_b = rtw_read_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK); 862 863 rf_cfgch_a &= ~RFCFGCH_CHANNEL_MASK; 864 rf_cfgch_b &= ~RFCFGCH_CHANNEL_MASK; 865 rf_cfgch_a |= (channel & RFCFGCH_CHANNEL_MASK); 866 rf_cfgch_b |= (channel & RFCFGCH_CHANNEL_MASK); 867 868 rf_cfgch_a &= ~RFCFGCH_BW_MASK; 869 switch (bw) { 870 case RTW_CHANNEL_WIDTH_20: 871 rf_cfgch_a |= RFCFGCH_BW_20M; 872 break; 873 case RTW_CHANNEL_WIDTH_40: 874 rf_cfgch_a |= RFCFGCH_BW_40M; 875 rf_rck = 0x00000C4C; 876 break; 877 default: 878 break; 879 } 880 881 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_cfgch_a); 882 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_cfgch_b); 883 884 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK1, RFREG_MASK, rf_rck); 885 rtw8703b_spur_cal(rtwdev, channel); 886 } 887 888 #define CCK_DFIR_NR_8703B 2 889 static const struct rtw_backup_info cck_dfir_cfg[][CCK_DFIR_NR_8703B] = { 890 [0] = { 891 { .len = 4, .reg = REG_CCK_TXSF2, .val = 0x5A7DA0BD }, 892 { .len = 4, .reg = REG_CCK_DBG, .val = 0x0000223B }, 893 }, 894 [1] = { 895 { .len = 4, .reg = REG_CCK_TXSF2, .val = 0x00000000 }, 896 { .len = 4, .reg = REG_CCK_DBG, .val = 0x00000000 }, 897 }, 898 }; 899 900 static void rtw8703b_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 901 u8 primary_ch_idx) 902 { 903 const struct rtw_backup_info *cck_dfir; 904 int i; 905 906 cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1]; 907 908 for (i = 0; i < CCK_DFIR_NR_8703B; i++, cck_dfir++) 909 rtw_write32(rtwdev, cck_dfir->reg, cck_dfir->val); 910 911 switch (bw) { 912 case RTW_CHANNEL_WIDTH_20: 913 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0); 914 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0); 915 rtw_write32_mask(rtwdev, REG_OFDM0_TX_PSD_NOISE, 916 GENMASK(31, 20), 0x0); 917 rtw_write32(rtwdev, REG_BBRX_DFIR, 0x4A880000); 918 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x19F60000); 919 break; 920 case RTW_CHANNEL_WIDTH_40: 921 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1); 922 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1); 923 rtw_write32(rtwdev, REG_BBRX_DFIR, 0x40100000); 924 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x51F60000); 925 rtw_write32_mask(rtwdev, REG_CCK0_SYS, BIT_CCK_SIDE_BAND, 926 primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0); 927 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, 0xC00, 928 primary_ch_idx == RTW_SC_20_UPPER ? 2 : 1); 929 930 rtw_write32_mask(rtwdev, REG_BB_PWR_SAV5_11N, GENMASK(27, 26), 931 primary_ch_idx == RTW_SC_20_UPPER ? 1 : 2); 932 break; 933 default: 934 break; 935 } 936 } 937 938 static void rtw8703b_set_channel(struct rtw_dev *rtwdev, u8 channel, 939 u8 bw, u8 primary_chan_idx) 940 { 941 rtw8703b_set_channel_rf(rtwdev, channel, bw); 942 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 943 rtw8703b_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 944 } 945 946 /* Not all indices are valid, based on available data. None of the 947 * known valid values are positive, so use 0x7f as "invalid". 948 */ 949 #define LNA_IDX_INVALID 0x7f 950 static const s8 lna_gain_table[16] = { 951 -2, LNA_IDX_INVALID, LNA_IDX_INVALID, LNA_IDX_INVALID, 952 -6, LNA_IDX_INVALID, LNA_IDX_INVALID, -19, 953 -32, LNA_IDX_INVALID, -36, -42, 954 LNA_IDX_INVALID, LNA_IDX_INVALID, LNA_IDX_INVALID, -48, 955 }; 956 957 static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx) 958 { 959 s8 lna_gain = 0; 960 961 if (lna_idx < ARRAY_SIZE(lna_gain_table)) 962 lna_gain = lna_gain_table[lna_idx]; 963 964 if (lna_gain >= 0) { 965 rtw_warn(rtwdev, "incorrect lna index (%d)\n", lna_idx); 966 return -120; 967 } 968 969 return lna_gain - 2 * vga_idx; 970 } 971 972 static void query_phy_status_cck(struct rtw_dev *rtwdev, u8 *phy_raw, 973 struct rtw_rx_pkt_stat *pkt_stat) 974 { 975 struct phy_status_8703b *phy_status = (struct phy_status_8703b *)phy_raw; 976 u8 vga_idx = phy_status->cck_agc_rpt_ofdm_cfosho_a & VGA_BITS; 977 u8 lna_idx = phy_status->cck_agc_rpt_ofdm_cfosho_a & LNA_L_BITS; 978 s8 rx_power; 979 980 if (rtwdev->dm_info.rx_cck_agc_report_type == 1) 981 lna_idx = FIELD_PREP(BIT_LNA_H_MASK, 982 phy_status->cck_rpt_b_ofdm_cfosho_b & LNA_H_BIT) 983 | FIELD_PREP(BIT_LNA_L_MASK, lna_idx); 984 else 985 lna_idx = FIELD_PREP(BIT_LNA_L_MASK, lna_idx); 986 rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx); 987 988 pkt_stat->rx_power[RF_PATH_A] = rx_power; 989 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 990 rtwdev->dm_info.rssi[RF_PATH_A] = pkt_stat->rssi; 991 pkt_stat->signal_power = rx_power; 992 } 993 994 static void query_phy_status_ofdm(struct rtw_dev *rtwdev, u8 *phy_raw, 995 struct rtw_rx_pkt_stat *pkt_stat) 996 { 997 struct phy_status_8703b *phy_status = (struct phy_status_8703b *)phy_raw; 998 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 999 s8 val_s8; 1000 1001 val_s8 = phy_status->path_agc[RF_PATH_A].gain & 0x3F; 1002 pkt_stat->rx_power[RF_PATH_A] = (val_s8 * 2) - 110; 1003 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 1004 pkt_stat->rx_snr[RF_PATH_A] = (s8)(phy_status->path_rxsnr[RF_PATH_A] / 2); 1005 1006 /* signal power reported by HW */ 1007 val_s8 = phy_status->cck_sig_qual_ofdm_pwdb_all >> 1; 1008 pkt_stat->signal_power = (val_s8 & 0x7f) - 110; 1009 1010 pkt_stat->rx_evm[RF_PATH_A] = phy_status->stream_rxevm[RF_PATH_A]; 1011 pkt_stat->cfo_tail[RF_PATH_A] = phy_status->path_cfotail[RF_PATH_A]; 1012 1013 dm_info->curr_rx_rate = pkt_stat->rate; 1014 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 1015 dm_info->rx_snr[RF_PATH_A] = pkt_stat->rx_snr[RF_PATH_A] >> 1; 1016 /* convert to KHz (used only for debugfs) */ 1017 dm_info->cfo_tail[RF_PATH_A] = (pkt_stat->cfo_tail[RF_PATH_A] * 5) >> 1; 1018 1019 /* (EVM value as s8 / 2) is dbm, should usually be in -33 to 0 1020 * range. rx_evm_dbm needs the absolute (positive) value. 1021 */ 1022 val_s8 = (s8)pkt_stat->rx_evm[RF_PATH_A]; 1023 val_s8 = clamp_t(s8, -val_s8 >> 1, 0, 64); 1024 val_s8 &= 0x3F; /* 64->0: second path of 1SS rate is 64 */ 1025 dm_info->rx_evm_dbm[RF_PATH_A] = val_s8; 1026 } 1027 1028 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 1029 struct rtw_rx_pkt_stat *pkt_stat) 1030 { 1031 if (pkt_stat->rate <= DESC_RATE11M) 1032 query_phy_status_cck(rtwdev, phy_status, pkt_stat); 1033 else 1034 query_phy_status_ofdm(rtwdev, phy_status, pkt_stat); 1035 } 1036 1037 static void rtw8703b_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 1038 struct rtw_rx_pkt_stat *pkt_stat, 1039 struct ieee80211_rx_status *rx_status) 1040 { 1041 struct ieee80211_hdr *hdr; 1042 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 1043 u8 *phy_status = NULL; 1044 1045 memset(pkt_stat, 0, sizeof(*pkt_stat)); 1046 1047 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 1048 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 1049 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 1050 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && 1051 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; 1052 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 1053 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 1054 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 1055 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 1056 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 1057 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 1058 pkt_stat->ppdu_cnt = 0; 1059 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 1060 1061 pkt_stat->drv_info_sz *= RX_DRV_INFO_SZ_UNIT_8703B; 1062 1063 if (pkt_stat->is_c2h) 1064 return; 1065 1066 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 1067 pkt_stat->drv_info_sz); 1068 1069 pkt_stat->bw = GET_RX_DESC_BW(rx_desc); 1070 1071 if (pkt_stat->phy_status) { 1072 phy_status = rx_desc + desc_sz + pkt_stat->shift; 1073 query_phy_status(rtwdev, phy_status, pkt_stat); 1074 } 1075 1076 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 1077 1078 /* Rtl8723cs driver checks for size < 14 or size > 8192 and 1079 * simply drops the packet. Maybe this should go into 1080 * rtw_rx_fill_rx_status()? 1081 */ 1082 if (pkt_stat->pkt_len == 0) { 1083 rx_status->flag |= RX_FLAG_NO_PSDU; 1084 rtw_dbg(rtwdev, RTW_DBG_RX, "zero length packet"); 1085 } 1086 } 1087 1088 #define ADDA_ON_VAL_8703B 0x03c00014 1089 1090 static 1091 void rtw8703b_iqk_config_mac(struct rtw_dev *rtwdev, 1092 const struct rtw8723x_iqk_backup_regs *backup) 1093 { 1094 rtw_write8(rtwdev, rtw8723x_common.iqk_mac8_regs[0], 0x3F); 1095 for (int i = 1; i < RTW8723X_IQK_MAC8_REG_NUM; i++) 1096 rtw_write8(rtwdev, rtw8723x_common.iqk_mac8_regs[i], 1097 backup->mac8[i] & (~BIT(3))); 1098 } 1099 1100 #define IQK_LTE_WRITE_VAL_8703B 0x00007700 1101 #define IQK_DELAY_TIME_8703B 4 1102 1103 static void rtw8703b_iqk_one_shot(struct rtw_dev *rtwdev, bool tx) 1104 { 1105 u32 regval; 1106 ktime_t t; 1107 s64 dur; 1108 int ret; 1109 1110 /* enter IQK mode */ 1111 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); 1112 rtw8723x_iqk_config_lte_path_gnt(rtwdev, IQK_LTE_WRITE_VAL_8703B); 1113 1114 /* One shot, LOK & IQK */ 1115 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf9000000); 1116 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf8000000); 1117 1118 t = ktime_get(); 1119 msleep(IQK_DELAY_TIME_8703B); 1120 ret = read_poll_timeout(rtw_read32, regval, regval != 0, 1000, 1121 100000, false, rtwdev, 1122 REG_IQK_RDY); 1123 dur = ktime_us_delta(ktime_get(), t); 1124 1125 if (ret) 1126 #if defined(__linux__) 1127 rtw_warn(rtwdev, "[IQK] %s timed out after %lldus!\n", 1128 tx ? "TX" : "RX", dur); 1129 #elif defined(__FreeBSD__) 1130 rtw_warn(rtwdev, "[IQK] %s timed out after %jdus!\n", 1131 tx ? "TX" : "RX", (intmax_t)dur); 1132 #endif 1133 else 1134 rtw_dbg(rtwdev, RTW_DBG_RFK, 1135 #if defined(__linux__) 1136 "[IQK] %s done after %lldus\n", 1137 tx ? "TX" : "RX", dur); 1138 #elif defined(__FreeBSD__) 1139 "[IQK] %s done after %jdus\n", 1140 tx ? "TX" : "RX", (intmax_t)dur); 1141 #endif 1142 } 1143 1144 static void rtw8703b_iqk_txrx_path_post(struct rtw_dev *rtwdev, 1145 const struct rtw8723x_iqk_backup_regs *backup) 1146 { 1147 rtw8723x_iqk_restore_lte_path_gnt(rtwdev, backup); 1148 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup->bb_sel_btg); 1149 1150 /* leave IQK mode */ 1151 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1152 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x0); 1153 } 1154 1155 static u8 rtw8703b_iqk_check_tx_failed(struct rtw_dev *rtwdev) 1156 { 1157 s32 tx_x, tx_y; 1158 u32 tx_fail; 1159 1160 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xeac = 0x%x\n", 1161 rtw_read32(rtwdev, REG_IQK_RES_RY)); 1162 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n", 1163 rtw_read32(rtwdev, REG_IQK_RES_TX), 1164 rtw_read32(rtwdev, REG_IQK_RES_TY)); 1165 rtw_dbg(rtwdev, RTW_DBG_RFK, 1166 "[IQK] 0xe90(before IQK) = 0x%x, 0xe98(after IQK) = 0x%x\n", 1167 rtw_read32(rtwdev, REG_IQK_RDY), 1168 rtw_read32(rtwdev, 0xe98)); 1169 1170 tx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_TX_FAIL); 1171 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 1172 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 1173 1174 if (!tx_fail && tx_x != IQK_TX_X_ERR && tx_y != IQK_TX_Y_ERR) 1175 return IQK_TX_OK; 1176 1177 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] A TX IQK failed\n"); 1178 1179 return 0; 1180 } 1181 1182 static u8 rtw8703b_iqk_check_rx_failed(struct rtw_dev *rtwdev) 1183 { 1184 s32 rx_x, rx_y; 1185 u32 rx_fail; 1186 1187 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n", 1188 rtw_read32(rtwdev, REG_IQK_RES_RX), 1189 rtw_read32(rtwdev, REG_IQK_RES_RY)); 1190 1191 rtw_dbg(rtwdev, RTW_DBG_RFK, 1192 "[IQK] 0xea0(before IQK) = 0x%x, 0xea8(after IQK) = 0x%x\n", 1193 rtw_read32(rtwdev, 0xea0), 1194 rtw_read32(rtwdev, 0xea8)); 1195 1196 rx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_RX_FAIL); 1197 rx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX); 1198 rx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY); 1199 rx_y = abs(iqkxy_to_s32(rx_y)); 1200 1201 if (!rx_fail && rx_x != IQK_RX_X_ERR && rx_y != IQK_RX_Y_ERR && 1202 rx_x < IQK_RX_X_UPPER && rx_x > IQK_RX_X_LOWER && 1203 rx_y < IQK_RX_Y_LMT) 1204 return IQK_RX_OK; 1205 1206 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] A RX IQK failed\n"); 1207 1208 return 0; 1209 } 1210 1211 static u8 rtw8703b_iqk_tx_path(struct rtw_dev *rtwdev, 1212 const struct rtw8723x_iqk_backup_regs *backup) 1213 { 1214 u8 status; 1215 1216 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A TX IQK!\n"); 1217 1218 /* IQK setting */ 1219 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); 1220 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 1221 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c); 1222 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c); 1223 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); 1224 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); 1225 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x8214030f); 1226 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28110000); 1227 rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000); 1228 rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000); 1229 1230 /* LO calibration setting */ 1231 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x00462911); 1232 1233 /* leave IQK mode */ 1234 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000); 1235 1236 /* PA, PAD setting */ 1237 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x1); 1238 rtw_write_rf(rtwdev, RF_PATH_A, 0x55, 0x7f, 0x7); 1239 rtw_write_rf(rtwdev, RF_PATH_A, 0x7f, RFREG_MASK, 0xd400); 1240 1241 rtw8703b_iqk_one_shot(rtwdev, true); 1242 status = rtw8703b_iqk_check_tx_failed(rtwdev); 1243 1244 rtw8703b_iqk_txrx_path_post(rtwdev, backup); 1245 1246 return status; 1247 } 1248 1249 static u8 rtw8703b_iqk_rx_path(struct rtw_dev *rtwdev, 1250 const struct rtw8723x_iqk_backup_regs *backup) 1251 { 1252 u8 status; 1253 u32 tx_x, tx_y; 1254 1255 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A RX IQK step 1!\n"); 1256 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @A RX IQK1 = 0x%x\n", 1257 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 1258 rtw_write32(rtwdev, REG_BB_SEL_BTG, 0x99000000); 1259 1260 /* disable IQC mode */ 1261 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1262 1263 /* IQK setting */ 1264 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); 1265 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 1266 1267 /* path IQK setting */ 1268 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c); 1269 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c); 1270 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); 1271 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); 1272 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x8216000f); 1273 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28110000); 1274 rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x28110000); 1275 rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000); 1276 1277 /* LOK setting */ 1278 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a911); 1279 1280 /* RX IQK mode */ 1281 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, 0x80000, 0x1); 1282 rtw_write_rf(rtwdev, RF_PATH_A, 0x30, RFREG_MASK, 0x30000); 1283 rtw_write_rf(rtwdev, RF_PATH_A, 0x31, RFREG_MASK, 0x00007); 1284 rtw_write_rf(rtwdev, RF_PATH_A, 0x32, RFREG_MASK, 0x57db7); 1285 1286 rtw8703b_iqk_one_shot(rtwdev, true); 1287 /* leave IQK mode */ 1288 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000); 1289 status = rtw8703b_iqk_check_tx_failed(rtwdev); 1290 1291 if (!status) 1292 goto restore; 1293 1294 /* second round */ 1295 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 1296 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 1297 1298 rtw_write32(rtwdev, REG_TXIQK_11N, BIT_SET_TXIQK_11N(tx_x, tx_y)); 1299 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n", 1300 rtw_read32(rtwdev, REG_TXIQK_11N), 1301 BIT_SET_TXIQK_11N(tx_x, tx_y)); 1302 1303 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A RX IQK step 2!\n"); 1304 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @A RX IQK 2 = 0x%x\n", 1305 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 1306 1307 /* IQK setting */ 1308 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 1309 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x38008c1c); 1310 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x18008c1c); 1311 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); 1312 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); 1313 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82110000); 1314 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160c1f); 1315 rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000); 1316 rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000); 1317 1318 /* LO calibration setting */ 1319 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a8d1); 1320 1321 /* leave IQK mode */ 1322 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000); 1323 /* modify RX IQK mode table */ 1324 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, 0x80000, 0x1); 1325 /* RF_RCK_OS, RF_TXPA_G1, RF_TXPA_G2 */ 1326 rtw_write_rf(rtwdev, RF_PATH_A, 0x30, RFREG_MASK, 0x30000); 1327 rtw_write_rf(rtwdev, RF_PATH_A, 0x31, RFREG_MASK, 0x00007); 1328 rtw_write_rf(rtwdev, RF_PATH_A, 0x32, RFREG_MASK, 0xf7d77); 1329 1330 /* PA, PAD setting */ 1331 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x1); 1332 rtw_write_rf(rtwdev, RF_PATH_A, 0x55, 0x7f, 0x5); 1333 1334 rtw8703b_iqk_one_shot(rtwdev, false); 1335 status |= rtw8703b_iqk_check_rx_failed(rtwdev); 1336 1337 restore: 1338 rtw8703b_iqk_txrx_path_post(rtwdev, backup); 1339 1340 return status; 1341 } 1342 1343 static 1344 void rtw8703b_iqk_one_round(struct rtw_dev *rtwdev, s32 result[][IQK_NR], u8 t, 1345 const struct rtw8723x_iqk_backup_regs *backup) 1346 { 1347 u32 i; 1348 u8 a_ok; 1349 1350 rtw_dbg(rtwdev, RTW_DBG_RFK, 1351 "[IQK] IQ Calibration for 1T1R_S0/S1 for %d times\n", t); 1352 1353 rtw8723x_iqk_path_adda_on(rtwdev, ADDA_ON_VAL_8703B); 1354 rtw8703b_iqk_config_mac(rtwdev, backup); 1355 rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf); 1356 rtw_write32(rtwdev, REG_BB_RX_PATH_11N, 0x03a05600); 1357 rtw_write32(rtwdev, REG_TRMUX_11N, 0x000800e4); 1358 rtw_write32(rtwdev, REG_BB_PWR_SAV1_11N, 0x25204000); 1359 1360 for (i = 0; i < PATH_IQK_RETRY; i++) { 1361 a_ok = rtw8703b_iqk_tx_path(rtwdev, backup); 1362 if (a_ok == IQK_TX_OK) { 1363 rtw_dbg(rtwdev, RTW_DBG_RFK, 1364 "[IQK] path A TX IQK success!\n"); 1365 result[t][IQK_S1_TX_X] = 1366 rtw_read32_mask(rtwdev, REG_IQK_RES_TX, 1367 BIT_MASK_RES_TX); 1368 result[t][IQK_S1_TX_Y] = 1369 rtw_read32_mask(rtwdev, REG_IQK_RES_TY, 1370 BIT_MASK_RES_TY); 1371 break; 1372 } 1373 1374 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A TX IQK fail!\n"); 1375 result[t][IQK_S1_TX_X] = 0x100; 1376 result[t][IQK_S1_TX_Y] = 0x0; 1377 } 1378 1379 for (i = 0; i < PATH_IQK_RETRY; i++) { 1380 a_ok = rtw8703b_iqk_rx_path(rtwdev, backup); 1381 if (a_ok == (IQK_TX_OK | IQK_RX_OK)) { 1382 rtw_dbg(rtwdev, RTW_DBG_RFK, 1383 "[IQK] path A RX IQK success!\n"); 1384 result[t][IQK_S1_RX_X] = 1385 rtw_read32_mask(rtwdev, REG_IQK_RES_RX, 1386 BIT_MASK_RES_RX); 1387 result[t][IQK_S1_RX_Y] = 1388 rtw_read32_mask(rtwdev, REG_IQK_RES_RY, 1389 BIT_MASK_RES_RY); 1390 break; 1391 } 1392 1393 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A RX IQK fail!\n"); 1394 result[t][IQK_S1_RX_X] = 0x100; 1395 result[t][IQK_S1_RX_Y] = 0x0; 1396 } 1397 1398 if (a_ok == 0x0) 1399 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A IQK fail!\n"); 1400 1401 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1402 mdelay(1); 1403 } 1404 1405 static 1406 void rtw8703b_iqk_fill_a_matrix(struct rtw_dev *rtwdev, const s32 result[]) 1407 { 1408 u32 tmp_rx_iqi = 0x40000100 & GENMASK(31, 16); 1409 s32 tx1_a, tx1_a_ext; 1410 s32 tx1_c, tx1_c_ext; 1411 s32 oldval_1; 1412 s32 x, y; 1413 1414 if (result[IQK_S1_TX_X] == 0) 1415 return; 1416 1417 oldval_1 = rtw_read32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 1418 BIT_MASK_TXIQ_ELM_D); 1419 1420 x = iqkxy_to_s32(result[IQK_S1_TX_X]); 1421 tx1_a = iqk_mult(x, oldval_1, &tx1_a_ext); 1422 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 1423 BIT_MASK_TXIQ_ELM_A, tx1_a); 1424 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, 1425 BIT_MASK_OFDM0_EXT_A, tx1_a_ext); 1426 1427 y = iqkxy_to_s32(result[IQK_S1_TX_Y]); 1428 tx1_c = iqk_mult(y, oldval_1, &tx1_c_ext); 1429 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1430 BIT_SET_TXIQ_ELM_C1(tx1_c)); 1431 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 1432 BIT_MASK_TXIQ_ELM_C, BIT_SET_TXIQ_ELM_C2(tx1_c)); 1433 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, 1434 BIT_MASK_OFDM0_EXT_C, tx1_c_ext); 1435 1436 rtw_dbg(rtwdev, RTW_DBG_RFK, 1437 "[IQK] X = 0x%x, TX1_A = 0x%x, oldval_1 0x%x\n", 1438 x, tx1_a, oldval_1); 1439 rtw_dbg(rtwdev, RTW_DBG_RFK, 1440 "[IQK] Y = 0x%x, TX1_C = 0x%x\n", y, tx1_c); 1441 1442 if (result[IQK_S1_RX_X] == 0) 1443 return; 1444 1445 tmp_rx_iqi |= FIELD_PREP(BIT_MASK_RXIQ_S1_X, result[IQK_S1_RX_X]); 1446 tmp_rx_iqi |= FIELD_PREP(BIT_MASK_RXIQ_S1_Y1, result[IQK_S1_RX_X]); 1447 rtw_write32(rtwdev, REG_A_RXIQI, tmp_rx_iqi); 1448 rtw_write32_mask(rtwdev, REG_RXIQK_MATRIX_LSB_11N, BIT_MASK_RXIQ_S1_Y2, 1449 BIT_SET_RXIQ_S1_Y2(result[IQK_S1_RX_Y])); 1450 } 1451 1452 static void rtw8703b_phy_calibration(struct rtw_dev *rtwdev) 1453 { 1454 /* For some reason path A is called S1 and B S0 in shared 1455 * rtw88 calibration data. 1456 */ 1457 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1458 struct rtw8723x_iqk_backup_regs backup; 1459 u8 final_candidate = IQK_ROUND_INVALID; 1460 s32 result[IQK_ROUND_SIZE][IQK_NR]; 1461 bool good; 1462 u8 i, j; 1463 1464 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] Start!\n"); 1465 1466 memset(result, 0, sizeof(result)); 1467 1468 rtw8723x_iqk_backup_path_ctrl(rtwdev, &backup); 1469 rtw8723x_iqk_backup_lte_path_gnt(rtwdev, &backup); 1470 rtw8723x_iqk_backup_regs(rtwdev, &backup); 1471 1472 for (i = IQK_ROUND_0; i <= IQK_ROUND_2; i++) { 1473 rtw8723x_iqk_config_path_ctrl(rtwdev); 1474 rtw8723x_iqk_config_lte_path_gnt(rtwdev, IQK_LTE_WRITE_VAL_8703B); 1475 1476 rtw8703b_iqk_one_round(rtwdev, result, i, &backup); 1477 1478 rtw_dbg(rtwdev, RTW_DBG_RFK, 1479 "[IQK] back to BB mode, load original values!\n"); 1480 if (i > IQK_ROUND_0) 1481 rtw8723x_iqk_restore_regs(rtwdev, &backup); 1482 rtw8723x_iqk_restore_lte_path_gnt(rtwdev, &backup); 1483 rtw8723x_iqk_restore_path_ctrl(rtwdev, &backup); 1484 1485 for (j = IQK_ROUND_0; j < i; j++) { 1486 good = rtw8723x_iqk_similarity_cmp(rtwdev, result, j, i); 1487 1488 if (good) { 1489 final_candidate = j; 1490 rtw_dbg(rtwdev, RTW_DBG_RFK, 1491 "[IQK] cmp %d:%d final_candidate is %x\n", 1492 j, i, final_candidate); 1493 goto iqk_done; 1494 } 1495 } 1496 } 1497 1498 if (final_candidate == IQK_ROUND_INVALID) { 1499 s32 reg_tmp = 0; 1500 1501 for (i = 0; i < IQK_NR; i++) 1502 reg_tmp += result[IQK_ROUND_HYBRID][i]; 1503 1504 if (reg_tmp != 0) { 1505 final_candidate = IQK_ROUND_HYBRID; 1506 } else { 1507 WARN(1, "IQK failed\n"); 1508 goto out; 1509 } 1510 } 1511 1512 iqk_done: 1513 /* only path A is calibrated in rtl8703b */ 1514 rtw8703b_iqk_fill_a_matrix(rtwdev, result[final_candidate]); 1515 1516 dm_info->iqk.result.s1_x = result[final_candidate][IQK_S1_TX_X]; 1517 dm_info->iqk.result.s1_y = result[final_candidate][IQK_S1_TX_Y]; 1518 dm_info->iqk.result.s0_x = result[final_candidate][IQK_S0_TX_X]; 1519 dm_info->iqk.result.s0_y = result[final_candidate][IQK_S0_TX_Y]; 1520 dm_info->iqk.done = true; 1521 1522 out: 1523 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup.bb_sel_btg); 1524 1525 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] final_candidate is %x\n", 1526 final_candidate); 1527 1528 for (i = IQK_ROUND_0; i < IQK_ROUND_SIZE; i++) 1529 rtw_dbg(rtwdev, RTW_DBG_RFK, 1530 "[IQK] Result %u: rege94_s1=%x rege9c_s1=%x regea4_s1=%x regeac_s1=%x rege94_s0=%x rege9c_s0=%x regea4_s0=%x regeac_s0=%x %s\n", 1531 i, 1532 result[i][0], result[i][1], result[i][2], result[i][3], 1533 result[i][4], result[i][5], result[i][6], result[i][7], 1534 final_candidate == i ? "(final candidate)" : ""); 1535 1536 rtw_dbg(rtwdev, RTW_DBG_RFK, 1537 "[IQK] 0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n", 1538 rtw_read32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE), 1539 rtw_read32(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N), 1540 rtw_read32(rtwdev, REG_A_RXIQI), 1541 rtw_read32(rtwdev, REG_RXIQK_MATRIX_LSB_11N)); 1542 rtw_dbg(rtwdev, RTW_DBG_RFK, 1543 "[IQK] 0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n", 1544 rtw_read32(rtwdev, REG_TXIQ_AB_S0), 1545 rtw_read32(rtwdev, REG_TXIQ_CD_S0), 1546 rtw_read32(rtwdev, REG_RXIQ_AB_S0)); 1547 1548 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] Finished.\n"); 1549 } 1550 1551 static void rtw8703b_set_iqk_matrix_by_result(struct rtw_dev *rtwdev, 1552 u32 ofdm_swing, u8 rf_path) 1553 { 1554 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1555 s32 ele_A, ele_D, ele_C; 1556 s32 ele_A_ext, ele_C_ext, ele_D_ext; 1557 s32 iqk_result_x; 1558 s32 iqk_result_y; 1559 s32 value32; 1560 1561 switch (rf_path) { 1562 default: 1563 case RF_PATH_A: 1564 iqk_result_x = dm_info->iqk.result.s1_x; 1565 iqk_result_y = dm_info->iqk.result.s1_y; 1566 break; 1567 case RF_PATH_B: 1568 iqk_result_x = dm_info->iqk.result.s0_x; 1569 iqk_result_y = dm_info->iqk.result.s0_y; 1570 break; 1571 } 1572 1573 /* new element D */ 1574 ele_D = OFDM_SWING_D(ofdm_swing); 1575 iqk_mult(iqk_result_x, ele_D, &ele_D_ext); 1576 /* new element A */ 1577 iqk_result_x = iqkxy_to_s32(iqk_result_x); 1578 ele_A = iqk_mult(iqk_result_x, ele_D, &ele_A_ext); 1579 /* new element C */ 1580 iqk_result_y = iqkxy_to_s32(iqk_result_y); 1581 ele_C = iqk_mult(iqk_result_y, ele_D, &ele_C_ext); 1582 1583 switch (rf_path) { 1584 case RF_PATH_A: 1585 default: 1586 /* write new elements A, C, D, and element B is always 0 */ 1587 value32 = BIT_SET_TXIQ_ELM_ACD(ele_A, ele_C, ele_D); 1588 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, value32); 1589 value32 = BIT_SET_TXIQ_ELM_C1(ele_C); 1590 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1591 value32); 1592 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1593 value32 &= ~BIT_MASK_OFDM0_EXTS; 1594 value32 |= BIT_SET_OFDM0_EXTS(ele_A_ext, ele_C_ext, ele_D_ext); 1595 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1596 break; 1597 1598 case RF_PATH_B: 1599 /* write new elements A, C, D, and element B is always 0 */ 1600 value32 = BIT_SET_TXIQ_ELM_ACD(ele_A, ele_C, ele_D); 1601 rtw_write32(rtwdev, REG_OFDM_0_XB_TX_IQ_IMBALANCE, value32); 1602 value32 = BIT_SET_TXIQ_ELM_C1(ele_C); 1603 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXB_LSB2_11N, MASKH4BITS, 1604 value32); 1605 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1606 value32 &= ~BIT_MASK_OFDM0_EXTS_B; 1607 value32 |= BIT_SET_OFDM0_EXTS_B(ele_A_ext, ele_C_ext, ele_D_ext); 1608 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1609 break; 1610 } 1611 } 1612 1613 static void rtw8703b_set_iqk_matrix(struct rtw_dev *rtwdev, s8 ofdm_index, 1614 u8 rf_path) 1615 { 1616 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1617 s32 value32; 1618 u32 ofdm_swing; 1619 1620 ofdm_index = clamp_t(s8, ofdm_index, 0, RTW_OFDM_SWING_TABLE_SIZE - 1); 1621 1622 ofdm_swing = rtw8703b_ofdm_swing_table[ofdm_index]; 1623 1624 if (dm_info->iqk.done) { 1625 rtw8703b_set_iqk_matrix_by_result(rtwdev, ofdm_swing, rf_path); 1626 return; 1627 } 1628 1629 switch (rf_path) { 1630 case RF_PATH_A: 1631 default: 1632 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, ofdm_swing); 1633 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1634 0x00); 1635 1636 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1637 value32 &= ~BIT_MASK_OFDM0_EXTS; 1638 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1639 break; 1640 1641 case RF_PATH_B: 1642 rtw_write32(rtwdev, REG_OFDM_0_XB_TX_IQ_IMBALANCE, ofdm_swing); 1643 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXB_LSB2_11N, MASKH4BITS, 1644 0x00); 1645 1646 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1647 value32 &= ~BIT_MASK_OFDM0_EXTS_B; 1648 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1649 break; 1650 } 1651 } 1652 1653 static void rtw8703b_pwrtrack_set_ofdm_pwr(struct rtw_dev *rtwdev, s8 swing_idx, 1654 s8 txagc_idx) 1655 { 1656 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1657 1658 dm_info->txagc_remnant_ofdm = txagc_idx; 1659 1660 /* Only path A is calibrated for rtl8703b */ 1661 rtw8703b_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_A); 1662 } 1663 1664 static void rtw8703b_pwrtrack_set_cck_pwr(struct rtw_dev *rtwdev, s8 swing_idx, 1665 s8 txagc_idx) 1666 { 1667 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1668 1669 dm_info->txagc_remnant_cck = txagc_idx; 1670 1671 swing_idx = clamp_t(s8, swing_idx, 0, RTW_CCK_SWING_TABLE_SIZE - 1); 1672 1673 BUILD_BUG_ON(ARRAY_SIZE(rtw8703b_cck_pwr_regs) 1674 != ARRAY_SIZE(rtw8703b_cck_swing_table[0])); 1675 1676 for (int i = 0; i < ARRAY_SIZE(rtw8703b_cck_pwr_regs); i++) 1677 rtw_write8(rtwdev, rtw8703b_cck_pwr_regs[i], 1678 rtw8703b_cck_swing_table[swing_idx][i]); 1679 } 1680 1681 static void rtw8703b_pwrtrack_set(struct rtw_dev *rtwdev, u8 path) 1682 { 1683 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1684 struct rtw_hal *hal = &rtwdev->hal; 1685 u8 limit_ofdm; 1686 u8 limit_cck = 21; 1687 s8 final_ofdm_swing_index; 1688 s8 final_cck_swing_index; 1689 1690 limit_ofdm = rtw8723x_pwrtrack_get_limit_ofdm(rtwdev); 1691 1692 final_ofdm_swing_index = dm_info->default_ofdm_index + 1693 dm_info->delta_power_index[path]; 1694 final_cck_swing_index = dm_info->default_cck_index + 1695 dm_info->delta_power_index[path]; 1696 1697 if (final_ofdm_swing_index > limit_ofdm) 1698 rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, limit_ofdm, 1699 final_ofdm_swing_index - limit_ofdm); 1700 else if (final_ofdm_swing_index < 0) 1701 rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, 0, 1702 final_ofdm_swing_index); 1703 else 1704 rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, final_ofdm_swing_index, 0); 1705 1706 if (final_cck_swing_index > limit_cck) 1707 rtw8703b_pwrtrack_set_cck_pwr(rtwdev, limit_cck, 1708 final_cck_swing_index - limit_cck); 1709 else if (final_cck_swing_index < 0) 1710 rtw8703b_pwrtrack_set_cck_pwr(rtwdev, 0, 1711 final_cck_swing_index); 1712 else 1713 rtw8703b_pwrtrack_set_cck_pwr(rtwdev, final_cck_swing_index, 0); 1714 1715 rtw_phy_set_tx_power_level(rtwdev, hal->current_channel); 1716 } 1717 1718 static void rtw8703b_phy_pwrtrack(struct rtw_dev *rtwdev) 1719 { 1720 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1721 struct rtw_swing_table swing_table; 1722 u8 thermal_value, delta, path; 1723 bool do_iqk = false; 1724 1725 rtw_phy_config_swing_table(rtwdev, &swing_table); 1726 1727 if (rtwdev->efuse.thermal_meter[0] == 0xff) 1728 return; 1729 1730 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 1731 1732 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 1733 1734 do_iqk = rtw_phy_pwrtrack_need_iqk(rtwdev); 1735 1736 if (do_iqk) 1737 rtw8723x_lck(rtwdev); 1738 1739 if (dm_info->pwr_trk_init_trigger) 1740 dm_info->pwr_trk_init_trigger = false; 1741 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 1742 RF_PATH_A)) 1743 goto iqk; 1744 1745 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 1746 1747 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); 1748 1749 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1750 s8 delta_cur, delta_last; 1751 1752 delta_last = dm_info->delta_power_index[path]; 1753 delta_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, 1754 path, RF_PATH_A, delta); 1755 if (delta_last == delta_cur) 1756 continue; 1757 1758 dm_info->delta_power_index[path] = delta_cur; 1759 rtw8703b_pwrtrack_set(rtwdev, path); 1760 } 1761 1762 rtw8723x_pwrtrack_set_xtal(rtwdev, RF_PATH_A, delta); 1763 1764 iqk: 1765 if (do_iqk) 1766 rtw8703b_phy_calibration(rtwdev); 1767 } 1768 1769 static void rtw8703b_pwr_track(struct rtw_dev *rtwdev) 1770 { 1771 struct rtw_efuse *efuse = &rtwdev->efuse; 1772 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1773 1774 if (efuse->power_track_type != 0) { 1775 rtw_warn(rtwdev, "unsupported power track type"); 1776 return; 1777 } 1778 1779 if (!dm_info->pwr_trk_triggered) { 1780 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 1781 GENMASK(17, 16), 0x03); 1782 dm_info->pwr_trk_triggered = true; 1783 return; 1784 } 1785 1786 rtw8703b_phy_pwrtrack(rtwdev); 1787 dm_info->pwr_trk_triggered = false; 1788 } 1789 1790 static void rtw8703b_coex_set_gnt_fix(struct rtw_dev *rtwdev) 1791 { 1792 } 1793 1794 static void rtw8703b_coex_set_gnt_debug(struct rtw_dev *rtwdev) 1795 { 1796 } 1797 1798 static void rtw8703b_coex_set_rfe_type(struct rtw_dev *rtwdev) 1799 { 1800 struct rtw_coex *coex = &rtwdev->coex; 1801 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 1802 1803 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; 1804 coex_rfe->ant_switch_polarity = 0; 1805 coex_rfe->ant_switch_exist = false; 1806 coex_rfe->ant_switch_with_bt = false; 1807 coex_rfe->ant_switch_diversity = false; 1808 coex_rfe->wlg_at_btg = true; 1809 1810 /* disable LTE coex on wifi side */ 1811 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0); 1812 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); 1813 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); 1814 } 1815 1816 static void rtw8703b_coex_set_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 1817 { 1818 } 1819 1820 static void rtw8703b_coex_set_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 1821 { 1822 } 1823 1824 static const u8 rtw8703b_pwrtrk_2gb_n[] = { 1825 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 1826 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 1827 }; 1828 1829 static const u8 rtw8703b_pwrtrk_2gb_p[] = { 1830 0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7, 1831 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15 1832 }; 1833 1834 static const u8 rtw8703b_pwrtrk_2ga_n[] = { 1835 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 1836 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 1837 }; 1838 1839 static const u8 rtw8703b_pwrtrk_2ga_p[] = { 1840 0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7, 1841 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15 1842 }; 1843 1844 static const u8 rtw8703b_pwrtrk_2g_cck_b_n[] = { 1845 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 1846 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 1847 }; 1848 1849 static const u8 rtw8703b_pwrtrk_2g_cck_b_p[] = { 1850 0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 1851 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13 1852 }; 1853 1854 static const u8 rtw8703b_pwrtrk_2g_cck_a_n[] = { 1855 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 1856 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 1857 }; 1858 1859 static const u8 rtw8703b_pwrtrk_2g_cck_a_p[] = { 1860 0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 1861 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13 1862 }; 1863 1864 static const s8 rtw8703b_pwrtrk_xtal_n[] = { 1865 0, 0, 0, -1, -1, -1, -1, -2, -2, -2, -3, -3, -3, -3, -3, 1866 -4, -2, -2, -1, -1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1 1867 }; 1868 1869 static const s8 rtw8703b_pwrtrk_xtal_p[] = { 1870 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 1, 0, -1, -1, -1, 1871 -2, -3, -7, -9, -10, -11, -14, -16, -18, -20, -22, -24, -26, -28, -30 1872 }; 1873 1874 static const struct rtw_pwr_track_tbl rtw8703b_rtw_pwr_track_tbl = { 1875 .pwrtrk_2gb_n = rtw8703b_pwrtrk_2gb_n, 1876 .pwrtrk_2gb_p = rtw8703b_pwrtrk_2gb_p, 1877 .pwrtrk_2ga_n = rtw8703b_pwrtrk_2ga_n, 1878 .pwrtrk_2ga_p = rtw8703b_pwrtrk_2ga_p, 1879 .pwrtrk_2g_cckb_n = rtw8703b_pwrtrk_2g_cck_b_n, 1880 .pwrtrk_2g_cckb_p = rtw8703b_pwrtrk_2g_cck_b_p, 1881 .pwrtrk_2g_ccka_n = rtw8703b_pwrtrk_2g_cck_a_n, 1882 .pwrtrk_2g_ccka_p = rtw8703b_pwrtrk_2g_cck_a_p, 1883 .pwrtrk_xtal_n = rtw8703b_pwrtrk_xtal_n, 1884 .pwrtrk_xtal_p = rtw8703b_pwrtrk_xtal_p, 1885 }; 1886 1887 /* Shared-Antenna Coex Table */ 1888 static const struct coex_table_para table_sant_8703b[] = { 1889 {0xffffffff, 0xffffffff}, /* case-0 */ 1890 {0x55555555, 0x55555555}, 1891 {0x66555555, 0x66555555}, 1892 {0xaaaaaaaa, 0xaaaaaaaa}, 1893 {0x5a5a5a5a, 0x5a5a5a5a}, 1894 {0xfafafafa, 0xfafafafa}, /* case-5 */ 1895 {0x6a5a5555, 0xaaaaaaaa}, 1896 {0x6a5a56aa, 0x6a5a56aa}, 1897 {0x6a5a5a5a, 0x6a5a5a5a}, 1898 {0x66555555, 0x5a5a5a5a}, 1899 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 1900 {0x66555555, 0x6a5a5aaa}, 1901 {0x66555555, 0x5a5a5aaa}, 1902 {0x66555555, 0x6aaa5aaa}, 1903 {0x66555555, 0xaaaa5aaa}, 1904 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 1905 {0xffff55ff, 0xfafafafa}, 1906 {0xffff55ff, 0x6afa5afa}, 1907 {0xaaffffaa, 0xfafafafa}, 1908 {0xaa5555aa, 0x5a5a5a5a}, 1909 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 1910 {0xaa5555aa, 0xaaaaaaaa}, 1911 {0xffffffff, 0x5a5a5a5a}, 1912 {0xffffffff, 0x5a5a5a5a}, 1913 {0xffffffff, 0x55555555}, 1914 {0xffffffff, 0x5a5a5aaa}, /* case-25 */ 1915 {0x55555555, 0x5a5a5a5a}, 1916 {0x55555555, 0xaaaaaaaa}, 1917 {0x55555555, 0x6a5a6a5a}, 1918 {0x66556655, 0x66556655}, 1919 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */ 1920 {0xffffffff, 0x5aaa5aaa}, 1921 {0x56555555, 0x5a5a5aaa}, 1922 }; 1923 1924 /* Shared-Antenna TDMA */ 1925 static const struct coex_tdma_para tdma_sant_8703b[] = { 1926 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 1927 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */ 1928 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 1929 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 1930 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1931 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ 1932 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1933 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 1934 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1935 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1936 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 1937 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 1938 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1939 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1940 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1941 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 1942 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1943 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 1944 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1945 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 1946 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 1947 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 1948 { {0x51, 0x0c, 0x03, 0x10, 0x54} }, 1949 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 1950 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 1951 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 1952 { {0x51, 0x08, 0x03, 0x10, 0x50} }, 1953 { {0x61, 0x08, 0x03, 0x11, 0x11} }, 1954 }; 1955 1956 static struct rtw_chip_ops rtw8703b_ops = { 1957 .mac_init = rtw8723x_mac_init, 1958 .dump_fw_crash = NULL, 1959 .shutdown = NULL, 1960 .read_efuse = rtw8703b_read_efuse, 1961 .phy_set_param = rtw8703b_phy_set_param, 1962 .set_channel = rtw8703b_set_channel, 1963 .query_rx_desc = rtw8703b_query_rx_desc, 1964 .read_rf = rtw_phy_read_rf_sipi, 1965 .write_rf = rtw_phy_write_rf_reg_sipi, 1966 .set_tx_power_index = rtw8723x_set_tx_power_index, 1967 .set_antenna = NULL, 1968 .cfg_ldo25 = rtw8723x_cfg_ldo25, 1969 .efuse_grant = rtw8723x_efuse_grant, 1970 .false_alarm_statistics = rtw8723x_false_alarm_statistics, 1971 .phy_calibration = rtw8703b_phy_calibration, 1972 .dpk_track = NULL, 1973 /* 8723d uses REG_CSRATIO to set dm_info.cck_pd_default, which 1974 * is used in its cck_pd_set function. According to comments 1975 * in the vendor driver code it doesn't exist in this chip 1976 * generation, only 0xa0a ("ODM_CCK_PD_THRESH", which is only 1977 * *written* to). 1978 */ 1979 .cck_pd_set = NULL, 1980 .pwr_track = rtw8703b_pwr_track, 1981 .config_bfee = NULL, 1982 .set_gid_table = NULL, 1983 .cfg_csi_rate = NULL, 1984 .adaptivity_init = NULL, 1985 .adaptivity = NULL, 1986 .cfo_init = NULL, 1987 .cfo_track = NULL, 1988 .config_tx_path = NULL, 1989 .config_txrx_mode = NULL, 1990 .fill_txdesc_checksum = rtw8723x_fill_txdesc_checksum, 1991 1992 /* for coex */ 1993 .coex_set_init = rtw8723x_coex_cfg_init, 1994 .coex_set_ant_switch = NULL, 1995 .coex_set_gnt_fix = rtw8703b_coex_set_gnt_fix, 1996 .coex_set_gnt_debug = rtw8703b_coex_set_gnt_debug, 1997 .coex_set_rfe_type = rtw8703b_coex_set_rfe_type, 1998 .coex_set_wl_tx_power = rtw8703b_coex_set_wl_tx_power, 1999 .coex_set_wl_rx_gain = rtw8703b_coex_set_wl_rx_gain, 2000 }; 2001 2002 const struct rtw_chip_info rtw8703b_hw_spec = { 2003 .ops = &rtw8703b_ops, 2004 .id = RTW_CHIP_TYPE_8703B, 2005 2006 .fw_name = "rtw88/rtw8703b_fw.bin", 2007 .wlan_cpu = RTW_WCPU_11N, 2008 .tx_pkt_desc_sz = 40, 2009 .tx_buf_desc_sz = 16, 2010 .rx_pkt_desc_sz = 24, 2011 .rx_buf_desc_sz = 8, 2012 .phy_efuse_size = 256, 2013 .log_efuse_size = 512, 2014 .ptct_efuse_size = 15, 2015 .txff_size = 32768, 2016 .rxff_size = 16384, 2017 .rsvd_drv_pg_num = 8, 2018 .band = RTW_BAND_2G, 2019 .page_size = TX_PAGE_SIZE, 2020 .csi_buf_pg_num = 0, 2021 .dig_min = 0x20, 2022 .txgi_factor = 1, 2023 .is_pwr_by_rate_dec = true, 2024 .rx_ldpc = false, 2025 .tx_stbc = false, 2026 .max_power_index = 0x3f, 2027 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16, 2028 .usb_tx_agg_desc_num = 1, /* Not sure if this chip has USB interface */ 2029 2030 .path_div_supported = false, 2031 .ht_supported = true, 2032 .vht_supported = false, 2033 .lps_deep_mode_supported = 0, 2034 2035 .sys_func_en = 0xFD, 2036 .pwr_on_seq = card_enable_flow_8703b, 2037 .pwr_off_seq = card_disable_flow_8703b, 2038 .rqpn_table = rqpn_table_8703b, 2039 .prioq_addrs = &rtw8723x_common.prioq_addrs, 2040 .page_table = page_table_8703b, 2041 /* used only in pci.c, not needed for SDIO devices */ 2042 .intf_table = NULL, 2043 2044 .dig = rtw8723x_common.dig, 2045 .dig_cck = rtw8723x_common.dig_cck, 2046 2047 .rf_sipi_addr = {0x840, 0x844}, 2048 .rf_sipi_read_addr = rtw8723x_common.rf_sipi_addr, 2049 .fix_rf_phy_num = 2, 2050 .ltecoex_addr = &rtw8723x_common.ltecoex_addr, 2051 2052 .mac_tbl = &rtw8703b_mac_tbl, 2053 .agc_tbl = &rtw8703b_agc_tbl, 2054 .bb_tbl = &rtw8703b_bb_tbl, 2055 .rf_tbl = {&rtw8703b_rf_a_tbl}, 2056 2057 .rfe_defs = rtw8703b_rfe_defs, 2058 .rfe_defs_size = ARRAY_SIZE(rtw8703b_rfe_defs), 2059 2060 .iqk_threshold = 8, 2061 .pwr_track_tbl = &rtw8703b_rtw_pwr_track_tbl, 2062 2063 /* WOWLAN firmware exists, but not implemented yet */ 2064 .wow_fw_name = "rtw88/rtw8703b_wow_fw.bin", 2065 .wowlan_stub = NULL, 2066 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN, 2067 2068 /* Vendor driver has a time-based format, converted from 2069 * 20180330 2070 */ 2071 .coex_para_ver = 0x0133ed6a, 2072 .bt_desired_ver = 0x1c, 2073 .scbd_support = true, 2074 .new_scbd10_def = true, 2075 .ble_hid_profile_support = false, 2076 .wl_mimo_ps_support = false, 2077 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 2078 .bt_rssi_type = COEX_BTRSSI_RATIO, 2079 .ant_isolation = 15, 2080 .rssi_tolerance = 2, 2081 .bt_rssi_step = bt_rssi_step_8703b, 2082 .wl_rssi_step = wl_rssi_step_8703b, 2083 /* sant -> shared antenna, nsant -> non-shared antenna 2084 * Not sure if 8703b versions with non-shard antenna even exist. 2085 */ 2086 .table_sant_num = ARRAY_SIZE(table_sant_8703b), 2087 .table_sant = table_sant_8703b, 2088 .table_nsant_num = 0, 2089 .table_nsant = NULL, 2090 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8703b), 2091 .tdma_sant = tdma_sant_8703b, 2092 .tdma_nsant_num = 0, 2093 .tdma_nsant = NULL, 2094 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8703b), 2095 .wl_rf_para_tx = rf_para_tx_8703b, 2096 .wl_rf_para_rx = rf_para_rx_8703b, 2097 .bt_afh_span_bw20 = 0x20, 2098 .bt_afh_span_bw40 = 0x30, 2099 .afh_5g_num = ARRAY_SIZE(afh_5g_8703b), 2100 .afh_5g = afh_5g_8703b, 2101 /* REG_BTG_SEL doesn't seem to have a counterpart in the 2102 * vendor driver. Mathematically it's REG_PAD_CTRL1 + 3. 2103 * 2104 * It is used in the cardemu_to_act power sequence by though 2105 * (by address, 0x0067), comment: "0x67[0] = 0 to disable 2106 * BT_GPS_SEL pins" That seems to fit. 2107 */ 2108 .btg_reg = NULL, 2109 /* These registers are used to read (and print) from if 2110 * CONFIG_RTW88_DEBUGFS is enabled. 2111 */ 2112 .coex_info_hw_regs_num = 0, 2113 .coex_info_hw_regs = NULL, 2114 }; 2115 EXPORT_SYMBOL(rtw8703b_hw_spec); 2116 2117 MODULE_FIRMWARE("rtw88/rtw8703b_fw.bin"); 2118 MODULE_FIRMWARE("rtw88/rtw8703b_wow_fw.bin"); 2119 2120 MODULE_AUTHOR("Fiona Klute <fiona.klute@gmx.de>"); 2121 MODULE_DESCRIPTION("Realtek 802.11n wireless 8703b driver"); 2122 MODULE_LICENSE("Dual BSD/GPL"); 2123