1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright Fiona Klute <fiona.klute@gmx.de> */ 3 4 #include <linux/of_net.h> 5 #include "main.h" 6 #include "coex.h" 7 #include "debug.h" 8 #include "mac.h" 9 #include "phy.h" 10 #include "reg.h" 11 #include "rx.h" 12 #include "rtw8703b.h" 13 #include "rtw8703b_tables.h" 14 #include "rtw8723x.h" 15 16 #define BIT_MASK_TXQ_INIT (BIT(7)) 17 #define WLAN_RL_VAL 0x3030 18 /* disable BAR */ 19 #define WLAN_BAR_VAL 0x0201ffff 20 #define WLAN_PIFS_VAL 0 21 #define WLAN_RX_PKT_LIMIT 0x18 22 #define WLAN_SLOT_TIME 0x09 23 #define WLAN_SPEC_SIFS 0x100a 24 #define WLAN_MAX_AGG_NR 0x1f 25 #define WLAN_AMPDU_MAX_TIME 0x70 26 27 /* unit is 32us */ 28 #define TBTT_PROHIBIT_SETUP_TIME 0x04 29 #define TBTT_PROHIBIT_HOLD_TIME 0x80 30 #define TBTT_PROHIBIT_HOLD_TIME_STOP_BCN 0x64 31 32 #define TRANS_SEQ_END \ 33 0xFFFF, \ 34 RTW_PWR_CUT_ALL_MSK, \ 35 RTW_PWR_INTF_ALL_MSK, \ 36 0, \ 37 RTW_PWR_CMD_END, 0, 0 38 39 /* rssi in percentage % (dbm = % - 100) */ 40 /* These are used to select simple signal quality levels, might need 41 * tweaking. Same for rf_para tables below. 42 */ 43 static const u8 wl_rssi_step_8703b[] = {60, 50, 44, 30}; 44 static const u8 bt_rssi_step_8703b[] = {30, 30, 30, 30}; 45 static const struct coex_5g_afh_map afh_5g_8703b[] = { {0, 0, 0} }; 46 47 /* Actually decreasing wifi TX power/RX gain isn't implemented in 48 * rtw8703b, but hopefully adjusting the BT side helps. 49 */ 50 static const struct coex_rf_para rf_para_tx_8703b[] = { 51 {0, 0, false, 7}, /* for normal */ 52 {0, 10, false, 7}, /* for WL-CPT */ 53 {1, 0, true, 4}, 54 {1, 2, true, 4}, 55 {1, 10, true, 4}, 56 {1, 15, true, 4} 57 }; 58 59 static const struct coex_rf_para rf_para_rx_8703b[] = { 60 {0, 0, false, 7}, /* for normal */ 61 {0, 10, false, 7}, /* for WL-CPT */ 62 {1, 0, true, 5}, 63 {1, 2, true, 5}, 64 {1, 10, true, 5}, 65 {1, 15, true, 5} 66 }; 67 68 static const u32 rtw8703b_ofdm_swing_table[] = { 69 0x0b40002d, /* 0, -15.0dB */ 70 0x0c000030, /* 1, -14.5dB */ 71 0x0cc00033, /* 2, -14.0dB */ 72 0x0d800036, /* 3, -13.5dB */ 73 0x0e400039, /* 4, -13.0dB */ 74 0x0f00003c, /* 5, -12.5dB */ 75 0x10000040, /* 6, -12.0dB */ 76 0x11000044, /* 7, -11.5dB */ 77 0x12000048, /* 8, -11.0dB */ 78 0x1300004c, /* 9, -10.5dB */ 79 0x14400051, /* 10, -10.0dB */ 80 0x15800056, /* 11, -9.5dB */ 81 0x16c0005b, /* 12, -9.0dB */ 82 0x18000060, /* 13, -8.5dB */ 83 0x19800066, /* 14, -8.0dB */ 84 0x1b00006c, /* 15, -7.5dB */ 85 0x1c800072, /* 16, -7.0dB */ 86 0x1e400079, /* 17, -6.5dB */ 87 0x20000080, /* 18, -6.0dB */ 88 0x22000088, /* 19, -5.5dB */ 89 0x24000090, /* 20, -5.0dB */ 90 0x26000098, /* 21, -4.5dB */ 91 0x288000a2, /* 22, -4.0dB */ 92 0x2ac000ab, /* 23, -3.5dB */ 93 0x2d4000b5, /* 24, -3.0dB */ 94 0x300000c0, /* 25, -2.5dB */ 95 0x32c000cb, /* 26, -2.0dB */ 96 0x35c000d7, /* 27, -1.5dB */ 97 0x390000e4, /* 28, -1.0dB */ 98 0x3c8000f2, /* 29, -0.5dB */ 99 0x40000100, /* 30, +0dB */ 100 0x43c0010f, /* 31, +0.5dB */ 101 0x47c0011f, /* 32, +1.0dB */ 102 0x4c000130, /* 33, +1.5dB */ 103 0x50800142, /* 34, +2.0dB */ 104 0x55400155, /* 35, +2.5dB */ 105 0x5a400169, /* 36, +3.0dB */ 106 0x5fc0017f, /* 37, +3.5dB */ 107 0x65400195, /* 38, +4.0dB */ 108 0x6b8001ae, /* 39, +4.5dB */ 109 0x71c001c7, /* 40, +5.0dB */ 110 0x788001e2, /* 41, +5.5dB */ 111 0x7f8001fe /* 42, +6.0dB */ 112 }; 113 114 static const u32 rtw8703b_cck_pwr_regs[] = { 115 0x0a22, 0x0a23, 0x0a24, 0x0a25, 0x0a26, 0x0a27, 0x0a28, 0x0a29, 116 0x0a9a, 0x0a9b, 0x0a9c, 0x0a9d, 0x0aa0, 0x0aa1, 0x0aa2, 0x0aa3, 117 }; 118 119 static const u8 rtw8703b_cck_swing_table[][16] = { 120 {0x44, 0x42, 0x3C, 0x33, 0x28, 0x1C, 0x13, 0x0B, 0x05, 0x02, 121 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-16dB*/ 122 {0x48, 0x46, 0x3F, 0x36, 0x2A, 0x1E, 0x14, 0x0B, 0x05, 0x02, 123 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15.5dB*/ 124 {0x4D, 0x4A, 0x43, 0x39, 0x2C, 0x20, 0x15, 0x0C, 0x06, 0x02, 125 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-15dB*/ 126 {0x51, 0x4F, 0x47, 0x3C, 0x2F, 0x22, 0x16, 0x0D, 0x06, 0x02, 127 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14.5dB*/ 128 {0x56, 0x53, 0x4B, 0x40, 0x32, 0x24, 0x17, 0x0E, 0x06, 0x02, 129 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-14dB*/ 130 {0x5B, 0x58, 0x50, 0x43, 0x35, 0x26, 0x19, 0x0E, 0x07, 0x02, 131 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13.5dB*/ 132 {0x60, 0x5D, 0x54, 0x47, 0x38, 0x28, 0x1A, 0x0F, 0x07, 0x02, 133 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-13dB*/ 134 {0x66, 0x63, 0x59, 0x4C, 0x3B, 0x2B, 0x1C, 0x10, 0x08, 0x02, 135 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12.5dB*/ 136 {0x6C, 0x69, 0x5F, 0x50, 0x3F, 0x2D, 0x1E, 0x11, 0x08, 0x03, 137 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-12dB*/ 138 {0x73, 0x6F, 0x64, 0x55, 0x42, 0x30, 0x1F, 0x12, 0x08, 0x03, 139 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11.5dB*/ 140 {0x79, 0x76, 0x6A, 0x5A, 0x46, 0x33, 0x21, 0x13, 0x09, 0x03, 141 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-11dB*/ 142 {0x81, 0x7C, 0x71, 0x5F, 0x4A, 0x36, 0x23, 0x14, 0x0A, 0x03, 143 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10.5dB*/ 144 {0x88, 0x84, 0x77, 0x65, 0x4F, 0x39, 0x25, 0x15, 0x0A, 0x03, 145 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-10dB*/ 146 {0x90, 0x8C, 0x7E, 0x6B, 0x54, 0x3C, 0x27, 0x17, 0x0B, 0x03, 147 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9.5dB*/ 148 {0x99, 0x94, 0x86, 0x71, 0x58, 0x40, 0x2A, 0x18, 0x0B, 0x04, 149 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-9dB*/ 150 {0xA2, 0x9D, 0x8E, 0x78, 0x5E, 0x43, 0x2C, 0x19, 0x0C, 0x04, 151 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8.5dB*/ 152 {0xAC, 0xA6, 0x96, 0x7F, 0x63, 0x47, 0x2F, 0x1B, 0x0D, 0x04, 153 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-8dB*/ 154 {0xB6, 0xB0, 0x9F, 0x87, 0x69, 0x4C, 0x32, 0x1D, 0x0D, 0x04, 155 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7.5dB*/ 156 {0xC1, 0xBA, 0xA8, 0x8F, 0x6F, 0x50, 0x35, 0x1E, 0x0E, 0x04, 157 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-7dB*/ 158 {0xCC, 0xC5, 0xB2, 0x97, 0x76, 0x55, 0x38, 0x20, 0x0F, 0x05, 159 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /*-6.5dB*/ 160 {0xD8, 0xD1, 0xBD, 0xA0, 0x7D, 0x5A, 0x3B, 0x22, 0x10, 0x05, 161 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /*-6dB*/ 162 }; 163 164 #define RTW_OFDM_SWING_TABLE_SIZE ARRAY_SIZE(rtw8703b_ofdm_swing_table) 165 #define RTW_CCK_SWING_TABLE_SIZE ARRAY_SIZE(rtw8703b_cck_swing_table) 166 167 static const struct rtw_pwr_seq_cmd trans_pre_enable_8703b[] = { 168 /* set up external crystal (XTAL) */ 169 {REG_PAD_CTRL1 + 2, 170 RTW_PWR_CUT_ALL_MSK, 171 RTW_PWR_INTF_ALL_MSK, 172 RTW_PWR_ADDR_MAC, 173 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 174 /* set CLK_REQ to high active */ 175 {0x0069, 176 RTW_PWR_CUT_ALL_MSK, 177 RTW_PWR_INTF_ALL_MSK, 178 RTW_PWR_ADDR_MAC, 179 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 180 /* unlock ISO/CLK/power control register */ 181 {REG_RSV_CTRL, 182 RTW_PWR_CUT_ALL_MSK, 183 RTW_PWR_INTF_ALL_MSK, 184 RTW_PWR_ADDR_MAC, 185 RTW_PWR_CMD_WRITE, 0xff, 0}, 186 {TRANS_SEQ_END}, 187 }; 188 189 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8703b[] = { 190 {0x0005, 191 RTW_PWR_CUT_ALL_MSK, 192 RTW_PWR_INTF_ALL_MSK, 193 RTW_PWR_ADDR_MAC, 194 RTW_PWR_CMD_WRITE, BIT(7), 0}, 195 {TRANS_SEQ_END}, 196 }; 197 198 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8703b[] = { 199 {0x0023, 200 RTW_PWR_CUT_ALL_MSK, 201 RTW_PWR_INTF_SDIO_MSK, 202 RTW_PWR_ADDR_MAC, 203 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 204 {0x0007, 205 RTW_PWR_CUT_ALL_MSK, 206 RTW_PWR_INTF_SDIO_MSK | RTW_PWR_INTF_USB_MSK, 207 RTW_PWR_ADDR_MAC, 208 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 209 {0x0006, 210 RTW_PWR_CUT_ALL_MSK, 211 RTW_PWR_INTF_ALL_MSK, 212 RTW_PWR_ADDR_MAC, 213 RTW_PWR_CMD_WRITE, BIT(0), 0}, 214 {0x0005, 215 RTW_PWR_CUT_ALL_MSK, 216 RTW_PWR_INTF_ALL_MSK, 217 RTW_PWR_ADDR_MAC, 218 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 219 {TRANS_SEQ_END}, 220 }; 221 222 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8703b[] = { 223 {0x0020, 224 RTW_PWR_CUT_ALL_MSK, 225 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 226 RTW_PWR_ADDR_MAC, 227 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 228 {0x0067, 229 RTW_PWR_CUT_ALL_MSK, 230 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 231 RTW_PWR_ADDR_MAC, 232 RTW_PWR_CMD_WRITE, BIT(4), 0}, 233 {0x0001, 234 RTW_PWR_CUT_ALL_MSK, 235 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 236 RTW_PWR_ADDR_MAC, 237 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 238 {0x0000, 239 RTW_PWR_CUT_ALL_MSK, 240 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 241 RTW_PWR_ADDR_MAC, 242 RTW_PWR_CMD_WRITE, BIT(5), 0}, 243 {0x0005, 244 RTW_PWR_CUT_ALL_MSK, 245 RTW_PWR_INTF_ALL_MSK, 246 RTW_PWR_ADDR_MAC, 247 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 248 {0x0075, 249 RTW_PWR_CUT_ALL_MSK, 250 RTW_PWR_INTF_PCI_MSK, 251 RTW_PWR_ADDR_MAC, 252 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 253 {0x0004, 254 RTW_PWR_CUT_ALL_MSK, 255 RTW_PWR_INTF_PCI_MSK, 256 RTW_PWR_ADDR_MAC, 257 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 258 {0x0004, 259 RTW_PWR_CUT_ALL_MSK, 260 RTW_PWR_INTF_PCI_MSK, 261 RTW_PWR_ADDR_MAC, 262 RTW_PWR_CMD_WRITE, BIT(3), 0}, 263 /* wait for power ready */ 264 {0x0006, 265 RTW_PWR_CUT_ALL_MSK, 266 RTW_PWR_INTF_ALL_MSK, 267 RTW_PWR_ADDR_MAC, 268 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 269 {0x0075, 270 RTW_PWR_CUT_ALL_MSK, 271 RTW_PWR_INTF_PCI_MSK, 272 RTW_PWR_ADDR_MAC, 273 RTW_PWR_CMD_WRITE, BIT(0), 0}, 274 {0x0006, 275 RTW_PWR_CUT_ALL_MSK, 276 RTW_PWR_INTF_ALL_MSK, 277 RTW_PWR_ADDR_MAC, 278 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 279 {0x0005, 280 RTW_PWR_CUT_ALL_MSK, 281 RTW_PWR_INTF_ALL_MSK, 282 RTW_PWR_ADDR_MAC, 283 RTW_PWR_CMD_WRITE, BIT(7), 0}, 284 {0x0005, 285 RTW_PWR_CUT_ALL_MSK, 286 RTW_PWR_INTF_ALL_MSK, 287 RTW_PWR_ADDR_MAC, 288 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 289 {0x0005, 290 RTW_PWR_CUT_ALL_MSK, 291 RTW_PWR_INTF_ALL_MSK, 292 RTW_PWR_ADDR_MAC, 293 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 294 {0x0005, 295 RTW_PWR_CUT_ALL_MSK, 296 RTW_PWR_INTF_ALL_MSK, 297 RTW_PWR_ADDR_MAC, 298 RTW_PWR_CMD_POLLING, BIT(0), 0}, 299 {0x0010, 300 RTW_PWR_CUT_ALL_MSK, 301 RTW_PWR_INTF_ALL_MSK, 302 RTW_PWR_ADDR_MAC, 303 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 304 {0x0049, 305 RTW_PWR_CUT_ALL_MSK, 306 RTW_PWR_INTF_ALL_MSK, 307 RTW_PWR_ADDR_MAC, 308 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 309 {0x0063, 310 RTW_PWR_CUT_ALL_MSK, 311 RTW_PWR_INTF_ALL_MSK, 312 RTW_PWR_ADDR_MAC, 313 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 314 {0x0062, 315 RTW_PWR_CUT_ALL_MSK, 316 RTW_PWR_INTF_ALL_MSK, 317 RTW_PWR_ADDR_MAC, 318 RTW_PWR_CMD_WRITE, BIT(1), 0}, 319 {0x0058, 320 RTW_PWR_CUT_ALL_MSK, 321 RTW_PWR_INTF_ALL_MSK, 322 RTW_PWR_ADDR_MAC, 323 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 324 {0x005A, 325 RTW_PWR_CUT_ALL_MSK, 326 RTW_PWR_INTF_ALL_MSK, 327 RTW_PWR_ADDR_MAC, 328 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 329 {0x0068, 330 RTW_PWR_CUT_TEST_MSK, 331 RTW_PWR_INTF_ALL_MSK, 332 RTW_PWR_ADDR_MAC, 333 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 334 {0x0069, 335 RTW_PWR_CUT_ALL_MSK, 336 RTW_PWR_INTF_ALL_MSK, 337 RTW_PWR_ADDR_MAC, 338 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 339 {TRANS_SEQ_END}, 340 }; 341 342 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8703b[] = { 343 {0x001f, 344 RTW_PWR_CUT_ALL_MSK, 345 RTW_PWR_INTF_ALL_MSK, 346 RTW_PWR_ADDR_MAC, 347 RTW_PWR_CMD_WRITE, 0xff, 0}, 348 {0x0049, 349 RTW_PWR_CUT_ALL_MSK, 350 RTW_PWR_INTF_ALL_MSK, 351 RTW_PWR_ADDR_MAC, 352 RTW_PWR_CMD_WRITE, BIT(1), 0}, 353 {0x0006, 354 RTW_PWR_CUT_ALL_MSK, 355 RTW_PWR_INTF_ALL_MSK, 356 RTW_PWR_ADDR_MAC, 357 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 358 {0x0005, 359 RTW_PWR_CUT_ALL_MSK, 360 RTW_PWR_INTF_ALL_MSK, 361 RTW_PWR_ADDR_MAC, 362 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 363 {0x0005, 364 RTW_PWR_CUT_ALL_MSK, 365 RTW_PWR_INTF_ALL_MSK, 366 RTW_PWR_ADDR_MAC, 367 RTW_PWR_CMD_POLLING, BIT(1), 0}, 368 {0x0010, 369 RTW_PWR_CUT_ALL_MSK, 370 RTW_PWR_INTF_ALL_MSK, 371 RTW_PWR_ADDR_MAC, 372 RTW_PWR_CMD_WRITE, BIT(6), 0}, 373 {0x0000, 374 RTW_PWR_CUT_ALL_MSK, 375 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 376 RTW_PWR_ADDR_MAC, 377 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 378 {0x0020, 379 RTW_PWR_CUT_ALL_MSK, 380 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 381 RTW_PWR_ADDR_MAC, 382 RTW_PWR_CMD_WRITE, BIT(0), 0}, 383 {TRANS_SEQ_END}, 384 }; 385 386 static const struct rtw_pwr_seq_cmd trans_act_to_reset_mcu_8703b[] = { 387 {REG_SYS_FUNC_EN + 1, 388 RTW_PWR_CUT_ALL_MSK, 389 RTW_PWR_INTF_SDIO_MSK, 390 RTW_PWR_ADDR_MAC, 391 RTW_PWR_CMD_WRITE, BIT_FEN_CPUEN, 0}, 392 /* reset MCU ready */ 393 {REG_MCUFW_CTRL, 394 RTW_PWR_CUT_ALL_MSK, 395 RTW_PWR_INTF_SDIO_MSK, 396 RTW_PWR_ADDR_MAC, 397 RTW_PWR_CMD_WRITE, 0xff, 0}, 398 /* reset MCU IO wrapper */ 399 {REG_RSV_CTRL + 1, 400 RTW_PWR_CUT_ALL_MSK, 401 RTW_PWR_INTF_SDIO_MSK, 402 RTW_PWR_ADDR_MAC, 403 RTW_PWR_CMD_WRITE, BIT(0), 0}, 404 {REG_RSV_CTRL + 1, 405 RTW_PWR_CUT_ALL_MSK, 406 RTW_PWR_INTF_SDIO_MSK, 407 RTW_PWR_ADDR_MAC, 408 RTW_PWR_CMD_WRITE, BIT(0), 1}, 409 {TRANS_SEQ_END}, 410 }; 411 412 static const struct rtw_pwr_seq_cmd trans_act_to_lps_8703b[] = { 413 {0x0301, 414 RTW_PWR_CUT_ALL_MSK, 415 RTW_PWR_INTF_ALL_MSK, 416 RTW_PWR_ADDR_MAC, 417 RTW_PWR_CMD_WRITE, 0xff, 0xff}, 418 {0x0522, 419 RTW_PWR_CUT_ALL_MSK, 420 RTW_PWR_INTF_ALL_MSK, 421 RTW_PWR_ADDR_MAC, 422 RTW_PWR_CMD_WRITE, 0xff, 0xff}, 423 {0x05f8, 424 RTW_PWR_CUT_ALL_MSK, 425 RTW_PWR_INTF_ALL_MSK, 426 RTW_PWR_ADDR_MAC, 427 RTW_PWR_CMD_POLLING, 0xff, 0}, 428 {0x05f9, 429 RTW_PWR_CUT_ALL_MSK, 430 RTW_PWR_INTF_ALL_MSK, 431 RTW_PWR_ADDR_MAC, 432 RTW_PWR_CMD_POLLING, 0xff, 0}, 433 {0x05fa, 434 RTW_PWR_CUT_ALL_MSK, 435 RTW_PWR_INTF_ALL_MSK, 436 RTW_PWR_ADDR_MAC, 437 RTW_PWR_CMD_POLLING, 0xff, 0}, 438 {0x05fb, 439 RTW_PWR_CUT_ALL_MSK, 440 RTW_PWR_INTF_ALL_MSK, 441 RTW_PWR_ADDR_MAC, 442 RTW_PWR_CMD_POLLING, 0xff, 0}, 443 {0x0002, 444 RTW_PWR_CUT_ALL_MSK, 445 RTW_PWR_INTF_ALL_MSK, 446 RTW_PWR_ADDR_MAC, 447 RTW_PWR_CMD_WRITE, BIT(0), 0}, 448 {0x0002, 449 RTW_PWR_CUT_ALL_MSK, 450 RTW_PWR_INTF_ALL_MSK, 451 RTW_PWR_ADDR_MAC, 452 RTW_PWR_CMD_DELAY, 0, RTW_PWR_DELAY_US}, 453 {0x0002, 454 RTW_PWR_CUT_ALL_MSK, 455 RTW_PWR_INTF_ALL_MSK, 456 RTW_PWR_ADDR_MAC, 457 RTW_PWR_CMD_WRITE, BIT(1), 0}, 458 {0x0100, 459 RTW_PWR_CUT_ALL_MSK, 460 RTW_PWR_INTF_ALL_MSK, 461 RTW_PWR_ADDR_MAC, 462 RTW_PWR_CMD_WRITE, 0xff, 0x03}, 463 {0x0101, 464 RTW_PWR_CUT_ALL_MSK, 465 RTW_PWR_INTF_ALL_MSK, 466 RTW_PWR_ADDR_MAC, 467 RTW_PWR_CMD_WRITE, BIT(1), 0}, 468 {0x0093, 469 RTW_PWR_CUT_ALL_MSK, 470 RTW_PWR_INTF_SDIO_MSK, 471 RTW_PWR_ADDR_MAC, 472 RTW_PWR_CMD_WRITE, 0xff, 0}, 473 {0x0553, 474 RTW_PWR_CUT_ALL_MSK, 475 RTW_PWR_INTF_ALL_MSK, 476 RTW_PWR_ADDR_MAC, 477 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 478 {TRANS_SEQ_END}, 479 }; 480 481 static const struct rtw_pwr_seq_cmd * const card_enable_flow_8703b[] = { 482 trans_pre_enable_8703b, 483 trans_carddis_to_cardemu_8703b, 484 trans_cardemu_to_act_8703b, 485 NULL 486 }; 487 488 static const struct rtw_pwr_seq_cmd * const card_disable_flow_8703b[] = { 489 trans_act_to_lps_8703b, 490 trans_act_to_reset_mcu_8703b, 491 trans_act_to_cardemu_8703b, 492 trans_cardemu_to_carddis_8703b, 493 NULL 494 }; 495 496 static const struct rtw_page_table page_table_8703b[] = { 497 {12, 2, 2, 0, 1}, 498 {12, 2, 2, 0, 1}, 499 {12, 2, 2, 0, 1}, 500 {12, 2, 2, 0, 1}, 501 {12, 2, 2, 0, 1}, 502 }; 503 504 static const struct rtw_rqpn rqpn_table_8703b[] = { 505 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 506 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 507 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 508 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 509 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 510 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 511 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 512 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 513 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 514 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 515 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 516 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 517 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 518 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 519 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 520 }; 521 522 /* Default power index table for RTL8703B, used if EFUSE does not 523 * contain valid data. Replaces EFUSE data from offset 0x10 (start of 524 * txpwr_idx_table). 525 */ 526 static const u8 rtw8703b_txpwr_idx_table[] = { 527 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 528 0x2D, 0x2D, 0x2D, 0x2D, 0x2D, 0x02 529 }; 530 531 static void try_mac_from_devicetree(struct rtw_dev *rtwdev) 532 { 533 #if defined(CONFIG_OF) 534 struct device_node *node = rtwdev->dev->of_node; 535 struct rtw_efuse *efuse = &rtwdev->efuse; 536 int ret; 537 538 if (node) { 539 ret = of_get_mac_address(node, efuse->addr); 540 if (ret == 0) { 541 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 542 "got wifi mac address from DT: %pM\n", 543 efuse->addr); 544 } 545 } 546 #endif 547 } 548 549 #define DBG_EFUSE_FIX(rtwdev, name) \ 550 rtw_dbg(rtwdev, RTW_DBG_EFUSE, "Fixed invalid EFUSE value: " \ 551 # name "=0x%x\n", rtwdev->efuse.name) 552 553 static int rtw8703b_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 554 { 555 struct rtw_efuse *efuse = &rtwdev->efuse; 556 u8 *pwr = (u8 *)efuse->txpwr_idx_table; 557 bool valid = false; 558 int ret; 559 560 ret = rtw8723x_read_efuse(rtwdev, log_map); 561 if (ret != 0) 562 return ret; 563 564 if (!is_valid_ether_addr(efuse->addr)) 565 try_mac_from_devicetree(rtwdev); 566 567 /* If TX power index table in EFUSE is invalid, fall back to 568 * built-in table. 569 */ 570 for (int i = 0; i < ARRAY_SIZE(rtw8703b_txpwr_idx_table); i++) 571 if (pwr[i] != 0xff) { 572 valid = true; 573 break; 574 } 575 if (!valid) { 576 for (int i = 0; i < ARRAY_SIZE(rtw8703b_txpwr_idx_table); i++) 577 pwr[i] = rtw8703b_txpwr_idx_table[i]; 578 rtw_dbg(rtwdev, RTW_DBG_EFUSE, 579 "Replaced invalid EFUSE TX power index table."); 580 rtw8723x_debug_txpwr_limit(rtwdev, 581 efuse->txpwr_idx_table, 2); 582 } 583 584 /* Override invalid antenna settings. */ 585 if (efuse->bt_setting == 0xff) { 586 /* shared antenna */ 587 efuse->bt_setting |= BIT(0); 588 /* RF path A */ 589 efuse->bt_setting &= ~BIT(6); 590 DBG_EFUSE_FIX(rtwdev, bt_setting); 591 } 592 593 /* Override invalid board options: The coex code incorrectly 594 * assumes that if bits 6 & 7 are set the board doesn't 595 * support coex. Regd is also derived from rf_board_option and 596 * should be 0 if there's no valid data. 597 */ 598 if (efuse->rf_board_option == 0xff) { 599 efuse->regd = 0; 600 efuse->rf_board_option &= GENMASK(5, 0); 601 DBG_EFUSE_FIX(rtwdev, rf_board_option); 602 } 603 604 /* Override invalid crystal cap setting, default comes from 605 * vendor driver. Chip specific. 606 */ 607 if (efuse->crystal_cap == 0xff) { 608 efuse->crystal_cap = 0x20; 609 DBG_EFUSE_FIX(rtwdev, crystal_cap); 610 } 611 612 return 0; 613 } 614 615 static void rtw8703b_pwrtrack_init(struct rtw_dev *rtwdev) 616 { 617 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 618 u8 path; 619 620 /* TODO: The vendor driver selects these using tables in 621 * halrf_powertracking_ce.c, functions are called 622 * get_swing_index and get_cck_swing_index. There the current 623 * fixed values are only the defaults in case no match is 624 * found. 625 */ 626 dm_info->default_ofdm_index = 30; 627 dm_info->default_cck_index = 20; 628 629 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) { 630 ewma_thermal_init(&dm_info->avg_thermal[path]); 631 dm_info->delta_power_index[path] = 0; 632 } 633 dm_info->pwr_trk_triggered = false; 634 dm_info->pwr_trk_init_trigger = true; 635 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 636 dm_info->txagc_remnant_cck = 0; 637 dm_info->txagc_remnant_ofdm[RF_PATH_A] = 0; 638 } 639 640 static void rtw8703b_phy_set_param(struct rtw_dev *rtwdev) 641 { 642 u8 xtal_cap = rtwdev->efuse.crystal_cap & 0x3F; 643 644 /* power on BB/RF domain */ 645 rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, 646 BIT_FEN_EN_25_1 | BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB); 647 rtw_write8_set(rtwdev, REG_RF_CTRL, 648 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 649 rtw_write_rf(rtwdev, RF_PATH_A, RF_WLINT, RFREG_MASK, 0x0780); 650 rtw_write8(rtwdev, REG_AFE_CTRL1 + 1, 0x80); 651 652 rtw_phy_load_tables(rtwdev); 653 654 rtw_write32_clr(rtwdev, REG_RCR, BIT_RCR_ADF); 655 /* 0xff is from vendor driver, rtw8723d uses 656 * BIT_HIQ_NO_LMT_EN_ROOT. Comment in vendor driver: "Packet 657 * in Hi Queue Tx immediately". I wonder if setting all bits 658 * is really necessary. 659 */ 660 rtw_write8_set(rtwdev, REG_HIQ_NO_LMT_EN, 0xff); 661 rtw_write16_set(rtwdev, REG_AFE_CTRL_4, BIT_CK320M_AFE_EN | BIT_EN_SYN); 662 663 rtw_write32_mask(rtwdev, REG_AFE_CTRL3, BIT_MASK_XTAL, 664 xtal_cap | (xtal_cap << 6)); 665 rtw_write32_set(rtwdev, REG_FPGA0_RFMOD, BIT_CCKEN | BIT_OFDMEN); 666 667 /* Init EDCA */ 668 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SPEC_SIFS); 669 rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, WLAN_SPEC_SIFS); 670 rtw_write16(rtwdev, REG_SIFS, WLAN_SPEC_SIFS); /* CCK */ 671 rtw_write16(rtwdev, REG_SIFS + 2, WLAN_SPEC_SIFS); /* OFDM */ 672 /* TXOP */ 673 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, 0x002FA226); 674 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, 0x005EA324); 675 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, 0x005EA42B); 676 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, 0x0000A44F); 677 678 /* Init retry */ 679 rtw_write8(rtwdev, REG_ACKTO, 0x40); 680 681 /* Set up RX aggregation. sdio.c also sets DMA mode, but not 682 * the burst parameters. 683 */ 684 rtw_write8(rtwdev, REG_RXDMA_MODE, 685 BIT_DMA_MODE | 686 FIELD_PREP_CONST(BIT_MASK_AGG_BURST_NUM, AGG_BURST_NUM) | 687 FIELD_PREP_CONST(BIT_MASK_AGG_BURST_SIZE, AGG_BURST_SIZE)); 688 689 /* Init beacon parameters */ 690 rtw_write8(rtwdev, REG_BCN_CTRL, 691 BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION | BIT_EN_TXBCN_RPT); 692 rtw_write8(rtwdev, REG_TBTT_PROHIBIT, TBTT_PROHIBIT_SETUP_TIME); 693 rtw_write8(rtwdev, REG_TBTT_PROHIBIT + 1, 694 TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF); 695 rtw_write8(rtwdev, REG_TBTT_PROHIBIT + 2, 696 (rtw_read8(rtwdev, REG_TBTT_PROHIBIT + 2) & 0xF0) 697 | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8)); 698 699 /* configure packet burst */ 700 rtw_write8_set(rtwdev, REG_SINGLE_AMPDU_CTRL, BIT_EN_SINGLE_APMDU); 701 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RX_PKT_LIMIT); 702 rtw_write8(rtwdev, REG_MAX_AGGR_NUM, WLAN_MAX_AGG_NR); 703 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_VAL); 704 rtw_write8_clr(rtwdev, REG_FWHW_TXQ_CTRL, BIT_MASK_TXQ_INIT); 705 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME, WLAN_AMPDU_MAX_TIME); 706 707 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 708 rtw_write16(rtwdev, REG_RETRY_LIMIT, WLAN_RL_VAL); 709 rtw_write32(rtwdev, REG_BAR_MODE_CTRL, WLAN_BAR_VAL); 710 rtw_write16(rtwdev, REG_ATIMWND, 0x2); 711 712 rtw_phy_init(rtwdev); 713 714 if (rtw_read32_mask(rtwdev, REG_BB_AMP, BIT_MASK_RX_LNA) != 0) { 715 rtwdev->dm_info.rx_cck_agc_report_type = 1; 716 } else { 717 rtwdev->dm_info.rx_cck_agc_report_type = 0; 718 rtw_warn(rtwdev, "unexpected cck agc report type"); 719 } 720 721 rtw8723x_lck(rtwdev); 722 723 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x50); 724 rtw_write32_mask(rtwdev, REG_OFDM0_XAAGC1, MASKBYTE0, 0x20); 725 726 rtw8703b_pwrtrack_init(rtwdev); 727 } 728 729 static bool rtw8703b_check_spur_ov_thres(struct rtw_dev *rtwdev, 730 u32 freq, u32 thres) 731 { 732 bool ret = false; 733 734 rtw_write32(rtwdev, REG_ANALOG_P4, DIS_3WIRE); 735 rtw_write32(rtwdev, REG_PSDFN, freq); 736 rtw_write32(rtwdev, REG_PSDFN, START_PSD | freq); 737 738 msleep(30); 739 if (rtw_read32(rtwdev, REG_PSDRPT) >= thres) 740 ret = true; 741 742 rtw_write32(rtwdev, REG_PSDFN, freq); 743 rtw_write32(rtwdev, REG_ANALOG_P4, EN_3WIRE); 744 745 return ret; 746 } 747 748 static void rtw8703b_cfg_notch(struct rtw_dev *rtwdev, u8 channel, bool notch) 749 { 750 if (!notch) { 751 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x1f); 752 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); 753 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 754 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 755 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 756 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); 757 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); 758 return; 759 } 760 761 switch (channel) { 762 case 5: 763 fallthrough; 764 case 13: 765 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xb); 766 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 767 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x06000000); 768 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 769 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 770 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); 771 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 772 break; 773 case 6: 774 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x4); 775 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 776 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000600); 777 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 778 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 779 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000000); 780 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 781 break; 782 case 7: 783 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x3); 784 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 785 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 786 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 787 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 788 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x06000000); 789 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 790 break; 791 case 8: 792 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0xa); 793 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 794 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 795 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 796 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 797 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00000380); 798 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 799 break; 800 case 14: 801 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_MASK_RXDSP, 0x5); 802 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x1); 803 rtw_write32(rtwdev, REG_OFDM1_CSI1, 0x00000000); 804 rtw_write32(rtwdev, REG_OFDM1_CSI2, 0x00000000); 805 rtw_write32(rtwdev, REG_OFDM1_CSI3, 0x00000000); 806 rtw_write32(rtwdev, REG_OFDM1_CSI4, 0x00180000); 807 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x1); 808 break; 809 default: 810 rtw_warn(rtwdev, 811 "Bug: Notch filter enable called for channel %u!", 812 channel); 813 rtw_write32_mask(rtwdev, REG_OFDM0_RXDSP, BIT_EN_RXDSP, 0x0); 814 rtw_write32_mask(rtwdev, REG_OFDM1_CFOTRK, BIT_EN_CFOTRK, 0x0); 815 break; 816 } 817 } 818 819 static void rtw8703b_spur_cal(struct rtw_dev *rtwdev, u8 channel) 820 { 821 bool notch; 822 u32 freq; 823 824 if (channel == 5) { 825 freq = FREQ_CH5; 826 } else if (channel == 6) { 827 freq = FREQ_CH6; 828 } else if (channel == 7) { 829 freq = FREQ_CH7; 830 } else if (channel == 8) { 831 freq = FREQ_CH8; 832 } else if (channel == 13) { 833 freq = FREQ_CH13; 834 } else if (channel == 14) { 835 freq = FREQ_CH14; 836 } else { 837 rtw8703b_cfg_notch(rtwdev, channel, false); 838 return; 839 } 840 841 notch = rtw8703b_check_spur_ov_thres(rtwdev, freq, SPUR_THRES); 842 rtw8703b_cfg_notch(rtwdev, channel, notch); 843 } 844 845 static void rtw8703b_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 846 { 847 u32 rf_cfgch_a; 848 u32 rf_cfgch_b; 849 /* default value for 20M */ 850 u32 rf_rck = 0x00000C08; 851 852 rf_cfgch_a = rtw_read_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK); 853 rf_cfgch_b = rtw_read_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK); 854 855 rf_cfgch_a &= ~RFCFGCH_CHANNEL_MASK; 856 rf_cfgch_b &= ~RFCFGCH_CHANNEL_MASK; 857 rf_cfgch_a |= (channel & RFCFGCH_CHANNEL_MASK); 858 rf_cfgch_b |= (channel & RFCFGCH_CHANNEL_MASK); 859 860 rf_cfgch_a &= ~RFCFGCH_BW_MASK; 861 switch (bw) { 862 case RTW_CHANNEL_WIDTH_20: 863 rf_cfgch_a |= RFCFGCH_BW_20M; 864 break; 865 case RTW_CHANNEL_WIDTH_40: 866 rf_cfgch_a |= RFCFGCH_BW_40M; 867 rf_rck = 0x00000C4C; 868 break; 869 default: 870 break; 871 } 872 873 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_cfgch_a); 874 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_cfgch_b); 875 876 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK1, RFREG_MASK, rf_rck); 877 rtw8703b_spur_cal(rtwdev, channel); 878 } 879 880 #define CCK_DFIR_NR_8703B 2 881 static const struct rtw_backup_info cck_dfir_cfg[][CCK_DFIR_NR_8703B] = { 882 [0] = { 883 { .len = 4, .reg = REG_CCK_TXSF2, .val = 0x5A7DA0BD }, 884 { .len = 4, .reg = REG_CCK_DBG, .val = 0x0000223B }, 885 }, 886 [1] = { 887 { .len = 4, .reg = REG_CCK_TXSF2, .val = 0x00000000 }, 888 { .len = 4, .reg = REG_CCK_DBG, .val = 0x00000000 }, 889 }, 890 }; 891 892 static void rtw8703b_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 893 u8 primary_ch_idx) 894 { 895 const struct rtw_backup_info *cck_dfir; 896 int i; 897 898 cck_dfir = channel <= 13 ? cck_dfir_cfg[0] : cck_dfir_cfg[1]; 899 900 for (i = 0; i < CCK_DFIR_NR_8703B; i++, cck_dfir++) 901 rtw_write32(rtwdev, cck_dfir->reg, cck_dfir->val); 902 903 switch (bw) { 904 case RTW_CHANNEL_WIDTH_20: 905 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x0); 906 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x0); 907 rtw_write32_mask(rtwdev, REG_OFDM0_TX_PSD_NOISE, 908 GENMASK(31, 30), 0x0); 909 rtw_write32(rtwdev, REG_BBRX_DFIR, 0x4A880000); 910 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x19F60000); 911 break; 912 case RTW_CHANNEL_WIDTH_40: 913 rtw_write32_mask(rtwdev, REG_FPGA0_RFMOD, BIT_MASK_RFMOD, 0x1); 914 rtw_write32_mask(rtwdev, REG_FPGA1_RFMOD, BIT_MASK_RFMOD, 0x1); 915 rtw_write32(rtwdev, REG_BBRX_DFIR, 0x40100000); 916 rtw_write32(rtwdev, REG_OFDM0_A_TX_AFE, 0x51F60000); 917 rtw_write32_mask(rtwdev, REG_CCK0_SYS, BIT_CCK_SIDE_BAND, 918 primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0); 919 rtw_write32_mask(rtwdev, REG_OFDM_FA_RSTD_11N, 0xC00, 920 primary_ch_idx == RTW_SC_20_UPPER ? 2 : 1); 921 922 rtw_write32_mask(rtwdev, REG_BB_PWR_SAV5_11N, GENMASK(27, 26), 923 primary_ch_idx == RTW_SC_20_UPPER ? 1 : 2); 924 break; 925 default: 926 break; 927 } 928 } 929 930 static void rtw8703b_set_channel(struct rtw_dev *rtwdev, u8 channel, 931 u8 bw, u8 primary_chan_idx) 932 { 933 rtw8703b_set_channel_rf(rtwdev, channel, bw); 934 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 935 rtw8703b_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 936 } 937 938 /* Not all indices are valid, based on available data. None of the 939 * known valid values are positive, so use 0x7f as "invalid". 940 */ 941 #define LNA_IDX_INVALID 0x7f 942 static const s8 lna_gain_table[16] = { 943 -2, LNA_IDX_INVALID, LNA_IDX_INVALID, LNA_IDX_INVALID, 944 -6, LNA_IDX_INVALID, LNA_IDX_INVALID, -19, 945 -32, LNA_IDX_INVALID, -36, -42, 946 LNA_IDX_INVALID, LNA_IDX_INVALID, LNA_IDX_INVALID, -48, 947 }; 948 949 static s8 get_cck_rx_pwr(struct rtw_dev *rtwdev, u8 lna_idx, u8 vga_idx) 950 { 951 s8 lna_gain = 0; 952 953 if (lna_idx < ARRAY_SIZE(lna_gain_table)) 954 lna_gain = lna_gain_table[lna_idx]; 955 956 if (lna_gain >= 0) { 957 rtw_warn(rtwdev, "incorrect lna index (%d)\n", lna_idx); 958 return -120; 959 } 960 961 return lna_gain - 2 * vga_idx; 962 } 963 964 static void query_phy_status_cck(struct rtw_dev *rtwdev, u8 *phy_raw, 965 struct rtw_rx_pkt_stat *pkt_stat) 966 { 967 struct phy_status_8703b *phy_status = (struct phy_status_8703b *)phy_raw; 968 u8 vga_idx = phy_status->cck_agc_rpt_ofdm_cfosho_a & VGA_BITS; 969 u8 lna_idx = phy_status->cck_agc_rpt_ofdm_cfosho_a & LNA_L_BITS; 970 s8 rx_power; 971 972 if (rtwdev->dm_info.rx_cck_agc_report_type == 1) 973 lna_idx = FIELD_PREP(BIT_LNA_H_MASK, 974 phy_status->cck_rpt_b_ofdm_cfosho_b & LNA_H_BIT) 975 | FIELD_PREP(BIT_LNA_L_MASK, lna_idx); 976 else 977 lna_idx = FIELD_PREP(BIT_LNA_L_MASK, lna_idx); 978 rx_power = get_cck_rx_pwr(rtwdev, lna_idx, vga_idx); 979 980 pkt_stat->rx_power[RF_PATH_A] = rx_power; 981 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 982 rtwdev->dm_info.rssi[RF_PATH_A] = pkt_stat->rssi; 983 pkt_stat->signal_power = rx_power; 984 } 985 986 static void query_phy_status_ofdm(struct rtw_dev *rtwdev, u8 *phy_raw, 987 struct rtw_rx_pkt_stat *pkt_stat) 988 { 989 struct phy_status_8703b *phy_status = (struct phy_status_8703b *)phy_raw; 990 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 991 s8 val_s8; 992 993 val_s8 = phy_status->path_agc[RF_PATH_A].gain & 0x3F; 994 pkt_stat->rx_power[RF_PATH_A] = (val_s8 * 2) - 110; 995 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 996 pkt_stat->rx_snr[RF_PATH_A] = (s8)(phy_status->path_rxsnr[RF_PATH_A] / 2); 997 998 /* signal power reported by HW */ 999 val_s8 = phy_status->cck_sig_qual_ofdm_pwdb_all >> 1; 1000 pkt_stat->signal_power = (val_s8 & 0x7f) - 110; 1001 1002 pkt_stat->rx_evm[RF_PATH_A] = phy_status->stream_rxevm[RF_PATH_A]; 1003 pkt_stat->cfo_tail[RF_PATH_A] = phy_status->path_cfotail[RF_PATH_A]; 1004 1005 dm_info->curr_rx_rate = pkt_stat->rate; 1006 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 1007 dm_info->rx_snr[RF_PATH_A] = pkt_stat->rx_snr[RF_PATH_A] >> 1; 1008 /* convert to KHz (used only for debugfs) */ 1009 dm_info->cfo_tail[RF_PATH_A] = (pkt_stat->cfo_tail[RF_PATH_A] * 5) >> 1; 1010 1011 /* (EVM value as s8 / 2) is dbm, should usually be in -33 to 0 1012 * range. rx_evm_dbm needs the absolute (positive) value. 1013 */ 1014 val_s8 = (s8)pkt_stat->rx_evm[RF_PATH_A]; 1015 val_s8 = clamp_t(s8, -val_s8 >> 1, 0, 64); 1016 val_s8 &= 0x3F; /* 64->0: second path of 1SS rate is 64 */ 1017 dm_info->rx_evm_dbm[RF_PATH_A] = val_s8; 1018 } 1019 1020 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 1021 struct rtw_rx_pkt_stat *pkt_stat) 1022 { 1023 if (pkt_stat->rate <= DESC_RATE11M) 1024 query_phy_status_cck(rtwdev, phy_status, pkt_stat); 1025 else 1026 query_phy_status_ofdm(rtwdev, phy_status, pkt_stat); 1027 } 1028 1029 #define ADDA_ON_VAL_8703B 0x03c00014 1030 1031 static 1032 void rtw8703b_iqk_config_mac(struct rtw_dev *rtwdev, 1033 const struct rtw8723x_iqk_backup_regs *backup) 1034 { 1035 rtw_write8(rtwdev, rtw8723x_common.iqk_mac8_regs[0], 0x3F); 1036 for (int i = 1; i < RTW8723X_IQK_MAC8_REG_NUM; i++) 1037 rtw_write8(rtwdev, rtw8723x_common.iqk_mac8_regs[i], 1038 backup->mac8[i] & (~BIT(3))); 1039 } 1040 1041 #define IQK_LTE_WRITE_VAL_8703B 0x00007700 1042 #define IQK_DELAY_TIME_8703B 4 1043 1044 static void rtw8703b_iqk_one_shot(struct rtw_dev *rtwdev, bool tx) 1045 { 1046 u32 regval; 1047 ktime_t t; 1048 s64 dur; 1049 int ret; 1050 1051 /* enter IQK mode */ 1052 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, EN_IQK); 1053 rtw8723x_iqk_config_lte_path_gnt(rtwdev, IQK_LTE_WRITE_VAL_8703B); 1054 1055 /* One shot, LOK & IQK */ 1056 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf9000000); 1057 rtw_write32(rtwdev, REG_IQK_AGC_PTS_11N, 0xf8000000); 1058 1059 t = ktime_get(); 1060 msleep(IQK_DELAY_TIME_8703B); 1061 ret = read_poll_timeout(rtw_read32, regval, regval != 0, 1000, 1062 100000, false, rtwdev, 1063 REG_IQK_RDY); 1064 dur = ktime_us_delta(ktime_get(), t); 1065 1066 if (ret) 1067 #if defined(__linux__) 1068 rtw_warn(rtwdev, "[IQK] %s timed out after %lldus!\n", 1069 tx ? "TX" : "RX", dur); 1070 #elif defined(__FreeBSD__) 1071 rtw_warn(rtwdev, "[IQK] %s timed out after %jdus!\n", 1072 tx ? "TX" : "RX", (intmax_t)dur); 1073 #endif 1074 else 1075 rtw_dbg(rtwdev, RTW_DBG_RFK, 1076 #if defined(__linux__) 1077 "[IQK] %s done after %lldus\n", 1078 tx ? "TX" : "RX", dur); 1079 #elif defined(__FreeBSD__) 1080 "[IQK] %s done after %jdus\n", 1081 tx ? "TX" : "RX", (intmax_t)dur); 1082 #endif 1083 } 1084 1085 static void rtw8703b_iqk_txrx_path_post(struct rtw_dev *rtwdev, 1086 const struct rtw8723x_iqk_backup_regs *backup) 1087 { 1088 rtw8723x_iqk_restore_lte_path_gnt(rtwdev, backup); 1089 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup->bb_sel_btg); 1090 1091 /* leave IQK mode */ 1092 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1093 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x0); 1094 } 1095 1096 static u8 rtw8703b_iqk_check_tx_failed(struct rtw_dev *rtwdev) 1097 { 1098 s32 tx_x, tx_y; 1099 u32 tx_fail; 1100 1101 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xeac = 0x%x\n", 1102 rtw_read32(rtwdev, REG_IQK_RES_RY)); 1103 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe94 = 0x%x, 0xe9c = 0x%x\n", 1104 rtw_read32(rtwdev, REG_IQK_RES_TX), 1105 rtw_read32(rtwdev, REG_IQK_RES_TY)); 1106 rtw_dbg(rtwdev, RTW_DBG_RFK, 1107 "[IQK] 0xe90(before IQK) = 0x%x, 0xe98(after IQK) = 0x%x\n", 1108 rtw_read32(rtwdev, REG_IQK_RDY), 1109 rtw_read32(rtwdev, 0xe98)); 1110 1111 tx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_TX_FAIL); 1112 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 1113 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 1114 1115 if (!tx_fail && tx_x != IQK_TX_X_ERR && tx_y != IQK_TX_Y_ERR) 1116 return IQK_TX_OK; 1117 1118 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] A TX IQK failed\n"); 1119 1120 return 0; 1121 } 1122 1123 static u8 rtw8703b_iqk_check_rx_failed(struct rtw_dev *rtwdev) 1124 { 1125 s32 rx_x, rx_y; 1126 u32 rx_fail; 1127 1128 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xea4 = 0x%x, 0xeac = 0x%x\n", 1129 rtw_read32(rtwdev, REG_IQK_RES_RX), 1130 rtw_read32(rtwdev, REG_IQK_RES_RY)); 1131 1132 rtw_dbg(rtwdev, RTW_DBG_RFK, 1133 "[IQK] 0xea0(before IQK) = 0x%x, 0xea8(after IQK) = 0x%x\n", 1134 rtw_read32(rtwdev, 0xea0), 1135 rtw_read32(rtwdev, 0xea8)); 1136 1137 rx_fail = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_IQK_RX_FAIL); 1138 rx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_RX, BIT_MASK_RES_RX); 1139 rx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_RY, BIT_MASK_RES_RY); 1140 rx_y = abs(iqkxy_to_s32(rx_y)); 1141 1142 if (!rx_fail && rx_x != IQK_RX_X_ERR && rx_y != IQK_RX_Y_ERR && 1143 rx_x < IQK_RX_X_UPPER && rx_x > IQK_RX_X_LOWER && 1144 rx_y < IQK_RX_Y_LMT) 1145 return IQK_RX_OK; 1146 1147 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] A RX IQK failed\n"); 1148 1149 return 0; 1150 } 1151 1152 static u8 rtw8703b_iqk_tx_path(struct rtw_dev *rtwdev, 1153 const struct rtw8723x_iqk_backup_regs *backup) 1154 { 1155 u8 status; 1156 1157 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A TX IQK!\n"); 1158 1159 /* IQK setting */ 1160 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); 1161 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 1162 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c); 1163 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c); 1164 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); 1165 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); 1166 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x8214030f); 1167 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28110000); 1168 rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000); 1169 rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000); 1170 1171 /* LO calibration setting */ 1172 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x00462911); 1173 1174 /* leave IQK mode */ 1175 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000); 1176 1177 /* PA, PAD setting */ 1178 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x1); 1179 rtw_write_rf(rtwdev, RF_PATH_A, 0x55, 0x7f, 0x7); 1180 rtw_write_rf(rtwdev, RF_PATH_A, 0x7f, RFREG_MASK, 0xd400); 1181 1182 rtw8703b_iqk_one_shot(rtwdev, true); 1183 status = rtw8703b_iqk_check_tx_failed(rtwdev); 1184 1185 rtw8703b_iqk_txrx_path_post(rtwdev, backup); 1186 1187 return status; 1188 } 1189 1190 static u8 rtw8703b_iqk_rx_path(struct rtw_dev *rtwdev, 1191 const struct rtw8723x_iqk_backup_regs *backup) 1192 { 1193 u8 status; 1194 u32 tx_x, tx_y; 1195 1196 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A RX IQK step 1!\n"); 1197 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @A RX IQK1 = 0x%x\n", 1198 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 1199 rtw_write32(rtwdev, REG_BB_SEL_BTG, 0x99000000); 1200 1201 /* disable IQC mode */ 1202 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1203 1204 /* IQK setting */ 1205 rtw_write32(rtwdev, REG_TXIQK_11N, 0x01007c00); 1206 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 1207 1208 /* path IQK setting */ 1209 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x18008c1c); 1210 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x38008c1c); 1211 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); 1212 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); 1213 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x8214030f); 1214 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28110000); 1215 rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000); 1216 rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000); 1217 1218 /* LOK setting */ 1219 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a911); 1220 1221 /* RX IQK mode */ 1222 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, 0x80000, 0x1); 1223 rtw_write_rf(rtwdev, RF_PATH_A, 0x30, RFREG_MASK, 0x30000); 1224 rtw_write_rf(rtwdev, RF_PATH_A, 0x31, RFREG_MASK, 0x00007); 1225 rtw_write_rf(rtwdev, RF_PATH_A, 0x32, RFREG_MASK, 0x57db7); 1226 1227 rtw8703b_iqk_one_shot(rtwdev, true); 1228 /* leave IQK mode */ 1229 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000); 1230 status = rtw8703b_iqk_check_tx_failed(rtwdev); 1231 1232 if (!status) 1233 goto restore; 1234 1235 /* second round */ 1236 tx_x = rtw_read32_mask(rtwdev, REG_IQK_RES_TX, BIT_MASK_RES_TX); 1237 tx_y = rtw_read32_mask(rtwdev, REG_IQK_RES_TY, BIT_MASK_RES_TY); 1238 1239 rtw_write32(rtwdev, REG_TXIQK_11N, BIT_SET_TXIQK_11N(tx_x, tx_y)); 1240 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0xe40 = 0x%x u4tmp = 0x%x\n", 1241 rtw_read32(rtwdev, REG_TXIQK_11N), 1242 BIT_SET_TXIQK_11N(tx_x, tx_y)); 1243 1244 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A RX IQK step 2!\n"); 1245 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] 0x67 @A RX IQK 2 = 0x%x\n", 1246 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3)); 1247 1248 /* IQK setting */ 1249 rtw_write32(rtwdev, REG_RXIQK_11N, 0x01004800); 1250 rtw_write32(rtwdev, REG_TXIQK_TONE_A_11N, 0x38008c1c); 1251 rtw_write32(rtwdev, REG_RXIQK_TONE_A_11N, 0x18008c1c); 1252 rtw_write32(rtwdev, REG_TX_IQK_TONE_B, 0x38008c1c); 1253 rtw_write32(rtwdev, REG_RX_IQK_TONE_B, 0x38008c1c); 1254 rtw_write32(rtwdev, REG_TXIQK_PI_A_11N, 0x82110000); 1255 rtw_write32(rtwdev, REG_RXIQK_PI_A_11N, 0x28160c1f); 1256 rtw_write32(rtwdev, REG_TXIQK_PI_B, 0x82110000); 1257 rtw_write32(rtwdev, REG_RXIQK_PI_B, 0x28110000); 1258 1259 /* LO calibration setting */ 1260 rtw_write32(rtwdev, REG_IQK_AGC_RSP_11N, 0x0046a8d1); 1261 1262 /* leave IQK mode */ 1263 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, 0xffffff00, 0x000000); 1264 /* modify RX IQK mode table */ 1265 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, 0x80000, 0x1); 1266 /* RF_RCK_OS, RF_TXPA_G1, RF_TXPA_G2 */ 1267 rtw_write_rf(rtwdev, RF_PATH_A, 0x30, RFREG_MASK, 0x30000); 1268 rtw_write_rf(rtwdev, RF_PATH_A, 0x31, RFREG_MASK, 0x00007); 1269 rtw_write_rf(rtwdev, RF_PATH_A, 0x32, RFREG_MASK, 0xf7d77); 1270 1271 /* PA, PAD setting */ 1272 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, 0x800, 0x1); 1273 rtw_write_rf(rtwdev, RF_PATH_A, 0x55, 0x7f, 0x5); 1274 1275 rtw8703b_iqk_one_shot(rtwdev, false); 1276 status |= rtw8703b_iqk_check_rx_failed(rtwdev); 1277 1278 restore: 1279 rtw8703b_iqk_txrx_path_post(rtwdev, backup); 1280 1281 return status; 1282 } 1283 1284 static 1285 void rtw8703b_iqk_one_round(struct rtw_dev *rtwdev, s32 result[][IQK_NR], u8 t, 1286 const struct rtw8723x_iqk_backup_regs *backup) 1287 { 1288 u32 i; 1289 u8 a_ok; 1290 1291 rtw_dbg(rtwdev, RTW_DBG_RFK, 1292 "[IQK] IQ Calibration for 1T1R_S0/S1 for %d times\n", t); 1293 1294 rtw8723x_iqk_path_adda_on(rtwdev, ADDA_ON_VAL_8703B); 1295 rtw8703b_iqk_config_mac(rtwdev, backup); 1296 rtw_write32_mask(rtwdev, REG_CCK_ANT_SEL_11N, 0x0f000000, 0xf); 1297 rtw_write32(rtwdev, REG_BB_RX_PATH_11N, 0x03a05600); 1298 rtw_write32(rtwdev, REG_TRMUX_11N, 0x000800e4); 1299 rtw_write32(rtwdev, REG_BB_PWR_SAV1_11N, 0x25204000); 1300 1301 for (i = 0; i < PATH_IQK_RETRY; i++) { 1302 a_ok = rtw8703b_iqk_tx_path(rtwdev, backup); 1303 if (a_ok == IQK_TX_OK) { 1304 rtw_dbg(rtwdev, RTW_DBG_RFK, 1305 "[IQK] path A TX IQK success!\n"); 1306 result[t][IQK_S1_TX_X] = 1307 rtw_read32_mask(rtwdev, REG_IQK_RES_TX, 1308 BIT_MASK_RES_TX); 1309 result[t][IQK_S1_TX_Y] = 1310 rtw_read32_mask(rtwdev, REG_IQK_RES_TY, 1311 BIT_MASK_RES_TY); 1312 break; 1313 } 1314 1315 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A TX IQK fail!\n"); 1316 result[t][IQK_S1_TX_X] = 0x100; 1317 result[t][IQK_S1_TX_Y] = 0x0; 1318 } 1319 1320 for (i = 0; i < PATH_IQK_RETRY; i++) { 1321 a_ok = rtw8703b_iqk_rx_path(rtwdev, backup); 1322 if (a_ok == (IQK_TX_OK | IQK_RX_OK)) { 1323 rtw_dbg(rtwdev, RTW_DBG_RFK, 1324 "[IQK] path A RX IQK success!\n"); 1325 result[t][IQK_S1_RX_X] = 1326 rtw_read32_mask(rtwdev, REG_IQK_RES_RX, 1327 BIT_MASK_RES_RX); 1328 result[t][IQK_S1_RX_Y] = 1329 rtw_read32_mask(rtwdev, REG_IQK_RES_RY, 1330 BIT_MASK_RES_RY); 1331 break; 1332 } 1333 1334 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A RX IQK fail!\n"); 1335 result[t][IQK_S1_RX_X] = 0x100; 1336 result[t][IQK_S1_RX_Y] = 0x0; 1337 } 1338 1339 if (a_ok == 0x0) 1340 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] path A IQK fail!\n"); 1341 1342 rtw_write32_mask(rtwdev, REG_FPGA0_IQK_11N, BIT_MASK_IQK_MOD, RST_IQK); 1343 mdelay(1); 1344 } 1345 1346 static 1347 void rtw8703b_iqk_fill_a_matrix(struct rtw_dev *rtwdev, const s32 result[]) 1348 { 1349 u32 tmp_rx_iqi = 0x40000100 & GENMASK(31, 16); 1350 s32 tx1_a, tx1_a_ext; 1351 s32 tx1_c, tx1_c_ext; 1352 s32 oldval_1; 1353 s32 x, y; 1354 1355 if (result[IQK_S1_TX_X] == 0) 1356 return; 1357 1358 oldval_1 = rtw_read32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 1359 BIT_MASK_TXIQ_ELM_D); 1360 1361 x = iqkxy_to_s32(result[IQK_S1_TX_X]); 1362 tx1_a = iqk_mult(x, oldval_1, &tx1_a_ext); 1363 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 1364 BIT_MASK_TXIQ_ELM_A, tx1_a); 1365 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, 1366 BIT_MASK_OFDM0_EXT_A, tx1_a_ext); 1367 1368 y = iqkxy_to_s32(result[IQK_S1_TX_Y]); 1369 tx1_c = iqk_mult(y, oldval_1, &tx1_c_ext); 1370 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1371 BIT_SET_TXIQ_ELM_C1(tx1_c)); 1372 rtw_write32_mask(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, 1373 BIT_MASK_TXIQ_ELM_C, BIT_SET_TXIQ_ELM_C2(tx1_c)); 1374 rtw_write32_mask(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, 1375 BIT_MASK_OFDM0_EXT_C, tx1_c_ext); 1376 1377 rtw_dbg(rtwdev, RTW_DBG_RFK, 1378 "[IQK] X = 0x%x, TX1_A = 0x%x, oldval_1 0x%x\n", 1379 x, tx1_a, oldval_1); 1380 rtw_dbg(rtwdev, RTW_DBG_RFK, 1381 "[IQK] Y = 0x%x, TX1_C = 0x%x\n", y, tx1_c); 1382 1383 if (result[IQK_S1_RX_X] == 0) 1384 return; 1385 1386 tmp_rx_iqi |= FIELD_PREP(BIT_MASK_RXIQ_S1_X, result[IQK_S1_RX_X]); 1387 tmp_rx_iqi |= FIELD_PREP(BIT_MASK_RXIQ_S1_Y1, result[IQK_S1_RX_Y]); 1388 rtw_write32(rtwdev, REG_A_RXIQI, tmp_rx_iqi); 1389 rtw_write32_mask(rtwdev, REG_RXIQK_MATRIX_LSB_11N, BIT_MASK_RXIQ_S1_Y2, 1390 BIT_SET_RXIQ_S1_Y2(result[IQK_S1_RX_Y])); 1391 } 1392 1393 static void rtw8703b_phy_calibration(struct rtw_dev *rtwdev) 1394 { 1395 /* For some reason path A is called S1 and B S0 in shared 1396 * rtw88 calibration data. 1397 */ 1398 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1399 struct rtw8723x_iqk_backup_regs backup; 1400 u8 final_candidate = IQK_ROUND_INVALID; 1401 s32 result[IQK_ROUND_SIZE][IQK_NR]; 1402 bool good; 1403 u8 i, j; 1404 1405 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] Start!\n"); 1406 1407 memset(result, 0, sizeof(result)); 1408 1409 rtw8723x_iqk_backup_path_ctrl(rtwdev, &backup); 1410 rtw8723x_iqk_backup_lte_path_gnt(rtwdev, &backup); 1411 rtw8723x_iqk_backup_regs(rtwdev, &backup); 1412 1413 for (i = IQK_ROUND_0; i <= IQK_ROUND_2; i++) { 1414 rtw8723x_iqk_config_path_ctrl(rtwdev); 1415 rtw8723x_iqk_config_lte_path_gnt(rtwdev, IQK_LTE_WRITE_VAL_8703B); 1416 1417 rtw8703b_iqk_one_round(rtwdev, result, i, &backup); 1418 1419 rtw_dbg(rtwdev, RTW_DBG_RFK, 1420 "[IQK] back to BB mode, load original values!\n"); 1421 if (i > IQK_ROUND_0) 1422 rtw8723x_iqk_restore_regs(rtwdev, &backup); 1423 rtw8723x_iqk_restore_lte_path_gnt(rtwdev, &backup); 1424 rtw8723x_iqk_restore_path_ctrl(rtwdev, &backup); 1425 1426 for (j = IQK_ROUND_0; j < i; j++) { 1427 good = rtw8723x_iqk_similarity_cmp(rtwdev, result, j, i); 1428 1429 if (good) { 1430 final_candidate = j; 1431 rtw_dbg(rtwdev, RTW_DBG_RFK, 1432 "[IQK] cmp %d:%d final_candidate is %x\n", 1433 j, i, final_candidate); 1434 goto iqk_done; 1435 } 1436 } 1437 } 1438 1439 if (final_candidate == IQK_ROUND_INVALID) { 1440 s32 reg_tmp = 0; 1441 1442 for (i = 0; i < IQK_NR; i++) 1443 reg_tmp += result[IQK_ROUND_HYBRID][i]; 1444 1445 if (reg_tmp != 0) { 1446 final_candidate = IQK_ROUND_HYBRID; 1447 } else { 1448 WARN(1, "IQK failed\n"); 1449 goto out; 1450 } 1451 } 1452 1453 iqk_done: 1454 /* only path A is calibrated in rtl8703b */ 1455 rtw8703b_iqk_fill_a_matrix(rtwdev, result[final_candidate]); 1456 1457 dm_info->iqk.result.s1_x = result[final_candidate][IQK_S1_TX_X]; 1458 dm_info->iqk.result.s1_y = result[final_candidate][IQK_S1_TX_Y]; 1459 dm_info->iqk.result.s0_x = result[final_candidate][IQK_S0_TX_X]; 1460 dm_info->iqk.result.s0_y = result[final_candidate][IQK_S0_TX_Y]; 1461 dm_info->iqk.done = true; 1462 1463 out: 1464 rtw_write32(rtwdev, REG_BB_SEL_BTG, backup.bb_sel_btg); 1465 1466 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] final_candidate is %x\n", 1467 final_candidate); 1468 1469 for (i = IQK_ROUND_0; i < IQK_ROUND_SIZE; i++) 1470 rtw_dbg(rtwdev, RTW_DBG_RFK, 1471 "[IQK] Result %u: rege94_s1=%x rege9c_s1=%x regea4_s1=%x regeac_s1=%x rege94_s0=%x rege9c_s0=%x regea4_s0=%x regeac_s0=%x %s\n", 1472 i, 1473 result[i][0], result[i][1], result[i][2], result[i][3], 1474 result[i][4], result[i][5], result[i][6], result[i][7], 1475 final_candidate == i ? "(final candidate)" : ""); 1476 1477 rtw_dbg(rtwdev, RTW_DBG_RFK, 1478 "[IQK] 0xc80 = 0x%x 0xc94 = 0x%x 0xc14 = 0x%x 0xca0 = 0x%x\n", 1479 rtw_read32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE), 1480 rtw_read32(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N), 1481 rtw_read32(rtwdev, REG_A_RXIQI), 1482 rtw_read32(rtwdev, REG_RXIQK_MATRIX_LSB_11N)); 1483 rtw_dbg(rtwdev, RTW_DBG_RFK, 1484 "[IQK] 0xcd0 = 0x%x 0xcd4 = 0x%x 0xcd8 = 0x%x\n", 1485 rtw_read32(rtwdev, REG_TXIQ_AB_S0), 1486 rtw_read32(rtwdev, REG_TXIQ_CD_S0), 1487 rtw_read32(rtwdev, REG_RXIQ_AB_S0)); 1488 1489 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] Finished.\n"); 1490 } 1491 1492 static void rtw8703b_set_iqk_matrix_by_result(struct rtw_dev *rtwdev, 1493 u32 ofdm_swing, u8 rf_path) 1494 { 1495 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1496 s32 ele_A, ele_D, ele_C; 1497 s32 ele_A_ext, ele_C_ext, ele_D_ext; 1498 s32 iqk_result_x; 1499 s32 iqk_result_y; 1500 s32 value32; 1501 1502 switch (rf_path) { 1503 default: 1504 case RF_PATH_A: 1505 iqk_result_x = dm_info->iqk.result.s1_x; 1506 iqk_result_y = dm_info->iqk.result.s1_y; 1507 break; 1508 case RF_PATH_B: 1509 iqk_result_x = dm_info->iqk.result.s0_x; 1510 iqk_result_y = dm_info->iqk.result.s0_y; 1511 break; 1512 } 1513 1514 /* new element D */ 1515 ele_D = OFDM_SWING_D(ofdm_swing); 1516 iqk_mult(iqk_result_x, ele_D, &ele_D_ext); 1517 /* new element A */ 1518 iqk_result_x = iqkxy_to_s32(iqk_result_x); 1519 ele_A = iqk_mult(iqk_result_x, ele_D, &ele_A_ext); 1520 /* new element C */ 1521 iqk_result_y = iqkxy_to_s32(iqk_result_y); 1522 ele_C = iqk_mult(iqk_result_y, ele_D, &ele_C_ext); 1523 1524 switch (rf_path) { 1525 case RF_PATH_A: 1526 default: 1527 /* write new elements A, C, D, and element B is always 0 */ 1528 value32 = BIT_SET_TXIQ_ELM_ACD(ele_A, ele_C, ele_D); 1529 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, value32); 1530 value32 = BIT_SET_TXIQ_ELM_C1(ele_C); 1531 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1532 value32); 1533 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1534 value32 &= ~BIT_MASK_OFDM0_EXTS; 1535 value32 |= BIT_SET_OFDM0_EXTS(ele_A_ext, ele_C_ext, ele_D_ext); 1536 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1537 break; 1538 1539 case RF_PATH_B: 1540 /* write new elements A, C, D, and element B is always 0 */ 1541 value32 = BIT_SET_TXIQ_ELM_ACD(ele_A, ele_C, ele_D); 1542 rtw_write32(rtwdev, REG_OFDM_0_XB_TX_IQ_IMBALANCE, value32); 1543 value32 = BIT_SET_TXIQ_ELM_C1(ele_C); 1544 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXB_LSB2_11N, MASKH4BITS, 1545 value32); 1546 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1547 value32 &= ~BIT_MASK_OFDM0_EXTS_B; 1548 value32 |= BIT_SET_OFDM0_EXTS_B(ele_A_ext, ele_C_ext, ele_D_ext); 1549 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1550 break; 1551 } 1552 } 1553 1554 static void rtw8703b_set_iqk_matrix(struct rtw_dev *rtwdev, s8 ofdm_index, 1555 u8 rf_path) 1556 { 1557 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1558 s32 value32; 1559 u32 ofdm_swing; 1560 1561 ofdm_index = clamp_t(s8, ofdm_index, 0, RTW_OFDM_SWING_TABLE_SIZE - 1); 1562 1563 ofdm_swing = rtw8703b_ofdm_swing_table[ofdm_index]; 1564 1565 if (dm_info->iqk.done) { 1566 rtw8703b_set_iqk_matrix_by_result(rtwdev, ofdm_swing, rf_path); 1567 return; 1568 } 1569 1570 switch (rf_path) { 1571 case RF_PATH_A: 1572 default: 1573 rtw_write32(rtwdev, REG_OFDM_0_XA_TX_IQ_IMBALANCE, ofdm_swing); 1574 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXA_LSB2_11N, MASKH4BITS, 1575 0x00); 1576 1577 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1578 value32 &= ~BIT_MASK_OFDM0_EXTS; 1579 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1580 break; 1581 1582 case RF_PATH_B: 1583 rtw_write32(rtwdev, REG_OFDM_0_XB_TX_IQ_IMBALANCE, ofdm_swing); 1584 rtw_write32_mask(rtwdev, REG_TXIQK_MATRIXB_LSB2_11N, MASKH4BITS, 1585 0x00); 1586 1587 value32 = rtw_read32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD); 1588 value32 &= ~BIT_MASK_OFDM0_EXTS_B; 1589 rtw_write32(rtwdev, REG_OFDM_0_ECCA_THRESHOLD, value32); 1590 break; 1591 } 1592 } 1593 1594 static void rtw8703b_pwrtrack_set_ofdm_pwr(struct rtw_dev *rtwdev, s8 swing_idx, 1595 s8 txagc_idx) 1596 { 1597 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1598 1599 dm_info->txagc_remnant_ofdm[RF_PATH_A] = txagc_idx; 1600 1601 /* Only path A is calibrated for rtl8703b */ 1602 rtw8703b_set_iqk_matrix(rtwdev, swing_idx, RF_PATH_A); 1603 } 1604 1605 static void rtw8703b_pwrtrack_set_cck_pwr(struct rtw_dev *rtwdev, s8 swing_idx, 1606 s8 txagc_idx) 1607 { 1608 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1609 1610 dm_info->txagc_remnant_cck = txagc_idx; 1611 1612 swing_idx = clamp_t(s8, swing_idx, 0, RTW_CCK_SWING_TABLE_SIZE - 1); 1613 1614 BUILD_BUG_ON(ARRAY_SIZE(rtw8703b_cck_pwr_regs) 1615 != ARRAY_SIZE(rtw8703b_cck_swing_table[0])); 1616 1617 for (int i = 0; i < ARRAY_SIZE(rtw8703b_cck_pwr_regs); i++) 1618 rtw_write8(rtwdev, rtw8703b_cck_pwr_regs[i], 1619 rtw8703b_cck_swing_table[swing_idx][i]); 1620 } 1621 1622 static void rtw8703b_pwrtrack_set(struct rtw_dev *rtwdev, u8 path) 1623 { 1624 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1625 struct rtw_hal *hal = &rtwdev->hal; 1626 u8 limit_ofdm; 1627 u8 limit_cck = 21; 1628 s8 final_ofdm_swing_index; 1629 s8 final_cck_swing_index; 1630 1631 limit_ofdm = rtw8723x_pwrtrack_get_limit_ofdm(rtwdev); 1632 1633 final_ofdm_swing_index = dm_info->default_ofdm_index + 1634 dm_info->delta_power_index[path]; 1635 final_cck_swing_index = dm_info->default_cck_index + 1636 dm_info->delta_power_index[path]; 1637 1638 if (final_ofdm_swing_index > limit_ofdm) 1639 rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, limit_ofdm, 1640 final_ofdm_swing_index - limit_ofdm); 1641 else if (final_ofdm_swing_index < 0) 1642 rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, 0, 1643 final_ofdm_swing_index); 1644 else 1645 rtw8703b_pwrtrack_set_ofdm_pwr(rtwdev, final_ofdm_swing_index, 0); 1646 1647 if (final_cck_swing_index > limit_cck) 1648 rtw8703b_pwrtrack_set_cck_pwr(rtwdev, limit_cck, 1649 final_cck_swing_index - limit_cck); 1650 else if (final_cck_swing_index < 0) 1651 rtw8703b_pwrtrack_set_cck_pwr(rtwdev, 0, 1652 final_cck_swing_index); 1653 else 1654 rtw8703b_pwrtrack_set_cck_pwr(rtwdev, final_cck_swing_index, 0); 1655 1656 rtw_phy_set_tx_power_level(rtwdev, hal->current_channel); 1657 } 1658 1659 static void rtw8703b_phy_pwrtrack(struct rtw_dev *rtwdev) 1660 { 1661 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1662 struct rtw_swing_table swing_table; 1663 u8 thermal_value, delta, path; 1664 bool do_iqk = false; 1665 1666 rtw_phy_config_swing_table(rtwdev, &swing_table); 1667 1668 if (rtwdev->efuse.thermal_meter[0] == 0xff) 1669 return; 1670 1671 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 1672 1673 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 1674 1675 do_iqk = rtw_phy_pwrtrack_need_iqk(rtwdev); 1676 1677 if (do_iqk) 1678 rtw8723x_lck(rtwdev); 1679 1680 if (dm_info->pwr_trk_init_trigger) 1681 dm_info->pwr_trk_init_trigger = false; 1682 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 1683 RF_PATH_A)) 1684 goto iqk; 1685 1686 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 1687 1688 delta = min_t(u8, delta, RTW_PWR_TRK_TBL_SZ - 1); 1689 1690 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1691 s8 delta_cur, delta_last; 1692 1693 delta_last = dm_info->delta_power_index[path]; 1694 delta_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, &swing_table, 1695 path, RF_PATH_A, delta); 1696 if (delta_last == delta_cur) 1697 continue; 1698 1699 dm_info->delta_power_index[path] = delta_cur; 1700 rtw8703b_pwrtrack_set(rtwdev, path); 1701 } 1702 1703 rtw8723x_pwrtrack_set_xtal(rtwdev, RF_PATH_A, delta); 1704 1705 iqk: 1706 if (do_iqk) 1707 rtw8703b_phy_calibration(rtwdev); 1708 } 1709 1710 static void rtw8703b_pwr_track(struct rtw_dev *rtwdev) 1711 { 1712 struct rtw_efuse *efuse = &rtwdev->efuse; 1713 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1714 1715 if (efuse->power_track_type != 0) { 1716 rtw_warn(rtwdev, "unsupported power track type"); 1717 return; 1718 } 1719 1720 if (!dm_info->pwr_trk_triggered) { 1721 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 1722 GENMASK(17, 16), 0x03); 1723 dm_info->pwr_trk_triggered = true; 1724 return; 1725 } 1726 1727 rtw8703b_phy_pwrtrack(rtwdev); 1728 dm_info->pwr_trk_triggered = false; 1729 } 1730 1731 static void rtw8703b_coex_set_gnt_fix(struct rtw_dev *rtwdev) 1732 { 1733 } 1734 1735 static void rtw8703b_coex_set_gnt_debug(struct rtw_dev *rtwdev) 1736 { 1737 } 1738 1739 static void rtw8703b_coex_set_rfe_type(struct rtw_dev *rtwdev) 1740 { 1741 struct rtw_coex *coex = &rtwdev->coex; 1742 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 1743 1744 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; 1745 coex_rfe->ant_switch_polarity = 0; 1746 coex_rfe->ant_switch_exist = false; 1747 coex_rfe->ant_switch_with_bt = false; 1748 coex_rfe->ant_switch_diversity = false; 1749 coex_rfe->wlg_at_btg = true; 1750 1751 /* disable LTE coex on wifi side */ 1752 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0); 1753 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); 1754 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); 1755 } 1756 1757 static void rtw8703b_coex_set_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 1758 { 1759 } 1760 1761 static void rtw8703b_coex_set_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 1762 { 1763 } 1764 1765 static const u8 rtw8703b_pwrtrk_2gb_n[] = { 1766 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 1767 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 1768 }; 1769 1770 static const u8 rtw8703b_pwrtrk_2gb_p[] = { 1771 0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7, 1772 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15 1773 }; 1774 1775 static const u8 rtw8703b_pwrtrk_2ga_n[] = { 1776 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 1777 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 1778 }; 1779 1780 static const u8 rtw8703b_pwrtrk_2ga_p[] = { 1781 0, 1, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 7, 7, 7, 1782 8, 8, 9, 9, 10, 10, 11, 11, 12, 13, 13, 14, 14, 15, 15 1783 }; 1784 1785 static const u8 rtw8703b_pwrtrk_2g_cck_b_n[] = { 1786 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 1787 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 1788 }; 1789 1790 static const u8 rtw8703b_pwrtrk_2g_cck_b_p[] = { 1791 0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 1792 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13 1793 }; 1794 1795 static const u8 rtw8703b_pwrtrk_2g_cck_a_n[] = { 1796 0, 0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 1797 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 1798 }; 1799 1800 static const u8 rtw8703b_pwrtrk_2g_cck_a_p[] = { 1801 0, 0, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 6, 1802 7, 7, 8, 8, 8, 9, 10, 10, 10, 11, 11, 12, 12, 13, 13 1803 }; 1804 1805 static const s8 rtw8703b_pwrtrk_xtal_n[] = { 1806 0, 0, 0, -1, -1, -1, -1, -2, -2, -2, -3, -3, -3, -3, -3, 1807 -4, -2, -2, -1, -1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1 1808 }; 1809 1810 static const s8 rtw8703b_pwrtrk_xtal_p[] = { 1811 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 1, 0, -1, -1, -1, 1812 -2, -3, -7, -9, -10, -11, -14, -16, -18, -20, -22, -24, -26, -28, -30 1813 }; 1814 1815 static const struct rtw_pwr_track_tbl rtw8703b_rtw_pwr_track_tbl = { 1816 .pwrtrk_2gb_n = rtw8703b_pwrtrk_2gb_n, 1817 .pwrtrk_2gb_p = rtw8703b_pwrtrk_2gb_p, 1818 .pwrtrk_2ga_n = rtw8703b_pwrtrk_2ga_n, 1819 .pwrtrk_2ga_p = rtw8703b_pwrtrk_2ga_p, 1820 .pwrtrk_2g_cckb_n = rtw8703b_pwrtrk_2g_cck_b_n, 1821 .pwrtrk_2g_cckb_p = rtw8703b_pwrtrk_2g_cck_b_p, 1822 .pwrtrk_2g_ccka_n = rtw8703b_pwrtrk_2g_cck_a_n, 1823 .pwrtrk_2g_ccka_p = rtw8703b_pwrtrk_2g_cck_a_p, 1824 .pwrtrk_xtal_n = rtw8703b_pwrtrk_xtal_n, 1825 .pwrtrk_xtal_p = rtw8703b_pwrtrk_xtal_p, 1826 }; 1827 1828 static const struct rtw_rfe_def rtw8703b_rfe_defs[] = { 1829 [0] = { .phy_pg_tbl = &rtw8703b_bb_pg_tbl, 1830 .txpwr_lmt_tbl = &rtw8703b_txpwr_lmt_tbl, 1831 .pwr_track_tbl = &rtw8703b_rtw_pwr_track_tbl, }, 1832 }; 1833 1834 /* Shared-Antenna Coex Table */ 1835 static const struct coex_table_para table_sant_8703b[] = { 1836 {0xffffffff, 0xffffffff}, /* case-0 */ 1837 {0x55555555, 0x55555555}, 1838 {0x66555555, 0x66555555}, 1839 {0xaaaaaaaa, 0xaaaaaaaa}, 1840 {0x5a5a5a5a, 0x5a5a5a5a}, 1841 {0xfafafafa, 0xfafafafa}, /* case-5 */ 1842 {0x6a5a5555, 0xaaaaaaaa}, 1843 {0x6a5a56aa, 0x6a5a56aa}, 1844 {0x6a5a5a5a, 0x6a5a5a5a}, 1845 {0x66555555, 0x5a5a5a5a}, 1846 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 1847 {0x66555555, 0x6a5a5aaa}, 1848 {0x66555555, 0x5a5a5aaa}, 1849 {0x66555555, 0x6aaa5aaa}, 1850 {0x66555555, 0xaaaa5aaa}, 1851 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 1852 {0xffff55ff, 0xfafafafa}, 1853 {0xffff55ff, 0x6afa5afa}, 1854 {0xaaffffaa, 0xfafafafa}, 1855 {0xaa5555aa, 0x5a5a5a5a}, 1856 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 1857 {0xaa5555aa, 0xaaaaaaaa}, 1858 {0xffffffff, 0x5a5a5a5a}, 1859 {0xffffffff, 0x5a5a5a5a}, 1860 {0xffffffff, 0x55555555}, 1861 {0xffffffff, 0x5a5a5aaa}, /* case-25 */ 1862 {0x55555555, 0x5a5a5a5a}, 1863 {0x55555555, 0xaaaaaaaa}, 1864 {0x55555555, 0x6a5a6a5a}, 1865 {0x66556655, 0x66556655}, 1866 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */ 1867 {0xffffffff, 0x5aaa5aaa}, 1868 {0x56555555, 0x5a5a5aaa}, 1869 }; 1870 1871 /* Shared-Antenna TDMA */ 1872 static const struct coex_tdma_para tdma_sant_8703b[] = { 1873 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 1874 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */ 1875 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 1876 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 1877 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 1878 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ 1879 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 1880 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 1881 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 1882 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 1883 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 1884 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 1885 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 1886 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 1887 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 1888 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 1889 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 1890 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 1891 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 1892 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 1893 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 1894 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 1895 { {0x51, 0x0c, 0x03, 0x10, 0x54} }, 1896 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 1897 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 1898 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 1899 { {0x51, 0x08, 0x03, 0x10, 0x50} }, 1900 { {0x61, 0x08, 0x03, 0x11, 0x11} }, 1901 }; 1902 1903 static const struct rtw_chip_ops rtw8703b_ops = { 1904 .power_on = rtw_power_on, 1905 .power_off = rtw_power_off, 1906 .mac_init = rtw8723x_mac_init, 1907 .dump_fw_crash = NULL, 1908 .shutdown = NULL, 1909 .read_efuse = rtw8703b_read_efuse, 1910 .phy_set_param = rtw8703b_phy_set_param, 1911 .set_channel = rtw8703b_set_channel, 1912 .query_phy_status = query_phy_status, 1913 .read_rf = rtw_phy_read_rf_sipi, 1914 .write_rf = rtw_phy_write_rf_reg_sipi, 1915 .set_tx_power_index = rtw8723x_set_tx_power_index, 1916 .set_antenna = NULL, 1917 .cfg_ldo25 = rtw8723x_cfg_ldo25, 1918 .efuse_grant = rtw8723x_efuse_grant, 1919 .false_alarm_statistics = rtw8723x_false_alarm_statistics, 1920 .phy_calibration = rtw8703b_phy_calibration, 1921 .dpk_track = NULL, 1922 /* 8723d uses REG_CSRATIO to set dm_info.cck_pd_default, which 1923 * is used in its cck_pd_set function. According to comments 1924 * in the vendor driver code it doesn't exist in this chip 1925 * generation, only 0xa0a ("ODM_CCK_PD_THRESH", which is only 1926 * *written* to). 1927 */ 1928 .cck_pd_set = NULL, 1929 .pwr_track = rtw8703b_pwr_track, 1930 .config_bfee = NULL, 1931 .set_gid_table = NULL, 1932 .cfg_csi_rate = NULL, 1933 .adaptivity_init = NULL, 1934 .adaptivity = NULL, 1935 .cfo_init = NULL, 1936 .cfo_track = NULL, 1937 .config_tx_path = NULL, 1938 .config_txrx_mode = NULL, 1939 .fill_txdesc_checksum = rtw8723x_fill_txdesc_checksum, 1940 1941 /* for coex */ 1942 .coex_set_init = rtw8723x_coex_cfg_init, 1943 .coex_set_ant_switch = NULL, 1944 .coex_set_gnt_fix = rtw8703b_coex_set_gnt_fix, 1945 .coex_set_gnt_debug = rtw8703b_coex_set_gnt_debug, 1946 .coex_set_rfe_type = rtw8703b_coex_set_rfe_type, 1947 .coex_set_wl_tx_power = rtw8703b_coex_set_wl_tx_power, 1948 .coex_set_wl_rx_gain = rtw8703b_coex_set_wl_rx_gain, 1949 }; 1950 1951 const struct rtw_chip_info rtw8703b_hw_spec = { 1952 .ops = &rtw8703b_ops, 1953 .id = RTW_CHIP_TYPE_8703B, 1954 1955 .fw_name = "rtw88/rtw8703b_fw.bin", 1956 .wlan_cpu = RTW_WCPU_11N, 1957 .tx_pkt_desc_sz = 40, 1958 .tx_buf_desc_sz = 16, 1959 .rx_pkt_desc_sz = 24, 1960 .rx_buf_desc_sz = 8, 1961 .phy_efuse_size = 256, 1962 .log_efuse_size = 512, 1963 .ptct_efuse_size = 15, 1964 .txff_size = 32768, 1965 .rxff_size = 16384, 1966 .rsvd_drv_pg_num = 8, 1967 .band = RTW_BAND_2G, 1968 .page_size = TX_PAGE_SIZE, 1969 .csi_buf_pg_num = 0, 1970 .dig_min = 0x20, 1971 .txgi_factor = 1, 1972 .is_pwr_by_rate_dec = true, 1973 .rx_ldpc = false, 1974 .tx_stbc = false, 1975 .max_power_index = 0x3f, 1976 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16, 1977 .usb_tx_agg_desc_num = 1, /* Not sure if this chip has USB interface */ 1978 .hw_feature_report = true, 1979 .c2h_ra_report_size = 7, 1980 .old_datarate_fb_limit = true, 1981 1982 .path_div_supported = false, 1983 .ht_supported = true, 1984 .vht_supported = false, 1985 .lps_deep_mode_supported = 0, 1986 1987 .sys_func_en = 0xFD, 1988 .pwr_on_seq = card_enable_flow_8703b, 1989 .pwr_off_seq = card_disable_flow_8703b, 1990 .rqpn_table = rqpn_table_8703b, 1991 .prioq_addrs = &rtw8723x_common.prioq_addrs, 1992 .page_table = page_table_8703b, 1993 /* used only in pci.c, not needed for SDIO devices */ 1994 .intf_table = NULL, 1995 1996 .dig = rtw8723x_common.dig, 1997 .dig_cck = rtw8723x_common.dig_cck, 1998 1999 .rf_sipi_addr = {0x840, 0x844}, 2000 .rf_sipi_read_addr = rtw8723x_common.rf_sipi_addr, 2001 .fix_rf_phy_num = 2, 2002 .ltecoex_addr = &rtw8723x_common.ltecoex_addr, 2003 2004 .mac_tbl = &rtw8703b_mac_tbl, 2005 .agc_tbl = &rtw8703b_agc_tbl, 2006 .bb_tbl = &rtw8703b_bb_tbl, 2007 .rf_tbl = {&rtw8703b_rf_a_tbl}, 2008 2009 .rfe_defs = rtw8703b_rfe_defs, 2010 .rfe_defs_size = ARRAY_SIZE(rtw8703b_rfe_defs), 2011 2012 .iqk_threshold = 8, 2013 2014 /* WOWLAN firmware exists, but not implemented yet */ 2015 .wow_fw_name = "rtw88/rtw8703b_wow_fw.bin", 2016 .wowlan_stub = NULL, 2017 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN, 2018 2019 /* Vendor driver has a time-based format, converted from 2020 * 20180330 2021 */ 2022 .coex_para_ver = 0x0133ed6a, 2023 .bt_desired_ver = 0x1c, 2024 .scbd_support = true, 2025 .new_scbd10_def = true, 2026 .ble_hid_profile_support = false, 2027 .wl_mimo_ps_support = false, 2028 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 2029 .bt_rssi_type = COEX_BTRSSI_RATIO, 2030 .ant_isolation = 15, 2031 .rssi_tolerance = 2, 2032 .bt_rssi_step = bt_rssi_step_8703b, 2033 .wl_rssi_step = wl_rssi_step_8703b, 2034 /* sant -> shared antenna, nsant -> non-shared antenna 2035 * Not sure if 8703b versions with non-shard antenna even exist. 2036 */ 2037 .table_sant_num = ARRAY_SIZE(table_sant_8703b), 2038 .table_sant = table_sant_8703b, 2039 .table_nsant_num = 0, 2040 .table_nsant = NULL, 2041 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8703b), 2042 .tdma_sant = tdma_sant_8703b, 2043 .tdma_nsant_num = 0, 2044 .tdma_nsant = NULL, 2045 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8703b), 2046 .wl_rf_para_tx = rf_para_tx_8703b, 2047 .wl_rf_para_rx = rf_para_rx_8703b, 2048 .bt_afh_span_bw20 = 0x20, 2049 .bt_afh_span_bw40 = 0x30, 2050 .afh_5g_num = ARRAY_SIZE(afh_5g_8703b), 2051 .afh_5g = afh_5g_8703b, 2052 /* REG_BTG_SEL doesn't seem to have a counterpart in the 2053 * vendor driver. Mathematically it's REG_PAD_CTRL1 + 3. 2054 * 2055 * It is used in the cardemu_to_act power sequence by though 2056 * (by address, 0x0067), comment: "0x67[0] = 0 to disable 2057 * BT_GPS_SEL pins" That seems to fit. 2058 */ 2059 .btg_reg = NULL, 2060 /* These registers are used to read (and print) from if 2061 * CONFIG_RTW88_DEBUGFS is enabled. 2062 */ 2063 .coex_info_hw_regs_num = 0, 2064 .coex_info_hw_regs = NULL, 2065 }; 2066 EXPORT_SYMBOL(rtw8703b_hw_spec); 2067 2068 MODULE_FIRMWARE("rtw88/rtw8703b_fw.bin"); 2069 MODULE_FIRMWARE("rtw88/rtw8703b_wow_fw.bin"); 2070 2071 MODULE_AUTHOR("Fiona Klute <fiona.klute@gmx.de>"); 2072 MODULE_DESCRIPTION("Realtek 802.11n wireless 8703b driver"); 2073 MODULE_LICENSE("Dual BSD/GPL"); 2074