1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #if defined(__FreeBSD__) 6 #define LINUXKPI_PARAM_PREFIX rtw88_pci_ 7 #endif 8 9 #include <linux/module.h> 10 #include <linux/pci.h> 11 #include "main.h" 12 #include "pci.h" 13 #include "reg.h" 14 #include "tx.h" 15 #include "rx.h" 16 #include "fw.h" 17 #include "ps.h" 18 #include "debug.h" 19 #if defined(__FreeBSD__) 20 #include <linux/pm.h> 21 #endif 22 23 static bool rtw_disable_msi; 24 static bool rtw_pci_disable_aspm; 25 module_param_named(disable_msi, rtw_disable_msi, bool, 0644); 26 module_param_named(disable_aspm, rtw_pci_disable_aspm, bool, 0644); 27 MODULE_PARM_DESC(disable_msi, "Set Y to disable MSI interrupt support"); 28 MODULE_PARM_DESC(disable_aspm, "Set Y to disable PCI ASPM support"); 29 30 static u32 rtw_pci_tx_queue_idx_addr[] = { 31 [RTW_TX_QUEUE_BK] = RTK_PCI_TXBD_IDX_BKQ, 32 [RTW_TX_QUEUE_BE] = RTK_PCI_TXBD_IDX_BEQ, 33 [RTW_TX_QUEUE_VI] = RTK_PCI_TXBD_IDX_VIQ, 34 [RTW_TX_QUEUE_VO] = RTK_PCI_TXBD_IDX_VOQ, 35 [RTW_TX_QUEUE_MGMT] = RTK_PCI_TXBD_IDX_MGMTQ, 36 [RTW_TX_QUEUE_HI0] = RTK_PCI_TXBD_IDX_HI0Q, 37 [RTW_TX_QUEUE_H2C] = RTK_PCI_TXBD_IDX_H2CQ, 38 }; 39 40 static u8 rtw_pci_get_tx_qsel(struct sk_buff *skb, u8 queue) 41 { 42 switch (queue) { 43 case RTW_TX_QUEUE_BCN: 44 return TX_DESC_QSEL_BEACON; 45 case RTW_TX_QUEUE_H2C: 46 return TX_DESC_QSEL_H2C; 47 case RTW_TX_QUEUE_MGMT: 48 return TX_DESC_QSEL_MGMT; 49 case RTW_TX_QUEUE_HI0: 50 return TX_DESC_QSEL_HIGH; 51 default: 52 return skb->priority; 53 } 54 }; 55 56 static u8 rtw_pci_read8(struct rtw_dev *rtwdev, u32 addr) 57 { 58 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 59 60 #if defined(__linux__) 61 return readb(rtwpci->mmap + addr); 62 #elif defined(__FreeBSD__) 63 u8 val; 64 65 val = bus_read_1((struct resource *)rtwpci->mmap, addr); 66 rtw_dbg(rtwdev, RTW_DBG_IO_RW, "R08 (%#010x) -> %#04x\n", addr, val); 67 return (val); 68 #endif 69 } 70 71 static u16 rtw_pci_read16(struct rtw_dev *rtwdev, u32 addr) 72 { 73 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 74 75 #if defined(__linux__) 76 return readw(rtwpci->mmap + addr); 77 #elif defined(__FreeBSD__) 78 u16 val; 79 80 val = bus_read_2((struct resource *)rtwpci->mmap, addr); 81 rtw_dbg(rtwdev, RTW_DBG_IO_RW, "R16 (%#010x) -> %#06x\n", addr, val); 82 return (val); 83 #endif 84 } 85 86 static u32 rtw_pci_read32(struct rtw_dev *rtwdev, u32 addr) 87 { 88 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 89 90 #if defined(__linux__) 91 return readl(rtwpci->mmap + addr); 92 #elif defined(__FreeBSD__) 93 u32 val; 94 95 val = bus_read_4((struct resource *)rtwpci->mmap, addr); 96 rtw_dbg(rtwdev, RTW_DBG_IO_RW, "R32 (%#010x) -> %#010x\n", addr, val); 97 return (val); 98 #endif 99 } 100 101 static void rtw_pci_write8(struct rtw_dev *rtwdev, u32 addr, u8 val) 102 { 103 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 104 105 #if defined(__linux__) 106 writeb(val, rtwpci->mmap + addr); 107 #elif defined(__FreeBSD__) 108 rtw_dbg(rtwdev, RTW_DBG_IO_RW, "W08 (%#010x) <- %#04x\n", addr, val); 109 return (bus_write_1((struct resource *)rtwpci->mmap, addr, val)); 110 #endif 111 } 112 113 static void rtw_pci_write16(struct rtw_dev *rtwdev, u32 addr, u16 val) 114 { 115 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 116 117 #if defined(__linux__) 118 writew(val, rtwpci->mmap + addr); 119 #elif defined(__FreeBSD__) 120 rtw_dbg(rtwdev, RTW_DBG_IO_RW, "W16 (%#010x) <- %#06x\n", addr, val); 121 return (bus_write_2((struct resource *)rtwpci->mmap, addr, val)); 122 #endif 123 } 124 125 static void rtw_pci_write32(struct rtw_dev *rtwdev, u32 addr, u32 val) 126 { 127 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 128 129 #if defined(__linux__) 130 writel(val, rtwpci->mmap + addr); 131 #elif defined(__FreeBSD__) 132 rtw_dbg(rtwdev, RTW_DBG_IO_RW, "W32 (%#010x) <- %#010x\n", addr, val); 133 return (bus_write_4((struct resource *)rtwpci->mmap, addr, val)); 134 #endif 135 } 136 137 #if defined(__linux__) && 0 138 static inline void *rtw_pci_get_tx_desc(struct rtw_pci_tx_ring *tx_ring, u8 idx) 139 { 140 int offset = tx_ring->r.desc_size * idx; 141 142 return tx_ring->r.head + offset; 143 } 144 #endif 145 146 static void rtw_pci_free_tx_ring_skbs(struct rtw_dev *rtwdev, 147 struct rtw_pci_tx_ring *tx_ring) 148 { 149 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 150 struct rtw_pci_tx_data *tx_data; 151 struct sk_buff *skb, *tmp; 152 dma_addr_t dma; 153 154 /* free every skb remained in tx list */ 155 skb_queue_walk_safe(&tx_ring->queue, skb, tmp) { 156 __skb_unlink(skb, &tx_ring->queue); 157 tx_data = rtw_pci_get_tx_data(skb); 158 dma = tx_data->dma; 159 160 dma_unmap_single(&pdev->dev, dma, skb->len, DMA_TO_DEVICE); 161 dev_kfree_skb_any(skb); 162 } 163 } 164 165 static void rtw_pci_free_tx_ring(struct rtw_dev *rtwdev, 166 struct rtw_pci_tx_ring *tx_ring) 167 { 168 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 169 u8 *head = tx_ring->r.head; 170 u32 len = tx_ring->r.len; 171 int ring_sz = len * tx_ring->r.desc_size; 172 173 rtw_pci_free_tx_ring_skbs(rtwdev, tx_ring); 174 175 /* free the ring itself */ 176 dma_free_coherent(&pdev->dev, ring_sz, head, tx_ring->r.dma); 177 tx_ring->r.head = NULL; 178 } 179 180 static void rtw_pci_free_rx_ring_skbs(struct rtw_dev *rtwdev, 181 struct rtw_pci_rx_ring *rx_ring) 182 { 183 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 184 struct sk_buff *skb; 185 int buf_sz = RTK_PCI_RX_BUF_SIZE; 186 dma_addr_t dma; 187 int i; 188 189 for (i = 0; i < rx_ring->r.len; i++) { 190 skb = rx_ring->buf[i]; 191 if (!skb) 192 continue; 193 194 dma = *((dma_addr_t *)skb->cb); 195 dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE); 196 dev_kfree_skb(skb); 197 rx_ring->buf[i] = NULL; 198 } 199 } 200 201 static void rtw_pci_free_rx_ring(struct rtw_dev *rtwdev, 202 struct rtw_pci_rx_ring *rx_ring) 203 { 204 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 205 u8 *head = rx_ring->r.head; 206 int ring_sz = rx_ring->r.desc_size * rx_ring->r.len; 207 208 rtw_pci_free_rx_ring_skbs(rtwdev, rx_ring); 209 210 dma_free_coherent(&pdev->dev, ring_sz, head, rx_ring->r.dma); 211 } 212 213 static void rtw_pci_free_trx_ring(struct rtw_dev *rtwdev) 214 { 215 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 216 struct rtw_pci_tx_ring *tx_ring; 217 struct rtw_pci_rx_ring *rx_ring; 218 int i; 219 220 for (i = 0; i < RTK_MAX_TX_QUEUE_NUM; i++) { 221 tx_ring = &rtwpci->tx_rings[i]; 222 rtw_pci_free_tx_ring(rtwdev, tx_ring); 223 } 224 225 for (i = 0; i < RTK_MAX_RX_QUEUE_NUM; i++) { 226 rx_ring = &rtwpci->rx_rings[i]; 227 rtw_pci_free_rx_ring(rtwdev, rx_ring); 228 } 229 } 230 231 static int rtw_pci_init_tx_ring(struct rtw_dev *rtwdev, 232 struct rtw_pci_tx_ring *tx_ring, 233 u8 desc_size, u32 len) 234 { 235 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 236 int ring_sz = desc_size * len; 237 dma_addr_t dma; 238 u8 *head; 239 240 if (len > TRX_BD_IDX_MASK) { 241 rtw_err(rtwdev, "len %d exceeds maximum TX entries\n", len); 242 return -EINVAL; 243 } 244 245 head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); 246 if (!head) { 247 rtw_err(rtwdev, "failed to allocate tx ring\n"); 248 return -ENOMEM; 249 } 250 251 skb_queue_head_init(&tx_ring->queue); 252 tx_ring->r.head = head; 253 tx_ring->r.dma = dma; 254 tx_ring->r.len = len; 255 tx_ring->r.desc_size = desc_size; 256 tx_ring->r.wp = 0; 257 tx_ring->r.rp = 0; 258 259 return 0; 260 } 261 262 static int rtw_pci_reset_rx_desc(struct rtw_dev *rtwdev, struct sk_buff *skb, 263 struct rtw_pci_rx_ring *rx_ring, 264 u32 idx, u32 desc_sz) 265 { 266 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 267 struct rtw_pci_rx_buffer_desc *buf_desc; 268 int buf_sz = RTK_PCI_RX_BUF_SIZE; 269 dma_addr_t dma; 270 271 if (!skb) 272 return -EINVAL; 273 274 dma = dma_map_single(&pdev->dev, skb->data, buf_sz, DMA_FROM_DEVICE); 275 if (dma_mapping_error(&pdev->dev, dma)) 276 return -EBUSY; 277 278 *((dma_addr_t *)skb->cb) = dma; 279 buf_desc = (struct rtw_pci_rx_buffer_desc *)(rx_ring->r.head + 280 idx * desc_sz); 281 memset(buf_desc, 0, sizeof(*buf_desc)); 282 buf_desc->buf_size = cpu_to_le16(RTK_PCI_RX_BUF_SIZE); 283 buf_desc->dma = cpu_to_le32(dma); 284 285 return 0; 286 } 287 288 static void rtw_pci_sync_rx_desc_device(struct rtw_dev *rtwdev, dma_addr_t dma, 289 struct rtw_pci_rx_ring *rx_ring, 290 u32 idx, u32 desc_sz) 291 { 292 struct device *dev = rtwdev->dev; 293 struct rtw_pci_rx_buffer_desc *buf_desc; 294 int buf_sz = RTK_PCI_RX_BUF_SIZE; 295 296 dma_sync_single_for_device(dev, dma, buf_sz, DMA_FROM_DEVICE); 297 298 buf_desc = (struct rtw_pci_rx_buffer_desc *)(rx_ring->r.head + 299 idx * desc_sz); 300 memset(buf_desc, 0, sizeof(*buf_desc)); 301 buf_desc->buf_size = cpu_to_le16(RTK_PCI_RX_BUF_SIZE); 302 buf_desc->dma = cpu_to_le32(dma); 303 } 304 305 static int rtw_pci_init_rx_ring(struct rtw_dev *rtwdev, 306 struct rtw_pci_rx_ring *rx_ring, 307 u8 desc_size, u32 len) 308 { 309 struct pci_dev *pdev = to_pci_dev(rtwdev->dev); 310 struct sk_buff *skb = NULL; 311 dma_addr_t dma; 312 u8 *head; 313 int ring_sz = desc_size * len; 314 int buf_sz = RTK_PCI_RX_BUF_SIZE; 315 int i, allocated; 316 int ret = 0; 317 318 head = dma_alloc_coherent(&pdev->dev, ring_sz, &dma, GFP_KERNEL); 319 if (!head) { 320 rtw_err(rtwdev, "failed to allocate rx ring\n"); 321 return -ENOMEM; 322 } 323 rx_ring->r.head = head; 324 325 for (i = 0; i < len; i++) { 326 skb = dev_alloc_skb(buf_sz); 327 if (!skb) { 328 allocated = i; 329 ret = -ENOMEM; 330 goto err_out; 331 } 332 333 memset(skb->data, 0, buf_sz); 334 rx_ring->buf[i] = skb; 335 ret = rtw_pci_reset_rx_desc(rtwdev, skb, rx_ring, i, desc_size); 336 if (ret) { 337 allocated = i; 338 dev_kfree_skb_any(skb); 339 goto err_out; 340 } 341 } 342 343 rx_ring->r.dma = dma; 344 rx_ring->r.len = len; 345 rx_ring->r.desc_size = desc_size; 346 rx_ring->r.wp = 0; 347 rx_ring->r.rp = 0; 348 349 return 0; 350 351 err_out: 352 for (i = 0; i < allocated; i++) { 353 skb = rx_ring->buf[i]; 354 if (!skb) 355 continue; 356 dma = *((dma_addr_t *)skb->cb); 357 dma_unmap_single(&pdev->dev, dma, buf_sz, DMA_FROM_DEVICE); 358 dev_kfree_skb_any(skb); 359 rx_ring->buf[i] = NULL; 360 } 361 dma_free_coherent(&pdev->dev, ring_sz, head, dma); 362 363 rtw_err(rtwdev, "failed to init rx buffer\n"); 364 365 return ret; 366 } 367 368 static int rtw_pci_init_trx_ring(struct rtw_dev *rtwdev) 369 { 370 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 371 struct rtw_pci_tx_ring *tx_ring; 372 struct rtw_pci_rx_ring *rx_ring; 373 struct rtw_chip_info *chip = rtwdev->chip; 374 int i = 0, j = 0, tx_alloced = 0, rx_alloced = 0; 375 int tx_desc_size, rx_desc_size; 376 u32 len; 377 int ret; 378 379 tx_desc_size = chip->tx_buf_desc_sz; 380 381 for (i = 0; i < RTK_MAX_TX_QUEUE_NUM; i++) { 382 tx_ring = &rtwpci->tx_rings[i]; 383 len = max_num_of_tx_queue(i); 384 ret = rtw_pci_init_tx_ring(rtwdev, tx_ring, tx_desc_size, len); 385 if (ret) 386 goto out; 387 } 388 389 rx_desc_size = chip->rx_buf_desc_sz; 390 391 for (j = 0; j < RTK_MAX_RX_QUEUE_NUM; j++) { 392 rx_ring = &rtwpci->rx_rings[j]; 393 ret = rtw_pci_init_rx_ring(rtwdev, rx_ring, rx_desc_size, 394 RTK_MAX_RX_DESC_NUM); 395 if (ret) 396 goto out; 397 } 398 399 return 0; 400 401 out: 402 tx_alloced = i; 403 for (i = 0; i < tx_alloced; i++) { 404 tx_ring = &rtwpci->tx_rings[i]; 405 rtw_pci_free_tx_ring(rtwdev, tx_ring); 406 } 407 408 rx_alloced = j; 409 for (j = 0; j < rx_alloced; j++) { 410 rx_ring = &rtwpci->rx_rings[j]; 411 rtw_pci_free_rx_ring(rtwdev, rx_ring); 412 } 413 414 return ret; 415 } 416 417 static void rtw_pci_deinit(struct rtw_dev *rtwdev) 418 { 419 rtw_pci_free_trx_ring(rtwdev); 420 } 421 422 static int rtw_pci_init(struct rtw_dev *rtwdev) 423 { 424 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 425 int ret = 0; 426 427 rtwpci->irq_mask[0] = IMR_HIGHDOK | 428 IMR_MGNTDOK | 429 IMR_BKDOK | 430 IMR_BEDOK | 431 IMR_VIDOK | 432 IMR_VODOK | 433 IMR_ROK | 434 IMR_BCNDMAINT_E | 435 IMR_C2HCMD | 436 0; 437 rtwpci->irq_mask[1] = IMR_TXFOVW | 438 0; 439 rtwpci->irq_mask[3] = IMR_H2CDOK | 440 0; 441 spin_lock_init(&rtwpci->irq_lock); 442 spin_lock_init(&rtwpci->hwirq_lock); 443 ret = rtw_pci_init_trx_ring(rtwdev); 444 445 return ret; 446 } 447 448 static void rtw_pci_reset_buf_desc(struct rtw_dev *rtwdev) 449 { 450 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 451 u32 len; 452 u8 tmp; 453 dma_addr_t dma; 454 455 tmp = rtw_read8(rtwdev, RTK_PCI_CTRL + 3); 456 rtw_write8(rtwdev, RTK_PCI_CTRL + 3, tmp | 0xf7); 457 458 dma = rtwpci->tx_rings[RTW_TX_QUEUE_BCN].r.dma; 459 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_BCNQ, dma); 460 461 if (!rtw_chip_wcpu_11n(rtwdev)) { 462 len = rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.len; 463 dma = rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.dma; 464 rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.rp = 0; 465 rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.wp = 0; 466 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_H2CQ, len & TRX_BD_IDX_MASK); 467 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_H2CQ, dma); 468 } 469 470 len = rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.len; 471 dma = rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.dma; 472 rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.rp = 0; 473 rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.wp = 0; 474 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_BKQ, len & TRX_BD_IDX_MASK); 475 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_BKQ, dma); 476 477 len = rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.len; 478 dma = rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.dma; 479 rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.rp = 0; 480 rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.wp = 0; 481 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_BEQ, len & TRX_BD_IDX_MASK); 482 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_BEQ, dma); 483 484 len = rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.len; 485 dma = rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.dma; 486 rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.rp = 0; 487 rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.wp = 0; 488 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_VOQ, len & TRX_BD_IDX_MASK); 489 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_VOQ, dma); 490 491 len = rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.len; 492 dma = rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.dma; 493 rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.rp = 0; 494 rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.wp = 0; 495 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_VIQ, len & TRX_BD_IDX_MASK); 496 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_VIQ, dma); 497 498 len = rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.len; 499 dma = rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.dma; 500 rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.rp = 0; 501 rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.wp = 0; 502 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_MGMTQ, len & TRX_BD_IDX_MASK); 503 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_MGMTQ, dma); 504 505 len = rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.len; 506 dma = rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.dma; 507 rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.rp = 0; 508 rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.wp = 0; 509 rtw_write16(rtwdev, RTK_PCI_TXBD_NUM_HI0Q, len & TRX_BD_IDX_MASK); 510 rtw_write32(rtwdev, RTK_PCI_TXBD_DESA_HI0Q, dma); 511 512 len = rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.len; 513 dma = rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.dma; 514 rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.rp = 0; 515 rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.wp = 0; 516 rtw_write16(rtwdev, RTK_PCI_RXBD_NUM_MPDUQ, len & TRX_BD_IDX_MASK); 517 rtw_write32(rtwdev, RTK_PCI_RXBD_DESA_MPDUQ, dma); 518 519 /* reset read/write point */ 520 rtw_write32(rtwdev, RTK_PCI_TXBD_RWPTR_CLR, 0xffffffff); 521 522 /* reset H2C Queue index in a single write */ 523 if (rtw_chip_wcpu_11ac(rtwdev)) 524 rtw_write32_set(rtwdev, RTK_PCI_TXBD_H2CQ_CSR, 525 BIT_CLR_H2CQ_HOST_IDX | BIT_CLR_H2CQ_HW_IDX); 526 } 527 528 static void rtw_pci_reset_trx_ring(struct rtw_dev *rtwdev) 529 { 530 rtw_pci_reset_buf_desc(rtwdev); 531 } 532 533 static void rtw_pci_enable_interrupt(struct rtw_dev *rtwdev, 534 struct rtw_pci *rtwpci, bool exclude_rx) 535 { 536 unsigned long flags; 537 u32 imr0_unmask = exclude_rx ? IMR_ROK : 0; 538 539 spin_lock_irqsave(&rtwpci->hwirq_lock, flags); 540 541 rtw_write32(rtwdev, RTK_PCI_HIMR0, rtwpci->irq_mask[0] & ~imr0_unmask); 542 rtw_write32(rtwdev, RTK_PCI_HIMR1, rtwpci->irq_mask[1]); 543 if (rtw_chip_wcpu_11ac(rtwdev)) 544 rtw_write32(rtwdev, RTK_PCI_HIMR3, rtwpci->irq_mask[3]); 545 546 rtwpci->irq_enabled = true; 547 548 spin_unlock_irqrestore(&rtwpci->hwirq_lock, flags); 549 } 550 551 static void rtw_pci_disable_interrupt(struct rtw_dev *rtwdev, 552 struct rtw_pci *rtwpci) 553 { 554 unsigned long flags; 555 556 spin_lock_irqsave(&rtwpci->hwirq_lock, flags); 557 558 if (!rtwpci->irq_enabled) 559 goto out; 560 561 rtw_write32(rtwdev, RTK_PCI_HIMR0, 0); 562 rtw_write32(rtwdev, RTK_PCI_HIMR1, 0); 563 if (rtw_chip_wcpu_11ac(rtwdev)) 564 rtw_write32(rtwdev, RTK_PCI_HIMR3, 0); 565 566 rtwpci->irq_enabled = false; 567 568 out: 569 spin_unlock_irqrestore(&rtwpci->hwirq_lock, flags); 570 } 571 572 static void rtw_pci_dma_reset(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci) 573 { 574 /* reset dma and rx tag */ 575 rtw_write32_set(rtwdev, RTK_PCI_CTRL, 576 BIT_RST_TRXDMA_INTF | BIT_RX_TAG_EN); 577 rtwpci->rx_tag = 0; 578 } 579 580 static int rtw_pci_setup(struct rtw_dev *rtwdev) 581 { 582 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 583 584 rtw_pci_reset_trx_ring(rtwdev); 585 rtw_pci_dma_reset(rtwdev, rtwpci); 586 587 return 0; 588 } 589 590 static void rtw_pci_dma_release(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci) 591 { 592 struct rtw_pci_tx_ring *tx_ring; 593 u8 queue; 594 595 rtw_pci_reset_trx_ring(rtwdev); 596 for (queue = 0; queue < RTK_MAX_TX_QUEUE_NUM; queue++) { 597 tx_ring = &rtwpci->tx_rings[queue]; 598 rtw_pci_free_tx_ring_skbs(rtwdev, tx_ring); 599 } 600 } 601 602 static void rtw_pci_napi_start(struct rtw_dev *rtwdev) 603 { 604 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 605 606 if (test_and_set_bit(RTW_PCI_FLAG_NAPI_RUNNING, rtwpci->flags)) 607 return; 608 609 napi_enable(&rtwpci->napi); 610 } 611 612 static void rtw_pci_napi_stop(struct rtw_dev *rtwdev) 613 { 614 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 615 616 if (!test_and_clear_bit(RTW_PCI_FLAG_NAPI_RUNNING, rtwpci->flags)) 617 return; 618 619 napi_synchronize(&rtwpci->napi); 620 napi_disable(&rtwpci->napi); 621 } 622 623 static int rtw_pci_start(struct rtw_dev *rtwdev) 624 { 625 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 626 627 rtw_pci_napi_start(rtwdev); 628 629 spin_lock_bh(&rtwpci->irq_lock); 630 rtwpci->running = true; 631 rtw_pci_enable_interrupt(rtwdev, rtwpci, false); 632 spin_unlock_bh(&rtwpci->irq_lock); 633 634 return 0; 635 } 636 637 static void rtw_pci_stop(struct rtw_dev *rtwdev) 638 { 639 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 640 struct pci_dev *pdev = rtwpci->pdev; 641 642 spin_lock_bh(&rtwpci->irq_lock); 643 rtwpci->running = false; 644 rtw_pci_disable_interrupt(rtwdev, rtwpci); 645 spin_unlock_bh(&rtwpci->irq_lock); 646 647 synchronize_irq(pdev->irq); 648 rtw_pci_napi_stop(rtwdev); 649 650 spin_lock_bh(&rtwpci->irq_lock); 651 rtw_pci_dma_release(rtwdev, rtwpci); 652 spin_unlock_bh(&rtwpci->irq_lock); 653 } 654 655 static void rtw_pci_deep_ps_enter(struct rtw_dev *rtwdev) 656 { 657 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 658 struct rtw_pci_tx_ring *tx_ring; 659 bool tx_empty = true; 660 u8 queue; 661 662 if (rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_TX_WAKE)) 663 goto enter_deep_ps; 664 665 lockdep_assert_held(&rtwpci->irq_lock); 666 667 /* Deep PS state is not allowed to TX-DMA */ 668 for (queue = 0; queue < RTK_MAX_TX_QUEUE_NUM; queue++) { 669 /* BCN queue is rsvd page, does not have DMA interrupt 670 * H2C queue is managed by firmware 671 */ 672 if (queue == RTW_TX_QUEUE_BCN || 673 queue == RTW_TX_QUEUE_H2C) 674 continue; 675 676 tx_ring = &rtwpci->tx_rings[queue]; 677 678 /* check if there is any skb DMAing */ 679 if (skb_queue_len(&tx_ring->queue)) { 680 tx_empty = false; 681 break; 682 } 683 } 684 685 if (!tx_empty) { 686 rtw_dbg(rtwdev, RTW_DBG_PS, 687 "TX path not empty, cannot enter deep power save state\n"); 688 return; 689 } 690 enter_deep_ps: 691 set_bit(RTW_FLAG_LEISURE_PS_DEEP, rtwdev->flags); 692 rtw_power_mode_change(rtwdev, true); 693 } 694 695 static void rtw_pci_deep_ps_leave(struct rtw_dev *rtwdev) 696 { 697 #if defined(__linux__) 698 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 699 700 lockdep_assert_held(&rtwpci->irq_lock); 701 #elif defined(__FreeBSD__) 702 lockdep_assert_held(&((struct rtw_pci *)rtwdev->priv)->irq_lock); 703 #endif 704 705 if (test_and_clear_bit(RTW_FLAG_LEISURE_PS_DEEP, rtwdev->flags)) 706 rtw_power_mode_change(rtwdev, false); 707 } 708 709 static void rtw_pci_deep_ps(struct rtw_dev *rtwdev, bool enter) 710 { 711 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 712 713 spin_lock_bh(&rtwpci->irq_lock); 714 715 if (enter && !test_bit(RTW_FLAG_LEISURE_PS_DEEP, rtwdev->flags)) 716 rtw_pci_deep_ps_enter(rtwdev); 717 718 if (!enter && test_bit(RTW_FLAG_LEISURE_PS_DEEP, rtwdev->flags)) 719 rtw_pci_deep_ps_leave(rtwdev); 720 721 spin_unlock_bh(&rtwpci->irq_lock); 722 } 723 724 static u8 ac_to_hwq[] = { 725 [IEEE80211_AC_VO] = RTW_TX_QUEUE_VO, 726 [IEEE80211_AC_VI] = RTW_TX_QUEUE_VI, 727 [IEEE80211_AC_BE] = RTW_TX_QUEUE_BE, 728 [IEEE80211_AC_BK] = RTW_TX_QUEUE_BK, 729 }; 730 731 #if defined(__linux__) 732 static_assert(ARRAY_SIZE(ac_to_hwq) == IEEE80211_NUM_ACS); 733 #elif defined(__FreeBSD__) 734 rtw88_static_assert(ARRAY_SIZE(ac_to_hwq) == IEEE80211_NUM_ACS); 735 #endif 736 737 static u8 rtw_hw_queue_mapping(struct sk_buff *skb) 738 { 739 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 740 __le16 fc = hdr->frame_control; 741 u8 q_mapping = skb_get_queue_mapping(skb); 742 u8 queue; 743 744 if (unlikely(ieee80211_is_beacon(fc))) 745 queue = RTW_TX_QUEUE_BCN; 746 else if (unlikely(ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))) 747 queue = RTW_TX_QUEUE_MGMT; 748 else if (WARN_ON_ONCE(q_mapping >= ARRAY_SIZE(ac_to_hwq))) 749 queue = ac_to_hwq[IEEE80211_AC_BE]; 750 else 751 queue = ac_to_hwq[q_mapping]; 752 753 return queue; 754 } 755 756 static void rtw_pci_release_rsvd_page(struct rtw_pci *rtwpci, 757 struct rtw_pci_tx_ring *ring) 758 { 759 struct sk_buff *prev = skb_dequeue(&ring->queue); 760 struct rtw_pci_tx_data *tx_data; 761 dma_addr_t dma; 762 763 if (!prev) 764 return; 765 766 tx_data = rtw_pci_get_tx_data(prev); 767 dma = tx_data->dma; 768 dma_unmap_single(&rtwpci->pdev->dev, dma, prev->len, DMA_TO_DEVICE); 769 dev_kfree_skb_any(prev); 770 } 771 772 static void rtw_pci_dma_check(struct rtw_dev *rtwdev, 773 struct rtw_pci_rx_ring *rx_ring, 774 u32 idx) 775 { 776 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 777 struct rtw_chip_info *chip = rtwdev->chip; 778 struct rtw_pci_rx_buffer_desc *buf_desc; 779 u32 desc_sz = chip->rx_buf_desc_sz; 780 u16 total_pkt_size; 781 782 buf_desc = (struct rtw_pci_rx_buffer_desc *)(rx_ring->r.head + 783 idx * desc_sz); 784 total_pkt_size = le16_to_cpu(buf_desc->total_pkt_size); 785 786 /* rx tag mismatch, throw a warning */ 787 if (total_pkt_size != rtwpci->rx_tag) 788 rtw_warn(rtwdev, "pci bus timeout, check dma status\n"); 789 790 rtwpci->rx_tag = (rtwpci->rx_tag + 1) % RX_TAG_MAX; 791 } 792 793 static u32 __pci_get_hw_tx_ring_rp(struct rtw_dev *rtwdev, u8 pci_q) 794 { 795 u32 bd_idx_addr = rtw_pci_tx_queue_idx_addr[pci_q]; 796 u32 bd_idx = rtw_read16(rtwdev, bd_idx_addr + 2); 797 798 return FIELD_GET(TRX_BD_IDX_MASK, bd_idx); 799 } 800 801 static void __pci_flush_queue(struct rtw_dev *rtwdev, u8 pci_q, bool drop) 802 { 803 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 804 struct rtw_pci_tx_ring *ring = &rtwpci->tx_rings[pci_q]; 805 u32 cur_rp; 806 u8 i; 807 808 /* Because the time taked by the I/O in __pci_get_hw_tx_ring_rp is a 809 * bit dynamic, it's hard to define a reasonable fixed total timeout to 810 * use read_poll_timeout* helper. Instead, we can ensure a reasonable 811 * polling times, so we just use for loop with udelay here. 812 */ 813 for (i = 0; i < 30; i++) { 814 cur_rp = __pci_get_hw_tx_ring_rp(rtwdev, pci_q); 815 if (cur_rp == ring->r.wp) 816 return; 817 818 udelay(1); 819 } 820 821 if (!drop) 822 rtw_warn(rtwdev, "timed out to flush pci tx ring[%d]\n", pci_q); 823 } 824 825 static void __rtw_pci_flush_queues(struct rtw_dev *rtwdev, u32 pci_queues, 826 bool drop) 827 { 828 u8 q; 829 830 for (q = 0; q < RTK_MAX_TX_QUEUE_NUM; q++) { 831 /* It may be not necessary to flush BCN and H2C tx queues. */ 832 if (q == RTW_TX_QUEUE_BCN || q == RTW_TX_QUEUE_H2C) 833 continue; 834 835 if (pci_queues & BIT(q)) 836 __pci_flush_queue(rtwdev, q, drop); 837 } 838 } 839 840 static void rtw_pci_flush_queues(struct rtw_dev *rtwdev, u32 queues, bool drop) 841 { 842 u32 pci_queues = 0; 843 u8 i; 844 845 /* If all of the hardware queues are requested to flush, 846 * flush all of the pci queues. 847 */ 848 if (queues == BIT(rtwdev->hw->queues) - 1) { 849 pci_queues = BIT(RTK_MAX_TX_QUEUE_NUM) - 1; 850 } else { 851 for (i = 0; i < rtwdev->hw->queues; i++) 852 if (queues & BIT(i)) 853 pci_queues |= BIT(ac_to_hwq[i]); 854 } 855 856 __rtw_pci_flush_queues(rtwdev, pci_queues, drop); 857 } 858 859 static void rtw_pci_tx_kick_off_queue(struct rtw_dev *rtwdev, u8 queue) 860 { 861 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 862 struct rtw_pci_tx_ring *ring; 863 u32 bd_idx; 864 865 ring = &rtwpci->tx_rings[queue]; 866 bd_idx = rtw_pci_tx_queue_idx_addr[queue]; 867 868 spin_lock_bh(&rtwpci->irq_lock); 869 if (!rtw_fw_feature_check(&rtwdev->fw, FW_FEATURE_TX_WAKE)) 870 rtw_pci_deep_ps_leave(rtwdev); 871 rtw_write16(rtwdev, bd_idx, ring->r.wp & TRX_BD_IDX_MASK); 872 spin_unlock_bh(&rtwpci->irq_lock); 873 } 874 875 static void rtw_pci_tx_kick_off(struct rtw_dev *rtwdev) 876 { 877 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 878 u8 queue; 879 880 for (queue = 0; queue < RTK_MAX_TX_QUEUE_NUM; queue++) 881 if (test_and_clear_bit(queue, rtwpci->tx_queued)) 882 rtw_pci_tx_kick_off_queue(rtwdev, queue); 883 } 884 885 static int rtw_pci_tx_write_data(struct rtw_dev *rtwdev, 886 struct rtw_tx_pkt_info *pkt_info, 887 struct sk_buff *skb, u8 queue) 888 { 889 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 890 struct rtw_chip_info *chip = rtwdev->chip; 891 struct rtw_pci_tx_ring *ring; 892 struct rtw_pci_tx_data *tx_data; 893 dma_addr_t dma; 894 u32 tx_pkt_desc_sz = chip->tx_pkt_desc_sz; 895 u32 tx_buf_desc_sz = chip->tx_buf_desc_sz; 896 u32 size; 897 u32 psb_len; 898 u8 *pkt_desc; 899 struct rtw_pci_tx_buffer_desc *buf_desc; 900 901 ring = &rtwpci->tx_rings[queue]; 902 903 size = skb->len; 904 905 if (queue == RTW_TX_QUEUE_BCN) 906 rtw_pci_release_rsvd_page(rtwpci, ring); 907 else if (!avail_desc(ring->r.wp, ring->r.rp, ring->r.len)) 908 return -ENOSPC; 909 910 pkt_desc = skb_push(skb, chip->tx_pkt_desc_sz); 911 memset(pkt_desc, 0, tx_pkt_desc_sz); 912 pkt_info->qsel = rtw_pci_get_tx_qsel(skb, queue); 913 rtw_tx_fill_tx_desc(pkt_info, skb); 914 dma = dma_map_single(&rtwpci->pdev->dev, skb->data, skb->len, 915 DMA_TO_DEVICE); 916 if (dma_mapping_error(&rtwpci->pdev->dev, dma)) 917 return -EBUSY; 918 919 /* after this we got dma mapped, there is no way back */ 920 buf_desc = get_tx_buffer_desc(ring, tx_buf_desc_sz); 921 memset(buf_desc, 0, tx_buf_desc_sz); 922 psb_len = (skb->len - 1) / 128 + 1; 923 if (queue == RTW_TX_QUEUE_BCN) 924 psb_len |= 1 << RTK_PCI_TXBD_OWN_OFFSET; 925 926 buf_desc[0].psb_len = cpu_to_le16(psb_len); 927 buf_desc[0].buf_size = cpu_to_le16(tx_pkt_desc_sz); 928 buf_desc[0].dma = cpu_to_le32(dma); 929 buf_desc[1].buf_size = cpu_to_le16(size); 930 buf_desc[1].dma = cpu_to_le32(dma + tx_pkt_desc_sz); 931 932 tx_data = rtw_pci_get_tx_data(skb); 933 tx_data->dma = dma; 934 tx_data->sn = pkt_info->sn; 935 936 spin_lock_bh(&rtwpci->irq_lock); 937 938 skb_queue_tail(&ring->queue, skb); 939 940 if (queue == RTW_TX_QUEUE_BCN) 941 goto out_unlock; 942 943 /* update write-index, and kick it off later */ 944 set_bit(queue, rtwpci->tx_queued); 945 if (++ring->r.wp >= ring->r.len) 946 ring->r.wp = 0; 947 948 out_unlock: 949 spin_unlock_bh(&rtwpci->irq_lock); 950 951 return 0; 952 } 953 954 static int rtw_pci_write_data_rsvd_page(struct rtw_dev *rtwdev, u8 *buf, 955 u32 size) 956 { 957 struct sk_buff *skb; 958 struct rtw_tx_pkt_info pkt_info = {0}; 959 u8 reg_bcn_work; 960 int ret; 961 962 skb = rtw_tx_write_data_rsvd_page_get(rtwdev, &pkt_info, buf, size); 963 if (!skb) 964 return -ENOMEM; 965 966 ret = rtw_pci_tx_write_data(rtwdev, &pkt_info, skb, RTW_TX_QUEUE_BCN); 967 if (ret) { 968 rtw_err(rtwdev, "failed to write rsvd page data\n"); 969 return ret; 970 } 971 972 /* reserved pages go through beacon queue */ 973 reg_bcn_work = rtw_read8(rtwdev, RTK_PCI_TXBD_BCN_WORK); 974 reg_bcn_work |= BIT_PCI_BCNQ_FLAG; 975 rtw_write8(rtwdev, RTK_PCI_TXBD_BCN_WORK, reg_bcn_work); 976 977 return 0; 978 } 979 980 static int rtw_pci_write_data_h2c(struct rtw_dev *rtwdev, u8 *buf, u32 size) 981 { 982 struct sk_buff *skb; 983 struct rtw_tx_pkt_info pkt_info = {0}; 984 int ret; 985 986 skb = rtw_tx_write_data_h2c_get(rtwdev, &pkt_info, buf, size); 987 if (!skb) 988 return -ENOMEM; 989 990 ret = rtw_pci_tx_write_data(rtwdev, &pkt_info, skb, RTW_TX_QUEUE_H2C); 991 if (ret) { 992 rtw_err(rtwdev, "failed to write h2c data\n"); 993 return ret; 994 } 995 996 rtw_pci_tx_kick_off_queue(rtwdev, RTW_TX_QUEUE_H2C); 997 998 return 0; 999 } 1000 1001 static int rtw_pci_tx_write(struct rtw_dev *rtwdev, 1002 struct rtw_tx_pkt_info *pkt_info, 1003 struct sk_buff *skb) 1004 { 1005 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1006 struct rtw_pci_tx_ring *ring; 1007 u8 queue = rtw_hw_queue_mapping(skb); 1008 int ret; 1009 1010 ret = rtw_pci_tx_write_data(rtwdev, pkt_info, skb, queue); 1011 if (ret) 1012 return ret; 1013 1014 ring = &rtwpci->tx_rings[queue]; 1015 spin_lock_bh(&rtwpci->irq_lock); 1016 if (avail_desc(ring->r.wp, ring->r.rp, ring->r.len) < 2) { 1017 ieee80211_stop_queue(rtwdev->hw, skb_get_queue_mapping(skb)); 1018 ring->queue_stopped = true; 1019 } 1020 spin_unlock_bh(&rtwpci->irq_lock); 1021 1022 return 0; 1023 } 1024 1025 static void rtw_pci_tx_isr(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci, 1026 u8 hw_queue) 1027 { 1028 struct ieee80211_hw *hw = rtwdev->hw; 1029 struct ieee80211_tx_info *info; 1030 struct rtw_pci_tx_ring *ring; 1031 struct rtw_pci_tx_data *tx_data; 1032 struct sk_buff *skb; 1033 u32 count; 1034 u32 bd_idx_addr; 1035 u32 bd_idx, cur_rp, rp_idx; 1036 u16 q_map; 1037 1038 ring = &rtwpci->tx_rings[hw_queue]; 1039 1040 bd_idx_addr = rtw_pci_tx_queue_idx_addr[hw_queue]; 1041 bd_idx = rtw_read32(rtwdev, bd_idx_addr); 1042 cur_rp = bd_idx >> 16; 1043 cur_rp &= TRX_BD_IDX_MASK; 1044 rp_idx = ring->r.rp; 1045 if (cur_rp >= ring->r.rp) 1046 count = cur_rp - ring->r.rp; 1047 else 1048 count = ring->r.len - (ring->r.rp - cur_rp); 1049 1050 while (count--) { 1051 skb = skb_dequeue(&ring->queue); 1052 if (!skb) { 1053 rtw_err(rtwdev, "failed to dequeue %d skb TX queue %d, BD=0x%08x, rp %d -> %d\n", 1054 count, hw_queue, bd_idx, ring->r.rp, cur_rp); 1055 break; 1056 } 1057 tx_data = rtw_pci_get_tx_data(skb); 1058 dma_unmap_single(&rtwpci->pdev->dev, tx_data->dma, skb->len, 1059 DMA_TO_DEVICE); 1060 1061 /* just free command packets from host to card */ 1062 if (hw_queue == RTW_TX_QUEUE_H2C) { 1063 dev_kfree_skb_irq(skb); 1064 continue; 1065 } 1066 1067 if (ring->queue_stopped && 1068 avail_desc(ring->r.wp, rp_idx, ring->r.len) > 4) { 1069 q_map = skb_get_queue_mapping(skb); 1070 ieee80211_wake_queue(hw, q_map); 1071 ring->queue_stopped = false; 1072 } 1073 1074 if (++rp_idx >= ring->r.len) 1075 rp_idx = 0; 1076 1077 skb_pull(skb, rtwdev->chip->tx_pkt_desc_sz); 1078 1079 info = IEEE80211_SKB_CB(skb); 1080 1081 /* enqueue to wait for tx report */ 1082 if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) { 1083 rtw_tx_report_enqueue(rtwdev, skb, tx_data->sn); 1084 continue; 1085 } 1086 1087 /* always ACK for others, then they won't be marked as drop */ 1088 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 1089 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 1090 else 1091 info->flags |= IEEE80211_TX_STAT_ACK; 1092 1093 ieee80211_tx_info_clear_status(info); 1094 ieee80211_tx_status_irqsafe(hw, skb); 1095 } 1096 1097 ring->r.rp = cur_rp; 1098 } 1099 1100 static void rtw_pci_rx_isr(struct rtw_dev *rtwdev) 1101 { 1102 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1103 struct napi_struct *napi = &rtwpci->napi; 1104 1105 napi_schedule(napi); 1106 } 1107 1108 static int rtw_pci_get_hw_rx_ring_nr(struct rtw_dev *rtwdev, 1109 struct rtw_pci *rtwpci) 1110 { 1111 struct rtw_pci_rx_ring *ring; 1112 int count = 0; 1113 u32 tmp, cur_wp; 1114 1115 ring = &rtwpci->rx_rings[RTW_RX_QUEUE_MPDU]; 1116 tmp = rtw_read32(rtwdev, RTK_PCI_RXBD_IDX_MPDUQ); 1117 cur_wp = u32_get_bits(tmp, TRX_BD_HW_IDX_MASK); 1118 if (cur_wp >= ring->r.wp) 1119 count = cur_wp - ring->r.wp; 1120 else 1121 count = ring->r.len - (ring->r.wp - cur_wp); 1122 1123 return count; 1124 } 1125 1126 static u32 rtw_pci_rx_napi(struct rtw_dev *rtwdev, struct rtw_pci *rtwpci, 1127 u8 hw_queue, u32 limit) 1128 { 1129 struct rtw_chip_info *chip = rtwdev->chip; 1130 struct napi_struct *napi = &rtwpci->napi; 1131 struct rtw_pci_rx_ring *ring = &rtwpci->rx_rings[RTW_RX_QUEUE_MPDU]; 1132 struct rtw_rx_pkt_stat pkt_stat; 1133 struct ieee80211_rx_status rx_status; 1134 struct sk_buff *skb, *new; 1135 u32 cur_rp = ring->r.rp; 1136 u32 count, rx_done = 0; 1137 u32 pkt_offset; 1138 u32 pkt_desc_sz = chip->rx_pkt_desc_sz; 1139 u32 buf_desc_sz = chip->rx_buf_desc_sz; 1140 u32 new_len; 1141 u8 *rx_desc; 1142 dma_addr_t dma; 1143 1144 count = rtw_pci_get_hw_rx_ring_nr(rtwdev, rtwpci); 1145 count = min(count, limit); 1146 1147 while (count--) { 1148 rtw_pci_dma_check(rtwdev, ring, cur_rp); 1149 skb = ring->buf[cur_rp]; 1150 dma = *((dma_addr_t *)skb->cb); 1151 dma_sync_single_for_cpu(rtwdev->dev, dma, RTK_PCI_RX_BUF_SIZE, 1152 DMA_FROM_DEVICE); 1153 rx_desc = skb->data; 1154 chip->ops->query_rx_desc(rtwdev, rx_desc, &pkt_stat, &rx_status); 1155 1156 /* offset from rx_desc to payload */ 1157 pkt_offset = pkt_desc_sz + pkt_stat.drv_info_sz + 1158 pkt_stat.shift; 1159 1160 /* allocate a new skb for this frame, 1161 * discard the frame if none available 1162 */ 1163 new_len = pkt_stat.pkt_len + pkt_offset; 1164 new = dev_alloc_skb(new_len); 1165 if (WARN_ONCE(!new, "rx routine starvation\n")) 1166 goto next_rp; 1167 1168 /* put the DMA data including rx_desc from phy to new skb */ 1169 skb_put_data(new, skb->data, new_len); 1170 1171 if (pkt_stat.is_c2h) { 1172 rtw_fw_c2h_cmd_rx_irqsafe(rtwdev, pkt_offset, new); 1173 } else { 1174 /* remove rx_desc */ 1175 skb_pull(new, pkt_offset); 1176 1177 rtw_rx_stats(rtwdev, pkt_stat.vif, new); 1178 memcpy(new->cb, &rx_status, sizeof(rx_status)); 1179 ieee80211_rx_napi(rtwdev->hw, NULL, new, napi); 1180 rx_done++; 1181 } 1182 1183 next_rp: 1184 /* new skb delivered to mac80211, re-enable original skb DMA */ 1185 rtw_pci_sync_rx_desc_device(rtwdev, dma, ring, cur_rp, 1186 buf_desc_sz); 1187 1188 /* host read next element in ring */ 1189 if (++cur_rp >= ring->r.len) 1190 cur_rp = 0; 1191 } 1192 1193 ring->r.rp = cur_rp; 1194 /* 'rp', the last position we have read, is seen as previous posistion 1195 * of 'wp' that is used to calculate 'count' next time. 1196 */ 1197 ring->r.wp = cur_rp; 1198 rtw_write16(rtwdev, RTK_PCI_RXBD_IDX_MPDUQ, ring->r.rp); 1199 1200 return rx_done; 1201 } 1202 1203 static void rtw_pci_irq_recognized(struct rtw_dev *rtwdev, 1204 struct rtw_pci *rtwpci, u32 *irq_status) 1205 { 1206 unsigned long flags; 1207 1208 spin_lock_irqsave(&rtwpci->hwirq_lock, flags); 1209 1210 irq_status[0] = rtw_read32(rtwdev, RTK_PCI_HISR0); 1211 irq_status[1] = rtw_read32(rtwdev, RTK_PCI_HISR1); 1212 if (rtw_chip_wcpu_11ac(rtwdev)) 1213 irq_status[3] = rtw_read32(rtwdev, RTK_PCI_HISR3); 1214 else 1215 irq_status[3] = 0; 1216 irq_status[0] &= rtwpci->irq_mask[0]; 1217 irq_status[1] &= rtwpci->irq_mask[1]; 1218 irq_status[3] &= rtwpci->irq_mask[3]; 1219 rtw_write32(rtwdev, RTK_PCI_HISR0, irq_status[0]); 1220 rtw_write32(rtwdev, RTK_PCI_HISR1, irq_status[1]); 1221 if (rtw_chip_wcpu_11ac(rtwdev)) 1222 rtw_write32(rtwdev, RTK_PCI_HISR3, irq_status[3]); 1223 1224 spin_unlock_irqrestore(&rtwpci->hwirq_lock, flags); 1225 } 1226 1227 static irqreturn_t rtw_pci_interrupt_handler(int irq, void *dev) 1228 { 1229 struct rtw_dev *rtwdev = dev; 1230 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1231 1232 /* disable RTW PCI interrupt to avoid more interrupts before the end of 1233 * thread function 1234 * 1235 * disable HIMR here to also avoid new HISR flag being raised before 1236 * the HISRs have been Write-1-cleared for MSI. If not all of the HISRs 1237 * are cleared, the edge-triggered interrupt will not be generated when 1238 * a new HISR flag is set. 1239 */ 1240 rtw_pci_disable_interrupt(rtwdev, rtwpci); 1241 1242 return IRQ_WAKE_THREAD; 1243 } 1244 1245 static irqreturn_t rtw_pci_interrupt_threadfn(int irq, void *dev) 1246 { 1247 struct rtw_dev *rtwdev = dev; 1248 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1249 u32 irq_status[4]; 1250 bool rx = false; 1251 1252 spin_lock_bh(&rtwpci->irq_lock); 1253 rtw_pci_irq_recognized(rtwdev, rtwpci, irq_status); 1254 1255 if (irq_status[0] & IMR_MGNTDOK) 1256 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_MGMT); 1257 if (irq_status[0] & IMR_HIGHDOK) 1258 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_HI0); 1259 if (irq_status[0] & IMR_BEDOK) 1260 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_BE); 1261 if (irq_status[0] & IMR_BKDOK) 1262 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_BK); 1263 if (irq_status[0] & IMR_VODOK) 1264 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_VO); 1265 if (irq_status[0] & IMR_VIDOK) 1266 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_VI); 1267 if (irq_status[3] & IMR_H2CDOK) 1268 rtw_pci_tx_isr(rtwdev, rtwpci, RTW_TX_QUEUE_H2C); 1269 if (irq_status[0] & IMR_ROK) { 1270 rtw_pci_rx_isr(rtwdev); 1271 rx = true; 1272 } 1273 if (unlikely(irq_status[0] & IMR_C2HCMD)) 1274 rtw_fw_c2h_cmd_isr(rtwdev); 1275 1276 /* all of the jobs for this interrupt have been done */ 1277 if (rtwpci->running) 1278 rtw_pci_enable_interrupt(rtwdev, rtwpci, rx); 1279 spin_unlock_bh(&rtwpci->irq_lock); 1280 1281 return IRQ_HANDLED; 1282 } 1283 1284 static int rtw_pci_io_mapping(struct rtw_dev *rtwdev, 1285 struct pci_dev *pdev) 1286 { 1287 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1288 unsigned long len; 1289 u8 bar_id = 2; 1290 int ret; 1291 1292 ret = pci_request_regions(pdev, KBUILD_MODNAME); 1293 if (ret) { 1294 rtw_err(rtwdev, "failed to request pci regions\n"); 1295 return ret; 1296 } 1297 1298 #if defined(__FreeBSD__) 1299 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 1300 if (ret) { 1301 rtw_err(rtwdev, "failed to set dma mask to 32-bit\n"); 1302 goto err_release_regions; 1303 } 1304 1305 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 1306 if (ret) { 1307 rtw_err(rtwdev, "failed to set consistent dma mask to 32-bit\n"); 1308 goto err_release_regions; 1309 } 1310 #endif 1311 1312 len = pci_resource_len(pdev, bar_id); 1313 #if defined(__FreeBSD__) 1314 linuxkpi_pcim_want_to_use_bus_functions(pdev); 1315 #endif 1316 rtwpci->mmap = pci_iomap(pdev, bar_id, len); 1317 if (!rtwpci->mmap) { 1318 pci_release_regions(pdev); 1319 rtw_err(rtwdev, "failed to map pci memory\n"); 1320 return -ENOMEM; 1321 } 1322 1323 return 0; 1324 #if defined(__FreeBSD__) 1325 err_release_regions: 1326 pci_release_regions(pdev); 1327 return ret; 1328 #endif 1329 } 1330 1331 static void rtw_pci_io_unmapping(struct rtw_dev *rtwdev, 1332 struct pci_dev *pdev) 1333 { 1334 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1335 1336 if (rtwpci->mmap) { 1337 pci_iounmap(pdev, rtwpci->mmap); 1338 pci_release_regions(pdev); 1339 } 1340 } 1341 1342 static void rtw_dbi_write8(struct rtw_dev *rtwdev, u16 addr, u8 data) 1343 { 1344 u16 write_addr; 1345 u16 remainder = addr & ~(BITS_DBI_WREN | BITS_DBI_ADDR_MASK); 1346 u8 flag; 1347 u8 cnt; 1348 1349 write_addr = addr & BITS_DBI_ADDR_MASK; 1350 write_addr |= u16_encode_bits(BIT(remainder), BITS_DBI_WREN); 1351 rtw_write8(rtwdev, REG_DBI_WDATA_V1 + remainder, data); 1352 rtw_write16(rtwdev, REG_DBI_FLAG_V1, write_addr); 1353 rtw_write8(rtwdev, REG_DBI_FLAG_V1 + 2, BIT_DBI_WFLAG >> 16); 1354 1355 for (cnt = 0; cnt < RTW_PCI_WR_RETRY_CNT; cnt++) { 1356 flag = rtw_read8(rtwdev, REG_DBI_FLAG_V1 + 2); 1357 if (flag == 0) 1358 return; 1359 1360 udelay(10); 1361 } 1362 1363 WARN(flag, "failed to write to DBI register, addr=0x%04x\n", addr); 1364 } 1365 1366 static int rtw_dbi_read8(struct rtw_dev *rtwdev, u16 addr, u8 *value) 1367 { 1368 u16 read_addr = addr & BITS_DBI_ADDR_MASK; 1369 u8 flag; 1370 u8 cnt; 1371 1372 rtw_write16(rtwdev, REG_DBI_FLAG_V1, read_addr); 1373 rtw_write8(rtwdev, REG_DBI_FLAG_V1 + 2, BIT_DBI_RFLAG >> 16); 1374 1375 for (cnt = 0; cnt < RTW_PCI_WR_RETRY_CNT; cnt++) { 1376 flag = rtw_read8(rtwdev, REG_DBI_FLAG_V1 + 2); 1377 if (flag == 0) { 1378 read_addr = REG_DBI_RDATA_V1 + (addr & 3); 1379 *value = rtw_read8(rtwdev, read_addr); 1380 return 0; 1381 } 1382 1383 udelay(10); 1384 } 1385 1386 WARN(1, "failed to read DBI register, addr=0x%04x\n", addr); 1387 return -EIO; 1388 } 1389 1390 static void rtw_mdio_write(struct rtw_dev *rtwdev, u8 addr, u16 data, bool g1) 1391 { 1392 u8 page; 1393 u8 wflag; 1394 u8 cnt; 1395 1396 rtw_write16(rtwdev, REG_MDIO_V1, data); 1397 1398 page = addr < RTW_PCI_MDIO_PG_SZ ? 0 : 1; 1399 page += g1 ? RTW_PCI_MDIO_PG_OFFS_G1 : RTW_PCI_MDIO_PG_OFFS_G2; 1400 rtw_write8(rtwdev, REG_PCIE_MIX_CFG, addr & BITS_MDIO_ADDR_MASK); 1401 rtw_write8(rtwdev, REG_PCIE_MIX_CFG + 3, page); 1402 rtw_write32_mask(rtwdev, REG_PCIE_MIX_CFG, BIT_MDIO_WFLAG_V1, 1); 1403 1404 for (cnt = 0; cnt < RTW_PCI_WR_RETRY_CNT; cnt++) { 1405 wflag = rtw_read32_mask(rtwdev, REG_PCIE_MIX_CFG, 1406 BIT_MDIO_WFLAG_V1); 1407 if (wflag == 0) 1408 return; 1409 1410 udelay(10); 1411 } 1412 1413 WARN(wflag, "failed to write to MDIO register, addr=0x%02x\n", addr); 1414 } 1415 1416 static void rtw_pci_clkreq_set(struct rtw_dev *rtwdev, bool enable) 1417 { 1418 u8 value; 1419 int ret; 1420 1421 if (rtw_pci_disable_aspm) 1422 return; 1423 1424 ret = rtw_dbi_read8(rtwdev, RTK_PCIE_LINK_CFG, &value); 1425 if (ret) { 1426 rtw_err(rtwdev, "failed to read CLKREQ_L1, ret=%d", ret); 1427 return; 1428 } 1429 1430 if (enable) 1431 value |= BIT_CLKREQ_SW_EN; 1432 else 1433 value &= ~BIT_CLKREQ_SW_EN; 1434 1435 rtw_dbi_write8(rtwdev, RTK_PCIE_LINK_CFG, value); 1436 } 1437 1438 static void rtw_pci_clkreq_pad_low(struct rtw_dev *rtwdev, bool enable) 1439 { 1440 u8 value; 1441 int ret; 1442 1443 ret = rtw_dbi_read8(rtwdev, RTK_PCIE_LINK_CFG, &value); 1444 if (ret) { 1445 rtw_err(rtwdev, "failed to read CLKREQ_L1, ret=%d", ret); 1446 return; 1447 } 1448 1449 if (enable) 1450 value &= ~BIT_CLKREQ_N_PAD; 1451 else 1452 value |= BIT_CLKREQ_N_PAD; 1453 1454 rtw_dbi_write8(rtwdev, RTK_PCIE_LINK_CFG, value); 1455 } 1456 1457 static void rtw_pci_aspm_set(struct rtw_dev *rtwdev, bool enable) 1458 { 1459 u8 value; 1460 int ret; 1461 1462 if (rtw_pci_disable_aspm) 1463 return; 1464 1465 ret = rtw_dbi_read8(rtwdev, RTK_PCIE_LINK_CFG, &value); 1466 if (ret) { 1467 rtw_err(rtwdev, "failed to read ASPM, ret=%d", ret); 1468 return; 1469 } 1470 1471 if (enable) 1472 value |= BIT_L1_SW_EN; 1473 else 1474 value &= ~BIT_L1_SW_EN; 1475 1476 rtw_dbi_write8(rtwdev, RTK_PCIE_LINK_CFG, value); 1477 } 1478 1479 static void rtw_pci_link_ps(struct rtw_dev *rtwdev, bool enter) 1480 { 1481 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1482 1483 /* Like CLKREQ, ASPM is also implemented by two HW modules, and can 1484 * only be enabled when host supports it. 1485 * 1486 * And ASPM mechanism should be enabled when driver/firmware enters 1487 * power save mode, without having heavy traffic. Because we've 1488 * experienced some inter-operability issues that the link tends 1489 * to enter L1 state on the fly even when driver is having high 1490 * throughput. This is probably because the ASPM behavior slightly 1491 * varies from different SOC. 1492 */ 1493 if (!(rtwpci->link_ctrl & PCI_EXP_LNKCTL_ASPM_L1)) 1494 return; 1495 1496 if ((enter && atomic_dec_if_positive(&rtwpci->link_usage) == 0) || 1497 (!enter && atomic_inc_return(&rtwpci->link_usage) == 1)) 1498 rtw_pci_aspm_set(rtwdev, enter); 1499 } 1500 1501 static void rtw_pci_link_cfg(struct rtw_dev *rtwdev) 1502 { 1503 struct rtw_chip_info *chip = rtwdev->chip; 1504 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1505 struct pci_dev *pdev = rtwpci->pdev; 1506 u16 link_ctrl; 1507 int ret; 1508 1509 /* RTL8822CE has enabled REFCLK auto calibration, it does not need 1510 * to add clock delay to cover the REFCLK timing gap. 1511 */ 1512 if (chip->id == RTW_CHIP_TYPE_8822C) 1513 rtw_dbi_write8(rtwdev, RTK_PCIE_CLKDLY_CTRL, 0); 1514 1515 /* Though there is standard PCIE configuration space to set the 1516 * link control register, but by Realtek's design, driver should 1517 * check if host supports CLKREQ/ASPM to enable the HW module. 1518 * 1519 * These functions are implemented by two HW modules associated, 1520 * one is responsible to access PCIE configuration space to 1521 * follow the host settings, and another is in charge of doing 1522 * CLKREQ/ASPM mechanisms, it is default disabled. Because sometimes 1523 * the host does not support it, and due to some reasons or wrong 1524 * settings (ex. CLKREQ# not Bi-Direction), it could lead to device 1525 * loss if HW misbehaves on the link. 1526 * 1527 * Hence it's designed that driver should first check the PCIE 1528 * configuration space is sync'ed and enabled, then driver can turn 1529 * on the other module that is actually working on the mechanism. 1530 */ 1531 ret = pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &link_ctrl); 1532 if (ret) { 1533 rtw_err(rtwdev, "failed to read PCI cap, ret=%d\n", ret); 1534 return; 1535 } 1536 1537 if (link_ctrl & PCI_EXP_LNKCTL_CLKREQ_EN) 1538 rtw_pci_clkreq_set(rtwdev, true); 1539 1540 rtwpci->link_ctrl = link_ctrl; 1541 } 1542 1543 static void rtw_pci_interface_cfg(struct rtw_dev *rtwdev) 1544 { 1545 struct rtw_chip_info *chip = rtwdev->chip; 1546 1547 switch (chip->id) { 1548 case RTW_CHIP_TYPE_8822C: 1549 if (rtwdev->hal.cut_version >= RTW_CHIP_VER_CUT_D) 1550 rtw_write32_mask(rtwdev, REG_HCI_MIX_CFG, 1551 BIT_PCIE_EMAC_PDN_AUX_TO_FAST_CLK, 1); 1552 break; 1553 default: 1554 break; 1555 } 1556 } 1557 1558 static void rtw_pci_phy_cfg(struct rtw_dev *rtwdev) 1559 { 1560 struct rtw_chip_info *chip = rtwdev->chip; 1561 const struct rtw_intf_phy_para *para; 1562 u16 cut; 1563 u16 value; 1564 u16 offset; 1565 int i; 1566 1567 cut = BIT(0) << rtwdev->hal.cut_version; 1568 1569 for (i = 0; i < chip->intf_table->n_gen1_para; i++) { 1570 para = &chip->intf_table->gen1_para[i]; 1571 if (!(para->cut_mask & cut)) 1572 continue; 1573 if (para->offset == 0xffff) 1574 break; 1575 offset = para->offset; 1576 value = para->value; 1577 if (para->ip_sel == RTW_IP_SEL_PHY) 1578 rtw_mdio_write(rtwdev, offset, value, true); 1579 else 1580 rtw_dbi_write8(rtwdev, offset, value); 1581 } 1582 1583 for (i = 0; i < chip->intf_table->n_gen2_para; i++) { 1584 para = &chip->intf_table->gen2_para[i]; 1585 if (!(para->cut_mask & cut)) 1586 continue; 1587 if (para->offset == 0xffff) 1588 break; 1589 offset = para->offset; 1590 value = para->value; 1591 if (para->ip_sel == RTW_IP_SEL_PHY) 1592 rtw_mdio_write(rtwdev, offset, value, false); 1593 else 1594 rtw_dbi_write8(rtwdev, offset, value); 1595 } 1596 1597 rtw_pci_link_cfg(rtwdev); 1598 } 1599 1600 static int __maybe_unused rtw_pci_suspend(struct device *dev) 1601 { 1602 struct ieee80211_hw *hw = dev_get_drvdata(dev); 1603 struct rtw_dev *rtwdev = hw->priv; 1604 struct rtw_chip_info *chip = rtwdev->chip; 1605 struct rtw_efuse *efuse = &rtwdev->efuse; 1606 1607 if (chip->id == RTW_CHIP_TYPE_8822C && efuse->rfe_option == 6) 1608 rtw_pci_clkreq_pad_low(rtwdev, true); 1609 return 0; 1610 } 1611 1612 static int __maybe_unused rtw_pci_resume(struct device *dev) 1613 { 1614 struct ieee80211_hw *hw = dev_get_drvdata(dev); 1615 struct rtw_dev *rtwdev = hw->priv; 1616 struct rtw_chip_info *chip = rtwdev->chip; 1617 struct rtw_efuse *efuse = &rtwdev->efuse; 1618 1619 if (chip->id == RTW_CHIP_TYPE_8822C && efuse->rfe_option == 6) 1620 rtw_pci_clkreq_pad_low(rtwdev, false); 1621 return 0; 1622 } 1623 1624 SIMPLE_DEV_PM_OPS(rtw_pm_ops, rtw_pci_suspend, rtw_pci_resume); 1625 EXPORT_SYMBOL(rtw_pm_ops); 1626 1627 static int rtw_pci_claim(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1628 { 1629 int ret; 1630 1631 ret = pci_enable_device(pdev); 1632 if (ret) { 1633 rtw_err(rtwdev, "failed to enable pci device\n"); 1634 return ret; 1635 } 1636 1637 pci_set_master(pdev); 1638 pci_set_drvdata(pdev, rtwdev->hw); 1639 SET_IEEE80211_DEV(rtwdev->hw, &pdev->dev); 1640 1641 return 0; 1642 } 1643 1644 static void rtw_pci_declaim(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1645 { 1646 pci_clear_master(pdev); 1647 pci_disable_device(pdev); 1648 } 1649 1650 static int rtw_pci_setup_resource(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1651 { 1652 struct rtw_pci *rtwpci; 1653 int ret; 1654 1655 rtwpci = (struct rtw_pci *)rtwdev->priv; 1656 rtwpci->pdev = pdev; 1657 1658 /* after this driver can access to hw registers */ 1659 ret = rtw_pci_io_mapping(rtwdev, pdev); 1660 if (ret) { 1661 rtw_err(rtwdev, "failed to request pci io region\n"); 1662 goto err_out; 1663 } 1664 1665 ret = rtw_pci_init(rtwdev); 1666 if (ret) { 1667 rtw_err(rtwdev, "failed to allocate pci resources\n"); 1668 goto err_io_unmap; 1669 } 1670 1671 return 0; 1672 1673 err_io_unmap: 1674 rtw_pci_io_unmapping(rtwdev, pdev); 1675 1676 err_out: 1677 return ret; 1678 } 1679 1680 static void rtw_pci_destroy(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1681 { 1682 rtw_pci_deinit(rtwdev); 1683 rtw_pci_io_unmapping(rtwdev, pdev); 1684 } 1685 1686 static struct rtw_hci_ops rtw_pci_ops = { 1687 .tx_write = rtw_pci_tx_write, 1688 .tx_kick_off = rtw_pci_tx_kick_off, 1689 .flush_queues = rtw_pci_flush_queues, 1690 .setup = rtw_pci_setup, 1691 .start = rtw_pci_start, 1692 .stop = rtw_pci_stop, 1693 .deep_ps = rtw_pci_deep_ps, 1694 .link_ps = rtw_pci_link_ps, 1695 .interface_cfg = rtw_pci_interface_cfg, 1696 1697 .read8 = rtw_pci_read8, 1698 .read16 = rtw_pci_read16, 1699 .read32 = rtw_pci_read32, 1700 .write8 = rtw_pci_write8, 1701 .write16 = rtw_pci_write16, 1702 .write32 = rtw_pci_write32, 1703 .write_data_rsvd_page = rtw_pci_write_data_rsvd_page, 1704 .write_data_h2c = rtw_pci_write_data_h2c, 1705 }; 1706 1707 static int rtw_pci_request_irq(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1708 { 1709 unsigned int flags = PCI_IRQ_LEGACY; 1710 int ret; 1711 1712 if (!rtw_disable_msi) 1713 flags |= PCI_IRQ_MSI; 1714 1715 ret = pci_alloc_irq_vectors(pdev, 1, 1, flags); 1716 if (ret < 0) { 1717 rtw_err(rtwdev, "failed to alloc PCI irq vectors\n"); 1718 return ret; 1719 } 1720 1721 ret = devm_request_threaded_irq(rtwdev->dev, pdev->irq, 1722 rtw_pci_interrupt_handler, 1723 rtw_pci_interrupt_threadfn, 1724 IRQF_SHARED, KBUILD_MODNAME, rtwdev); 1725 if (ret) { 1726 rtw_err(rtwdev, "failed to request irq %d\n", ret); 1727 pci_free_irq_vectors(pdev); 1728 } 1729 1730 return ret; 1731 } 1732 1733 static void rtw_pci_free_irq(struct rtw_dev *rtwdev, struct pci_dev *pdev) 1734 { 1735 devm_free_irq(rtwdev->dev, pdev->irq, rtwdev); 1736 pci_free_irq_vectors(pdev); 1737 } 1738 1739 static int rtw_pci_napi_poll(struct napi_struct *napi, int budget) 1740 { 1741 struct rtw_pci *rtwpci = container_of(napi, struct rtw_pci, napi); 1742 struct rtw_dev *rtwdev = container_of((void *)rtwpci, struct rtw_dev, 1743 priv); 1744 int work_done = 0; 1745 1746 if (rtwpci->rx_no_aspm) 1747 rtw_pci_link_ps(rtwdev, false); 1748 1749 while (work_done < budget) { 1750 u32 work_done_once; 1751 1752 work_done_once = rtw_pci_rx_napi(rtwdev, rtwpci, RTW_RX_QUEUE_MPDU, 1753 budget - work_done); 1754 if (work_done_once == 0) 1755 break; 1756 work_done += work_done_once; 1757 } 1758 if (work_done < budget) { 1759 napi_complete_done(napi, work_done); 1760 spin_lock_bh(&rtwpci->irq_lock); 1761 if (rtwpci->running) 1762 rtw_pci_enable_interrupt(rtwdev, rtwpci, false); 1763 spin_unlock_bh(&rtwpci->irq_lock); 1764 /* When ISR happens during polling and before napi_complete 1765 * while no further data is received. Data on the dma_ring will 1766 * not be processed immediately. Check whether dma ring is 1767 * empty and perform napi_schedule accordingly. 1768 */ 1769 if (rtw_pci_get_hw_rx_ring_nr(rtwdev, rtwpci)) 1770 napi_schedule(napi); 1771 } 1772 if (rtwpci->rx_no_aspm) 1773 rtw_pci_link_ps(rtwdev, true); 1774 1775 return work_done; 1776 } 1777 1778 static void rtw_pci_napi_init(struct rtw_dev *rtwdev) 1779 { 1780 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1781 1782 init_dummy_netdev(&rtwpci->netdev); 1783 netif_napi_add(&rtwpci->netdev, &rtwpci->napi, rtw_pci_napi_poll, 1784 RTW_NAPI_WEIGHT_NUM); 1785 } 1786 1787 static void rtw_pci_napi_deinit(struct rtw_dev *rtwdev) 1788 { 1789 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; 1790 1791 rtw_pci_napi_stop(rtwdev); 1792 netif_napi_del(&rtwpci->napi); 1793 } 1794 1795 int rtw_pci_probe(struct pci_dev *pdev, 1796 const struct pci_device_id *id) 1797 { 1798 struct pci_dev *bridge = pci_upstream_bridge(pdev); 1799 struct ieee80211_hw *hw; 1800 struct rtw_dev *rtwdev; 1801 struct rtw_pci *rtwpci; 1802 int drv_data_size; 1803 int ret; 1804 1805 drv_data_size = sizeof(struct rtw_dev) + sizeof(struct rtw_pci); 1806 hw = ieee80211_alloc_hw(drv_data_size, &rtw_ops); 1807 if (!hw) { 1808 dev_err(&pdev->dev, "failed to allocate hw\n"); 1809 return -ENOMEM; 1810 } 1811 1812 rtwdev = hw->priv; 1813 rtwdev->hw = hw; 1814 rtwdev->dev = &pdev->dev; 1815 rtwdev->chip = (struct rtw_chip_info *)id->driver_data; 1816 rtwdev->hci.ops = &rtw_pci_ops; 1817 rtwdev->hci.type = RTW_HCI_TYPE_PCIE; 1818 1819 rtwpci = (struct rtw_pci *)rtwdev->priv; 1820 atomic_set(&rtwpci->link_usage, 1); 1821 1822 ret = rtw_core_init(rtwdev); 1823 if (ret) 1824 goto err_release_hw; 1825 1826 rtw_dbg(rtwdev, RTW_DBG_PCI, 1827 "rtw88 pci probe: vendor=0x%4.04X device=0x%4.04X rev=%d\n", 1828 pdev->vendor, pdev->device, pdev->revision); 1829 1830 ret = rtw_pci_claim(rtwdev, pdev); 1831 if (ret) { 1832 rtw_err(rtwdev, "failed to claim pci device\n"); 1833 goto err_deinit_core; 1834 } 1835 1836 ret = rtw_pci_setup_resource(rtwdev, pdev); 1837 if (ret) { 1838 rtw_err(rtwdev, "failed to setup pci resources\n"); 1839 goto err_pci_declaim; 1840 } 1841 1842 rtw_pci_napi_init(rtwdev); 1843 1844 ret = rtw_chip_info_setup(rtwdev); 1845 if (ret) { 1846 rtw_err(rtwdev, "failed to setup chip information\n"); 1847 goto err_destroy_pci; 1848 } 1849 1850 /* Disable PCIe ASPM L1 while doing NAPI poll for 8821CE */ 1851 if (pdev->device == 0xc821 && bridge->vendor == PCI_VENDOR_ID_INTEL) 1852 rtwpci->rx_no_aspm = true; 1853 1854 rtw_pci_phy_cfg(rtwdev); 1855 1856 ret = rtw_register_hw(rtwdev, hw); 1857 if (ret) { 1858 rtw_err(rtwdev, "failed to register hw\n"); 1859 goto err_destroy_pci; 1860 } 1861 1862 ret = rtw_pci_request_irq(rtwdev, pdev); 1863 if (ret) { 1864 ieee80211_unregister_hw(hw); 1865 goto err_destroy_pci; 1866 } 1867 1868 return 0; 1869 1870 err_destroy_pci: 1871 rtw_pci_napi_deinit(rtwdev); 1872 rtw_pci_destroy(rtwdev, pdev); 1873 1874 err_pci_declaim: 1875 rtw_pci_declaim(rtwdev, pdev); 1876 1877 err_deinit_core: 1878 rtw_core_deinit(rtwdev); 1879 1880 err_release_hw: 1881 ieee80211_free_hw(hw); 1882 1883 return ret; 1884 } 1885 EXPORT_SYMBOL(rtw_pci_probe); 1886 1887 void rtw_pci_remove(struct pci_dev *pdev) 1888 { 1889 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 1890 struct rtw_dev *rtwdev; 1891 struct rtw_pci *rtwpci; 1892 1893 if (!hw) 1894 return; 1895 1896 rtwdev = hw->priv; 1897 rtwpci = (struct rtw_pci *)rtwdev->priv; 1898 1899 rtw_unregister_hw(rtwdev, hw); 1900 rtw_pci_disable_interrupt(rtwdev, rtwpci); 1901 rtw_pci_napi_deinit(rtwdev); 1902 rtw_pci_destroy(rtwdev, pdev); 1903 rtw_pci_declaim(rtwdev, pdev); 1904 rtw_pci_free_irq(rtwdev, pdev); 1905 rtw_core_deinit(rtwdev); 1906 ieee80211_free_hw(hw); 1907 } 1908 EXPORT_SYMBOL(rtw_pci_remove); 1909 1910 void rtw_pci_shutdown(struct pci_dev *pdev) 1911 { 1912 struct ieee80211_hw *hw = pci_get_drvdata(pdev); 1913 struct rtw_dev *rtwdev; 1914 struct rtw_chip_info *chip; 1915 1916 if (!hw) 1917 return; 1918 1919 rtwdev = hw->priv; 1920 chip = rtwdev->chip; 1921 1922 if (chip->ops->shutdown) 1923 chip->ops->shutdown(rtwdev); 1924 1925 pci_set_power_state(pdev, PCI_D3hot); 1926 } 1927 EXPORT_SYMBOL(rtw_pci_shutdown); 1928 1929 MODULE_AUTHOR("Realtek Corporation"); 1930 MODULE_DESCRIPTION("Realtek 802.11ac wireless PCI driver"); 1931 MODULE_LICENSE("Dual BSD/GPL"); 1932 #if defined(__FreeBSD__) 1933 MODULE_VERSION(rtw_pci, 1); 1934 MODULE_DEPEND(rtw_pci, linuxkpi, 1, 1, 1); 1935 MODULE_DEPEND(rtw_pci, linuxkpi_wlan, 1, 1, 1); 1936 #ifdef CONFIG_RTW88_DEBUGFS 1937 MODULE_DEPEND(rtw_pci, debugfs, 1, 1, 1); 1938 #endif 1939 #endif 1940