1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTK_MAIN_H_ 6 #define __RTK_MAIN_H_ 7 8 #include <net/mac80211.h> 9 #include <linux/vmalloc.h> 10 #include <linux/firmware.h> 11 #include <linux/average.h> 12 #include <linux/bitops.h> 13 #include <linux/bitfield.h> 14 #include <linux/iopoll.h> 15 #include <linux/interrupt.h> 16 #include <linux/workqueue.h> 17 #if defined(__FreeBSD__) 18 #include <linux/kernel.h> 19 #include <linux/delay.h> 20 #include <linux/etherdevice.h> 21 #include <linux/rcupdate.h> 22 #include <linux/lockdep.h> 23 #include <linux/seq_file.h> 24 #endif 25 26 #include "util.h" 27 28 #define RTW_NAPI_WEIGHT_NUM 64 29 #define RTW_MAX_MAC_ID_NUM 32 30 #define RTW_MAX_SEC_CAM_NUM 32 31 #define MAX_PG_CAM_BACKUP_NUM 8 32 33 #define RTW_SCAN_MAX_SSIDS 4 34 #define RTW_SCAN_MAX_IE_LEN 128 35 36 #define RTW_MAX_PATTERN_NUM 12 37 #define RTW_MAX_PATTERN_MASK_SIZE 16 38 #define RTW_MAX_PATTERN_SIZE 128 39 40 #define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2) 41 42 #define RFREG_MASK 0xfffff 43 #define INV_RF_DATA 0xffffffff 44 #define TX_PAGE_SIZE_SHIFT 7 45 46 #define RTW_CHANNEL_WIDTH_MAX 3 47 #define RTW_RF_PATH_MAX 4 48 #define HW_FEATURE_LEN 13 49 50 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */ 51 52 extern bool rtw_bf_support; 53 extern bool rtw_disable_lps_deep_mode; 54 extern unsigned int rtw_debug_mask; 55 extern bool rtw_edcca_enabled; 56 extern const struct ieee80211_ops rtw_ops; 57 58 #define RTW_MAX_CHANNEL_NUM_2G 14 59 #define RTW_MAX_CHANNEL_NUM_5G 49 60 61 struct rtw_dev; 62 63 enum rtw_hci_type { 64 RTW_HCI_TYPE_PCIE, 65 RTW_HCI_TYPE_USB, 66 RTW_HCI_TYPE_SDIO, 67 68 RTW_HCI_TYPE_UNDEFINE, 69 }; 70 71 struct rtw_hci { 72 struct rtw_hci_ops *ops; 73 enum rtw_hci_type type; 74 75 u32 rpwm_addr; 76 u32 cpwm_addr; 77 78 u8 bulkout_num; 79 }; 80 81 #define IS_CH_5G_BAND_1(channel) ((channel) >= 36 && (channel <= 48)) 82 #define IS_CH_5G_BAND_2(channel) ((channel) >= 52 && (channel <= 64)) 83 #define IS_CH_5G_BAND_3(channel) ((channel) >= 100 && (channel <= 144)) 84 #define IS_CH_5G_BAND_4(channel) ((channel) >= 149 && (channel <= 177)) 85 86 #define IS_CH_5G_BAND_MID(channel) \ 87 (IS_CH_5G_BAND_2(channel) || IS_CH_5G_BAND_3(channel)) 88 89 #define IS_CH_2G_BAND(channel) ((channel) <= 14) 90 #define IS_CH_5G_BAND(channel) \ 91 (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel) || \ 92 IS_CH_5G_BAND_3(channel) || IS_CH_5G_BAND_4(channel)) 93 94 enum rtw_supported_band { 95 RTW_BAND_2G = BIT(NL80211_BAND_2GHZ), 96 RTW_BAND_5G = BIT(NL80211_BAND_5GHZ), 97 RTW_BAND_60G = BIT(NL80211_BAND_60GHZ), 98 }; 99 100 /* now, support upto 80M bw */ 101 #define RTW_MAX_CHANNEL_WIDTH RTW_CHANNEL_WIDTH_80 102 103 enum rtw_bandwidth { 104 RTW_CHANNEL_WIDTH_20 = 0, 105 RTW_CHANNEL_WIDTH_40 = 1, 106 RTW_CHANNEL_WIDTH_80 = 2, 107 RTW_CHANNEL_WIDTH_160 = 3, 108 RTW_CHANNEL_WIDTH_80_80 = 4, 109 RTW_CHANNEL_WIDTH_5 = 5, 110 RTW_CHANNEL_WIDTH_10 = 6, 111 }; 112 113 enum rtw_sc_offset { 114 RTW_SC_DONT_CARE = 0, 115 RTW_SC_20_UPPER = 1, 116 RTW_SC_20_LOWER = 2, 117 RTW_SC_20_UPMOST = 3, 118 RTW_SC_20_LOWEST = 4, 119 RTW_SC_40_UPPER = 9, 120 RTW_SC_40_LOWER = 10, 121 }; 122 123 enum rtw_net_type { 124 RTW_NET_NO_LINK = 0, 125 RTW_NET_AD_HOC = 1, 126 RTW_NET_MGD_LINKED = 2, 127 RTW_NET_AP_MODE = 3, 128 }; 129 130 enum rtw_rf_type { 131 RF_1T1R = 0, 132 RF_1T2R = 1, 133 RF_2T2R = 2, 134 RF_2T3R = 3, 135 RF_2T4R = 4, 136 RF_3T3R = 5, 137 RF_3T4R = 6, 138 RF_4T4R = 7, 139 RF_TYPE_MAX, 140 }; 141 142 enum rtw_rf_path { 143 RF_PATH_A = 0, 144 RF_PATH_B = 1, 145 RF_PATH_C = 2, 146 RF_PATH_D = 3, 147 }; 148 149 enum rtw_bb_path { 150 BB_PATH_A = BIT(0), 151 BB_PATH_B = BIT(1), 152 BB_PATH_C = BIT(2), 153 BB_PATH_D = BIT(3), 154 155 BB_PATH_AB = (BB_PATH_A | BB_PATH_B), 156 BB_PATH_AC = (BB_PATH_A | BB_PATH_C), 157 BB_PATH_AD = (BB_PATH_A | BB_PATH_D), 158 BB_PATH_BC = (BB_PATH_B | BB_PATH_C), 159 BB_PATH_BD = (BB_PATH_B | BB_PATH_D), 160 BB_PATH_CD = (BB_PATH_C | BB_PATH_D), 161 162 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C), 163 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D), 164 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D), 165 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D), 166 167 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D), 168 }; 169 170 enum rtw_rate_section { 171 RTW_RATE_SECTION_CCK = 0, 172 RTW_RATE_SECTION_OFDM, 173 RTW_RATE_SECTION_HT_1S, 174 RTW_RATE_SECTION_HT_2S, 175 RTW_RATE_SECTION_VHT_1S, 176 RTW_RATE_SECTION_VHT_2S, 177 178 /* keep last */ 179 RTW_RATE_SECTION_MAX, 180 }; 181 182 enum rtw_wireless_set { 183 WIRELESS_CCK = 0x00000001, 184 WIRELESS_OFDM = 0x00000002, 185 WIRELESS_HT = 0x00000004, 186 WIRELESS_VHT = 0x00000008, 187 }; 188 189 #define HT_STBC_EN BIT(0) 190 #define VHT_STBC_EN BIT(1) 191 #define HT_LDPC_EN BIT(0) 192 #define VHT_LDPC_EN BIT(1) 193 194 enum rtw_chip_type { 195 RTW_CHIP_TYPE_8822B, 196 RTW_CHIP_TYPE_8822C, 197 RTW_CHIP_TYPE_8723D, 198 RTW_CHIP_TYPE_8821C, 199 }; 200 201 enum rtw_tx_queue_type { 202 /* the order of AC queues matters */ 203 RTW_TX_QUEUE_BK = 0x0, 204 RTW_TX_QUEUE_BE = 0x1, 205 RTW_TX_QUEUE_VI = 0x2, 206 RTW_TX_QUEUE_VO = 0x3, 207 208 RTW_TX_QUEUE_BCN = 0x4, 209 RTW_TX_QUEUE_MGMT = 0x5, 210 RTW_TX_QUEUE_HI0 = 0x6, 211 RTW_TX_QUEUE_H2C = 0x7, 212 /* keep it last */ 213 RTK_MAX_TX_QUEUE_NUM 214 }; 215 216 enum rtw_rx_queue_type { 217 RTW_RX_QUEUE_MPDU = 0x0, 218 RTW_RX_QUEUE_C2H = 0x1, 219 /* keep it last */ 220 RTK_MAX_RX_QUEUE_NUM 221 }; 222 223 enum rtw_fw_type { 224 RTW_NORMAL_FW = 0x0, 225 RTW_WOWLAN_FW = 0x1, 226 }; 227 228 enum rtw_rate_index { 229 RTW_RATEID_BGN_40M_2SS = 0, 230 RTW_RATEID_BGN_40M_1SS = 1, 231 RTW_RATEID_BGN_20M_2SS = 2, 232 RTW_RATEID_BGN_20M_1SS = 3, 233 RTW_RATEID_GN_N2SS = 4, 234 RTW_RATEID_GN_N1SS = 5, 235 RTW_RATEID_BG = 6, 236 RTW_RATEID_G = 7, 237 RTW_RATEID_B_20M = 8, 238 RTW_RATEID_ARFR0_AC_2SS = 9, 239 RTW_RATEID_ARFR1_AC_1SS = 10, 240 RTW_RATEID_ARFR2_AC_2G_1SS = 11, 241 RTW_RATEID_ARFR3_AC_2G_2SS = 12, 242 RTW_RATEID_ARFR4_AC_3SS = 13, 243 RTW_RATEID_ARFR5_N_3SS = 14, 244 RTW_RATEID_ARFR7_N_4SS = 15, 245 RTW_RATEID_ARFR6_AC_4SS = 16 246 }; 247 248 enum rtw_trx_desc_rate { 249 DESC_RATE1M = 0x00, 250 DESC_RATE2M = 0x01, 251 DESC_RATE5_5M = 0x02, 252 DESC_RATE11M = 0x03, 253 254 DESC_RATE6M = 0x04, 255 DESC_RATE9M = 0x05, 256 DESC_RATE12M = 0x06, 257 DESC_RATE18M = 0x07, 258 DESC_RATE24M = 0x08, 259 DESC_RATE36M = 0x09, 260 DESC_RATE48M = 0x0a, 261 DESC_RATE54M = 0x0b, 262 263 DESC_RATEMCS0 = 0x0c, 264 DESC_RATEMCS1 = 0x0d, 265 DESC_RATEMCS2 = 0x0e, 266 DESC_RATEMCS3 = 0x0f, 267 DESC_RATEMCS4 = 0x10, 268 DESC_RATEMCS5 = 0x11, 269 DESC_RATEMCS6 = 0x12, 270 DESC_RATEMCS7 = 0x13, 271 DESC_RATEMCS8 = 0x14, 272 DESC_RATEMCS9 = 0x15, 273 DESC_RATEMCS10 = 0x16, 274 DESC_RATEMCS11 = 0x17, 275 DESC_RATEMCS12 = 0x18, 276 DESC_RATEMCS13 = 0x19, 277 DESC_RATEMCS14 = 0x1a, 278 DESC_RATEMCS15 = 0x1b, 279 DESC_RATEMCS16 = 0x1c, 280 DESC_RATEMCS17 = 0x1d, 281 DESC_RATEMCS18 = 0x1e, 282 DESC_RATEMCS19 = 0x1f, 283 DESC_RATEMCS20 = 0x20, 284 DESC_RATEMCS21 = 0x21, 285 DESC_RATEMCS22 = 0x22, 286 DESC_RATEMCS23 = 0x23, 287 DESC_RATEMCS24 = 0x24, 288 DESC_RATEMCS25 = 0x25, 289 DESC_RATEMCS26 = 0x26, 290 DESC_RATEMCS27 = 0x27, 291 DESC_RATEMCS28 = 0x28, 292 DESC_RATEMCS29 = 0x29, 293 DESC_RATEMCS30 = 0x2a, 294 DESC_RATEMCS31 = 0x2b, 295 296 DESC_RATEVHT1SS_MCS0 = 0x2c, 297 DESC_RATEVHT1SS_MCS1 = 0x2d, 298 DESC_RATEVHT1SS_MCS2 = 0x2e, 299 DESC_RATEVHT1SS_MCS3 = 0x2f, 300 DESC_RATEVHT1SS_MCS4 = 0x30, 301 DESC_RATEVHT1SS_MCS5 = 0x31, 302 DESC_RATEVHT1SS_MCS6 = 0x32, 303 DESC_RATEVHT1SS_MCS7 = 0x33, 304 DESC_RATEVHT1SS_MCS8 = 0x34, 305 DESC_RATEVHT1SS_MCS9 = 0x35, 306 307 DESC_RATEVHT2SS_MCS0 = 0x36, 308 DESC_RATEVHT2SS_MCS1 = 0x37, 309 DESC_RATEVHT2SS_MCS2 = 0x38, 310 DESC_RATEVHT2SS_MCS3 = 0x39, 311 DESC_RATEVHT2SS_MCS4 = 0x3a, 312 DESC_RATEVHT2SS_MCS5 = 0x3b, 313 DESC_RATEVHT2SS_MCS6 = 0x3c, 314 DESC_RATEVHT2SS_MCS7 = 0x3d, 315 DESC_RATEVHT2SS_MCS8 = 0x3e, 316 DESC_RATEVHT2SS_MCS9 = 0x3f, 317 318 DESC_RATEVHT3SS_MCS0 = 0x40, 319 DESC_RATEVHT3SS_MCS1 = 0x41, 320 DESC_RATEVHT3SS_MCS2 = 0x42, 321 DESC_RATEVHT3SS_MCS3 = 0x43, 322 DESC_RATEVHT3SS_MCS4 = 0x44, 323 DESC_RATEVHT3SS_MCS5 = 0x45, 324 DESC_RATEVHT3SS_MCS6 = 0x46, 325 DESC_RATEVHT3SS_MCS7 = 0x47, 326 DESC_RATEVHT3SS_MCS8 = 0x48, 327 DESC_RATEVHT3SS_MCS9 = 0x49, 328 329 DESC_RATEVHT4SS_MCS0 = 0x4a, 330 DESC_RATEVHT4SS_MCS1 = 0x4b, 331 DESC_RATEVHT4SS_MCS2 = 0x4c, 332 DESC_RATEVHT4SS_MCS3 = 0x4d, 333 DESC_RATEVHT4SS_MCS4 = 0x4e, 334 DESC_RATEVHT4SS_MCS5 = 0x4f, 335 DESC_RATEVHT4SS_MCS6 = 0x50, 336 DESC_RATEVHT4SS_MCS7 = 0x51, 337 DESC_RATEVHT4SS_MCS8 = 0x52, 338 DESC_RATEVHT4SS_MCS9 = 0x53, 339 340 DESC_RATE_MAX, 341 }; 342 343 enum rtw_regulatory_domains { 344 RTW_REGD_FCC = 0, 345 RTW_REGD_MKK = 1, 346 RTW_REGD_ETSI = 2, 347 RTW_REGD_IC = 3, 348 RTW_REGD_KCC = 4, 349 RTW_REGD_ACMA = 5, 350 RTW_REGD_CHILE = 6, 351 RTW_REGD_UKRAINE = 7, 352 RTW_REGD_MEXICO = 8, 353 RTW_REGD_CN = 9, 354 RTW_REGD_WW, 355 356 RTW_REGD_MAX 357 }; 358 359 enum rtw_txq_flags { 360 RTW_TXQ_AMPDU, 361 RTW_TXQ_BLOCK_BA, 362 }; 363 364 enum rtw_flags { 365 RTW_FLAG_RUNNING, 366 RTW_FLAG_FW_RUNNING, 367 RTW_FLAG_SCANNING, 368 RTW_FLAG_INACTIVE_PS, 369 RTW_FLAG_LEISURE_PS, 370 RTW_FLAG_LEISURE_PS_DEEP, 371 RTW_FLAG_DIG_DISABLE, 372 RTW_FLAG_BUSY_TRAFFIC, 373 RTW_FLAG_WOWLAN, 374 RTW_FLAG_RESTARTING, 375 RTW_FLAG_RESTART_TRIGGERING, 376 RTW_FLAG_FORCE_LOWEST_RATE, 377 378 NUM_OF_RTW_FLAGS, 379 }; 380 381 enum rtw_evm { 382 RTW_EVM_OFDM = 0, 383 RTW_EVM_1SS, 384 RTW_EVM_2SS_A, 385 RTW_EVM_2SS_B, 386 /* keep it last */ 387 RTW_EVM_NUM 388 }; 389 390 enum rtw_snr { 391 RTW_SNR_OFDM_A = 0, 392 RTW_SNR_OFDM_B, 393 RTW_SNR_OFDM_C, 394 RTW_SNR_OFDM_D, 395 RTW_SNR_1SS_A, 396 RTW_SNR_1SS_B, 397 RTW_SNR_1SS_C, 398 RTW_SNR_1SS_D, 399 RTW_SNR_2SS_A, 400 RTW_SNR_2SS_B, 401 RTW_SNR_2SS_C, 402 RTW_SNR_2SS_D, 403 /* keep it last */ 404 RTW_SNR_NUM 405 }; 406 407 enum rtw_wow_flags { 408 RTW_WOW_FLAG_EN_MAGIC_PKT, 409 RTW_WOW_FLAG_EN_REKEY_PKT, 410 RTW_WOW_FLAG_EN_DISCONNECT, 411 412 /* keep it last */ 413 RTW_WOW_FLAG_MAX, 414 }; 415 416 /* the power index is represented by differences, which cck-1s & ht40-1s are 417 * the base values, so for 1s's differences, there are only ht20 & ofdm 418 */ 419 struct rtw_2g_1s_pwr_idx_diff { 420 #ifdef __LITTLE_ENDIAN 421 s8 ofdm:4; 422 s8 bw20:4; 423 #else 424 s8 bw20:4; 425 s8 ofdm:4; 426 #endif 427 } __packed; 428 429 struct rtw_2g_ns_pwr_idx_diff { 430 #ifdef __LITTLE_ENDIAN 431 s8 bw20:4; 432 s8 bw40:4; 433 s8 cck:4; 434 s8 ofdm:4; 435 #else 436 s8 ofdm:4; 437 s8 cck:4; 438 s8 bw40:4; 439 s8 bw20:4; 440 #endif 441 } __packed; 442 443 struct rtw_2g_txpwr_idx { 444 u8 cck_base[6]; 445 u8 bw40_base[5]; 446 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff; 447 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff; 448 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff; 449 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff; 450 }; 451 452 struct rtw_5g_ht_1s_pwr_idx_diff { 453 #ifdef __LITTLE_ENDIAN 454 s8 ofdm:4; 455 s8 bw20:4; 456 #else 457 s8 bw20:4; 458 s8 ofdm:4; 459 #endif 460 } __packed; 461 462 struct rtw_5g_ht_ns_pwr_idx_diff { 463 #ifdef __LITTLE_ENDIAN 464 s8 bw20:4; 465 s8 bw40:4; 466 #else 467 s8 bw40:4; 468 s8 bw20:4; 469 #endif 470 } __packed; 471 472 struct rtw_5g_ofdm_ns_pwr_idx_diff { 473 #ifdef __LITTLE_ENDIAN 474 s8 ofdm_3s:4; 475 s8 ofdm_2s:4; 476 s8 ofdm_4s:4; 477 s8 res:4; 478 #else 479 s8 res:4; 480 s8 ofdm_4s:4; 481 s8 ofdm_2s:4; 482 s8 ofdm_3s:4; 483 #endif 484 } __packed; 485 486 struct rtw_5g_vht_ns_pwr_idx_diff { 487 #ifdef __LITTLE_ENDIAN 488 s8 bw160:4; 489 s8 bw80:4; 490 #else 491 s8 bw80:4; 492 s8 bw160:4; 493 #endif 494 } __packed; 495 496 struct rtw_5g_txpwr_idx { 497 u8 bw40_base[14]; 498 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff; 499 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff; 500 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff; 501 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff; 502 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff; 503 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff; 504 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff; 505 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff; 506 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff; 507 }; 508 509 struct rtw_txpwr_idx { 510 struct rtw_2g_txpwr_idx pwr_idx_2g; 511 struct rtw_5g_txpwr_idx pwr_idx_5g; 512 }; 513 514 struct rtw_timer_list { 515 struct timer_list timer; 516 void (*function)(void *data); 517 void *args; 518 }; 519 520 struct rtw_channel_params { 521 u8 center_chan; 522 u8 bandwidth; 523 u8 primary_chan_idx; 524 /* center channel by different available bandwidth, 525 * val of (bw > current bandwidth) is invalid 526 */ 527 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 528 }; 529 530 struct rtw_hw_reg { 531 u32 addr; 532 u32 mask; 533 }; 534 535 struct rtw_ltecoex_addr { 536 u32 ctrl; 537 u32 wdata; 538 u32 rdata; 539 }; 540 541 struct rtw_reg_domain { 542 u32 addr; 543 u32 mask; 544 #define RTW_REG_DOMAIN_MAC32 0 545 #define RTW_REG_DOMAIN_MAC16 1 546 #define RTW_REG_DOMAIN_MAC8 2 547 #define RTW_REG_DOMAIN_RF_A 3 548 #define RTW_REG_DOMAIN_RF_B 4 549 #define RTW_REG_DOMAIN_NL 0xFF 550 u8 domain; 551 }; 552 553 struct rtw_rf_sipi_addr { 554 u32 hssi_1; 555 u32 hssi_2; 556 u32 lssi_read; 557 u32 lssi_read_pi; 558 }; 559 560 struct rtw_hw_reg_offset { 561 struct rtw_hw_reg hw_reg; 562 u8 offset; 563 }; 564 565 struct rtw_backup_info { 566 u8 len; 567 u32 reg; 568 u32 val; 569 }; 570 571 enum rtw_vif_port_set { 572 PORT_SET_MAC_ADDR = BIT(0), 573 PORT_SET_BSSID = BIT(1), 574 PORT_SET_NET_TYPE = BIT(2), 575 PORT_SET_AID = BIT(3), 576 PORT_SET_BCN_CTRL = BIT(4), 577 }; 578 579 struct rtw_vif_port { 580 struct rtw_hw_reg mac_addr; 581 struct rtw_hw_reg bssid; 582 struct rtw_hw_reg net_type; 583 struct rtw_hw_reg aid; 584 struct rtw_hw_reg bcn_ctrl; 585 }; 586 587 struct rtw_tx_pkt_info { 588 u32 tx_pkt_size; 589 u8 offset; 590 u8 pkt_offset; 591 u8 mac_id; 592 u8 rate_id; 593 u8 rate; 594 u8 qsel; 595 u8 bw; 596 u8 sec_type; 597 u8 sn; 598 bool ampdu_en; 599 u8 ampdu_factor; 600 u8 ampdu_density; 601 u16 seq; 602 bool stbc; 603 bool ldpc; 604 bool dis_rate_fallback; 605 bool bmc; 606 bool use_rate; 607 bool ls; 608 bool fs; 609 bool short_gi; 610 bool report; 611 bool rts; 612 bool dis_qselseq; 613 bool en_hwseq; 614 u8 hw_ssn_sel; 615 bool nav_use_hdr; 616 bool bt_null; 617 }; 618 619 struct rtw_rx_pkt_stat { 620 bool phy_status; 621 bool icv_err; 622 bool crc_err; 623 bool decrypted; 624 bool is_c2h; 625 626 s32 signal_power; 627 u16 pkt_len; 628 u8 bw; 629 u8 drv_info_sz; 630 u8 shift; 631 u8 rate; 632 u8 mac_id; 633 u8 cam_id; 634 u8 ppdu_cnt; 635 u32 tsf_low; 636 s8 rx_power[RTW_RF_PATH_MAX]; 637 u8 rssi; 638 u8 rxsc; 639 s8 rx_snr[RTW_RF_PATH_MAX]; 640 u8 rx_evm[RTW_RF_PATH_MAX]; 641 s8 cfo_tail[RTW_RF_PATH_MAX]; 642 u16 freq; 643 u8 band; 644 645 struct rtw_sta_info *si; 646 struct ieee80211_vif *vif; 647 struct ieee80211_hdr *hdr; 648 }; 649 650 DECLARE_EWMA(tp, 10, 2); 651 652 struct rtw_traffic_stats { 653 /* units in bytes */ 654 u64 tx_unicast; 655 u64 rx_unicast; 656 657 /* count for packets */ 658 u64 tx_cnt; 659 u64 rx_cnt; 660 661 /* units in Mbps */ 662 u32 tx_throughput; 663 u32 rx_throughput; 664 struct ewma_tp tx_ewma_tp; 665 struct ewma_tp rx_ewma_tp; 666 }; 667 668 enum rtw_lps_mode { 669 RTW_MODE_ACTIVE = 0, 670 RTW_MODE_LPS = 1, 671 RTW_MODE_WMM_PS = 2, 672 }; 673 674 enum rtw_lps_deep_mode { 675 LPS_DEEP_MODE_NONE = 0, 676 LPS_DEEP_MODE_LCLK = 1, 677 LPS_DEEP_MODE_PG = 2, 678 }; 679 680 enum rtw_pwr_state { 681 RTW_RF_OFF = 0x0, 682 RTW_RF_ON = 0x4, 683 RTW_ALL_ON = 0xc, 684 }; 685 686 struct rtw_lps_conf { 687 enum rtw_lps_mode mode; 688 enum rtw_lps_deep_mode deep_mode; 689 enum rtw_lps_deep_mode wow_deep_mode; 690 enum rtw_pwr_state state; 691 u8 awake_interval; 692 u8 rlbm; 693 u8 smart_ps; 694 u8 port_id; 695 bool sec_cam_backup; 696 bool pattern_cam_backup; 697 }; 698 699 enum rtw_hw_key_type { 700 RTW_CAM_NONE = 0, 701 RTW_CAM_WEP40 = 1, 702 RTW_CAM_TKIP = 2, 703 RTW_CAM_AES = 4, 704 RTW_CAM_WEP104 = 5, 705 }; 706 707 struct rtw_cam_entry { 708 bool valid; 709 bool group; 710 u8 addr[ETH_ALEN]; 711 u8 hw_key_type; 712 struct ieee80211_key_conf *key; 713 }; 714 715 struct rtw_sec_desc { 716 /* search strategy */ 717 bool default_key_search; 718 719 u32 total_cam_num; 720 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM]; 721 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM); 722 }; 723 724 struct rtw_tx_report { 725 /* protect the tx report queue */ 726 spinlock_t q_lock; 727 struct sk_buff_head queue; 728 atomic_t sn; 729 struct timer_list purge_timer; 730 }; 731 732 struct rtw_ra_report { 733 struct rate_info txrate; 734 u32 bit_rate; 735 u8 desc_rate; 736 }; 737 738 struct rtw_txq { 739 struct list_head list; 740 741 unsigned long flags; 742 unsigned long last_push; 743 }; 744 745 #define RTW_BC_MC_MACID 1 746 DECLARE_EWMA(rssi, 10, 16); 747 748 struct rtw_sta_info { 749 struct ieee80211_sta *sta; 750 struct ieee80211_vif *vif; 751 752 struct ewma_rssi avg_rssi; 753 u8 rssi_level; 754 755 u8 mac_id; 756 u8 rate_id; 757 enum rtw_bandwidth bw_mode; 758 enum rtw_rf_type rf_type; 759 enum rtw_wireless_set wireless_set; 760 u8 stbc_en:2; 761 u8 ldpc_en:2; 762 bool sgi_enable; 763 bool vht_enable; 764 bool updated; 765 u8 init_ra_lv; 766 u64 ra_mask; 767 768 DECLARE_BITMAP(tid_ba, IEEE80211_NUM_TIDS); 769 770 struct rtw_ra_report ra_report; 771 772 bool use_cfg_mask; 773 struct cfg80211_bitrate_mask *mask; 774 }; 775 776 enum rtw_bfee_role { 777 RTW_BFEE_NONE, 778 RTW_BFEE_SU, 779 RTW_BFEE_MU 780 }; 781 782 struct rtw_bfee { 783 enum rtw_bfee_role role; 784 785 u16 p_aid; 786 u8 g_id; 787 u8 mac_addr[ETH_ALEN]; 788 u8 sound_dim; 789 790 /* SU-MIMO */ 791 u8 su_reg_index; 792 793 /* MU-MIMO */ 794 u16 aid; 795 }; 796 797 struct rtw_bf_info { 798 u8 bfer_mu_cnt; 799 u8 bfer_su_cnt; 800 DECLARE_BITMAP(bfer_su_reg_maping, 2); 801 u8 cur_csi_rpt_rate; 802 }; 803 804 struct rtw_vif { 805 enum rtw_net_type net_type; 806 u16 aid; 807 u8 mac_addr[ETH_ALEN]; 808 u8 bssid[ETH_ALEN]; 809 u8 port; 810 u8 bcn_ctrl; 811 struct list_head rsvd_page_list; 812 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 813 const struct rtw_vif_port *conf; 814 struct cfg80211_scan_request *scan_req; 815 struct ieee80211_scan_ies *scan_ies; 816 817 struct rtw_traffic_stats stats; 818 819 struct rtw_bfee bfee; 820 }; 821 822 struct rtw_regulatory { 823 char alpha2[2]; 824 u8 txpwr_regd_2g; 825 u8 txpwr_regd_5g; 826 }; 827 828 enum rtw_regd_state { 829 RTW_REGD_STATE_WORLDWIDE, 830 RTW_REGD_STATE_PROGRAMMED, 831 RTW_REGD_STATE_SETTING, 832 833 RTW_REGD_STATE_NR, 834 }; 835 836 struct rtw_regd { 837 enum rtw_regd_state state; 838 const struct rtw_regulatory *regulatory; 839 enum nl80211_dfs_regions dfs_region; 840 }; 841 842 struct rtw_chip_ops { 843 int (*mac_init)(struct rtw_dev *rtwdev); 844 int (*dump_fw_crash)(struct rtw_dev *rtwdev); 845 void (*shutdown)(struct rtw_dev *rtwdev); 846 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map); 847 void (*phy_set_param)(struct rtw_dev *rtwdev); 848 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel, 849 u8 bandwidth, u8 primary_chan_idx); 850 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc, 851 struct rtw_rx_pkt_stat *pkt_stat, 852 struct ieee80211_rx_status *rx_status); 853 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 854 u32 addr, u32 mask); 855 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path, 856 u32 addr, u32 mask, u32 data); 857 void (*set_tx_power_index)(struct rtw_dev *rtwdev); 858 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset, 859 u32 size); 860 int (*set_antenna)(struct rtw_dev *rtwdev, 861 u32 antenna_tx, 862 u32 antenna_rx); 863 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable); 864 void (*efuse_grant)(struct rtw_dev *rtwdev, bool enable); 865 void (*false_alarm_statistics)(struct rtw_dev *rtwdev); 866 void (*phy_calibration)(struct rtw_dev *rtwdev); 867 void (*dpk_track)(struct rtw_dev *rtwdev); 868 void (*cck_pd_set)(struct rtw_dev *rtwdev, u8 level); 869 void (*pwr_track)(struct rtw_dev *rtwdev); 870 void (*config_bfee)(struct rtw_dev *rtwdev, struct rtw_vif *vif, 871 struct rtw_bfee *bfee, bool enable); 872 void (*set_gid_table)(struct rtw_dev *rtwdev, 873 struct ieee80211_vif *vif, 874 struct ieee80211_bss_conf *conf); 875 void (*cfg_csi_rate)(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate, 876 u8 fixrate_en, u8 *new_rate); 877 void (*adaptivity_init)(struct rtw_dev *rtwdev); 878 void (*adaptivity)(struct rtw_dev *rtwdev); 879 void (*cfo_init)(struct rtw_dev *rtwdev); 880 void (*cfo_track)(struct rtw_dev *rtwdev); 881 void (*config_tx_path)(struct rtw_dev *rtwdev, u8 tx_path, 882 enum rtw_bb_path tx_path_1ss, 883 enum rtw_bb_path tx_path_cck, 884 bool is_tx2_path); 885 886 /* for coex */ 887 void (*coex_set_init)(struct rtw_dev *rtwdev); 888 void (*coex_set_ant_switch)(struct rtw_dev *rtwdev, 889 u8 ctrl_type, u8 pos_type); 890 void (*coex_set_gnt_fix)(struct rtw_dev *rtwdev); 891 void (*coex_set_gnt_debug)(struct rtw_dev *rtwdev); 892 void (*coex_set_rfe_type)(struct rtw_dev *rtwdev); 893 void (*coex_set_wl_tx_power)(struct rtw_dev *rtwdev, u8 wl_pwr); 894 void (*coex_set_wl_rx_gain)(struct rtw_dev *rtwdev, bool low_gain); 895 }; 896 897 #define RTW_PWR_POLLING_CNT 20000 898 899 #define RTW_PWR_CMD_READ 0x00 900 #define RTW_PWR_CMD_WRITE 0x01 901 #define RTW_PWR_CMD_POLLING 0x02 902 #define RTW_PWR_CMD_DELAY 0x03 903 #define RTW_PWR_CMD_END 0x04 904 905 /* define the base address of each block */ 906 #define RTW_PWR_ADDR_MAC 0x00 907 #define RTW_PWR_ADDR_USB 0x01 908 #define RTW_PWR_ADDR_PCIE 0x02 909 #define RTW_PWR_ADDR_SDIO 0x03 910 911 #define RTW_PWR_INTF_SDIO_MSK BIT(0) 912 #define RTW_PWR_INTF_USB_MSK BIT(1) 913 #define RTW_PWR_INTF_PCI_MSK BIT(2) 914 #define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 915 916 #define RTW_PWR_CUT_TEST_MSK BIT(0) 917 #define RTW_PWR_CUT_A_MSK BIT(1) 918 #define RTW_PWR_CUT_B_MSK BIT(2) 919 #define RTW_PWR_CUT_C_MSK BIT(3) 920 #define RTW_PWR_CUT_D_MSK BIT(4) 921 #define RTW_PWR_CUT_E_MSK BIT(5) 922 #define RTW_PWR_CUT_F_MSK BIT(6) 923 #define RTW_PWR_CUT_G_MSK BIT(7) 924 #define RTW_PWR_CUT_ALL_MSK 0xFF 925 926 enum rtw_pwr_seq_cmd_delay_unit { 927 RTW_PWR_DELAY_US, 928 RTW_PWR_DELAY_MS, 929 }; 930 931 struct rtw_pwr_seq_cmd { 932 u16 offset; 933 u8 cut_mask; 934 u8 intf_mask; 935 u8 base:4; 936 u8 cmd:4; 937 u8 mask; 938 u8 value; 939 }; 940 941 enum rtw_chip_ver { 942 RTW_CHIP_VER_CUT_A = 0x00, 943 RTW_CHIP_VER_CUT_B = 0x01, 944 RTW_CHIP_VER_CUT_C = 0x02, 945 RTW_CHIP_VER_CUT_D = 0x03, 946 RTW_CHIP_VER_CUT_E = 0x04, 947 RTW_CHIP_VER_CUT_F = 0x05, 948 RTW_CHIP_VER_CUT_G = 0x06, 949 }; 950 951 #define RTW_INTF_PHY_PLATFORM_ALL 0 952 953 enum rtw_intf_phy_cut { 954 RTW_INTF_PHY_CUT_A = BIT(0), 955 RTW_INTF_PHY_CUT_B = BIT(1), 956 RTW_INTF_PHY_CUT_C = BIT(2), 957 RTW_INTF_PHY_CUT_D = BIT(3), 958 RTW_INTF_PHY_CUT_E = BIT(4), 959 RTW_INTF_PHY_CUT_F = BIT(5), 960 RTW_INTF_PHY_CUT_G = BIT(6), 961 RTW_INTF_PHY_CUT_ALL = 0xFFFF, 962 }; 963 964 enum rtw_ip_sel { 965 RTW_IP_SEL_PHY = 0, 966 RTW_IP_SEL_MAC = 1, 967 RTW_IP_SEL_DBI = 2, 968 969 RTW_IP_SEL_UNDEF = 0xFFFF 970 }; 971 972 enum rtw_pq_map_id { 973 RTW_PQ_MAP_VO = 0x0, 974 RTW_PQ_MAP_VI = 0x1, 975 RTW_PQ_MAP_BE = 0x2, 976 RTW_PQ_MAP_BK = 0x3, 977 RTW_PQ_MAP_MG = 0x4, 978 RTW_PQ_MAP_HI = 0x5, 979 RTW_PQ_MAP_NUM = 0x6, 980 981 RTW_PQ_MAP_UNDEF, 982 }; 983 984 enum rtw_dma_mapping { 985 RTW_DMA_MAPPING_EXTRA = 0, 986 RTW_DMA_MAPPING_LOW = 1, 987 RTW_DMA_MAPPING_NORMAL = 2, 988 RTW_DMA_MAPPING_HIGH = 3, 989 990 RTW_DMA_MAPPING_MAX, 991 RTW_DMA_MAPPING_UNDEF, 992 }; 993 994 struct rtw_rqpn { 995 enum rtw_dma_mapping dma_map_vo; 996 enum rtw_dma_mapping dma_map_vi; 997 enum rtw_dma_mapping dma_map_be; 998 enum rtw_dma_mapping dma_map_bk; 999 enum rtw_dma_mapping dma_map_mg; 1000 enum rtw_dma_mapping dma_map_hi; 1001 }; 1002 1003 struct rtw_prioq_addr { 1004 u32 rsvd; 1005 u32 avail; 1006 }; 1007 1008 struct rtw_prioq_addrs { 1009 struct rtw_prioq_addr prio[RTW_DMA_MAPPING_MAX]; 1010 bool wsize; 1011 }; 1012 1013 struct rtw_page_table { 1014 u16 hq_num; 1015 u16 nq_num; 1016 u16 lq_num; 1017 u16 exq_num; 1018 u16 gapq_num; 1019 }; 1020 1021 struct rtw_intf_phy_para { 1022 u16 offset; 1023 u16 value; 1024 u16 ip_sel; 1025 u16 cut_mask; 1026 u16 platform; 1027 }; 1028 1029 struct rtw_wow_pattern { 1030 u16 crc; 1031 u8 type; 1032 u8 valid; 1033 u8 mask[RTW_MAX_PATTERN_MASK_SIZE]; 1034 }; 1035 1036 struct rtw_pno_request { 1037 bool inited; 1038 u32 match_set_cnt; 1039 struct cfg80211_match_set *match_sets; 1040 u8 channel_cnt; 1041 struct ieee80211_channel *channels; 1042 struct cfg80211_sched_scan_plan scan_plan; 1043 }; 1044 1045 struct rtw_wow_param { 1046 struct ieee80211_vif *wow_vif; 1047 DECLARE_BITMAP(flags, RTW_WOW_FLAG_MAX); 1048 u8 txpause; 1049 u8 pattern_cnt; 1050 struct rtw_wow_pattern patterns[RTW_MAX_PATTERN_NUM]; 1051 1052 bool ips_enabled; 1053 struct rtw_pno_request pno_req; 1054 }; 1055 1056 struct rtw_intf_phy_para_table { 1057 const struct rtw_intf_phy_para *usb2_para; 1058 const struct rtw_intf_phy_para *usb3_para; 1059 const struct rtw_intf_phy_para *gen1_para; 1060 const struct rtw_intf_phy_para *gen2_para; 1061 u8 n_usb2_para; 1062 u8 n_usb3_para; 1063 u8 n_gen1_para; 1064 u8 n_gen2_para; 1065 }; 1066 1067 struct rtw_table { 1068 const void *data; 1069 const u32 size; 1070 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl); 1071 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl, 1072 u32 addr, u32 data); 1073 enum rtw_rf_path rf_path; 1074 }; 1075 1076 static inline void rtw_load_table(struct rtw_dev *rtwdev, 1077 const struct rtw_table *tbl) 1078 { 1079 (*tbl->parse)(rtwdev, tbl); 1080 } 1081 1082 enum rtw_rfe_fem { 1083 RTW_RFE_IFEM, 1084 RTW_RFE_EFEM, 1085 RTW_RFE_IFEM2G_EFEM5G, 1086 RTW_RFE_NUM, 1087 }; 1088 1089 struct rtw_rfe_def { 1090 const struct rtw_table *phy_pg_tbl; 1091 const struct rtw_table *txpwr_lmt_tbl; 1092 const struct rtw_table *agc_btg_tbl; 1093 }; 1094 1095 #define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \ 1096 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1097 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1098 } 1099 1100 #define RTW_DEF_RFE_EXT(chip, bb_pg, pwrlmt, btg) { \ 1101 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \ 1102 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \ 1103 .agc_btg_tbl = &rtw ## chip ## _agc_btg_type ## btg ## _tbl, \ 1104 } 1105 1106 #define RTW_PWR_TRK_5G_1 0 1107 #define RTW_PWR_TRK_5G_2 1 1108 #define RTW_PWR_TRK_5G_3 2 1109 #define RTW_PWR_TRK_5G_NUM 3 1110 1111 #define RTW_PWR_TRK_TBL_SZ 30 1112 1113 /* This table stores the values of TX power that will be adjusted by power 1114 * tracking. 1115 * 1116 * For 5G bands, there are 3 different settings. 1117 * For 2G there are cck rate and ofdm rate with different settings. 1118 */ 1119 struct rtw_pwr_track_tbl { 1120 const u8 *pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM]; 1121 const u8 *pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM]; 1122 const u8 *pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM]; 1123 const u8 *pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM]; 1124 const u8 *pwrtrk_2gb_n; 1125 const u8 *pwrtrk_2gb_p; 1126 const u8 *pwrtrk_2ga_n; 1127 const u8 *pwrtrk_2ga_p; 1128 const u8 *pwrtrk_2g_cckb_n; 1129 const u8 *pwrtrk_2g_cckb_p; 1130 const u8 *pwrtrk_2g_ccka_n; 1131 const u8 *pwrtrk_2g_ccka_p; 1132 const s8 *pwrtrk_xtal_n; 1133 const s8 *pwrtrk_xtal_p; 1134 }; 1135 1136 enum rtw_wlan_cpu { 1137 RTW_WCPU_11AC, 1138 RTW_WCPU_11N, 1139 }; 1140 1141 enum rtw_fw_fifo_sel { 1142 RTW_FW_FIFO_SEL_TX, 1143 RTW_FW_FIFO_SEL_RX, 1144 RTW_FW_FIFO_SEL_RSVD_PAGE, 1145 RTW_FW_FIFO_SEL_REPORT, 1146 RTW_FW_FIFO_SEL_LLT, 1147 RTW_FW_FIFO_SEL_RXBUF_FW, 1148 1149 RTW_FW_FIFO_MAX, 1150 }; 1151 1152 enum rtw_fwcd_item { 1153 RTW_FWCD_TLV, 1154 RTW_FWCD_REG, 1155 RTW_FWCD_ROM, 1156 RTW_FWCD_IMEM, 1157 RTW_FWCD_DMEM, 1158 RTW_FWCD_EMEM, 1159 }; 1160 1161 /* hardware configuration for each IC */ 1162 struct rtw_chip_info { 1163 struct rtw_chip_ops *ops; 1164 u8 id; 1165 1166 const char *fw_name; 1167 enum rtw_wlan_cpu wlan_cpu; 1168 u8 tx_pkt_desc_sz; 1169 u8 tx_buf_desc_sz; 1170 u8 rx_pkt_desc_sz; 1171 u8 rx_buf_desc_sz; 1172 u32 phy_efuse_size; 1173 u32 log_efuse_size; 1174 u32 ptct_efuse_size; 1175 u32 txff_size; 1176 u32 rxff_size; 1177 u32 fw_rxff_size; 1178 u8 band; 1179 u8 page_size; 1180 u8 csi_buf_pg_num; 1181 u8 dig_max; 1182 u8 dig_min; 1183 u8 txgi_factor; 1184 bool is_pwr_by_rate_dec; 1185 bool rx_ldpc; 1186 bool tx_stbc; 1187 u8 max_power_index; 1188 1189 u16 fw_fifo_addr[RTW_FW_FIFO_MAX]; 1190 const struct rtw_fwcd_segs *fwcd_segs; 1191 1192 u8 default_1ss_tx_path; 1193 1194 bool path_div_supported; 1195 bool ht_supported; 1196 bool vht_supported; 1197 u8 lps_deep_mode_supported; 1198 1199 /* init values */ 1200 u8 sys_func_en; 1201 const struct rtw_pwr_seq_cmd **pwr_on_seq; 1202 const struct rtw_pwr_seq_cmd **pwr_off_seq; 1203 const struct rtw_rqpn *rqpn_table; 1204 const struct rtw_prioq_addrs *prioq_addrs; 1205 const struct rtw_page_table *page_table; 1206 const struct rtw_intf_phy_para_table *intf_table; 1207 1208 const struct rtw_hw_reg *dig; 1209 const struct rtw_hw_reg *dig_cck; 1210 u32 rf_base_addr[2]; 1211 u32 rf_sipi_addr[2]; 1212 const struct rtw_rf_sipi_addr *rf_sipi_read_addr; 1213 u8 fix_rf_phy_num; 1214 const struct rtw_ltecoex_addr *ltecoex_addr; 1215 1216 const struct rtw_table *mac_tbl; 1217 const struct rtw_table *agc_tbl; 1218 const struct rtw_table *bb_tbl; 1219 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX]; 1220 const struct rtw_table *rfk_init_tbl; 1221 1222 const struct rtw_rfe_def *rfe_defs; 1223 u32 rfe_defs_size; 1224 1225 bool en_dis_dpd; 1226 u16 dpd_ratemask; 1227 u8 iqk_threshold; 1228 u8 lck_threshold; 1229 const struct rtw_pwr_track_tbl *pwr_track_tbl; 1230 1231 u8 bfer_su_max_num; 1232 u8 bfer_mu_max_num; 1233 1234 struct rtw_hw_reg_offset *edcca_th; 1235 s8 l2h_th_ini_cs; 1236 s8 l2h_th_ini_ad; 1237 1238 const char *wow_fw_name; 1239 const struct wiphy_wowlan_support *wowlan_stub; 1240 const u8 max_sched_scan_ssids; 1241 1242 /* for 8821c set channel */ 1243 u32 ch_param[3]; 1244 1245 /* coex paras */ 1246 u32 coex_para_ver; 1247 u8 bt_desired_ver; 1248 bool scbd_support; 1249 bool new_scbd10_def; /* true: fix 2M(8822c) */ 1250 bool ble_hid_profile_support; 1251 u8 pstdma_type; /* 0: LPSoff, 1:LPSon */ 1252 u8 bt_rssi_type; 1253 u8 ant_isolation; 1254 u8 rssi_tolerance; 1255 u8 table_sant_num; 1256 u8 table_nsant_num; 1257 u8 tdma_sant_num; 1258 u8 tdma_nsant_num; 1259 u8 bt_afh_span_bw20; 1260 u8 bt_afh_span_bw40; 1261 u8 afh_5g_num; 1262 u8 wl_rf_para_num; 1263 u8 coex_info_hw_regs_num; 1264 const u8 *bt_rssi_step; 1265 const u8 *wl_rssi_step; 1266 const struct coex_table_para *table_nsant; 1267 const struct coex_table_para *table_sant; 1268 const struct coex_tdma_para *tdma_sant; 1269 const struct coex_tdma_para *tdma_nsant; 1270 const struct coex_rf_para *wl_rf_para_tx; 1271 const struct coex_rf_para *wl_rf_para_rx; 1272 const struct coex_5g_afh_map *afh_5g; 1273 const struct rtw_hw_reg *btg_reg; 1274 const struct rtw_reg_domain *coex_info_hw_regs; 1275 u32 wl_fw_desired_ver; 1276 }; 1277 1278 enum rtw_coex_bt_state_cnt { 1279 COEX_CNT_BT_RETRY, 1280 COEX_CNT_BT_REINIT, 1281 COEX_CNT_BT_REENABLE, 1282 COEX_CNT_BT_POPEVENT, 1283 COEX_CNT_BT_SETUPLINK, 1284 COEX_CNT_BT_IGNWLANACT, 1285 COEX_CNT_BT_INQ, 1286 COEX_CNT_BT_PAGE, 1287 COEX_CNT_BT_ROLESWITCH, 1288 COEX_CNT_BT_AFHUPDATE, 1289 COEX_CNT_BT_INFOUPDATE, 1290 COEX_CNT_BT_IQK, 1291 COEX_CNT_BT_IQKFAIL, 1292 1293 COEX_CNT_BT_MAX 1294 }; 1295 1296 enum rtw_coex_wl_state_cnt { 1297 COEX_CNT_WL_SCANAP, 1298 COEX_CNT_WL_CONNPKT, 1299 COEX_CNT_WL_COEXRUN, 1300 COEX_CNT_WL_NOISY0, 1301 COEX_CNT_WL_NOISY1, 1302 COEX_CNT_WL_NOISY2, 1303 COEX_CNT_WL_5MS_NOEXTEND, 1304 COEX_CNT_WL_FW_NOTIFY, 1305 1306 COEX_CNT_WL_MAX 1307 }; 1308 1309 struct rtw_coex_rfe { 1310 bool ant_switch_exist; 1311 bool ant_switch_diversity; 1312 bool ant_switch_with_bt; 1313 u8 rfe_module_type; 1314 u8 ant_switch_polarity; 1315 1316 /* true if WLG at BTG, else at WLAG */ 1317 bool wlg_at_btg; 1318 }; 1319 1320 #define COEX_WL_TDMA_PARA_LENGTH 5 1321 1322 struct rtw_coex_dm { 1323 bool cur_ps_tdma_on; 1324 bool cur_wl_rx_low_gain_en; 1325 bool ignore_wl_act; 1326 1327 u8 reason; 1328 u8 bt_rssi_state[4]; 1329 u8 wl_rssi_state[4]; 1330 u8 wl_ch_info[3]; 1331 u8 cur_ps_tdma; 1332 u8 cur_table; 1333 u8 ps_tdma_para[5]; 1334 u8 cur_bt_pwr_lvl; 1335 u8 cur_bt_lna_lvl; 1336 u8 cur_wl_pwr_lvl; 1337 u8 bt_status; 1338 u32 cur_ant_pos_type; 1339 u32 cur_switch_status; 1340 u32 setting_tdma; 1341 u8 fw_tdma_para[COEX_WL_TDMA_PARA_LENGTH]; 1342 }; 1343 1344 #define COEX_BTINFO_SRC_WL_FW 0x0 1345 #define COEX_BTINFO_SRC_BT_RSP 0x1 1346 #define COEX_BTINFO_SRC_BT_ACT 0x2 1347 #define COEX_BTINFO_SRC_BT_IQK 0x3 1348 #define COEX_BTINFO_SRC_BT_SCBD 0x4 1349 #define COEX_BTINFO_SRC_H2C60 0x5 1350 #define COEX_BTINFO_SRC_MAX 0x6 1351 1352 #define COEX_INFO_FTP BIT(7) 1353 #define COEX_INFO_A2DP BIT(6) 1354 #define COEX_INFO_HID BIT(5) 1355 #define COEX_INFO_SCO_BUSY BIT(4) 1356 #define COEX_INFO_ACL_BUSY BIT(3) 1357 #define COEX_INFO_INQ_PAGE BIT(2) 1358 #define COEX_INFO_SCO_ESCO BIT(1) 1359 #define COEX_INFO_CONNECTION BIT(0) 1360 #define COEX_BTINFO_LENGTH_MAX 10 1361 #define COEX_BTINFO_LENGTH 7 1362 1363 struct rtw_coex_stat { 1364 bool bt_disabled; 1365 bool bt_disabled_pre; 1366 bool bt_link_exist; 1367 bool bt_whck_test; 1368 bool bt_inq_page; 1369 bool bt_inq_remain; 1370 bool bt_inq; 1371 bool bt_page; 1372 bool bt_ble_voice; 1373 bool bt_ble_exist; 1374 bool bt_hfp_exist; 1375 bool bt_a2dp_exist; 1376 bool bt_hid_exist; 1377 bool bt_pan_exist; /* PAN or OPP */ 1378 bool bt_opp_exist; /* OPP only */ 1379 bool bt_acl_busy; 1380 bool bt_fix_2M; 1381 bool bt_setup_link; 1382 bool bt_multi_link; 1383 bool bt_multi_link_pre; 1384 bool bt_multi_link_remain; 1385 bool bt_a2dp_sink; 1386 bool bt_a2dp_active; 1387 bool bt_reenable; 1388 bool bt_ble_scan_en; 1389 bool bt_init_scan; 1390 bool bt_slave; 1391 bool bt_418_hid_exist; 1392 bool bt_ble_hid_exist; 1393 bool bt_mailbox_reply; 1394 1395 bool wl_under_lps; 1396 bool wl_under_ips; 1397 bool wl_hi_pri_task1; 1398 bool wl_hi_pri_task2; 1399 bool wl_force_lps_ctrl; 1400 bool wl_gl_busy; 1401 bool wl_linkscan_proc; 1402 bool wl_ps_state_fail; 1403 bool wl_tx_limit_en; 1404 bool wl_ampdu_limit_en; 1405 bool wl_connected; 1406 bool wl_slot_extend; 1407 bool wl_cck_lock; 1408 bool wl_cck_lock_pre; 1409 bool wl_cck_lock_ever; 1410 bool wl_connecting; 1411 bool wl_slot_toggle; 1412 bool wl_slot_toggle_change; /* if toggle to no-toggle */ 1413 1414 u32 bt_supported_version; 1415 u32 bt_supported_feature; 1416 u32 hi_pri_tx; 1417 u32 hi_pri_rx; 1418 u32 lo_pri_tx; 1419 u32 lo_pri_rx; 1420 u32 patch_ver; 1421 u16 bt_reg_vendor_ae; 1422 u16 bt_reg_vendor_ac; 1423 s8 bt_rssi; 1424 u8 kt_ver; 1425 u8 gnt_workaround_state; 1426 u8 tdma_timer_base; 1427 u8 bt_profile_num; 1428 u8 bt_info_c2h[COEX_BTINFO_SRC_MAX][COEX_BTINFO_LENGTH_MAX]; 1429 u8 bt_info_lb2; 1430 u8 bt_info_lb3; 1431 u8 bt_info_hb0; 1432 u8 bt_info_hb1; 1433 u8 bt_info_hb2; 1434 u8 bt_info_hb3; 1435 u8 bt_ble_scan_type; 1436 u8 bt_hid_pair_num; 1437 u8 bt_hid_slot; 1438 u8 bt_a2dp_bitpool; 1439 u8 bt_iqk_state; 1440 1441 u16 wl_beacon_interval; 1442 u8 wl_noisy_level; 1443 u8 wl_fw_dbg_info[10]; 1444 u8 wl_fw_dbg_info_pre[10]; 1445 u8 wl_rx_rate; 1446 u8 wl_tx_rate; 1447 u8 wl_rts_rx_rate; 1448 u8 wl_coex_mode; 1449 u8 wl_iot_peer; 1450 u8 ampdu_max_time; 1451 u8 wl_tput_dir; 1452 1453 u8 wl_toggle_para[6]; 1454 u8 wl_toggle_interval; 1455 1456 u16 score_board; 1457 u16 retry_limit; 1458 1459 /* counters to record bt states */ 1460 u32 cnt_bt[COEX_CNT_BT_MAX]; 1461 1462 /* counters to record wifi states */ 1463 u32 cnt_wl[COEX_CNT_WL_MAX]; 1464 1465 /* counters to record bt c2h data */ 1466 u32 cnt_bt_info_c2h[COEX_BTINFO_SRC_MAX]; 1467 1468 u32 darfrc; 1469 u32 darfrch; 1470 }; 1471 1472 struct rtw_coex { 1473 /* protects coex info request section */ 1474 struct mutex mutex; 1475 struct sk_buff_head queue; 1476 wait_queue_head_t wait; 1477 1478 bool under_5g; 1479 bool stop_dm; 1480 bool freeze; 1481 bool freerun; 1482 bool wl_rf_off; 1483 bool manual_control; 1484 1485 struct rtw_coex_stat stat; 1486 struct rtw_coex_dm dm; 1487 struct rtw_coex_rfe rfe; 1488 1489 struct delayed_work bt_relink_work; 1490 struct delayed_work bt_reenable_work; 1491 struct delayed_work defreeze_work; 1492 struct delayed_work wl_remain_work; 1493 struct delayed_work bt_remain_work; 1494 struct delayed_work wl_connecting_work; 1495 struct delayed_work bt_multi_link_remain_work; 1496 struct delayed_work wl_ccklock_work; 1497 1498 }; 1499 1500 #define DPK_RF_REG_NUM 7 1501 #define DPK_RF_PATH_NUM 2 1502 #define DPK_BB_REG_NUM 18 1503 #define DPK_CHANNEL_WIDTH_80 1 1504 1505 DECLARE_EWMA(thermal, 10, 4); 1506 1507 struct rtw_dpk_info { 1508 bool is_dpk_pwr_on; 1509 bool is_reload; 1510 1511 DECLARE_BITMAP(dpk_path_ok, DPK_RF_PATH_NUM); 1512 1513 u8 thermal_dpk[DPK_RF_PATH_NUM]; 1514 struct ewma_thermal avg_thermal[DPK_RF_PATH_NUM]; 1515 1516 u32 gnt_control; 1517 u32 gnt_value; 1518 1519 u8 result[RTW_RF_PATH_MAX]; 1520 u8 dpk_txagc[RTW_RF_PATH_MAX]; 1521 u32 coef[RTW_RF_PATH_MAX][20]; 1522 u16 dpk_gs[RTW_RF_PATH_MAX]; 1523 u8 thermal_dpk_delta[RTW_RF_PATH_MAX]; 1524 u8 pre_pwsf[RTW_RF_PATH_MAX]; 1525 1526 u8 dpk_band; 1527 u8 dpk_ch; 1528 u8 dpk_bw; 1529 }; 1530 1531 struct rtw_phy_cck_pd_reg { 1532 u32 reg_pd; 1533 u32 mask_pd; 1534 u32 reg_cs; 1535 u32 mask_cs; 1536 }; 1537 1538 #define DACK_MSBK_BACKUP_NUM 0xf 1539 #define DACK_DCK_BACKUP_NUM 0x2 1540 1541 struct rtw_swing_table { 1542 const u8 *p[RTW_RF_PATH_MAX]; 1543 const u8 *n[RTW_RF_PATH_MAX]; 1544 }; 1545 1546 struct rtw_pkt_count { 1547 u16 num_bcn_pkt; 1548 u16 num_qry_pkt[DESC_RATE_MAX]; 1549 }; 1550 1551 DECLARE_EWMA(evm, 10, 4); 1552 DECLARE_EWMA(snr, 10, 4); 1553 1554 struct rtw_iqk_info { 1555 bool done; 1556 struct { 1557 u32 s1_x; 1558 u32 s1_y; 1559 u32 s0_x; 1560 u32 s0_y; 1561 } result; 1562 }; 1563 1564 enum rtw_rf_band { 1565 RF_BAND_2G_CCK, 1566 RF_BAND_2G_OFDM, 1567 RF_BAND_5G_L, 1568 RF_BAND_5G_M, 1569 RF_BAND_5G_H, 1570 RF_BAND_MAX 1571 }; 1572 1573 #define RF_GAIN_NUM 11 1574 #define RF_HW_OFFSET_NUM 10 1575 1576 struct rtw_gapk_info { 1577 u32 rf3f_bp[RF_BAND_MAX][RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1578 u32 rf3f_fs[RTW_RF_PATH_MAX][RF_GAIN_NUM]; 1579 bool txgapk_bp_done; 1580 s8 offset[RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1581 s8 fianl_offset[RF_GAIN_NUM][RTW_RF_PATH_MAX]; 1582 u8 read_txgain; 1583 u8 channel; 1584 }; 1585 1586 #define EDCCA_TH_L2H_IDX 0 1587 #define EDCCA_TH_H2L_IDX 1 1588 #define EDCCA_TH_L2H_LB 48 1589 #define EDCCA_ADC_BACKOFF 12 1590 #define EDCCA_IGI_BASE 50 1591 #define EDCCA_IGI_L2H_DIFF 8 1592 #define EDCCA_L2H_H2L_DIFF 7 1593 #define EDCCA_L2H_H2L_DIFF_NORMAL 8 1594 1595 enum rtw_edcca_mode { 1596 RTW_EDCCA_NORMAL = 0, 1597 RTW_EDCCA_ADAPTIVITY = 1, 1598 }; 1599 1600 struct rtw_cfo_track { 1601 bool is_adjust; 1602 u8 crystal_cap; 1603 s32 cfo_tail[RTW_RF_PATH_MAX]; 1604 s32 cfo_cnt[RTW_RF_PATH_MAX]; 1605 u32 packet_count; 1606 u32 packet_count_pre; 1607 }; 1608 1609 #define RRSR_INIT_2G 0x15f 1610 #define RRSR_INIT_5G 0x150 1611 1612 enum rtw_dm_cap { 1613 RTW_DM_CAP_NA, 1614 RTW_DM_CAP_TXGAPK, 1615 RTW_DM_CAP_NUM 1616 }; 1617 1618 struct rtw_dm_info { 1619 u32 cck_fa_cnt; 1620 u32 ofdm_fa_cnt; 1621 u32 total_fa_cnt; 1622 u32 cck_cca_cnt; 1623 u32 ofdm_cca_cnt; 1624 u32 total_cca_cnt; 1625 1626 u32 cck_ok_cnt; 1627 u32 cck_err_cnt; 1628 u32 ofdm_ok_cnt; 1629 u32 ofdm_err_cnt; 1630 u32 ht_ok_cnt; 1631 u32 ht_err_cnt; 1632 u32 vht_ok_cnt; 1633 u32 vht_err_cnt; 1634 1635 u8 min_rssi; 1636 u8 pre_min_rssi; 1637 u16 fa_history[4]; 1638 u8 igi_history[4]; 1639 u8 igi_bitmap; 1640 bool damping; 1641 u8 damping_cnt; 1642 u8 damping_rssi; 1643 1644 u8 cck_gi_u_bnd; 1645 u8 cck_gi_l_bnd; 1646 1647 u8 fix_rate; 1648 u8 tx_rate; 1649 u32 rrsr_val_init; 1650 u32 rrsr_mask_min; 1651 u8 thermal_avg[RTW_RF_PATH_MAX]; 1652 u8 thermal_meter_k; 1653 u8 thermal_meter_lck; 1654 s8 delta_power_index[RTW_RF_PATH_MAX]; 1655 s8 delta_power_index_last[RTW_RF_PATH_MAX]; 1656 u8 default_ofdm_index; 1657 bool pwr_trk_triggered; 1658 bool pwr_trk_init_trigger; 1659 struct ewma_thermal avg_thermal[RTW_RF_PATH_MAX]; 1660 s8 txagc_remnant_cck; 1661 s8 txagc_remnant_ofdm; 1662 1663 /* backup dack results for each path and I/Q */ 1664 u32 dack_adck[RTW_RF_PATH_MAX]; 1665 u16 dack_msbk[RTW_RF_PATH_MAX][2][DACK_MSBK_BACKUP_NUM]; 1666 u8 dack_dck[RTW_RF_PATH_MAX][2][DACK_DCK_BACKUP_NUM]; 1667 1668 struct rtw_dpk_info dpk_info; 1669 struct rtw_cfo_track cfo_track; 1670 1671 /* [bandwidth 0:20M/1:40M][number of path] */ 1672 u8 cck_pd_lv[2][RTW_RF_PATH_MAX]; 1673 u32 cck_fa_avg; 1674 u8 cck_pd_default; 1675 1676 /* save the last rx phy status for debug */ 1677 s8 rx_snr[RTW_RF_PATH_MAX]; 1678 u8 rx_evm_dbm[RTW_RF_PATH_MAX]; 1679 s16 cfo_tail[RTW_RF_PATH_MAX]; 1680 u8 rssi[RTW_RF_PATH_MAX]; 1681 u8 curr_rx_rate; 1682 struct rtw_pkt_count cur_pkt_count; 1683 struct rtw_pkt_count last_pkt_count; 1684 struct ewma_evm ewma_evm[RTW_EVM_NUM]; 1685 struct ewma_snr ewma_snr[RTW_SNR_NUM]; 1686 1687 u32 dm_flags; /* enum rtw_dm_cap */ 1688 struct rtw_iqk_info iqk; 1689 struct rtw_gapk_info gapk; 1690 bool is_bt_iqk_timeout; 1691 1692 s8 l2h_th_ini; 1693 enum rtw_edcca_mode edcca_mode; 1694 u8 scan_density; 1695 }; 1696 1697 struct rtw_efuse { 1698 u32 size; 1699 u32 physical_size; 1700 u32 logical_size; 1701 u32 protect_size; 1702 1703 u8 addr[ETH_ALEN]; 1704 u8 channel_plan; 1705 u8 country_code[2]; 1706 u8 rf_board_option; 1707 u8 rfe_option; 1708 u8 power_track_type; 1709 u8 thermal_meter[RTW_RF_PATH_MAX]; 1710 u8 thermal_meter_k; 1711 u8 crystal_cap; 1712 u8 ant_div_cfg; 1713 u8 ant_div_type; 1714 u8 regd; 1715 u8 afe; 1716 1717 u8 lna_type_2g; 1718 u8 lna_type_5g; 1719 u8 glna_type; 1720 u8 alna_type; 1721 bool ext_lna_2g; 1722 bool ext_lna_5g; 1723 u8 pa_type_2g; 1724 u8 pa_type_5g; 1725 u8 gpa_type; 1726 u8 apa_type; 1727 bool ext_pa_2g; 1728 bool ext_pa_5g; 1729 u8 tx_bb_swing_setting_2g; 1730 u8 tx_bb_swing_setting_5g; 1731 1732 bool btcoex; 1733 /* bt share antenna with wifi */ 1734 bool share_ant; 1735 u8 bt_setting; 1736 1737 struct { 1738 u8 hci; 1739 u8 bw; 1740 u8 ptcl; 1741 u8 nss; 1742 u8 ant_num; 1743 } hw_cap; 1744 1745 struct rtw_txpwr_idx txpwr_idx_table[4]; 1746 }; 1747 1748 struct rtw_phy_cond { 1749 #ifdef __LITTLE_ENDIAN 1750 u32 rfe:8; 1751 u32 intf:4; 1752 u32 pkg:4; 1753 u32 plat:4; 1754 u32 intf_rsvd:4; 1755 u32 cut:4; 1756 u32 branch:2; 1757 u32 neg:1; 1758 u32 pos:1; 1759 #else 1760 u32 pos:1; 1761 u32 neg:1; 1762 u32 branch:2; 1763 u32 cut:4; 1764 u32 intf_rsvd:4; 1765 u32 plat:4; 1766 u32 pkg:4; 1767 u32 intf:4; 1768 u32 rfe:8; 1769 #endif 1770 /* for intf:4 */ 1771 #define INTF_PCIE BIT(0) 1772 #define INTF_USB BIT(1) 1773 #define INTF_SDIO BIT(2) 1774 /* for branch:2 */ 1775 #define BRANCH_IF 0 1776 #define BRANCH_ELIF 1 1777 #define BRANCH_ELSE 2 1778 #define BRANCH_ENDIF 3 1779 }; 1780 1781 struct rtw_fifo_conf { 1782 /* tx fifo information */ 1783 u16 rsvd_boundary; 1784 u16 rsvd_pg_num; 1785 u16 rsvd_drv_pg_num; 1786 u16 txff_pg_num; 1787 u16 acq_pg_num; 1788 u16 rsvd_drv_addr; 1789 u16 rsvd_h2c_info_addr; 1790 u16 rsvd_h2c_sta_info_addr; 1791 u16 rsvd_h2cq_addr; 1792 u16 rsvd_cpu_instr_addr; 1793 u16 rsvd_fw_txbuf_addr; 1794 u16 rsvd_csibuf_addr; 1795 const struct rtw_rqpn *rqpn; 1796 }; 1797 1798 struct rtw_fwcd_desc { 1799 u32 size; 1800 u8 *next; 1801 u8 *data; 1802 }; 1803 1804 struct rtw_fwcd_segs { 1805 const u32 *segs; 1806 u8 num; 1807 }; 1808 1809 #define FW_CD_TYPE 0xffff 1810 #define FW_CD_LEN 4 1811 #define FW_CD_VAL 0xaabbccdd 1812 struct rtw_fw_state { 1813 const struct firmware *firmware; 1814 struct rtw_dev *rtwdev; 1815 struct completion completion; 1816 struct rtw_fwcd_desc fwcd_desc; 1817 u16 version; 1818 u8 sub_version; 1819 u8 sub_index; 1820 u16 h2c_version; 1821 u32 feature; 1822 }; 1823 1824 enum rtw_sar_sources { 1825 RTW_SAR_SOURCE_NONE, 1826 RTW_SAR_SOURCE_COMMON, 1827 }; 1828 1829 enum rtw_sar_bands { 1830 RTW_SAR_BAND_0, 1831 RTW_SAR_BAND_1, 1832 /* RTW_SAR_BAND_2, not used now */ 1833 RTW_SAR_BAND_3, 1834 RTW_SAR_BAND_4, 1835 1836 RTW_SAR_BAND_NR, 1837 }; 1838 1839 /* the union is reserved for other knids of SAR sources 1840 * which might not re-use same format with array common. 1841 */ 1842 union rtw_sar_cfg { 1843 s8 common[RTW_SAR_BAND_NR]; 1844 }; 1845 1846 struct rtw_sar { 1847 enum rtw_sar_sources src; 1848 union rtw_sar_cfg cfg[RTW_RF_PATH_MAX][RTW_RATE_SECTION_MAX]; 1849 }; 1850 1851 struct rtw_hal { 1852 u32 rcr; 1853 1854 u32 chip_version; 1855 u8 cut_version; 1856 u8 mp_chip; 1857 u8 oem_id; 1858 struct rtw_phy_cond phy_cond; 1859 1860 u8 ps_mode; 1861 u8 current_channel; 1862 u8 current_primary_channel_index; 1863 u8 current_band_width; 1864 u8 current_band_type; 1865 1866 /* center channel for different available bandwidth, 1867 * val of (bw > current_band_width) is invalid 1868 */ 1869 u8 cch_by_bw[RTW_MAX_CHANNEL_WIDTH + 1]; 1870 1871 u8 sec_ch_offset; 1872 u8 rf_type; 1873 u8 rf_path_num; 1874 u8 rf_phy_num; 1875 u32 antenna_tx; 1876 u32 antenna_rx; 1877 u8 bfee_sts_cap; 1878 1879 /* protect tx power section */ 1880 struct mutex tx_power_mutex; 1881 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX] 1882 [DESC_RATE_MAX]; 1883 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX] 1884 [DESC_RATE_MAX]; 1885 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX] 1886 [RTW_RATE_SECTION_MAX]; 1887 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX] 1888 [RTW_RATE_SECTION_MAX]; 1889 s8 tx_pwr_limit_2g[RTW_REGD_MAX] 1890 [RTW_CHANNEL_WIDTH_MAX] 1891 [RTW_RATE_SECTION_MAX] 1892 [RTW_MAX_CHANNEL_NUM_2G]; 1893 s8 tx_pwr_limit_5g[RTW_REGD_MAX] 1894 [RTW_CHANNEL_WIDTH_MAX] 1895 [RTW_RATE_SECTION_MAX] 1896 [RTW_MAX_CHANNEL_NUM_5G]; 1897 s8 tx_pwr_tbl[RTW_RF_PATH_MAX] 1898 [DESC_RATE_MAX]; 1899 1900 enum rtw_sar_bands sar_band; 1901 struct rtw_sar sar; 1902 }; 1903 1904 struct rtw_path_div { 1905 enum rtw_bb_path current_tx_path; 1906 u32 path_a_sum; 1907 u32 path_b_sum; 1908 u16 path_a_cnt; 1909 u16 path_b_cnt; 1910 }; 1911 1912 struct rtw_chan_info { 1913 int pri_ch_idx; 1914 int action_id; 1915 int bw; 1916 u8 extra_info; 1917 u8 channel; 1918 u16 timeout; 1919 }; 1920 1921 struct rtw_chan_list { 1922 u32 buf_size; 1923 u32 ch_num; 1924 u32 size; 1925 u16 addr; 1926 }; 1927 1928 struct rtw_hw_scan_info { 1929 struct ieee80211_vif *scanning_vif; 1930 u8 probe_pg_size; 1931 u8 op_pri_ch_idx; 1932 u8 op_chan; 1933 u8 op_bw; 1934 }; 1935 1936 struct rtw_dev { 1937 struct ieee80211_hw *hw; 1938 struct device *dev; 1939 1940 struct rtw_hci hci; 1941 1942 struct rtw_hw_scan_info scan_info; 1943 struct rtw_chip_info *chip; 1944 struct rtw_hal hal; 1945 struct rtw_fifo_conf fifo; 1946 struct rtw_fw_state fw; 1947 struct rtw_efuse efuse; 1948 struct rtw_sec_desc sec; 1949 struct rtw_traffic_stats stats; 1950 struct rtw_regd regd; 1951 struct rtw_bf_info bf_info; 1952 1953 struct rtw_dm_info dm_info; 1954 struct rtw_coex coex; 1955 1956 /* ensures exclusive access from mac80211 callbacks */ 1957 struct mutex mutex; 1958 1959 /* read/write rf register */ 1960 spinlock_t rf_lock; 1961 1962 /* watch dog every 2 sec */ 1963 struct delayed_work watch_dog_work; 1964 u32 watch_dog_cnt; 1965 1966 struct list_head rsvd_page_list; 1967 1968 /* c2h cmd queue & handler work */ 1969 struct sk_buff_head c2h_queue; 1970 struct work_struct c2h_work; 1971 struct work_struct fw_recovery_work; 1972 1973 /* used to protect txqs list */ 1974 spinlock_t txq_lock; 1975 struct list_head txqs; 1976 struct workqueue_struct *tx_wq; 1977 struct work_struct tx_work; 1978 struct work_struct ba_work; 1979 1980 struct rtw_tx_report tx_report; 1981 1982 struct { 1983 /* incicate the mail box to use with fw */ 1984 u8 last_box_num; 1985 /* protect to send h2c to fw */ 1986 spinlock_t lock; 1987 u32 seq; 1988 } h2c; 1989 1990 /* lps power state & handler work */ 1991 struct rtw_lps_conf lps_conf; 1992 bool ps_enabled; 1993 bool beacon_loss; 1994 struct completion lps_leave_check; 1995 1996 struct dentry *debugfs; 1997 1998 u8 sta_cnt; 1999 u32 rts_threshold; 2000 2001 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM); 2002 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS); 2003 2004 u8 mp_mode; 2005 struct rtw_path_div dm_path_div; 2006 2007 struct rtw_fw_state wow_fw; 2008 struct rtw_wow_param wow; 2009 2010 bool need_rfk; 2011 struct completion fw_scan_density; 2012 2013 /* hci related data, must be last */ 2014 u8 priv[] __aligned(sizeof(void *)); 2015 }; 2016 2017 #include "hci.h" 2018 2019 static inline bool rtw_is_assoc(struct rtw_dev *rtwdev) 2020 { 2021 return !!rtwdev->sta_cnt; 2022 } 2023 2024 static inline struct ieee80211_txq *rtwtxq_to_txq(struct rtw_txq *rtwtxq) 2025 { 2026 void *p = rtwtxq; 2027 2028 return container_of(p, struct ieee80211_txq, drv_priv); 2029 } 2030 2031 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw_vif *rtwvif) 2032 { 2033 void *p = rtwvif; 2034 2035 return container_of(p, struct ieee80211_vif, drv_priv); 2036 } 2037 2038 static inline bool rtw_ssid_equal(struct cfg80211_ssid *a, 2039 struct cfg80211_ssid *b) 2040 { 2041 if (!a || !b || a->ssid_len != b->ssid_len) 2042 return false; 2043 2044 if (memcmp(a->ssid, b->ssid, a->ssid_len)) 2045 return false; 2046 2047 return true; 2048 } 2049 2050 static inline void rtw_chip_efuse_grant_on(struct rtw_dev *rtwdev) 2051 { 2052 if (rtwdev->chip->ops->efuse_grant) 2053 rtwdev->chip->ops->efuse_grant(rtwdev, true); 2054 } 2055 2056 static inline void rtw_chip_efuse_grant_off(struct rtw_dev *rtwdev) 2057 { 2058 if (rtwdev->chip->ops->efuse_grant) 2059 rtwdev->chip->ops->efuse_grant(rtwdev, false); 2060 } 2061 2062 static inline bool rtw_chip_wcpu_11n(struct rtw_dev *rtwdev) 2063 { 2064 return rtwdev->chip->wlan_cpu == RTW_WCPU_11N; 2065 } 2066 2067 static inline bool rtw_chip_wcpu_11ac(struct rtw_dev *rtwdev) 2068 { 2069 return rtwdev->chip->wlan_cpu == RTW_WCPU_11AC; 2070 } 2071 2072 static inline bool rtw_chip_has_rx_ldpc(struct rtw_dev *rtwdev) 2073 { 2074 return rtwdev->chip->rx_ldpc; 2075 } 2076 2077 static inline bool rtw_chip_has_tx_stbc(struct rtw_dev *rtwdev) 2078 { 2079 return rtwdev->chip->tx_stbc; 2080 } 2081 2082 static inline void rtw_release_macid(struct rtw_dev *rtwdev, u8 mac_id) 2083 { 2084 clear_bit(mac_id, rtwdev->mac_id_map); 2085 } 2086 2087 static inline int rtw_chip_dump_fw_crash(struct rtw_dev *rtwdev) 2088 { 2089 if (rtwdev->chip->ops->dump_fw_crash) 2090 return rtwdev->chip->ops->dump_fw_crash(rtwdev); 2091 2092 return 0; 2093 } 2094 2095 void rtw_set_rx_freq_band(struct rtw_rx_pkt_stat *pkt_stat, u8 channel); 2096 void rtw_get_channel_params(struct cfg80211_chan_def *chandef, 2097 struct rtw_channel_params *ch_param); 2098 bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target); 2099 bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val); 2100 bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value); 2101 void rtw_restore_reg(struct rtw_dev *rtwdev, 2102 struct rtw_backup_info *bckp, u32 num); 2103 void rtw_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss); 2104 void rtw_set_channel(struct rtw_dev *rtwdev); 2105 void rtw_chip_prepare_tx(struct rtw_dev *rtwdev); 2106 void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 2107 u32 config); 2108 void rtw_tx_report_purge_timer(struct timer_list *t); 2109 void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si); 2110 void rtw_core_scan_start(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif, 2111 const u8 *mac_addr, bool hw_scan); 2112 void rtw_core_scan_complete(struct rtw_dev *rtwdev, struct ieee80211_vif *vif); 2113 int rtw_core_start(struct rtw_dev *rtwdev); 2114 void rtw_core_stop(struct rtw_dev *rtwdev); 2115 int rtw_chip_info_setup(struct rtw_dev *rtwdev); 2116 int rtw_core_init(struct rtw_dev *rtwdev); 2117 void rtw_core_deinit(struct rtw_dev *rtwdev); 2118 int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 2119 void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw); 2120 u16 rtw_desc_to_bitrate(u8 desc_rate); 2121 void rtw_vif_assoc_changed(struct rtw_vif *rtwvif, 2122 struct ieee80211_bss_conf *conf); 2123 int rtw_sta_add(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 2124 struct ieee80211_vif *vif); 2125 void rtw_sta_remove(struct rtw_dev *rtwdev, struct ieee80211_sta *sta, 2126 bool fw_exist); 2127 void rtw_fw_recovery(struct rtw_dev *rtwdev); 2128 void rtw_core_fw_scan_notify(struct rtw_dev *rtwdev, bool start); 2129 int rtw_dump_fw(struct rtw_dev *rtwdev, const u32 ocp_src, u32 size, 2130 u32 fwcd_item); 2131 int rtw_dump_reg(struct rtw_dev *rtwdev, const u32 addr, const u32 size); 2132 2133 #if defined(__linux__) 2134 #define rtw88_static_assert(_x) static_assert(_x) 2135 #elif defined(__FreeBSD__) 2136 #define rtw88_static_assert(_x) _Static_assert(_x, "bad array size") 2137 #endif 2138 2139 #endif 2140