1*2774f206SBjoern A. Zeeb /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2*2774f206SBjoern A. Zeeb /* Copyright(c) 2018-2019 Realtek Corporation 3*2774f206SBjoern A. Zeeb */ 4*2774f206SBjoern A. Zeeb 5*2774f206SBjoern A. Zeeb #ifndef __RTW_EFUSE_H__ 6*2774f206SBjoern A. Zeeb #define __RTW_EFUSE_H__ 7*2774f206SBjoern A. Zeeb 8*2774f206SBjoern A. Zeeb #define EFUSE_HW_CAP_IGNORE 0 9*2774f206SBjoern A. Zeeb #define EFUSE_HW_CAP_PTCL_VHT 3 10*2774f206SBjoern A. Zeeb #define EFUSE_HW_CAP_SUPP_BW80 7 11*2774f206SBjoern A. Zeeb #define EFUSE_HW_CAP_SUPP_BW40 6 12*2774f206SBjoern A. Zeeb 13*2774f206SBjoern A. Zeeb #define EFUSE_READ_FAIL 0xff 14*2774f206SBjoern A. Zeeb 15*2774f206SBjoern A. Zeeb #define GET_EFUSE_HW_CAP_HCI(hw_cap) \ 16*2774f206SBjoern A. Zeeb le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(3, 0)) 17*2774f206SBjoern A. Zeeb #define GET_EFUSE_HW_CAP_BW(hw_cap) \ 18*2774f206SBjoern A. Zeeb le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(18, 16)) 19*2774f206SBjoern A. Zeeb #define GET_EFUSE_HW_CAP_NSS(hw_cap) \ 20*2774f206SBjoern A. Zeeb le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(20, 19)) 21*2774f206SBjoern A. Zeeb #define GET_EFUSE_HW_CAP_ANT_NUM(hw_cap) \ 22*2774f206SBjoern A. Zeeb le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(23, 21)) 23*2774f206SBjoern A. Zeeb #define GET_EFUSE_HW_CAP_PTCL(hw_cap) \ 24*2774f206SBjoern A. Zeeb le32_get_bits(*((__le32 *)(hw_cap) + 0x01), GENMASK(27, 26)) 25*2774f206SBjoern A. Zeeb 26*2774f206SBjoern A. Zeeb int rtw_parse_efuse_map(struct rtw_dev *rtwdev); 27*2774f206SBjoern A. Zeeb int rtw_read8_physical_efuse(struct rtw_dev *rtwdev, u16 addr, u8 *data); 28*2774f206SBjoern A. Zeeb 29*2774f206SBjoern A. Zeeb #endif 30