xref: /freebsd/sys/contrib/dev/rtw88/bf.c (revision 924226fba12cc9a228c73b956e1b7fa24c60b055)
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019  Realtek Corporation.
3  */
4 
5 #include "main.h"
6 #include "reg.h"
7 #include "bf.h"
8 #include "debug.h"
9 
10 void rtw_bf_disassoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
11 		     struct ieee80211_bss_conf *bss_conf)
12 {
13 	struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
14 	struct rtw_bfee *bfee = &rtwvif->bfee;
15 	struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
16 
17 	if (bfee->role == RTW_BFEE_NONE)
18 		return;
19 
20 	if (bfee->role == RTW_BFEE_MU)
21 		bfinfo->bfer_mu_cnt--;
22 	else if (bfee->role == RTW_BFEE_SU)
23 		bfinfo->bfer_su_cnt--;
24 
25 	rtw_chip_config_bfee(rtwdev, rtwvif, bfee, false);
26 
27 	bfee->role = RTW_BFEE_NONE;
28 }
29 
30 void rtw_bf_assoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
31 		  struct ieee80211_bss_conf *bss_conf)
32 {
33 	struct ieee80211_hw *hw = rtwdev->hw;
34 	struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
35 	struct rtw_bfee *bfee = &rtwvif->bfee;
36 	struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
37 	struct rtw_chip_info *chip = rtwdev->chip;
38 	struct ieee80211_sta *sta;
39 	struct ieee80211_sta_vht_cap *vht_cap;
40 	struct ieee80211_sta_vht_cap *ic_vht_cap;
41 	const u8 *bssid = bss_conf->bssid;
42 	u32 sound_dim;
43 	u8 i;
44 
45 	if (!(chip->band & RTW_BAND_5G))
46 		return;
47 
48 	rcu_read_lock();
49 
50 	sta = ieee80211_find_sta(vif, bssid);
51 	if (!sta) {
52 #if defined(__linux__)
53 		rtw_warn(rtwdev, "failed to find station entry for bss %pM\n",
54 			 bssid);
55 #elif defined(__FreeBSD__)
56 		rtw_warn(rtwdev, "failed to find station entry for bss %6D\n",
57 			 bssid, ":");
58 #endif
59 		goto out_unlock;
60 	}
61 
62 	ic_vht_cap = &hw->wiphy->bands[NL80211_BAND_5GHZ]->vht_cap;
63 	vht_cap = &sta->deflink.vht_cap;
64 
65 	if ((ic_vht_cap->cap & IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE) &&
66 	    (vht_cap->cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE)) {
67 		if (bfinfo->bfer_mu_cnt >= chip->bfer_mu_max_num) {
68 			rtw_dbg(rtwdev, RTW_DBG_BF, "mu bfer number over limit\n");
69 			goto out_unlock;
70 		}
71 
72 		ether_addr_copy(bfee->mac_addr, bssid);
73 		bfee->role = RTW_BFEE_MU;
74 		bfee->p_aid = (bssid[5] << 1) | (bssid[4] >> 7);
75 		bfee->aid = bss_conf->aid;
76 		bfinfo->bfer_mu_cnt++;
77 
78 		rtw_chip_config_bfee(rtwdev, rtwvif, bfee, true);
79 	} else if ((ic_vht_cap->cap & IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE) &&
80 		   (vht_cap->cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) {
81 		if (bfinfo->bfer_su_cnt >= chip->bfer_su_max_num) {
82 			rtw_dbg(rtwdev, RTW_DBG_BF, "su bfer number over limit\n");
83 			goto out_unlock;
84 		}
85 
86 		sound_dim = vht_cap->cap &
87 			    IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK;
88 		sound_dim >>= IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_SHIFT;
89 
90 		ether_addr_copy(bfee->mac_addr, bssid);
91 		bfee->role = RTW_BFEE_SU;
92 		bfee->sound_dim = (u8)sound_dim;
93 		bfee->g_id = 0;
94 		bfee->p_aid = (bssid[5] << 1) | (bssid[4] >> 7);
95 		bfinfo->bfer_su_cnt++;
96 		for (i = 0; i < chip->bfer_su_max_num; i++) {
97 			if (!test_bit(i, bfinfo->bfer_su_reg_maping)) {
98 				set_bit(i, bfinfo->bfer_su_reg_maping);
99 				bfee->su_reg_index = i;
100 				break;
101 			}
102 		}
103 
104 		rtw_chip_config_bfee(rtwdev, rtwvif, bfee, true);
105 	}
106 
107 out_unlock:
108 	rcu_read_unlock();
109 }
110 
111 void rtw_bf_init_bfer_entry_mu(struct rtw_dev *rtwdev,
112 			       struct mu_bfer_init_para *param)
113 {
114 	u16 mu_bf_ctl = 0;
115 	u8 *addr = param->bfer_address;
116 	int i;
117 
118 	for (i = 0; i < ETH_ALEN; i++)
119 		rtw_write8(rtwdev, REG_ASSOCIATED_BFMER0_INFO + i, addr[i]);
120 	rtw_write16(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 6, param->paid);
121 	rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20, param->csi_para);
122 
123 	mu_bf_ctl = rtw_read16(rtwdev, REG_WMAC_MU_BF_CTL) & 0xC000;
124 	mu_bf_ctl |= param->my_aid | (param->csi_length_sel << 12);
125 	rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, mu_bf_ctl);
126 }
127 
128 void rtw_bf_cfg_sounding(struct rtw_dev *rtwdev, struct rtw_vif *vif,
129 			 enum rtw_trx_desc_rate rate)
130 {
131 	u32 psf_ctl = 0;
132 	u8 csi_rsc = 0x1;
133 
134 	psf_ctl = rtw_read32(rtwdev, REG_BBPSF_CTRL) |
135 		  BIT_WMAC_USE_NDPARATE |
136 		  (csi_rsc << 13);
137 
138 	rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
139 			RTW_SND_CTRL_SOUNDING);
140 	rtw_write8(rtwdev, REG_SND_PTCL_CTRL + 3, 0x26);
141 	rtw_write8_clr(rtwdev, REG_RXFLTMAP1, BIT_RXFLTMAP1_BF_REPORT_POLL);
142 	rtw_write8_clr(rtwdev, REG_RXFLTMAP4, BIT_RXFLTMAP4_BF_REPORT_POLL);
143 
144 	if (vif->net_type == RTW_NET_AP_MODE)
145 		rtw_write32(rtwdev, REG_BBPSF_CTRL, psf_ctl | BIT(12));
146 	else
147 		rtw_write32(rtwdev, REG_BBPSF_CTRL, psf_ctl & ~BIT(12));
148 }
149 
150 void rtw_bf_cfg_mu_bfee(struct rtw_dev *rtwdev, struct cfg_mumimo_para *param)
151 {
152 	u8 mu_tbl_sel;
153 	u8 mu_valid;
154 
155 	mu_valid = rtw_read8(rtwdev, REG_MU_TX_CTL) &
156 		   ~BIT_MASK_R_MU_TABLE_VALID;
157 
158 	rtw_write8(rtwdev, REG_MU_TX_CTL,
159 		   (mu_valid | BIT(0) | BIT(1)) & ~(BIT(7)));
160 
161 	mu_tbl_sel = rtw_read8(rtwdev, REG_MU_TX_CTL + 1) & 0xF8;
162 
163 	rtw_write8(rtwdev, REG_MU_TX_CTL + 1, mu_tbl_sel);
164 	rtw_write32(rtwdev, REG_MU_STA_GID_VLD, param->given_gid_tab[0]);
165 	rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO, param->given_user_pos[0]);
166 	rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO + 4,
167 		    param->given_user_pos[1]);
168 
169 	rtw_write8(rtwdev, REG_MU_TX_CTL + 1, mu_tbl_sel | 1);
170 	rtw_write32(rtwdev, REG_MU_STA_GID_VLD, param->given_gid_tab[1]);
171 	rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO, param->given_user_pos[2]);
172 	rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO + 4,
173 		    param->given_user_pos[3]);
174 }
175 
176 void rtw_bf_del_bfer_entry_mu(struct rtw_dev *rtwdev)
177 {
178 	rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO, 0);
179 	rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 4, 0);
180 	rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, 0);
181 	rtw_write8(rtwdev, REG_MU_TX_CTL, 0);
182 }
183 
184 void rtw_bf_del_sounding(struct rtw_dev *rtwdev)
185 {
186 	rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM, 0);
187 }
188 
189 void rtw_bf_enable_bfee_su(struct rtw_dev *rtwdev, struct rtw_vif *vif,
190 			   struct rtw_bfee *bfee)
191 {
192 	u8 nc_index = hweight8(rtwdev->hal.antenna_rx) - 1;
193 	u8 nr_index = bfee->sound_dim;
194 	u8 grouping = 0, codebookinfo = 1, coefficientsize = 3;
195 	u32 addr_bfer_info, addr_csi_rpt, csi_param;
196 	u8 i;
197 
198 	rtw_dbg(rtwdev, RTW_DBG_BF, "config as an su bfee\n");
199 
200 	switch (bfee->su_reg_index) {
201 	case 1:
202 		addr_bfer_info = REG_ASSOCIATED_BFMER1_INFO;
203 		addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20 + 2;
204 		break;
205 	case 0:
206 	default:
207 		addr_bfer_info = REG_ASSOCIATED_BFMER0_INFO;
208 		addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20;
209 		break;
210 	}
211 
212 	/* Sounding protocol control */
213 	rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
214 			RTW_SND_CTRL_SOUNDING);
215 
216 	/* MAC address/Partial AID of Beamformer */
217 	for (i = 0; i < ETH_ALEN; i++)
218 		rtw_write8(rtwdev, addr_bfer_info + i, bfee->mac_addr[i]);
219 
220 	csi_param = (u16)((coefficientsize << 10) |
221 			  (codebookinfo << 8) |
222 			  (grouping << 6) |
223 			  (nr_index << 3) |
224 			  nc_index);
225 	rtw_write16(rtwdev, addr_csi_rpt, csi_param);
226 
227 	/* ndp rx standby timer */
228 	rtw_write8(rtwdev, REG_SND_PTCL_CTRL + 3, RTW_NDP_RX_STANDBY_TIME);
229 }
230 EXPORT_SYMBOL(rtw_bf_enable_bfee_su);
231 
232 /* nc index: 1 2T2R 0 1T1R
233  * nr index: 1 use Nsts 0 use reg setting
234  * codebookinfo: 1 802.11ac 3 802.11n
235  */
236 void rtw_bf_enable_bfee_mu(struct rtw_dev *rtwdev, struct rtw_vif *vif,
237 			   struct rtw_bfee *bfee)
238 {
239 	struct rtw_bf_info *bf_info = &rtwdev->bf_info;
240 	struct mu_bfer_init_para param;
241 	u8 nc_index = hweight8(rtwdev->hal.antenna_rx) - 1;
242 	u8 nr_index = 1;
243 	u8 grouping = 0, codebookinfo = 1, coefficientsize = 0;
244 	u32 csi_param;
245 
246 	rtw_dbg(rtwdev, RTW_DBG_BF, "config as an mu bfee\n");
247 
248 	csi_param = (u16)((coefficientsize << 10) |
249 			  (codebookinfo << 8) |
250 			  (grouping << 6) |
251 			  (nr_index << 3) |
252 			  nc_index);
253 
254 	rtw_dbg(rtwdev, RTW_DBG_BF, "nc=%d nr=%d group=%d codebookinfo=%d coefficientsize=%d\n",
255 		nc_index, nr_index, grouping, codebookinfo,
256 		coefficientsize);
257 
258 	param.paid = bfee->p_aid;
259 	param.csi_para = csi_param;
260 	param.my_aid = bfee->aid & 0xfff;
261 	param.csi_length_sel = HAL_CSI_SEG_4K;
262 	ether_addr_copy(param.bfer_address, bfee->mac_addr);
263 
264 	rtw_bf_init_bfer_entry_mu(rtwdev, &param);
265 
266 	bf_info->cur_csi_rpt_rate = DESC_RATE6M;
267 	rtw_bf_cfg_sounding(rtwdev, vif, DESC_RATE6M);
268 
269 	/* accept action_no_ack */
270 	rtw_write16_set(rtwdev, REG_RXFLTMAP0, BIT_RXFLTMAP0_ACTIONNOACK);
271 
272 	/* accept NDPA and BF report poll */
273 	rtw_write16_set(rtwdev, REG_RXFLTMAP1, BIT_RXFLTMAP1_BF);
274 }
275 EXPORT_SYMBOL(rtw_bf_enable_bfee_mu);
276 
277 void rtw_bf_remove_bfee_su(struct rtw_dev *rtwdev,
278 			   struct rtw_bfee *bfee)
279 {
280 	struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
281 
282 	rtw_dbg(rtwdev, RTW_DBG_BF, "remove as a su bfee\n");
283 	rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
284 			RTW_SND_CTRL_REMOVE);
285 
286 	switch (bfee->su_reg_index) {
287 	case 0:
288 		rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO, 0);
289 		rtw_write16(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 4, 0);
290 		rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20, 0);
291 		break;
292 	case 1:
293 		rtw_write32(rtwdev, REG_ASSOCIATED_BFMER1_INFO, 0);
294 		rtw_write16(rtwdev, REG_ASSOCIATED_BFMER1_INFO + 4, 0);
295 		rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20 + 2, 0);
296 		break;
297 	}
298 
299 	clear_bit(bfee->su_reg_index, bfinfo->bfer_su_reg_maping);
300 	bfee->su_reg_index = 0xFF;
301 }
302 EXPORT_SYMBOL(rtw_bf_remove_bfee_su);
303 
304 void rtw_bf_remove_bfee_mu(struct rtw_dev *rtwdev,
305 			   struct rtw_bfee *bfee)
306 {
307 	struct rtw_bf_info *bfinfo = &rtwdev->bf_info;
308 
309 	rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM,
310 			RTW_SND_CTRL_REMOVE);
311 
312 	rtw_bf_del_bfer_entry_mu(rtwdev);
313 
314 	if (bfinfo->bfer_su_cnt == 0 && bfinfo->bfer_mu_cnt == 0)
315 		rtw_bf_del_sounding(rtwdev);
316 }
317 EXPORT_SYMBOL(rtw_bf_remove_bfee_mu);
318 
319 void rtw_bf_set_gid_table(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
320 			  struct ieee80211_bss_conf *conf)
321 {
322 	struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv;
323 	struct rtw_bfee *bfee = &rtwvif->bfee;
324 	struct cfg_mumimo_para param;
325 
326 	if (bfee->role != RTW_BFEE_MU) {
327 		rtw_dbg(rtwdev, RTW_DBG_BF, "this vif is not mu bfee\n");
328 		return;
329 	}
330 
331 	param.grouping_bitmap = 0;
332 	param.mu_tx_en = 0;
333 	memset(param.sounding_sts, 0, 6);
334 	memcpy(param.given_gid_tab, conf->mu_group.membership, 8);
335 	memcpy(param.given_user_pos, conf->mu_group.position, 16);
336 	rtw_dbg(rtwdev, RTW_DBG_BF, "STA0: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n",
337 		param.given_gid_tab[0], param.given_user_pos[0],
338 		param.given_user_pos[1]);
339 
340 	rtw_dbg(rtwdev, RTW_DBG_BF, "STA1: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n",
341 		param.given_gid_tab[1], param.given_user_pos[2],
342 		param.given_user_pos[3]);
343 
344 	rtw_bf_cfg_mu_bfee(rtwdev, &param);
345 }
346 EXPORT_SYMBOL(rtw_bf_set_gid_table);
347 
348 void rtw_bf_phy_init(struct rtw_dev *rtwdev)
349 {
350 	u8 tmp8;
351 	u32 tmp32;
352 	u8 retry_limit = 0xA;
353 	u8 ndpa_rate = 0x10;
354 	u8 ack_policy = 3;
355 
356 	tmp32 = rtw_read32(rtwdev, REG_MU_TX_CTL);
357 	/* Enable P1 aggr new packet according to P0 transfer time */
358 	tmp32 |= BIT_MU_P1_WAIT_STATE_EN;
359 	/* MU Retry Limit */
360 	tmp32 &= ~BIT_MASK_R_MU_RL;
361 	tmp32 |= (retry_limit << BIT_SHIFT_R_MU_RL) & BIT_MASK_R_MU_RL;
362 	/* Disable Tx MU-MIMO until sounding done */
363 	tmp32 &= ~BIT_EN_MU_MIMO;
364 	/* Clear validity of MU STAs */
365 	tmp32 &= ~BIT_MASK_R_MU_TABLE_VALID;
366 	rtw_write32(rtwdev, REG_MU_TX_CTL, tmp32);
367 
368 	/* MU-MIMO Option as default value */
369 	tmp8 = ack_policy << BIT_SHIFT_WMAC_TXMU_ACKPOLICY;
370 	tmp8 |= BIT_WMAC_TXMU_ACKPOLICY_EN;
371 	rtw_write8(rtwdev, REG_WMAC_MU_BF_OPTION, tmp8);
372 
373 	/* MU-MIMO Control as default value */
374 	rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, 0);
375 	/* Set MU NDPA rate & BW source */
376 	rtw_write32_set(rtwdev, REG_TXBF_CTRL, BIT_USE_NDPA_PARAMETER);
377 	/* Set NDPA Rate */
378 	rtw_write8(rtwdev, REG_NDPA_OPT_CTRL, ndpa_rate);
379 
380 	rtw_write32_mask(rtwdev, REG_BBPSF_CTRL, BIT_MASK_CSI_RATE,
381 			 DESC_RATE6M);
382 }
383 EXPORT_SYMBOL(rtw_bf_phy_init);
384 
385 void rtw_bf_cfg_csi_rate(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate,
386 			 u8 fixrate_en, u8 *new_rate)
387 {
388 	u32 csi_cfg;
389 	u16 cur_rrsr;
390 
391 	csi_cfg = rtw_read32(rtwdev, REG_BBPSF_CTRL) & ~BIT_MASK_CSI_RATE;
392 	cur_rrsr = rtw_read16(rtwdev, REG_RRSR);
393 
394 	if (rssi >= 40) {
395 		if (cur_rate != DESC_RATE54M) {
396 			cur_rrsr |= BIT(DESC_RATE54M);
397 			csi_cfg |= (DESC_RATE54M & BIT_MASK_CSI_RATE_VAL) <<
398 				   BIT_SHIFT_CSI_RATE;
399 			rtw_write16(rtwdev, REG_RRSR, cur_rrsr);
400 			rtw_write32(rtwdev, REG_BBPSF_CTRL, csi_cfg);
401 		}
402 		*new_rate = DESC_RATE54M;
403 	} else {
404 		if (cur_rate != DESC_RATE24M) {
405 			cur_rrsr &= ~BIT(DESC_RATE54M);
406 			csi_cfg |= (DESC_RATE54M & BIT_MASK_CSI_RATE_VAL) <<
407 				   BIT_SHIFT_CSI_RATE;
408 			rtw_write16(rtwdev, REG_RRSR, cur_rrsr);
409 			rtw_write32(rtwdev, REG_BBPSF_CTRL, csi_cfg);
410 		}
411 		*new_rate = DESC_RATE24M;
412 	}
413 }
414 EXPORT_SYMBOL(rtw_bf_cfg_csi_rate);
415