1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation. 3 */ 4 5 #include "main.h" 6 #include "reg.h" 7 #include "bf.h" 8 #include "debug.h" 9 10 void rtw_bf_disassoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 11 struct ieee80211_bss_conf *bss_conf) 12 { 13 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 14 struct rtw_bfee *bfee = &rtwvif->bfee; 15 struct rtw_bf_info *bfinfo = &rtwdev->bf_info; 16 17 if (bfee->role == RTW_BFEE_NONE) 18 return; 19 20 if (bfee->role == RTW_BFEE_MU) 21 bfinfo->bfer_mu_cnt--; 22 else if (bfee->role == RTW_BFEE_SU) 23 bfinfo->bfer_su_cnt--; 24 25 rtw_chip_config_bfee(rtwdev, rtwvif, bfee, false); 26 27 bfee->role = RTW_BFEE_NONE; 28 } 29 30 void rtw_bf_assoc(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 31 struct ieee80211_bss_conf *bss_conf) 32 { 33 const struct rtw_chip_info *chip = rtwdev->chip; 34 struct ieee80211_hw *hw = rtwdev->hw; 35 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 36 struct rtw_bfee *bfee = &rtwvif->bfee; 37 struct rtw_bf_info *bfinfo = &rtwdev->bf_info; 38 struct ieee80211_sta *sta; 39 struct ieee80211_sta_vht_cap *vht_cap; 40 struct ieee80211_sta_vht_cap *ic_vht_cap; 41 const u8 *bssid = bss_conf->bssid; 42 u32 sound_dim; 43 u8 i; 44 45 if (!(chip->band & RTW_BAND_5G)) 46 return; 47 48 rcu_read_lock(); 49 50 sta = ieee80211_find_sta(vif, bssid); 51 if (!sta) { 52 rcu_read_unlock(); 53 54 #if defined(__linux__) 55 rtw_warn(rtwdev, "failed to find station entry for bss %pM\n", 56 bssid); 57 #elif defined(__FreeBSD__) 58 rtw_warn(rtwdev, "failed to find station entry for bss %6D\n", 59 bssid, ":"); 60 #endif 61 return; 62 } 63 64 ic_vht_cap = &hw->wiphy->bands[NL80211_BAND_5GHZ]->vht_cap; 65 vht_cap = &sta->deflink.vht_cap; 66 67 rcu_read_unlock(); 68 69 if ((ic_vht_cap->cap & IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE) && 70 (vht_cap->cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE)) { 71 if (bfinfo->bfer_mu_cnt >= chip->bfer_mu_max_num) { 72 rtw_dbg(rtwdev, RTW_DBG_BF, "mu bfer number over limit\n"); 73 return; 74 } 75 76 ether_addr_copy(bfee->mac_addr, bssid); 77 bfee->role = RTW_BFEE_MU; 78 bfee->p_aid = (bssid[5] << 1) | (bssid[4] >> 7); 79 bfee->aid = vif->cfg.aid; 80 bfinfo->bfer_mu_cnt++; 81 82 rtw_chip_config_bfee(rtwdev, rtwvif, bfee, true); 83 } else if ((ic_vht_cap->cap & IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE) && 84 (vht_cap->cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 85 if (bfinfo->bfer_su_cnt >= chip->bfer_su_max_num) { 86 rtw_dbg(rtwdev, RTW_DBG_BF, "su bfer number over limit\n"); 87 return; 88 } 89 90 sound_dim = vht_cap->cap & 91 IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK; 92 sound_dim >>= IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_SHIFT; 93 94 ether_addr_copy(bfee->mac_addr, bssid); 95 bfee->role = RTW_BFEE_SU; 96 bfee->sound_dim = (u8)sound_dim; 97 bfee->g_id = 0; 98 bfee->p_aid = (bssid[5] << 1) | (bssid[4] >> 7); 99 bfinfo->bfer_su_cnt++; 100 for (i = 0; i < chip->bfer_su_max_num; i++) { 101 if (!test_bit(i, bfinfo->bfer_su_reg_maping)) { 102 set_bit(i, bfinfo->bfer_su_reg_maping); 103 bfee->su_reg_index = i; 104 break; 105 } 106 } 107 108 rtw_chip_config_bfee(rtwdev, rtwvif, bfee, true); 109 } 110 } 111 112 void rtw_bf_init_bfer_entry_mu(struct rtw_dev *rtwdev, 113 struct mu_bfer_init_para *param) 114 { 115 u16 mu_bf_ctl = 0; 116 u8 *addr = param->bfer_address; 117 int i; 118 119 for (i = 0; i < ETH_ALEN; i++) 120 rtw_write8(rtwdev, REG_ASSOCIATED_BFMER0_INFO + i, addr[i]); 121 rtw_write16(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 6, param->paid); 122 rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20, param->csi_para); 123 124 mu_bf_ctl = rtw_read16(rtwdev, REG_WMAC_MU_BF_CTL) & 0xC000; 125 mu_bf_ctl |= param->my_aid | (param->csi_length_sel << 12); 126 rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, mu_bf_ctl); 127 } 128 129 void rtw_bf_cfg_sounding(struct rtw_dev *rtwdev, struct rtw_vif *vif, 130 enum rtw_trx_desc_rate rate) 131 { 132 u32 psf_ctl = 0; 133 u8 csi_rsc = 0x1; 134 135 psf_ctl = rtw_read32(rtwdev, REG_BBPSF_CTRL) | 136 BIT_WMAC_USE_NDPARATE | 137 (csi_rsc << 13); 138 139 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM, 140 RTW_SND_CTRL_SOUNDING); 141 rtw_write8(rtwdev, REG_SND_PTCL_CTRL + 3, 0x26); 142 rtw_write8_clr(rtwdev, REG_RXFLTMAP1, BIT_RXFLTMAP1_BF_REPORT_POLL); 143 rtw_write8_clr(rtwdev, REG_RXFLTMAP4, BIT_RXFLTMAP4_BF_REPORT_POLL); 144 145 if (vif->net_type == RTW_NET_AP_MODE) 146 rtw_write32(rtwdev, REG_BBPSF_CTRL, psf_ctl | BIT(12)); 147 else 148 rtw_write32(rtwdev, REG_BBPSF_CTRL, psf_ctl & ~BIT(12)); 149 } 150 151 void rtw_bf_cfg_mu_bfee(struct rtw_dev *rtwdev, struct cfg_mumimo_para *param) 152 { 153 u8 mu_tbl_sel; 154 u8 mu_valid; 155 156 mu_valid = rtw_read8(rtwdev, REG_MU_TX_CTL) & 157 ~BIT_MASK_R_MU_TABLE_VALID; 158 159 rtw_write8(rtwdev, REG_MU_TX_CTL, 160 (mu_valid | BIT(0) | BIT(1)) & ~(BIT(7))); 161 162 mu_tbl_sel = rtw_read8(rtwdev, REG_MU_TX_CTL + 1) & 0xF8; 163 164 rtw_write8(rtwdev, REG_MU_TX_CTL + 1, mu_tbl_sel); 165 rtw_write32(rtwdev, REG_MU_STA_GID_VLD, param->given_gid_tab[0]); 166 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO, param->given_user_pos[0]); 167 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO + 4, 168 param->given_user_pos[1]); 169 170 rtw_write8(rtwdev, REG_MU_TX_CTL + 1, mu_tbl_sel | 1); 171 rtw_write32(rtwdev, REG_MU_STA_GID_VLD, param->given_gid_tab[1]); 172 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO, param->given_user_pos[2]); 173 rtw_write32(rtwdev, REG_MU_STA_USER_POS_INFO + 4, 174 param->given_user_pos[3]); 175 } 176 177 void rtw_bf_del_bfer_entry_mu(struct rtw_dev *rtwdev) 178 { 179 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO, 0); 180 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 4, 0); 181 rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, 0); 182 rtw_write8(rtwdev, REG_MU_TX_CTL, 0); 183 } 184 185 void rtw_bf_del_sounding(struct rtw_dev *rtwdev) 186 { 187 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM, 0); 188 } 189 190 void rtw_bf_enable_bfee_su(struct rtw_dev *rtwdev, struct rtw_vif *vif, 191 struct rtw_bfee *bfee) 192 { 193 u8 nc_index = hweight8(rtwdev->hal.antenna_rx) - 1; 194 u8 nr_index = bfee->sound_dim; 195 u8 grouping = 0, codebookinfo = 1, coefficientsize = 3; 196 u32 addr_bfer_info, addr_csi_rpt, csi_param; 197 u8 i; 198 199 rtw_dbg(rtwdev, RTW_DBG_BF, "config as an su bfee\n"); 200 201 switch (bfee->su_reg_index) { 202 case 1: 203 addr_bfer_info = REG_ASSOCIATED_BFMER1_INFO; 204 addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20 + 2; 205 break; 206 case 0: 207 default: 208 addr_bfer_info = REG_ASSOCIATED_BFMER0_INFO; 209 addr_csi_rpt = REG_TX_CSI_RPT_PARAM_BW20; 210 break; 211 } 212 213 /* Sounding protocol control */ 214 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM, 215 RTW_SND_CTRL_SOUNDING); 216 217 /* MAC address/Partial AID of Beamformer */ 218 for (i = 0; i < ETH_ALEN; i++) 219 rtw_write8(rtwdev, addr_bfer_info + i, bfee->mac_addr[i]); 220 221 csi_param = (u16)((coefficientsize << 10) | 222 (codebookinfo << 8) | 223 (grouping << 6) | 224 (nr_index << 3) | 225 nc_index); 226 rtw_write16(rtwdev, addr_csi_rpt, csi_param); 227 228 /* ndp rx standby timer */ 229 rtw_write8(rtwdev, REG_SND_PTCL_CTRL + 3, RTW_NDP_RX_STANDBY_TIME); 230 } 231 EXPORT_SYMBOL(rtw_bf_enable_bfee_su); 232 233 /* nc index: 1 2T2R 0 1T1R 234 * nr index: 1 use Nsts 0 use reg setting 235 * codebookinfo: 1 802.11ac 3 802.11n 236 */ 237 void rtw_bf_enable_bfee_mu(struct rtw_dev *rtwdev, struct rtw_vif *vif, 238 struct rtw_bfee *bfee) 239 { 240 struct rtw_bf_info *bf_info = &rtwdev->bf_info; 241 struct mu_bfer_init_para param; 242 u8 nc_index = hweight8(rtwdev->hal.antenna_rx) - 1; 243 u8 nr_index = 1; 244 u8 grouping = 0, codebookinfo = 1, coefficientsize = 0; 245 u32 csi_param; 246 247 rtw_dbg(rtwdev, RTW_DBG_BF, "config as an mu bfee\n"); 248 249 csi_param = (u16)((coefficientsize << 10) | 250 (codebookinfo << 8) | 251 (grouping << 6) | 252 (nr_index << 3) | 253 nc_index); 254 255 rtw_dbg(rtwdev, RTW_DBG_BF, "nc=%d nr=%d group=%d codebookinfo=%d coefficientsize=%d\n", 256 nc_index, nr_index, grouping, codebookinfo, 257 coefficientsize); 258 259 param.paid = bfee->p_aid; 260 param.csi_para = csi_param; 261 param.my_aid = bfee->aid & 0xfff; 262 param.csi_length_sel = HAL_CSI_SEG_4K; 263 ether_addr_copy(param.bfer_address, bfee->mac_addr); 264 265 rtw_bf_init_bfer_entry_mu(rtwdev, ¶m); 266 267 bf_info->cur_csi_rpt_rate = DESC_RATE6M; 268 rtw_bf_cfg_sounding(rtwdev, vif, DESC_RATE6M); 269 270 /* accept action_no_ack */ 271 rtw_write16_set(rtwdev, REG_RXFLTMAP0, BIT_RXFLTMAP0_ACTIONNOACK); 272 273 /* accept NDPA and BF report poll */ 274 rtw_write16_set(rtwdev, REG_RXFLTMAP1, BIT_RXFLTMAP1_BF); 275 } 276 EXPORT_SYMBOL(rtw_bf_enable_bfee_mu); 277 278 void rtw_bf_remove_bfee_su(struct rtw_dev *rtwdev, 279 struct rtw_bfee *bfee) 280 { 281 struct rtw_bf_info *bfinfo = &rtwdev->bf_info; 282 283 rtw_dbg(rtwdev, RTW_DBG_BF, "remove as a su bfee\n"); 284 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM, 285 RTW_SND_CTRL_REMOVE); 286 287 switch (bfee->su_reg_index) { 288 case 0: 289 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER0_INFO, 0); 290 rtw_write16(rtwdev, REG_ASSOCIATED_BFMER0_INFO + 4, 0); 291 rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20, 0); 292 break; 293 case 1: 294 rtw_write32(rtwdev, REG_ASSOCIATED_BFMER1_INFO, 0); 295 rtw_write16(rtwdev, REG_ASSOCIATED_BFMER1_INFO + 4, 0); 296 rtw_write16(rtwdev, REG_TX_CSI_RPT_PARAM_BW20 + 2, 0); 297 break; 298 } 299 300 clear_bit(bfee->su_reg_index, bfinfo->bfer_su_reg_maping); 301 bfee->su_reg_index = 0xFF; 302 } 303 EXPORT_SYMBOL(rtw_bf_remove_bfee_su); 304 305 void rtw_bf_remove_bfee_mu(struct rtw_dev *rtwdev, 306 struct rtw_bfee *bfee) 307 { 308 struct rtw_bf_info *bfinfo = &rtwdev->bf_info; 309 310 rtw_write8_mask(rtwdev, REG_SND_PTCL_CTRL, BIT_MASK_BEAMFORM, 311 RTW_SND_CTRL_REMOVE); 312 313 rtw_bf_del_bfer_entry_mu(rtwdev); 314 315 if (bfinfo->bfer_su_cnt == 0 && bfinfo->bfer_mu_cnt == 0) 316 rtw_bf_del_sounding(rtwdev); 317 } 318 EXPORT_SYMBOL(rtw_bf_remove_bfee_mu); 319 320 void rtw_bf_set_gid_table(struct rtw_dev *rtwdev, struct ieee80211_vif *vif, 321 struct ieee80211_bss_conf *conf) 322 { 323 struct rtw_vif *rtwvif = (struct rtw_vif *)vif->drv_priv; 324 struct rtw_bfee *bfee = &rtwvif->bfee; 325 struct cfg_mumimo_para param; 326 327 if (bfee->role != RTW_BFEE_MU) { 328 rtw_dbg(rtwdev, RTW_DBG_BF, "this vif is not mu bfee\n"); 329 return; 330 } 331 332 param.grouping_bitmap = 0; 333 param.mu_tx_en = 0; 334 memset(param.sounding_sts, 0, 6); 335 memcpy(param.given_gid_tab, conf->mu_group.membership, 8); 336 memcpy(param.given_user_pos, conf->mu_group.position, 16); 337 rtw_dbg(rtwdev, RTW_DBG_BF, "STA0: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n", 338 param.given_gid_tab[0], param.given_user_pos[0], 339 param.given_user_pos[1]); 340 341 rtw_dbg(rtwdev, RTW_DBG_BF, "STA1: gid_valid=0x%x, user_position_l=0x%x, user_position_h=0x%x\n", 342 param.given_gid_tab[1], param.given_user_pos[2], 343 param.given_user_pos[3]); 344 345 rtw_bf_cfg_mu_bfee(rtwdev, ¶m); 346 } 347 EXPORT_SYMBOL(rtw_bf_set_gid_table); 348 349 void rtw_bf_phy_init(struct rtw_dev *rtwdev) 350 { 351 u8 tmp8; 352 u32 tmp32; 353 u8 retry_limit = 0xA; 354 u8 ndpa_rate = 0x10; 355 u8 ack_policy = 3; 356 357 tmp32 = rtw_read32(rtwdev, REG_MU_TX_CTL); 358 /* Enable P1 aggr new packet according to P0 transfer time */ 359 tmp32 |= BIT_MU_P1_WAIT_STATE_EN; 360 /* MU Retry Limit */ 361 tmp32 &= ~BIT_MASK_R_MU_RL; 362 tmp32 |= (retry_limit << BIT_SHIFT_R_MU_RL) & BIT_MASK_R_MU_RL; 363 /* Disable Tx MU-MIMO until sounding done */ 364 tmp32 &= ~BIT_EN_MU_MIMO; 365 /* Clear validity of MU STAs */ 366 tmp32 &= ~BIT_MASK_R_MU_TABLE_VALID; 367 rtw_write32(rtwdev, REG_MU_TX_CTL, tmp32); 368 369 /* MU-MIMO Option as default value */ 370 tmp8 = ack_policy << BIT_SHIFT_WMAC_TXMU_ACKPOLICY; 371 tmp8 |= BIT_WMAC_TXMU_ACKPOLICY_EN; 372 rtw_write8(rtwdev, REG_WMAC_MU_BF_OPTION, tmp8); 373 374 /* MU-MIMO Control as default value */ 375 rtw_write16(rtwdev, REG_WMAC_MU_BF_CTL, 0); 376 /* Set MU NDPA rate & BW source */ 377 rtw_write32_set(rtwdev, REG_TXBF_CTRL, BIT_USE_NDPA_PARAMETER); 378 /* Set NDPA Rate */ 379 rtw_write8(rtwdev, REG_NDPA_OPT_CTRL, ndpa_rate); 380 381 rtw_write32_mask(rtwdev, REG_BBPSF_CTRL, BIT_MASK_CSI_RATE, 382 DESC_RATE6M); 383 } 384 EXPORT_SYMBOL(rtw_bf_phy_init); 385 386 void rtw_bf_cfg_csi_rate(struct rtw_dev *rtwdev, u8 rssi, u8 cur_rate, 387 u8 fixrate_en, u8 *new_rate) 388 { 389 u32 csi_cfg; 390 u16 cur_rrsr; 391 392 csi_cfg = rtw_read32(rtwdev, REG_BBPSF_CTRL) & ~BIT_MASK_CSI_RATE; 393 cur_rrsr = rtw_read16(rtwdev, REG_RRSR); 394 395 if (rssi >= 40) { 396 if (cur_rate != DESC_RATE54M) { 397 cur_rrsr |= BIT(DESC_RATE54M); 398 csi_cfg |= (DESC_RATE54M & BIT_MASK_CSI_RATE_VAL) << 399 BIT_SHIFT_CSI_RATE; 400 rtw_write16(rtwdev, REG_RRSR, cur_rrsr); 401 rtw_write32(rtwdev, REG_BBPSF_CTRL, csi_cfg); 402 } 403 *new_rate = DESC_RATE54M; 404 } else { 405 if (cur_rate != DESC_RATE24M) { 406 cur_rrsr &= ~BIT(DESC_RATE54M); 407 csi_cfg |= (DESC_RATE54M & BIT_MASK_CSI_RATE_VAL) << 408 BIT_SHIFT_CSI_RATE; 409 rtw_write16(rtwdev, REG_RRSR, cur_rrsr); 410 rtw_write32(rtwdev, REG_BBPSF_CTRL, csi_cfg); 411 } 412 *new_rate = DESC_RATE24M; 413 } 414 } 415 EXPORT_SYMBOL(rtw_bf_cfg_csi_rate); 416