1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2020 MediaTek Inc. 3 * 4 * Author: Sean Wang <sean.wang@mediatek.com> 5 */ 6 7 #ifndef __MT76S_H 8 #define __MT76S_H 9 10 #define MT_PSE_PAGE_SZ 128 11 12 #define MCR_WCIR 0x0000 13 #define MCR_WHLPCR 0x0004 14 #define WHLPCR_FW_OWN_REQ_CLR BIT(9) 15 #define WHLPCR_FW_OWN_REQ_SET BIT(8) 16 #define WHLPCR_IS_DRIVER_OWN BIT(8) 17 #define WHLPCR_INT_EN_CLR BIT(1) 18 #define WHLPCR_INT_EN_SET BIT(0) 19 20 #define MCR_WSDIOCSR 0x0008 21 #define MCR_WHCR 0x000C 22 #define W_INT_CLR_CTRL BIT(1) 23 #define RECV_MAILBOX_RD_CLR_EN BIT(2) 24 #define WF_SYS_RSTB BIT(4) /* supported in CONNAC2 */ 25 #define WF_WHOLE_PATH_RSTB BIT(5) /* supported in CONNAC2 */ 26 #define WF_SDIO_WF_PATH_RSTB BIT(6) /* supported in CONNAC2 */ 27 #define MAX_HIF_RX_LEN_NUM GENMASK(13, 8) 28 #define MAX_HIF_RX_LEN_NUM_CONNAC2 GENMASK(14, 8) /* supported in CONNAC2 */ 29 #define WF_RST_DONE BIT(15) /* supported in CONNAC2 */ 30 #define RX_ENHANCE_MODE BIT(16) 31 32 #define MCR_WHISR 0x0010 33 #define MCR_WHIER 0x0014 34 #define WHIER_D2H_SW_INT GENMASK(31, 8) 35 #define WHIER_FW_OWN_BACK_INT_EN BIT(7) 36 #define WHIER_ABNORMAL_INT_EN BIT(6) 37 #define WHIER_WDT_INT_EN BIT(5) /* supported in CONNAC2 */ 38 #define WHIER_RX1_DONE_INT_EN BIT(2) 39 #define WHIER_RX0_DONE_INT_EN BIT(1) 40 #define WHIER_TX_DONE_INT_EN BIT(0) 41 #define WHIER_DEFAULT (WHIER_RX0_DONE_INT_EN | \ 42 WHIER_RX1_DONE_INT_EN | \ 43 WHIER_TX_DONE_INT_EN | \ 44 WHIER_ABNORMAL_INT_EN | \ 45 WHIER_D2H_SW_INT) 46 47 #define MCR_WASR 0x0020 48 #define MCR_WSICR 0x0024 49 #define MCR_WTSR0 0x0028 50 #define TQ0_CNT GENMASK(7, 0) 51 #define TQ1_CNT GENMASK(15, 8) 52 #define TQ2_CNT GENMASK(23, 16) 53 #define TQ3_CNT GENMASK(31, 24) 54 55 #define MCR_WTSR1 0x002c 56 #define TQ4_CNT GENMASK(7, 0) 57 #define TQ5_CNT GENMASK(15, 8) 58 #define TQ6_CNT GENMASK(23, 16) 59 #define TQ7_CNT GENMASK(31, 24) 60 61 #define MCR_WTDR1 0x0034 62 #define MCR_WRDR0 0x0050 63 #define MCR_WRDR1 0x0054 64 #define MCR_WRDR(p) (0x0050 + 4 * (p)) 65 #define MCR_H2DSM0R 0x0070 66 #define H2D_SW_INT_READ BIT(16) 67 #define H2D_SW_INT_WRITE BIT(17) 68 #define H2D_SW_INT_CLEAR_MAILBOX_ACK BIT(22) 69 70 #define MCR_H2DSM1R 0x0074 71 #define MCR_D2HRM0R 0x0078 72 #define MCR_D2HRM1R 0x007c 73 #define MCR_D2HRM2R 0x0080 74 #define MCR_WRPLR 0x0090 75 #define RX0_PACKET_LENGTH GENMASK(15, 0) 76 #define RX1_PACKET_LENGTH GENMASK(31, 16) 77 78 #define MCR_WTMDR 0x00b0 79 #define MCR_WTMCR 0x00b4 80 #define MCR_WTMDPCR0 0x00b8 81 #define MCR_WTMDPCR1 0x00bc 82 #define MCR_WPLRCR 0x00d4 83 #define MCR_WSR 0x00D8 84 #define MCR_CLKIOCR 0x0100 85 #define MCR_CMDIOCR 0x0104 86 #define MCR_DAT0IOCR 0x0108 87 #define MCR_DAT1IOCR 0x010C 88 #define MCR_DAT2IOCR 0x0110 89 #define MCR_DAT3IOCR 0x0114 90 #define MCR_CLKDLYCR 0x0118 91 #define MCR_CMDDLYCR 0x011C 92 #define MCR_ODATDLYCR 0x0120 93 #define MCR_IDATDLYCR1 0x0124 94 #define MCR_IDATDLYCR2 0x0128 95 #define MCR_ILCHCR 0x012C 96 #define MCR_WTQCR0 0x0130 97 #define MCR_WTQCR1 0x0134 98 #define MCR_WTQCR2 0x0138 99 #define MCR_WTQCR3 0x013C 100 #define MCR_WTQCR4 0x0140 101 #define MCR_WTQCR5 0x0144 102 #define MCR_WTQCR6 0x0148 103 #define MCR_WTQCR7 0x014C 104 #define MCR_WTQCR(x) (0x130 + 4 * (x)) 105 #define TXQ_CNT_L GENMASK(15, 0) 106 #define TXQ_CNT_H GENMASK(31, 16) 107 108 #define MCR_SWPCDBGR 0x0154 109 110 #define MCR_H2DSM2R 0x0160 /* supported in CONNAC2 */ 111 #define MCR_H2DSM3R 0x0164 /* supported in CONNAC2 */ 112 #define MCR_D2HRM3R 0x0174 /* supported in CONNAC2 */ 113 #define D2HRM3R_IS_DRIVER_OWN BIT(0) 114 #define MCR_WTQCR8 0x0190 /* supported in CONNAC2 */ 115 #define MCR_WTQCR9 0x0194 /* supported in CONNAC2 */ 116 #define MCR_WTQCR10 0x0198 /* supported in CONNAC2 */ 117 #define MCR_WTQCR11 0x019C /* supported in CONNAC2 */ 118 #define MCR_WTQCR12 0x01A0 /* supported in CONNAC2 */ 119 #define MCR_WTQCR13 0x01A4 /* supported in CONNAC2 */ 120 #define MCR_WTQCR14 0x01A8 /* supported in CONNAC2 */ 121 #define MCR_WTQCR15 0x01AC /* supported in CONNAC2 */ 122 123 enum mt76_connac_sdio_ver { 124 MT76_CONNAC_SDIO, 125 MT76_CONNAC2_SDIO, 126 }; 127 128 struct mt76s_intr { 129 u32 isr; 130 u32 *rec_mb; 131 struct { 132 u32 *wtqcr; 133 } tx; 134 struct { 135 u16 *len[2]; 136 u16 *num; 137 } rx; 138 }; 139 140 #endif 141