1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #ifndef __MT7996_H 7 #define __MT7996_H 8 9 #include <linux/interrupt.h> 10 #include <linux/ktime.h> 11 #if defined(__FreeBSD__) 12 #include <linux/uuid.h> 13 #endif 14 #include "../mt76_connac.h" 15 #include "regs.h" 16 17 #define MT7996_MAX_RADIOS 3 18 #define MT7996_MAX_INTERFACES 19 /* per-band */ 19 #define MT7996_MAX_WMM_SETS 4 20 #define MT7996_WTBL_BMC_SIZE (is_mt7992(&dev->mt76) ? 32 : 64) 21 #define MT7996_WTBL_RESERVED (mt7996_wtbl_size(dev) - 1) 22 #define MT7996_WTBL_STA (MT7996_WTBL_RESERVED - \ 23 mt7996_max_interface_num(dev)) 24 25 #define MT7996_WATCHDOG_TIME (HZ / 10) 26 #define MT7996_RESET_TIMEOUT (30 * HZ) 27 28 #define MT7996_TX_RING_SIZE 2048 29 #define MT7996_TX_MCU_RING_SIZE 256 30 #define MT7996_TX_FWDL_RING_SIZE 128 31 32 #define MT7996_RX_RING_SIZE 1536 33 #define MT7996_RX_MCU_RING_SIZE 512 34 #define MT7996_RX_MCU_RING_SIZE_WA 1024 35 36 #define MT7996_FIRMWARE_WA "mediatek/mt7996/mt7996_wa.bin" 37 #define MT7996_FIRMWARE_WM "mediatek/mt7996/mt7996_wm.bin" 38 #define MT7996_FIRMWARE_DSP "mediatek/mt7996/mt7996_dsp.bin" 39 #define MT7996_ROM_PATCH "mediatek/mt7996/mt7996_rom_patch.bin" 40 41 #define MT7996_FIRMWARE_WA_233 "mediatek/mt7996/mt7996_wa_233.bin" 42 #define MT7996_FIRMWARE_WM_233 "mediatek/mt7996/mt7996_wm_233.bin" 43 #define MT7996_FIRMWARE_DSP_233 MT7996_FIRMWARE_DSP 44 #define MT7996_ROM_PATCH_233 "mediatek/mt7996/mt7996_rom_patch_233.bin" 45 46 #define MT7992_FIRMWARE_WA "mediatek/mt7996/mt7992_wa.bin" 47 #define MT7992_FIRMWARE_WM "mediatek/mt7996/mt7992_wm.bin" 48 #define MT7992_FIRMWARE_DSP "mediatek/mt7996/mt7992_dsp.bin" 49 #define MT7992_ROM_PATCH "mediatek/mt7996/mt7992_rom_patch.bin" 50 51 #define MT7992_FIRMWARE_WA_23 "mediatek/mt7996/mt7992_wa_23.bin" 52 #define MT7992_FIRMWARE_WM_23 "mediatek/mt7996/mt7992_wm_23.bin" 53 #define MT7992_FIRMWARE_DSP_23 "mediatek/mt7996/mt7992_dsp_23.bin" 54 #define MT7992_ROM_PATCH_23 "mediatek/mt7996/mt7992_rom_patch_23.bin" 55 56 #define MT7996_EEPROM_DEFAULT "mediatek/mt7996/mt7996_eeprom.bin" 57 #define MT7996_EEPROM_DEFAULT_INT "mediatek/mt7996/mt7996_eeprom_2i5i6i.bin" 58 #define MT7996_EEPROM_DEFAULT_233 "mediatek/mt7996/mt7996_eeprom_233.bin" 59 #define MT7996_EEPROM_DEFAULT_233_INT "mediatek/mt7996/mt7996_eeprom_233_2i5i6i.bin" 60 61 #define MT7992_EEPROM_DEFAULT "mediatek/mt7996/mt7992_eeprom.bin" 62 #define MT7992_EEPROM_DEFAULT_INT "mediatek/mt7996/mt7992_eeprom_2i5i.bin" 63 #define MT7992_EEPROM_DEFAULT_MIX "mediatek/mt7996/mt7992_eeprom_2i5e.bin" 64 #define MT7992_EEPROM_DEFAULT_23 "mediatek/mt7996/mt7992_eeprom_23.bin" 65 #define MT7992_EEPROM_DEFAULT_23_INT "mediatek/mt7996/mt7992_eeprom_23_2i5i.bin" 66 67 #define MT7996_EEPROM_SIZE 7680 68 #define MT7996_EEPROM_BLOCK_SIZE 16 69 #define MT7996_TOKEN_SIZE 16384 70 #define MT7996_HW_TOKEN_SIZE 8192 71 72 #define MT7996_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */ 73 #define MT7996_CFEND_RATE_11B 0x03 /* 11B LP, 11M */ 74 #define MT7996_IBF_MAX_NC 2 75 #define MT7996_IBF_TIMEOUT 0x18 76 #define MT7996_IBF_TIMEOUT_LEGACY 0x48 77 78 #define MT7992_CFEND_RATE_DEFAULT 0x4b /* OFDM 6M */ 79 #define MT7992_IBF_TIMEOUT 0xff 80 81 #define MT7996_SKU_RATE_NUM 417 82 #define MT7996_SKU_PATH_NUM 494 83 84 #define MT7996_MAX_TWT_AGRT 16 85 #define MT7996_MAX_STA_TWT_AGRT 8 86 #define MT7996_MIN_TWT_DUR 64 87 #define MT7996_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 3) 88 89 /* NOTE: used to map mt76_rates. idx may change if firmware expands table */ 90 #define MT7996_BASIC_RATES_TBL 31 91 #define MT7996_BEACON_RATES_TBL 25 92 93 #define MT7996_THERMAL_THROTTLE_MAX 100 94 #define MT7996_CDEV_THROTTLE_MAX 99 95 #define MT7996_CRIT_TEMP_IDX 0 96 #define MT7996_MAX_TEMP_IDX 1 97 #define MT7996_CRIT_TEMP 110 98 #define MT7996_MAX_TEMP 120 99 100 #define MT7996_RRO_MAX_SESSION 1024 101 #define MT7996_RRO_WINDOW_MAX_LEN 1024 102 #define MT7996_RRO_ADDR_ELEM_LEN 128 103 #define MT7996_RRO_BA_BITMAP_LEN 2 104 #define MT7996_RRO_BA_BITMAP_CR_SIZE ((MT7996_RRO_MAX_SESSION * 128) / \ 105 MT7996_RRO_BA_BITMAP_LEN) 106 #define MT7996_RRO_BA_BITMAP_SESSION_SIZE (MT7996_RRO_MAX_SESSION / \ 107 MT7996_RRO_ADDR_ELEM_LEN) 108 #define MT7996_RRO_WINDOW_MAX_SIZE (MT7996_RRO_WINDOW_MAX_LEN * \ 109 MT7996_RRO_BA_BITMAP_SESSION_SIZE) 110 111 #define MT7996_RX_BUF_SIZE (1800 + \ 112 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 113 #define MT7996_RX_MSDU_PAGE_SIZE (128 + \ 114 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 115 116 struct mt7996_vif; 117 struct mt7996_sta; 118 struct mt7996_dfs_pulse; 119 struct mt7996_dfs_pattern; 120 121 enum mt7996_ram_type { 122 MT7996_RAM_TYPE_WM, 123 MT7996_RAM_TYPE_WA, 124 MT7996_RAM_TYPE_DSP, 125 }; 126 127 enum mt7996_var_type { 128 MT7996_VAR_TYPE_444, 129 MT7996_VAR_TYPE_233, 130 }; 131 132 enum mt7992_var_type { 133 MT7992_VAR_TYPE_44, 134 MT7992_VAR_TYPE_23, 135 }; 136 137 enum mt7996_fem_type { 138 MT7996_FEM_EXT, 139 MT7996_FEM_INT, 140 MT7996_FEM_MIX, 141 }; 142 143 enum mt7996_txq_id { 144 MT7996_TXQ_FWDL = 16, 145 MT7996_TXQ_MCU_WM, 146 MT7996_TXQ_BAND0, 147 MT7996_TXQ_BAND1, 148 MT7996_TXQ_MCU_WA, 149 MT7996_TXQ_BAND2, 150 }; 151 152 enum mt7996_rxq_id { 153 MT7996_RXQ_MCU_WM = 0, 154 MT7996_RXQ_MCU_WA, 155 MT7996_RXQ_MCU_WA_MAIN = 2, 156 MT7996_RXQ_MCU_WA_EXT = 3, /* for mt7992 */ 157 MT7996_RXQ_MCU_WA_TRI = 3, 158 MT7996_RXQ_BAND0 = 4, 159 MT7996_RXQ_BAND1 = 5, /* for mt7992 */ 160 MT7996_RXQ_BAND2 = 5, 161 MT7996_RXQ_RRO_BAND0 = 8, 162 MT7996_RXQ_RRO_BAND1 = 8,/* unused */ 163 MT7996_RXQ_RRO_BAND2 = 6, 164 MT7996_RXQ_MSDU_PG_BAND0 = 10, 165 MT7996_RXQ_MSDU_PG_BAND1 = 11, 166 MT7996_RXQ_MSDU_PG_BAND2 = 12, 167 MT7996_RXQ_TXFREE0 = 9, 168 MT7996_RXQ_TXFREE1 = 9, 169 MT7996_RXQ_TXFREE2 = 7, 170 MT7996_RXQ_RRO_IND = 0, 171 }; 172 173 struct mt7996_twt_flow { 174 struct list_head list; 175 u64 start_tsf; 176 u64 tsf; 177 u32 duration; 178 u16 wcid; 179 __le16 mantissa; 180 u8 exp; 181 u8 table_id; 182 u8 id; 183 u8 protection:1; 184 u8 flowtype:1; 185 u8 trigger:1; 186 u8 sched:1; 187 }; 188 189 DECLARE_EWMA(avg_signal, 10, 8) 190 191 struct mt7996_sta { 192 struct mt76_wcid wcid; /* must be first */ 193 194 struct mt7996_vif *vif; 195 196 struct list_head rc_list; 197 u32 airtime_ac[8]; 198 199 int ack_signal; 200 struct ewma_avg_signal avg_ack_signal; 201 202 unsigned long changed; 203 204 struct mt76_connac_sta_key_conf bip; 205 206 struct { 207 u8 flowid_mask; 208 struct mt7996_twt_flow flow[MT7996_MAX_STA_TWT_AGRT]; 209 } twt; 210 }; 211 212 struct mt7996_vif_link { 213 struct mt76_vif_link mt76; /* must be first */ 214 215 struct mt7996_sta sta; 216 struct mt7996_phy *phy; 217 218 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS]; 219 struct cfg80211_bitrate_mask bitrate_mask; 220 }; 221 222 struct mt7996_vif { 223 struct mt7996_vif_link deflink; /* must be first */ 224 struct mt76_vif_data mt76; 225 }; 226 227 /* crash-dump */ 228 struct mt7996_crash_data { 229 guid_t guid; 230 struct timespec64 timestamp; 231 232 u8 *memdump_buf; 233 size_t memdump_buf_len; 234 }; 235 236 struct mt7996_hif { 237 struct list_head list; 238 239 struct device *dev; 240 void __iomem *regs; 241 int irq; 242 }; 243 244 struct mt7996_wed_rro_addr { 245 u32 head_low; 246 u32 head_high : 4; 247 u32 count: 11; 248 u32 oor: 1; 249 u32 rsv : 8; 250 u32 signature : 8; 251 }; 252 253 struct mt7996_wed_rro_session_id { 254 struct list_head list; 255 u16 id; 256 }; 257 258 struct mt7996_phy { 259 struct mt76_phy *mt76; 260 struct mt7996_dev *dev; 261 262 struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 263 264 struct thermal_cooling_device *cdev; 265 u8 cdev_state; 266 u8 throttle_state; 267 u32 throttle_temp[2]; /* 0: critical high, 1: maximum */ 268 269 u32 rxfilter; 270 u64 omac_mask; 271 272 u16 noise; 273 274 s16 coverage_class; 275 u8 slottime; 276 277 u8 rdd_state; 278 279 u16 beacon_rate; 280 281 u32 rx_ampdu_ts; 282 u32 ampdu_ref; 283 int txpower; 284 285 struct mt76_mib_stats mib; 286 struct mt76_channel_state state_ts; 287 288 u16 orig_chainmask; 289 290 bool has_aux_rx; 291 bool counter_reset; 292 }; 293 294 struct mt7996_dev { 295 union { /* must be first */ 296 struct mt76_dev mt76; 297 struct mt76_phy mphy; 298 }; 299 300 struct mt7996_phy *radio_phy[MT7996_MAX_RADIOS]; 301 struct wiphy_radio radios[MT7996_MAX_RADIOS]; 302 struct wiphy_radio_freq_range radio_freqs[MT7996_MAX_RADIOS]; 303 304 struct mt7996_hif *hif2; 305 struct mt7996_reg_desc reg; 306 u8 q_id[MT7996_MAX_QUEUE]; 307 u32 q_int_mask[MT7996_MAX_QUEUE]; 308 u32 q_wfdma_mask; 309 310 const struct mt76_bus_ops *bus_ops; 311 struct mt7996_phy phy; 312 313 /* monitor rx chain configured channel */ 314 struct cfg80211_chan_def rdd2_chandef; 315 struct mt7996_phy *rdd2_phy; 316 317 u16 chainmask; 318 u8 chainshift[__MT_MAX_BAND]; 319 u32 hif_idx; 320 321 struct work_struct init_work; 322 struct work_struct rc_work; 323 struct work_struct dump_work; 324 struct work_struct reset_work; 325 wait_queue_head_t reset_wait; 326 struct { 327 u32 state; 328 u32 wa_reset_count; 329 u32 wm_reset_count; 330 bool hw_full_reset:1; 331 bool hw_init_done:1; 332 bool restart:1; 333 } recovery; 334 335 /* protects coredump data */ 336 struct mutex dump_mutex; 337 #ifdef CONFIG_DEV_COREDUMP 338 struct { 339 struct mt7996_crash_data *crash_data; 340 } coredump; 341 #endif 342 343 struct list_head sta_rc_list; 344 struct list_head twt_list; 345 346 u32 hw_pattern; 347 348 bool flash_mode:1; 349 bool has_eht:1; 350 bool has_rro:1; 351 352 struct { 353 struct { 354 void *ptr; 355 dma_addr_t phy_addr; 356 } ba_bitmap[MT7996_RRO_BA_BITMAP_LEN]; 357 struct { 358 void *ptr; 359 dma_addr_t phy_addr; 360 } addr_elem[MT7996_RRO_ADDR_ELEM_LEN]; 361 struct { 362 void *ptr; 363 dma_addr_t phy_addr; 364 } session; 365 366 struct work_struct work; 367 struct list_head poll_list; 368 spinlock_t lock; 369 } wed_rro; 370 371 bool ibf; 372 u8 fw_debug_wm; 373 u8 fw_debug_wa; 374 u8 fw_debug_bin; 375 u16 fw_debug_seq; 376 377 struct dentry *debugfs_dir; 378 struct rchan *relay_fwlog; 379 380 struct { 381 u16 table_mask; 382 u8 n_agrt; 383 } twt; 384 385 spinlock_t reg_lock; 386 387 u8 wtbl_size_group; 388 struct { 389 u8 type:4; 390 u8 fem:4; 391 } var; 392 }; 393 394 enum { 395 WFDMA0 = 0x0, 396 WFDMA1, 397 WFDMA_EXT, 398 __MT_WFDMA_MAX, 399 }; 400 401 enum { 402 MT_RX_SEL0, 403 MT_RX_SEL1, 404 MT_RX_SEL2, /* monitor chain */ 405 }; 406 407 enum mt7996_rdd_cmd { 408 RDD_STOP, 409 RDD_START, 410 RDD_DET_MODE, 411 RDD_RADAR_EMULATE, 412 RDD_START_TXQ = 20, 413 RDD_CAC_START = 50, 414 RDD_CAC_END, 415 RDD_NORMAL_START, 416 RDD_DISABLE_DFS_CAL, 417 RDD_PULSE_DBG, 418 RDD_READ_PULSE, 419 RDD_RESUME_BF, 420 RDD_IRQ_OFF, 421 }; 422 423 static inline struct mt7996_dev * 424 mt7996_hw_dev(struct ieee80211_hw *hw) 425 { 426 struct mt76_phy *phy = hw->priv; 427 428 return container_of(phy->dev, struct mt7996_dev, mt76); 429 } 430 431 static inline struct mt7996_phy * 432 __mt7996_phy(struct mt7996_dev *dev, enum mt76_band_id band) 433 { 434 struct mt76_phy *phy = dev->mt76.phys[band]; 435 436 if (!phy) 437 return NULL; 438 439 return phy->priv; 440 } 441 442 static inline struct mt7996_phy * 443 mt7996_phy2(struct mt7996_dev *dev) 444 { 445 return __mt7996_phy(dev, MT_BAND1); 446 } 447 448 static inline struct mt7996_phy * 449 mt7996_phy3(struct mt7996_dev *dev) 450 { 451 return __mt7996_phy(dev, MT_BAND2); 452 } 453 454 static inline bool 455 mt7996_band_valid(struct mt7996_dev *dev, u8 band) 456 { 457 if (is_mt7992(&dev->mt76)) 458 return band <= MT_BAND1; 459 460 return band <= MT_BAND2; 461 } 462 463 static inline bool 464 mt7996_has_background_radar(struct mt7996_dev *dev) 465 { 466 switch (mt76_chip(&dev->mt76)) { 467 case 0x7990: 468 if (dev->var.type == MT7996_VAR_TYPE_233) 469 return false; 470 break; 471 case 0x7992: 472 if (dev->var.type == MT7992_VAR_TYPE_23) 473 return false; 474 break; 475 default: 476 return false; 477 } 478 479 return true; 480 } 481 482 static inline struct mt7996_phy * 483 mt7996_band_phy(struct mt7996_dev *dev, enum nl80211_band band) 484 { 485 struct mt76_phy *mphy; 486 487 mphy = dev->mt76.band_phys[band]; 488 if (!mphy) 489 return NULL; 490 491 return mphy->priv; 492 } 493 494 static inline struct mt7996_vif_link * 495 mt7996_vif_link(struct mt7996_dev *dev, struct ieee80211_vif *vif, int link_id) 496 { 497 return (struct mt7996_vif_link *)mt76_vif_link(&dev->mt76, vif, link_id); 498 } 499 500 static inline struct mt7996_phy * 501 mt7996_vif_link_phy(struct mt7996_vif_link *link) 502 { 503 struct mt76_phy *mphy = mt76_vif_link_phy(&link->mt76); 504 505 if (!mphy) 506 return NULL; 507 508 return mphy->priv; 509 } 510 511 static inline struct mt7996_vif_link * 512 mt7996_vif_conf_link(struct mt7996_dev *dev, struct ieee80211_vif *vif, 513 struct ieee80211_bss_conf *link_conf) 514 { 515 return (struct mt7996_vif_link *)mt76_vif_conf_link(&dev->mt76, vif, 516 link_conf); 517 } 518 519 #define mt7996_for_each_phy(dev, phy) \ 520 for (int __i = 0; __i < ARRAY_SIZE((dev)->radio_phy); __i++) \ 521 if (((phy) = (dev)->radio_phy[__i]) != NULL) 522 523 extern const struct ieee80211_ops mt7996_ops; 524 extern struct pci_driver mt7996_pci_driver; 525 extern struct pci_driver mt7996_hif_driver; 526 527 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev, 528 void __iomem *mem_base, u32 device_id); 529 void mt7996_wfsys_reset(struct mt7996_dev *dev); 530 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance); 531 u64 __mt7996_get_tsf(struct ieee80211_hw *hw, struct mt7996_vif *mvif); 532 int mt7996_register_device(struct mt7996_dev *dev); 533 void mt7996_unregister_device(struct mt7996_dev *dev); 534 int mt7996_vif_link_add(struct mt76_phy *mphy, struct ieee80211_vif *vif, 535 struct ieee80211_bss_conf *link_conf, 536 struct mt76_vif_link *mlink); 537 void mt7996_vif_link_remove(struct mt76_phy *mphy, struct ieee80211_vif *vif, 538 struct ieee80211_bss_conf *link_conf, 539 struct mt76_vif_link *mlink); 540 int mt7996_eeprom_init(struct mt7996_dev *dev); 541 int mt7996_eeprom_parse_hw_cap(struct mt7996_dev *dev, struct mt7996_phy *phy); 542 int mt7996_eeprom_get_target_power(struct mt7996_dev *dev, 543 struct ieee80211_channel *chan); 544 s8 mt7996_eeprom_get_power_delta(struct mt7996_dev *dev, int band); 545 int mt7996_dma_init(struct mt7996_dev *dev); 546 void mt7996_dma_reset(struct mt7996_dev *dev, bool force); 547 void mt7996_dma_prefetch(struct mt7996_dev *dev); 548 void mt7996_dma_cleanup(struct mt7996_dev *dev); 549 void mt7996_dma_start(struct mt7996_dev *dev, bool reset, bool wed_reset); 550 int mt7996_init_tx_queues(struct mt7996_phy *phy, int idx, 551 int n_desc, int ring_base, struct mtk_wed_device *wed); 552 void mt7996_init_txpower(struct mt7996_phy *phy); 553 int mt7996_txbf_init(struct mt7996_dev *dev); 554 void mt7996_reset(struct mt7996_dev *dev); 555 int mt7996_run(struct mt7996_phy *phy); 556 int mt7996_mcu_init(struct mt7996_dev *dev); 557 int mt7996_mcu_init_firmware(struct mt7996_dev *dev); 558 int mt7996_mcu_twt_agrt_update(struct mt7996_dev *dev, 559 struct mt7996_vif *mvif, 560 struct mt7996_twt_flow *flow, 561 int cmd); 562 int mt7996_mcu_add_dev_info(struct mt7996_phy *phy, struct ieee80211_vif *vif, 563 struct ieee80211_bss_conf *link_conf, 564 struct mt76_vif_link *mlink, bool enable); 565 int mt7996_mcu_add_bss_info(struct mt7996_phy *phy, struct ieee80211_vif *vif, 566 struct ieee80211_bss_conf *link_conf, 567 struct mt76_vif_link *mlink, int enable); 568 int mt7996_mcu_add_sta(struct mt7996_dev *dev, struct ieee80211_vif *vif, 569 struct mt76_vif_link *mlink, 570 struct ieee80211_sta *sta, int conn_state, bool newly); 571 int mt7996_mcu_add_tx_ba(struct mt7996_dev *dev, 572 struct ieee80211_ampdu_params *params, 573 bool add); 574 int mt7996_mcu_add_rx_ba(struct mt7996_dev *dev, 575 struct ieee80211_ampdu_params *params, 576 bool add); 577 int mt7996_mcu_update_bss_color(struct mt7996_dev *dev, 578 struct mt76_vif_link *mlink, 579 struct cfg80211_he_bss_color *he_bss_color); 580 int mt7996_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 581 struct ieee80211_bss_conf *link_conf); 582 int mt7996_mcu_beacon_inband_discov(struct mt7996_dev *dev, 583 struct ieee80211_vif *vif, u32 changed); 584 int mt7996_mcu_add_obss_spr(struct mt7996_phy *phy, struct ieee80211_vif *vif, 585 struct ieee80211_he_obss_pd *he_obss_pd); 586 int mt7996_mcu_add_rate_ctrl(struct mt7996_dev *dev, struct ieee80211_vif *vif, 587 struct ieee80211_sta *sta, bool changed); 588 int mt7996_set_channel(struct mt76_phy *mphy); 589 int mt7996_mcu_set_chan_info(struct mt7996_phy *phy, u16 tag); 590 int mt7996_mcu_set_tx(struct mt7996_dev *dev, struct ieee80211_vif *vif, 591 struct ieee80211_bss_conf *link_conf); 592 int mt7996_mcu_set_fixed_rate_ctrl(struct mt7996_dev *dev, 593 void *data, u16 version); 594 int mt7996_mcu_set_fixed_field(struct mt7996_dev *dev, struct ieee80211_vif *vif, 595 struct ieee80211_sta *sta, void *data, u32 field); 596 int mt7996_mcu_set_eeprom(struct mt7996_dev *dev); 597 int mt7996_mcu_get_eeprom(struct mt7996_dev *dev, u32 offset, u8 *buf, u32 buf_len); 598 int mt7996_mcu_get_eeprom_free_block(struct mt7996_dev *dev, u8 *block_num); 599 int mt7996_mcu_get_chip_config(struct mt7996_dev *dev, u32 *cap); 600 int mt7996_mcu_set_ser(struct mt7996_dev *dev, u8 action, u8 set, u8 band); 601 int mt7996_mcu_set_txbf(struct mt7996_dev *dev, u8 action); 602 int mt7996_mcu_set_fcc5_lpn(struct mt7996_dev *dev, int val); 603 int mt7996_mcu_set_pulse_th(struct mt7996_dev *dev, 604 const struct mt7996_dfs_pulse *pulse); 605 int mt7996_mcu_set_radar_th(struct mt7996_dev *dev, int index, 606 const struct mt7996_dfs_pattern *pattern); 607 int mt7996_mcu_set_radio_en(struct mt7996_phy *phy, bool enable); 608 int mt7996_mcu_set_rts_thresh(struct mt7996_phy *phy, u32 val); 609 int mt7996_mcu_set_timing(struct mt7996_phy *phy, struct ieee80211_vif *vif, 610 struct ieee80211_bss_conf *link_conf); 611 int mt7996_mcu_get_chan_mib_info(struct mt7996_phy *phy, bool chan_switch); 612 int mt7996_mcu_get_temperature(struct mt7996_phy *phy); 613 int mt7996_mcu_set_thermal_throttling(struct mt7996_phy *phy, u8 state); 614 int mt7996_mcu_set_thermal_protect(struct mt7996_phy *phy, bool enable); 615 int mt7996_mcu_set_txpower_sku(struct mt7996_phy *phy); 616 int mt7996_mcu_rdd_cmd(struct mt7996_dev *dev, int cmd, u8 index, 617 u8 rx_sel, u8 val); 618 int mt7996_mcu_rdd_background_enable(struct mt7996_phy *phy, 619 struct cfg80211_chan_def *chandef); 620 int mt7996_mcu_set_fixed_rate_table(struct mt7996_phy *phy, u8 table_idx, 621 u16 rate_idx, bool beacon); 622 int mt7996_mcu_rf_regval(struct mt7996_dev *dev, u32 regidx, u32 *val, bool set); 623 int mt7996_mcu_set_hdr_trans(struct mt7996_dev *dev, bool hdr_trans); 624 int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u16 val); 625 int mt7996_mcu_wa_cmd(struct mt7996_dev *dev, int cmd, u32 a1, u32 a2, u32 a3); 626 int mt7996_mcu_fw_log_2_host(struct mt7996_dev *dev, u8 type, u8 ctrl); 627 int mt7996_mcu_fw_dbg_ctrl(struct mt7996_dev *dev, u32 module, u8 level); 628 int mt7996_mcu_trigger_assert(struct mt7996_dev *dev); 629 void mt7996_mcu_rx_event(struct mt7996_dev *dev, struct sk_buff *skb); 630 void mt7996_mcu_exit(struct mt7996_dev *dev); 631 int mt7996_mcu_get_all_sta_info(struct mt7996_phy *phy, u16 tag); 632 int mt7996_mcu_wed_rro_reset_sessions(struct mt7996_dev *dev, u16 id); 633 int mt7996_mcu_set_sniffer_mode(struct mt7996_phy *phy, bool enabled); 634 635 static inline u8 mt7996_max_interface_num(struct mt7996_dev *dev) 636 { 637 return min(MT7996_MAX_INTERFACES * (1 + mt7996_band_valid(dev, MT_BAND1) + 638 mt7996_band_valid(dev, MT_BAND2)), 639 MT7996_WTBL_BMC_SIZE); 640 } 641 642 static inline u16 mt7996_wtbl_size(struct mt7996_dev *dev) 643 { 644 return (dev->wtbl_size_group << 8) + MT7996_WTBL_BMC_SIZE; 645 } 646 647 void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg, 648 u32 clear, u32 set); 649 650 static inline void mt7996_irq_enable(struct mt7996_dev *dev, u32 mask) 651 { 652 if (dev->hif2) 653 mt7996_dual_hif_set_irq_mask(dev, false, 0, mask); 654 else 655 mt76_set_irq_mask(&dev->mt76, 0, 0, mask); 656 657 tasklet_schedule(&dev->mt76.irq_tasklet); 658 } 659 660 static inline void mt7996_irq_disable(struct mt7996_dev *dev, u32 mask) 661 { 662 if (dev->hif2) 663 mt7996_dual_hif_set_irq_mask(dev, true, mask, 0); 664 else 665 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0); 666 } 667 668 void mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset, 669 size_t len); 670 671 static inline u16 mt7996_rx_chainmask(struct mt7996_phy *phy) 672 { 673 int max_nss = hweight8(phy->mt76->hw->wiphy->available_antennas_tx); 674 int cur_nss = hweight8(phy->mt76->antenna_mask); 675 u16 tx_chainmask = phy->mt76->chainmask; 676 677 if (cur_nss != max_nss) 678 return tx_chainmask; 679 680 return tx_chainmask | (BIT(fls(tx_chainmask)) * phy->has_aux_rx); 681 } 682 683 void mt7996_mac_init(struct mt7996_dev *dev); 684 u32 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev *dev, u16 wcid, u8 dw); 685 bool mt7996_mac_wtbl_update(struct mt7996_dev *dev, int idx, u32 mask); 686 void mt7996_mac_reset_counters(struct mt7996_phy *phy); 687 void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy); 688 void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band); 689 void mt7996_mac_enable_rtscts(struct mt7996_dev *dev, 690 struct ieee80211_vif *vif, bool enable); 691 void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi, 692 struct sk_buff *skb, struct mt76_wcid *wcid, 693 struct ieee80211_key_conf *key, int pid, 694 enum mt76_txq_id qid, u32 changed); 695 void mt7996_mac_set_coverage_class(struct mt7996_phy *phy); 696 int mt7996_mac_sta_add(struct mt76_dev *mdev, struct ieee80211_vif *vif, 697 struct ieee80211_sta *sta); 698 int mt7996_mac_sta_event(struct mt76_dev *mdev, struct ieee80211_vif *vif, 699 struct ieee80211_sta *sta, enum mt76_sta_event ev); 700 void mt7996_mac_sta_remove(struct mt76_dev *mdev, struct ieee80211_vif *vif, 701 struct ieee80211_sta *sta); 702 void mt7996_mac_work(struct work_struct *work); 703 void mt7996_mac_reset_work(struct work_struct *work); 704 void mt7996_mac_dump_work(struct work_struct *work); 705 void mt7996_mac_sta_rc_work(struct work_struct *work); 706 void mt7996_mac_update_stats(struct mt7996_phy *phy); 707 void mt7996_mac_twt_teardown_flow(struct mt7996_dev *dev, 708 struct mt7996_sta *msta, 709 u8 flowid); 710 void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw, 711 struct ieee80211_sta *sta, 712 struct ieee80211_twt_setup *twt); 713 int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 714 enum mt76_txq_id qid, struct mt76_wcid *wcid, 715 struct ieee80211_sta *sta, 716 struct mt76_tx_info *tx_info); 717 void mt7996_tx_token_put(struct mt7996_dev *dev); 718 void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 719 struct sk_buff *skb, u32 *info); 720 bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len); 721 void mt7996_stats_work(struct work_struct *work); 722 int mt76_dfs_start_rdd(struct mt7996_dev *dev, bool force); 723 int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy); 724 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy); 725 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy); 726 void mt7996_update_channel(struct mt76_phy *mphy); 727 int mt7996_init_debugfs(struct mt7996_dev *dev); 728 void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len); 729 bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len); 730 int mt7996_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif, 731 struct ieee80211_key_conf *key, int mcu_cmd, 732 struct mt76_wcid *wcid, enum set_key_cmd cmd); 733 int mt7996_mcu_bcn_prot_enable(struct mt7996_dev *dev, struct ieee80211_vif *vif, 734 struct ieee80211_key_conf *key); 735 int mt7996_mcu_wtbl_update_hdr_trans(struct mt7996_dev *dev, 736 struct ieee80211_vif *vif, 737 struct ieee80211_sta *sta); 738 int mt7996_mcu_cp_support(struct mt7996_dev *dev, u8 mode); 739 #ifdef CONFIG_MAC80211_DEBUGFS 740 void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 741 struct ieee80211_sta *sta, struct dentry *dir); 742 #endif 743 int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr, 744 bool hif2, int *irq); 745 u32 mt7996_wed_init_buf(void *ptr, dma_addr_t phys, int token_id); 746 747 #ifdef CONFIG_MTK_DEBUG 748 int mt7996_mtk_init_debugfs(struct mt7996_phy *phy, struct dentry *dir); 749 #endif 750 751 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 752 int mt7996_dma_rro_init(struct mt7996_dev *dev); 753 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 754 755 #endif 756