1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/pci.h> 9 #include <linux/rtnetlink.h> 10 11 #include "mt7996.h" 12 #include "mac.h" 13 #include "mcu.h" 14 #include "../trace.h" 15 #include "../dma.h" 16 17 static bool wed_enable; 18 module_param(wed_enable, bool, 0644); 19 #if defined(__FreeBSD__) 20 MODULE_PARM_DESC(wed_enable, "Enable Wireless Ethernet Dispatch support"); 21 #endif 22 23 static const struct __base mt7996_reg_base[] = { 24 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } }, 25 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } }, 26 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } }, 27 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } }, 28 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } }, 29 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } }, 30 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } }, 31 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } }, 32 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } }, 33 [WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } }, 34 }; 35 36 static const u32 mt7996_offs[] = { 37 [MIB_RVSR0] = 0x720, 38 [MIB_RVSR1] = 0x724, 39 [MIB_BTSCR5] = 0x788, 40 [MIB_BTSCR6] = 0x798, 41 [MIB_RSCR1] = 0x7ac, 42 [MIB_RSCR27] = 0x954, 43 [MIB_RSCR28] = 0x958, 44 [MIB_RSCR29] = 0x95c, 45 [MIB_RSCR30] = 0x960, 46 [MIB_RSCR31] = 0x964, 47 [MIB_RSCR33] = 0x96c, 48 [MIB_RSCR35] = 0x974, 49 [MIB_RSCR36] = 0x978, 50 [MIB_BSCR0] = 0x9cc, 51 [MIB_BSCR1] = 0x9d0, 52 [MIB_BSCR2] = 0x9d4, 53 [MIB_BSCR3] = 0x9d8, 54 [MIB_BSCR4] = 0x9dc, 55 [MIB_BSCR5] = 0x9e0, 56 [MIB_BSCR6] = 0x9e4, 57 [MIB_BSCR7] = 0x9e8, 58 [MIB_BSCR17] = 0xa10, 59 [MIB_TRDR1] = 0xa28, 60 }; 61 62 static const u32 mt7992_offs[] = { 63 [MIB_RVSR0] = 0x760, 64 [MIB_RVSR1] = 0x764, 65 [MIB_BTSCR5] = 0x7c8, 66 [MIB_BTSCR6] = 0x7d8, 67 [MIB_RSCR1] = 0x7f0, 68 [MIB_RSCR27] = 0x998, 69 [MIB_RSCR28] = 0x99c, 70 [MIB_RSCR29] = 0x9a0, 71 [MIB_RSCR30] = 0x9a4, 72 [MIB_RSCR31] = 0x9a8, 73 [MIB_RSCR33] = 0x9b0, 74 [MIB_RSCR35] = 0x9b8, 75 [MIB_RSCR36] = 0x9bc, 76 [MIB_BSCR0] = 0xac8, 77 [MIB_BSCR1] = 0xacc, 78 [MIB_BSCR2] = 0xad0, 79 [MIB_BSCR3] = 0xad4, 80 [MIB_BSCR4] = 0xad8, 81 [MIB_BSCR5] = 0xadc, 82 [MIB_BSCR6] = 0xae0, 83 [MIB_BSCR7] = 0xae4, 84 [MIB_BSCR17] = 0xb0c, 85 [MIB_TRDR1] = 0xb24, 86 }; 87 88 static const struct __map mt7996_reg_map[] = { 89 { 0x54000000, 0x02000, 0x1000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */ 90 { 0x55000000, 0x03000, 0x1000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */ 91 { 0x56000000, 0x04000, 0x1000 }, /* WFDMA reserved */ 92 { 0x57000000, 0x05000, 0x1000 }, /* WFDMA MCU wrap CR */ 93 { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ 94 { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */ 95 { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */ 96 { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */ 97 { 0x820cc000, 0x0e000, 0x1000 }, /* WF_UMAC_TOP (PP) */ 98 { 0x74030000, 0x10000, 0x1000 }, /* PCIe MAC */ 99 { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 100 { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 101 { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 102 { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 103 { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 104 { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 105 { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */ 106 { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 107 { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */ 108 { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 109 { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 110 { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 111 { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 112 { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 113 { 0x820ca000, 0x26000, 0x2000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */ 114 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 115 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */ 116 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ 117 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */ 118 { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 119 { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 120 { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 121 { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 122 { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 123 { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 124 { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 125 { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 126 { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 127 { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 128 { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 129 { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 130 { 0x820cc000, 0xa5000, 0x2000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */ 131 { 0x820c4000, 0xa8000, 0x4000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */ 132 { 0x820b0000, 0xae000, 0x1000 }, /* [APB2] WFSYS_ON */ 133 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 134 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 135 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, wfdma */ 136 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */ 137 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ 138 { 0x0, 0x0, 0x0 }, /* imply end of search */ 139 }; 140 141 static u32 mt7996_reg_map_l1(struct mt7996_dev *dev, u32 addr) 142 { 143 u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr); 144 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr); 145 146 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1, 147 MT_HIF_REMAP_L1_MASK, 148 FIELD_PREP(MT_HIF_REMAP_L1_MASK, base)); 149 /* use read to push write */ 150 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1); 151 152 return MT_HIF_REMAP_BASE_L1 + offset; 153 } 154 155 static u32 mt7996_reg_map_l2(struct mt7996_dev *dev, u32 addr) 156 { 157 u32 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr); 158 u32 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr); 159 160 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2, 161 MT_HIF_REMAP_L2_MASK, 162 FIELD_PREP(MT_HIF_REMAP_L2_MASK, base)); 163 /* use read to push write */ 164 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2); 165 166 return MT_HIF_REMAP_BASE_L2 + offset; 167 } 168 169 static u32 __mt7996_reg_addr(struct mt7996_dev *dev, u32 addr) 170 { 171 int i; 172 173 if (addr < 0x100000) 174 return addr; 175 176 for (i = 0; i < dev->reg.map_size; i++) { 177 u32 ofs; 178 179 if (addr < dev->reg.map[i].phys) 180 continue; 181 182 ofs = addr - dev->reg.map[i].phys; 183 if (ofs >= dev->reg.map[i].size) 184 continue; 185 186 return dev->reg.map[i].mapped + ofs; 187 } 188 189 return 0; 190 } 191 192 static u32 __mt7996_reg_remap_addr(struct mt7996_dev *dev, u32 addr) 193 { 194 if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) || 195 (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) || 196 (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END)) 197 return mt7996_reg_map_l1(dev, addr); 198 199 if (dev_is_pci(dev->mt76.dev) && 200 ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) || 201 addr >= MT_CBTOP2_PHY_START)) 202 return mt7996_reg_map_l1(dev, addr); 203 204 /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */ 205 if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) { 206 addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE; 207 return mt7996_reg_map_l1(dev, addr); 208 } 209 210 return mt7996_reg_map_l2(dev, addr); 211 } 212 213 void mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset, 214 size_t len) 215 { 216 u32 addr = __mt7996_reg_addr(dev, offset); 217 218 if (addr) { 219 #if defined(__linux__) 220 memcpy_fromio(buf, dev->mt76.mmio.regs + addr, len); 221 #elif defined(__FreeBSD__) 222 memcpy_fromio(buf, (u8 *)dev->mt76.mmio.regs + addr, len); 223 #endif 224 return; 225 } 226 227 spin_lock_bh(&dev->reg_lock); 228 #if defined(__linux__) 229 memcpy_fromio(buf, dev->mt76.mmio.regs + 230 #elif defined(__FreeBSD__) 231 memcpy_fromio(buf, (u8 *)dev->mt76.mmio.regs + 232 #endif 233 __mt7996_reg_remap_addr(dev, offset), len); 234 spin_unlock_bh(&dev->reg_lock); 235 } 236 237 static u32 mt7996_rr(struct mt76_dev *mdev, u32 offset) 238 { 239 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 240 u32 addr = __mt7996_reg_addr(dev, offset), val; 241 242 if (addr) 243 return dev->bus_ops->rr(mdev, addr); 244 245 spin_lock_bh(&dev->reg_lock); 246 val = dev->bus_ops->rr(mdev, __mt7996_reg_remap_addr(dev, offset)); 247 spin_unlock_bh(&dev->reg_lock); 248 249 return val; 250 } 251 252 static void mt7996_wr(struct mt76_dev *mdev, u32 offset, u32 val) 253 { 254 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 255 u32 addr = __mt7996_reg_addr(dev, offset); 256 257 if (addr) { 258 dev->bus_ops->wr(mdev, addr, val); 259 return; 260 } 261 262 spin_lock_bh(&dev->reg_lock); 263 dev->bus_ops->wr(mdev, __mt7996_reg_remap_addr(dev, offset), val); 264 spin_unlock_bh(&dev->reg_lock); 265 } 266 267 static u32 mt7996_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 268 { 269 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 270 u32 addr = __mt7996_reg_addr(dev, offset); 271 272 if (addr) 273 return dev->bus_ops->rmw(mdev, addr, mask, val); 274 275 spin_lock_bh(&dev->reg_lock); 276 val = dev->bus_ops->rmw(mdev, __mt7996_reg_remap_addr(dev, offset), mask, val); 277 spin_unlock_bh(&dev->reg_lock); 278 279 return val; 280 } 281 282 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 283 static int mt7996_mmio_wed_reset(struct mtk_wed_device *wed) 284 { 285 struct mt76_dev *mdev = container_of(wed, struct mt76_dev, mmio.wed); 286 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 287 struct mt76_phy *mphy = &dev->mphy; 288 int ret; 289 290 ASSERT_RTNL(); 291 292 if (test_and_set_bit(MT76_STATE_WED_RESET, &mphy->state)) 293 return -EBUSY; 294 295 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_TRIGGER, UNI_CMD_SER_SET_RECOVER_L1, 296 mphy->band_idx); 297 if (ret) 298 goto out; 299 300 rtnl_unlock(); 301 if (!wait_for_completion_timeout(&mdev->mmio.wed_reset, 20 * HZ)) { 302 dev_err(mdev->dev, "wed reset timeout\n"); 303 ret = -ETIMEDOUT; 304 } 305 rtnl_lock(); 306 out: 307 clear_bit(MT76_STATE_WED_RESET, &mphy->state); 308 309 return ret; 310 } 311 #endif 312 313 int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr, 314 bool hif2, int *irq) 315 { 316 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 317 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 318 struct pci_dev *pci_dev = pdev_ptr; 319 u32 hif1_ofs = 0; 320 321 if (!wed_enable) 322 return 0; 323 324 dev->has_rro = true; 325 326 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 327 328 if (hif2) 329 wed = &dev->mt76.mmio.wed_hif2; 330 331 wed->wlan.pci_dev = pci_dev; 332 wed->wlan.bus_type = MTK_WED_BUS_PCIE; 333 334 wed->wlan.base = devm_ioremap(dev->mt76.dev, 335 pci_resource_start(pci_dev, 0), 336 pci_resource_len(pci_dev, 0)); 337 wed->wlan.phy_base = pci_resource_start(pci_dev, 0); 338 339 if (hif2) { 340 wed->wlan.wpdma_int = wed->wlan.phy_base + 341 MT_INT_PCIE1_SOURCE_CSR_EXT; 342 wed->wlan.wpdma_mask = wed->wlan.phy_base + 343 MT_INT_PCIE1_MASK_CSR; 344 wed->wlan.wpdma_tx = wed->wlan.phy_base + hif1_ofs + 345 MT_TXQ_RING_BASE(0) + 346 MT7996_TXQ_BAND2 * MT_RING_SIZE; 347 if (dev->has_rro) { 348 wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs + 349 MT_RXQ_RING_BASE(0) + 350 MT7996_RXQ_TXFREE2 * MT_RING_SIZE; 351 wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_EXT) - 1; 352 } else { 353 wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs + 354 MT_RXQ_RING_BASE(0) + 355 MT7996_RXQ_MCU_WA_TRI * MT_RING_SIZE; 356 wed->wlan.txfree_tbit = ffs(MT_INT_RX_DONE_WA_TRI) - 1; 357 } 358 359 wed->wlan.wpdma_rx_glo = wed->wlan.phy_base + hif1_ofs + MT_WFDMA0_GLO_CFG; 360 wed->wlan.wpdma_rx = wed->wlan.phy_base + hif1_ofs + 361 MT_RXQ_RING_BASE(MT7996_RXQ_BAND0) + 362 MT7996_RXQ_BAND0 * MT_RING_SIZE; 363 364 wed->wlan.id = 0x7991; 365 wed->wlan.tx_tbit[0] = ffs(MT_INT_TX_DONE_BAND2) - 1; 366 } else { 367 wed->wlan.hw_rro = dev->has_rro; /* default on */ 368 wed->wlan.wpdma_int = wed->wlan.phy_base + MT_INT_SOURCE_CSR; 369 wed->wlan.wpdma_mask = wed->wlan.phy_base + MT_INT_MASK_CSR; 370 wed->wlan.wpdma_tx = wed->wlan.phy_base + MT_TXQ_RING_BASE(0) + 371 MT7996_TXQ_BAND0 * MT_RING_SIZE; 372 373 wed->wlan.wpdma_rx_glo = wed->wlan.phy_base + MT_WFDMA0_GLO_CFG; 374 375 wed->wlan.wpdma_rx = wed->wlan.phy_base + 376 MT_RXQ_RING_BASE(MT7996_RXQ_BAND0) + 377 MT7996_RXQ_BAND0 * MT_RING_SIZE; 378 379 wed->wlan.wpdma_rx_rro[0] = wed->wlan.phy_base + 380 MT_RXQ_RING_BASE(MT7996_RXQ_RRO_BAND0) + 381 MT7996_RXQ_RRO_BAND0 * MT_RING_SIZE; 382 wed->wlan.wpdma_rx_rro[1] = wed->wlan.phy_base + hif1_ofs + 383 MT_RXQ_RING_BASE(MT7996_RXQ_RRO_BAND2) + 384 MT7996_RXQ_RRO_BAND2 * MT_RING_SIZE; 385 wed->wlan.wpdma_rx_pg = wed->wlan.phy_base + 386 MT_RXQ_RING_BASE(MT7996_RXQ_MSDU_PG_BAND0) + 387 MT7996_RXQ_MSDU_PG_BAND0 * MT_RING_SIZE; 388 389 wed->wlan.rx_nbuf = 65536; 390 wed->wlan.rx_npkt = dev->hif2 ? 32768 : 24576; 391 wed->wlan.rx_size = SKB_WITH_OVERHEAD(MT_RX_BUF_SIZE); 392 393 wed->wlan.rx_tbit[0] = ffs(MT_INT_RX_DONE_BAND0) - 1; 394 wed->wlan.rx_tbit[1] = ffs(MT_INT_RX_DONE_BAND2) - 1; 395 396 wed->wlan.rro_rx_tbit[0] = ffs(MT_INT_RX_DONE_RRO_BAND0) - 1; 397 wed->wlan.rro_rx_tbit[1] = ffs(MT_INT_RX_DONE_RRO_BAND2) - 1; 398 399 wed->wlan.rx_pg_tbit[0] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND0) - 1; 400 wed->wlan.rx_pg_tbit[1] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND1) - 1; 401 wed->wlan.rx_pg_tbit[2] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND2) - 1; 402 403 wed->wlan.tx_tbit[0] = ffs(MT_INT_TX_DONE_BAND0) - 1; 404 wed->wlan.tx_tbit[1] = ffs(MT_INT_TX_DONE_BAND1) - 1; 405 if (dev->has_rro) { 406 wed->wlan.wpdma_txfree = wed->wlan.phy_base + MT_RXQ_RING_BASE(0) + 407 MT7996_RXQ_TXFREE0 * MT_RING_SIZE; 408 wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_MAIN) - 1; 409 } else { 410 wed->wlan.txfree_tbit = ffs(MT_INT_RX_DONE_WA_MAIN) - 1; 411 wed->wlan.wpdma_txfree = wed->wlan.phy_base + MT_RXQ_RING_BASE(0) + 412 MT7996_RXQ_MCU_WA_MAIN * MT_RING_SIZE; 413 } 414 dev->mt76.rx_token_size = MT7996_TOKEN_SIZE + wed->wlan.rx_npkt; 415 } 416 417 wed->wlan.nbuf = MT7996_HW_TOKEN_SIZE; 418 wed->wlan.token_start = MT7996_TOKEN_SIZE - wed->wlan.nbuf; 419 420 wed->wlan.amsdu_max_subframes = 8; 421 wed->wlan.amsdu_max_len = 1536; 422 423 wed->wlan.init_buf = mt7996_wed_init_buf; 424 wed->wlan.init_rx_buf = mt76_wed_init_rx_buf; 425 wed->wlan.release_rx_buf = mt76_wed_release_rx_buf; 426 wed->wlan.offload_enable = mt76_wed_offload_enable; 427 wed->wlan.offload_disable = mt76_wed_offload_disable; 428 if (!hif2) { 429 wed->wlan.reset = mt7996_mmio_wed_reset; 430 wed->wlan.reset_complete = mt76_wed_reset_complete; 431 } 432 433 if (mtk_wed_device_attach(wed)) 434 return 0; 435 436 *irq = wed->irq; 437 dev->mt76.dma_dev = wed->dev; 438 439 return 1; 440 #else 441 return 0; 442 #endif 443 } 444 445 static int mt7996_mmio_init(struct mt76_dev *mdev, 446 void __iomem *mem_base, 447 u32 device_id) 448 { 449 struct mt76_bus_ops *bus_ops; 450 struct mt7996_dev *dev; 451 452 dev = container_of(mdev, struct mt7996_dev, mt76); 453 mt76_mmio_init(&dev->mt76, mem_base); 454 spin_lock_init(&dev->reg_lock); 455 456 switch (device_id) { 457 case 0x7990: 458 dev->reg.base = mt7996_reg_base; 459 dev->reg.offs_rev = mt7996_offs; 460 dev->reg.map = mt7996_reg_map; 461 dev->reg.map_size = ARRAY_SIZE(mt7996_reg_map); 462 break; 463 case 0x7992: 464 dev->reg.base = mt7996_reg_base; 465 dev->reg.offs_rev = mt7992_offs; 466 dev->reg.map = mt7996_reg_map; 467 dev->reg.map_size = ARRAY_SIZE(mt7996_reg_map); 468 break; 469 default: 470 return -EINVAL; 471 } 472 473 dev->bus_ops = dev->mt76.bus; 474 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 475 GFP_KERNEL); 476 if (!bus_ops) 477 return -ENOMEM; 478 479 bus_ops->rr = mt7996_rr; 480 bus_ops->wr = mt7996_wr; 481 bus_ops->rmw = mt7996_rmw; 482 dev->mt76.bus = bus_ops; 483 484 mdev->rev = (device_id << 16) | (mt76_rr(dev, MT_HW_REV) & 0xff); 485 486 dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev); 487 488 return 0; 489 } 490 491 void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg, 492 u32 clear, u32 set) 493 { 494 struct mt76_dev *mdev = &dev->mt76; 495 unsigned long flags; 496 497 spin_lock_irqsave(&mdev->mmio.irq_lock, flags); 498 499 mdev->mmio.irqmask &= ~clear; 500 mdev->mmio.irqmask |= set; 501 502 if (write_reg) { 503 if (mtk_wed_device_active(&mdev->mmio.wed)) { 504 mtk_wed_device_irq_set_mask(&mdev->mmio.wed, 505 mdev->mmio.irqmask); 506 if (mtk_wed_device_active(&mdev->mmio.wed_hif2)) { 507 mtk_wed_device_irq_set_mask(&mdev->mmio.wed_hif2, 508 mdev->mmio.irqmask); 509 } 510 } else { 511 mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask); 512 mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask); 513 } 514 } 515 516 spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags); 517 } 518 519 static void mt7996_rx_poll_complete(struct mt76_dev *mdev, 520 enum mt76_rxq_id q) 521 { 522 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 523 524 mt7996_irq_enable(dev, MT_INT_RX(q)); 525 } 526 527 /* TODO: support 2/4/6/8 MSI-X vectors */ 528 static void mt7996_irq_tasklet(struct tasklet_struct *t) 529 { 530 struct mt7996_dev *dev = from_tasklet(dev, t, mt76.irq_tasklet); 531 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 532 struct mtk_wed_device *wed_hif2 = &dev->mt76.mmio.wed_hif2; 533 u32 i, intr, mask, intr1 = 0; 534 535 if (dev->hif2 && mtk_wed_device_active(wed_hif2)) { 536 mtk_wed_device_irq_set_mask(wed_hif2, 0); 537 intr1 = mtk_wed_device_irq_get(wed_hif2, 538 dev->mt76.mmio.irqmask); 539 if (intr1 & MT_INT_RX_TXFREE_EXT) 540 napi_schedule(&dev->mt76.napi[MT_RXQ_TXFREE_BAND2]); 541 } 542 543 if (mtk_wed_device_active(wed)) { 544 mtk_wed_device_irq_set_mask(wed, 0); 545 intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask); 546 intr |= (intr1 & ~MT_INT_RX_TXFREE_EXT); 547 } else { 548 mt76_wr(dev, MT_INT_MASK_CSR, 0); 549 if (dev->hif2) 550 mt76_wr(dev, MT_INT1_MASK_CSR, 0); 551 552 intr = mt76_rr(dev, MT_INT_SOURCE_CSR); 553 intr &= dev->mt76.mmio.irqmask; 554 mt76_wr(dev, MT_INT_SOURCE_CSR, intr); 555 if (dev->hif2) { 556 intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR); 557 intr1 &= dev->mt76.mmio.irqmask; 558 mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1); 559 intr |= intr1; 560 } 561 } 562 563 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); 564 565 mask = intr & MT_INT_RX_DONE_ALL; 566 if (intr & MT_INT_TX_DONE_MCU) 567 mask |= MT_INT_TX_DONE_MCU; 568 mt7996_irq_disable(dev, mask); 569 570 if (intr & MT_INT_TX_DONE_MCU) 571 napi_schedule(&dev->mt76.tx_napi); 572 573 for (i = 0; i < __MT_RXQ_MAX; i++) { 574 if ((intr & MT_INT_RX(i))) 575 napi_schedule(&dev->mt76.napi[i]); 576 } 577 578 if (intr & MT_INT_MCU_CMD) { 579 u32 val = mt76_rr(dev, MT_MCU_CMD); 580 581 mt76_wr(dev, MT_MCU_CMD, val); 582 if (val & (MT_MCU_CMD_ERROR_MASK | MT_MCU_CMD_WDT_MASK)) { 583 dev->recovery.state = val; 584 mt7996_reset(dev); 585 } 586 } 587 } 588 589 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance) 590 { 591 struct mt7996_dev *dev = dev_instance; 592 593 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) 594 mtk_wed_device_irq_set_mask(&dev->mt76.mmio.wed, 0); 595 else 596 mt76_wr(dev, MT_INT_MASK_CSR, 0); 597 598 if (dev->hif2) { 599 if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2)) 600 mtk_wed_device_irq_set_mask(&dev->mt76.mmio.wed_hif2, 0); 601 else 602 mt76_wr(dev, MT_INT1_MASK_CSR, 0); 603 } 604 605 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) 606 return IRQ_NONE; 607 608 tasklet_schedule(&dev->mt76.irq_tasklet); 609 610 return IRQ_HANDLED; 611 } 612 613 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev, 614 void __iomem *mem_base, u32 device_id) 615 { 616 static const struct mt76_driver_ops drv_ops = { 617 /* txwi_size = txd size + txp size */ 618 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_fw_txp), 619 .link_data_size = sizeof(struct mt7996_vif_link), 620 .drv_flags = MT_DRV_TXWI_NO_FREE | 621 MT_DRV_AMSDU_OFFLOAD | 622 MT_DRV_HW_MGMT_TXQ, 623 .survey_flags = SURVEY_INFO_TIME_TX | 624 SURVEY_INFO_TIME_RX | 625 SURVEY_INFO_TIME_BSS_RX, 626 .token_size = MT7996_TOKEN_SIZE, 627 .tx_prepare_skb = mt7996_tx_prepare_skb, 628 .tx_complete_skb = mt76_connac_tx_complete_skb, 629 .rx_skb = mt7996_queue_rx_skb, 630 .rx_check = mt7996_rx_check, 631 .rx_poll_complete = mt7996_rx_poll_complete, 632 .sta_add = mt7996_mac_sta_add, 633 .sta_event = mt7996_mac_sta_event, 634 .sta_remove = mt7996_mac_sta_remove, 635 .update_survey = mt7996_update_channel, 636 .set_channel = mt7996_set_channel, 637 .vif_link_add = mt7996_vif_link_add, 638 .vif_link_remove = mt7996_vif_link_remove, 639 }; 640 struct mt7996_dev *dev; 641 struct mt76_dev *mdev; 642 int ret; 643 644 mdev = mt76_alloc_device(pdev, sizeof(*dev), &mt7996_ops, &drv_ops); 645 if (!mdev) 646 return ERR_PTR(-ENOMEM); 647 648 dev = container_of(mdev, struct mt7996_dev, mt76); 649 650 ret = mt7996_mmio_init(mdev, mem_base, device_id); 651 if (ret) 652 goto error; 653 654 tasklet_setup(&mdev->irq_tasklet, mt7996_irq_tasklet); 655 656 mt76_wr(dev, MT_INT_MASK_CSR, 0); 657 658 return dev; 659 660 error: 661 mt76_free_device(&dev->mt76); 662 663 return ERR_PTR(ret); 664 } 665 666 static int __init mt7996_init(void) 667 { 668 int ret; 669 670 ret = pci_register_driver(&mt7996_hif_driver); 671 if (ret) 672 return ret; 673 674 ret = pci_register_driver(&mt7996_pci_driver); 675 if (ret) 676 pci_unregister_driver(&mt7996_hif_driver); 677 678 return ret; 679 } 680 681 static void __exit mt7996_exit(void) 682 { 683 pci_unregister_driver(&mt7996_pci_driver); 684 pci_unregister_driver(&mt7996_hif_driver); 685 } 686 687 module_init(mt7996_init); 688 module_exit(mt7996_exit); 689 MODULE_DESCRIPTION("MediaTek MT7996 MMIO helpers"); 690 MODULE_LICENSE("Dual BSD/GPL"); 691