1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/module.h> 8 #include <linux/pci.h> 9 #include <linux/rtnetlink.h> 10 11 #include "mt7996.h" 12 #include "mac.h" 13 #include "mcu.h" 14 #include "../trace.h" 15 #include "../dma.h" 16 17 static bool wed_enable; 18 module_param(wed_enable, bool, 0644); 19 #if defined(__FreeBSD__) 20 MODULE_PARM_DESC(wed_enable, "Enable Wireless Ethernet Dispatch support"); 21 #endif 22 23 static const struct __base mt7996_reg_base[] = { 24 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } }, 25 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } }, 26 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } }, 27 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } }, 28 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } }, 29 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } }, 30 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } }, 31 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } }, 32 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } }, 33 [WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } }, 34 }; 35 36 static const u32 mt7996_offs[] = { 37 [MIB_RVSR0] = 0x720, 38 [MIB_RVSR1] = 0x724, 39 [MIB_BTSCR5] = 0x788, 40 [MIB_BTSCR6] = 0x798, 41 [MIB_RSCR1] = 0x7ac, 42 [MIB_RSCR27] = 0x954, 43 [MIB_RSCR28] = 0x958, 44 [MIB_RSCR29] = 0x95c, 45 [MIB_RSCR30] = 0x960, 46 [MIB_RSCR31] = 0x964, 47 [MIB_RSCR33] = 0x96c, 48 [MIB_RSCR35] = 0x974, 49 [MIB_RSCR36] = 0x978, 50 [MIB_BSCR0] = 0x9cc, 51 [MIB_BSCR1] = 0x9d0, 52 [MIB_BSCR2] = 0x9d4, 53 [MIB_BSCR3] = 0x9d8, 54 [MIB_BSCR4] = 0x9dc, 55 [MIB_BSCR5] = 0x9e0, 56 [MIB_BSCR6] = 0x9e4, 57 [MIB_BSCR7] = 0x9e8, 58 [MIB_BSCR17] = 0xa10, 59 [MIB_TRDR1] = 0xa28, 60 [HIF_REMAP_L1] = 0x24, 61 [HIF_REMAP_BASE_L1] = 0x130000, 62 [HIF_REMAP_L2] = 0x1b4, 63 [HIF_REMAP_BASE_L2] = 0x1000, 64 [CBTOP1_PHY_END] = 0x77ffffff, 65 [INFRA_MCU_END] = 0x7c3fffff, 66 [WTBLON_WDUCR] = 0x370, 67 [WTBL_UPDATE] = 0x380, 68 [WTBL_ITCR] = 0x3b0, 69 [WTBL_ITCR0] = 0x3b8, 70 [WTBL_ITCR1] = 0x3bc, 71 }; 72 73 static const u32 mt7992_offs[] = { 74 [MIB_RVSR0] = 0x760, 75 [MIB_RVSR1] = 0x764, 76 [MIB_BTSCR5] = 0x7c8, 77 [MIB_BTSCR6] = 0x7d8, 78 [MIB_RSCR1] = 0x7f0, 79 [MIB_RSCR27] = 0x998, 80 [MIB_RSCR28] = 0x99c, 81 [MIB_RSCR29] = 0x9a0, 82 [MIB_RSCR30] = 0x9a4, 83 [MIB_RSCR31] = 0x9a8, 84 [MIB_RSCR33] = 0x9b0, 85 [MIB_RSCR35] = 0x9b8, 86 [MIB_RSCR36] = 0x9bc, 87 [MIB_BSCR0] = 0xac8, 88 [MIB_BSCR1] = 0xacc, 89 [MIB_BSCR2] = 0xad0, 90 [MIB_BSCR3] = 0xad4, 91 [MIB_BSCR4] = 0xad8, 92 [MIB_BSCR5] = 0xadc, 93 [MIB_BSCR6] = 0xae0, 94 [MIB_BSCR7] = 0xae4, 95 [MIB_BSCR17] = 0xb0c, 96 [MIB_TRDR1] = 0xb24, 97 [HIF_REMAP_L1] = 0x8, 98 [HIF_REMAP_BASE_L1] = 0x40000, 99 [HIF_REMAP_L2] = 0x1b4, 100 [HIF_REMAP_BASE_L2] = 0x1000, 101 [CBTOP1_PHY_END] = 0x77ffffff, 102 [INFRA_MCU_END] = 0x7c3fffff, 103 [WTBLON_WDUCR] = 0x370, 104 [WTBL_UPDATE] = 0x380, 105 [WTBL_ITCR] = 0x3b0, 106 [WTBL_ITCR0] = 0x3b8, 107 [WTBL_ITCR1] = 0x3bc, 108 }; 109 110 static const u32 mt7990_offs[] = { 111 [MIB_RVSR0] = 0x800, 112 [MIB_RVSR1] = 0x804, 113 [MIB_BTSCR5] = 0x868, 114 [MIB_BTSCR6] = 0x878, 115 [MIB_RSCR1] = 0x890, 116 [MIB_RSCR27] = 0xa38, 117 [MIB_RSCR28] = 0xa3c, 118 [MIB_RSCR29] = 0xa40, 119 [MIB_RSCR30] = 0xa44, 120 [MIB_RSCR31] = 0xa48, 121 [MIB_RSCR33] = 0xa50, 122 [MIB_RSCR35] = 0xa58, 123 [MIB_RSCR36] = 0xa5c, 124 [MIB_BSCR0] = 0xbb8, 125 [MIB_BSCR1] = 0xbbc, 126 [MIB_BSCR2] = 0xbc0, 127 [MIB_BSCR3] = 0xbc4, 128 [MIB_BSCR4] = 0xbc8, 129 [MIB_BSCR5] = 0xbcc, 130 [MIB_BSCR6] = 0xbd0, 131 [MIB_BSCR7] = 0xbd4, 132 [MIB_BSCR17] = 0xbfc, 133 [MIB_TRDR1] = 0xc14, 134 [HIF_REMAP_L1] = 0x8, 135 [HIF_REMAP_BASE_L1] = 0x40000, 136 [HIF_REMAP_L2] = 0x1b8, 137 [HIF_REMAP_BASE_L2] = 0x110000, 138 [CBTOP1_PHY_END] = 0x7fffffff, 139 [INFRA_MCU_END] = 0x7cffffff, 140 [WTBLON_WDUCR] = 0x400, 141 [WTBL_UPDATE] = 0x410, 142 [WTBL_ITCR] = 0x440, 143 [WTBL_ITCR0] = 0x448, 144 [WTBL_ITCR1] = 0x44c, 145 }; 146 147 static const struct __map mt7996_reg_map[] = { 148 { 0x54000000, 0x02000, 0x1000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */ 149 { 0x55000000, 0x03000, 0x1000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */ 150 { 0x56000000, 0x04000, 0x1000 }, /* WFDMA reserved */ 151 { 0x57000000, 0x05000, 0x1000 }, /* WFDMA MCU wrap CR */ 152 { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ 153 { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */ 154 { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */ 155 { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */ 156 { 0x820cc000, 0x0e000, 0x1000 }, /* WF_UMAC_TOP (PP) */ 157 { 0x74030000, 0x10000, 0x1000 }, /* PCIe MAC */ 158 { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 159 { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 160 { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 161 { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 162 { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 163 { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 164 { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */ 165 { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 166 { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */ 167 { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 168 { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 169 { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 170 { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 171 { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 172 { 0x820ca000, 0x26000, 0x2000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */ 173 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 174 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */ 175 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ 176 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */ 177 { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 178 { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 179 { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 180 { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 181 { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 182 { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 183 { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 184 { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 185 { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 186 { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 187 { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 188 { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 189 { 0x820cc000, 0xa5000, 0x2000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */ 190 { 0x820c4000, 0xa8000, 0x4000 }, /* WF_LMAC_TOP BN1 (WF_MUCOP) */ 191 { 0x820b0000, 0xae000, 0x1000 }, /* [APB2] WFSYS_ON */ 192 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 193 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 194 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, wfdma */ 195 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */ 196 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ 197 { 0x0, 0x0, 0x0 }, /* imply end of search */ 198 }; 199 200 static const struct __map mt7990_reg_map[] = { 201 {0x54000000, 0x02000, 0x1000}, /* WFDMA_0 (PCIE0 MCU DMA0) */ 202 {0x55000000, 0x03000, 0x1000}, /* WFDMA_1 (PCIE0 MCU DMA1) */ 203 {0x56000000, 0x04000, 0x1000}, /* WFDMA_2 (Reserved) */ 204 {0x57000000, 0x05000, 0x1000}, /* WFDMA_3 (MCU wrap CR) */ 205 {0x58000000, 0x06000, 0x1000}, /* WFDMA_4 (PCIE1 MCU DMA0 (MEM_DMA)) */ 206 {0x59000000, 0x07000, 0x1000}, /* WFDMA_5 (PCIE1 MCU DMA1) */ 207 {0x820c0000, 0x08000, 0x4000}, /* WF_UMAC_TOP (PLE) */ 208 {0x820c8000, 0x0c000, 0x2000}, /* WF_UMAC_TOP (PSE) */ 209 {0x820cc000, 0x0e000, 0x2000}, /* WF_UMAC_TOP (PP) */ 210 {0x820e0000, 0x20000, 0x0400}, /* WF_LMAC_TOP BN0 (WF_CFG) */ 211 {0x820e1000, 0x20400, 0x0200}, /* WF_LMAC_TOP BN0 (WF_TRB) */ 212 {0x820e2000, 0x20800, 0x0400}, /* WF_LMAC_TOP BN0 (WF_AGG) */ 213 {0x820e3000, 0x20c00, 0x0400}, /* WF_LMAC_TOP BN0 (WF_ARB) */ 214 {0x820e4000, 0x21000, 0x0400}, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 215 {0x820e5000, 0x21400, 0x0800}, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 216 {0x820ce000, 0x21c00, 0x0200}, /* WF_LMAC_TOP (WF_SEC) */ 217 {0x820e7000, 0x21e00, 0x0200}, /* WF_LMAC_TOP BN0 (WF_DMA) */ 218 {0x820cf000, 0x22000, 0x1000}, /* WF_LMAC_TOP (WF_PF) */ 219 {0x820e9000, 0x23400, 0x0200}, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 220 {0x820ea000, 0x24000, 0x0200}, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 221 {0x820eb000, 0x24200, 0x0400}, /* WF_LMAC_TOP BN0 (WF_LPON) */ 222 {0x820ec000, 0x24600, 0x0200}, /* WF_LMAC_TOP BN0 (WF_INT) */ 223 {0x820ed000, 0x24800, 0x0800}, /* WF_LMAC_TOP BN0 (WF_MIB) */ 224 {0x820ca000, 0x26000, 0x2000}, /* WF_LMAC_TOP BN0 (WF_MUCOP) */ 225 {0x820d0000, 0x30000, 0x10000}, /* WF_LMAC_TOP (WF_WTBLON) */ 226 {0x00400000, 0x80000, 0x10000}, /* WF_MCU_SYSRAM */ 227 {0x820f0000, 0xa0000, 0x0400}, /* WF_LMAC_TOP BN1 (WF_CFG) */ 228 {0x820f1000, 0xa0600, 0x0200}, /* WF_LMAC_TOP BN1 (WF_TRB) */ 229 {0x820f2000, 0xa0800, 0x0400}, /* WF_LMAC_TOP BN1 (WF_AGG) */ 230 {0x820f3000, 0xa0c00, 0x0400}, /* WF_LMAC_TOP BN1 (WF_ARB) */ 231 {0x820f4000, 0xa1000, 0x0400}, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 232 {0x820f5000, 0xa1400, 0x0800}, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 233 {0x820f7000, 0xa1e00, 0x0200}, /* WF_LMAC_TOP BN1 (WF_DMA) */ 234 {0x820f9000, 0xa3400, 0x0200}, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 235 {0x820fa000, 0xa4000, 0x0200}, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 236 {0x820fb000, 0xa4200, 0x0400}, /* WF_LMAC_TOP BN1 (WF_LPON) */ 237 {0x820fc000, 0xa4600, 0x0200}, /* WF_LMAC_TOP BN1 (WF_INT) */ 238 {0x820fd000, 0xa4800, 0x0800}, /* WF_LMAC_TOP BN1 (WF_MIB) */ 239 {0x820cc000, 0xa5000, 0x2000}, /* WF_LMAC_TOP BN1 (WF_MUCOP) */ 240 {0x820c4000, 0xa8000, 0x4000}, /* WF_LMAC_TOP (WF_UWTBL) */ 241 {0x81030000, 0xae000, 0x100}, /* WFSYS_AON part 1 */ 242 {0x81031000, 0xae100, 0x100}, /* WFSYS_AON part 2 */ 243 {0x81032000, 0xae200, 0x100}, /* WFSYS_AON part 3 */ 244 {0x81033000, 0xae300, 0x100}, /* WFSYS_AON part 4 */ 245 {0x81034000, 0xae400, 0x100}, /* WFSYS_AON part 5 */ 246 {0x80020000, 0xb0000, 0x10000}, /* WF_TOP_MISC_OFF */ 247 {0x81020000, 0xc0000, 0x10000}, /* WF_TOP_MISC_ON */ 248 {0x81040000, 0x120000, 0x1000}, /* WF_MCU_CFG_ON */ 249 {0x81050000, 0x121000, 0x1000}, /* WF_MCU_EINT */ 250 {0x81060000, 0x122000, 0x1000}, /* WF_MCU_GPT */ 251 {0x81070000, 0x123000, 0x1000}, /* WF_MCU_WDT */ 252 {0x80010000, 0x124000, 0x1000}, /* WF_AXIDMA */ 253 {0x7c020000, 0xd0000, 0x10000}, /* CONN_INFRA, wfdma for from CODA flow use */ 254 {0x7c060000, 0xe0000, 0x10000}, /* CONN_INFRA, conn_host_csr_top for from CODA flow use */ 255 {0x20020000, 0xd0000, 0x10000}, /* CONN_INFRA, wfdma */ 256 {0x20060000, 0xe0000, 0x10000}, /* CONN_INFRA, conn_host_csr_top */ 257 {0x7c000000, 0xf0000, 0x10000}, /* CONN_INFRA */ 258 {0x70020000, 0x1f0000, 0x9000}, /* PCIE remapping (AP2CONN) */ 259 {0x0, 0x0, 0x0}, /* imply end of search */ 260 }; 261 262 static u32 mt7996_reg_map_l1(struct mt7996_dev *dev, u32 addr) 263 { 264 u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr); 265 u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr); 266 u32 l1_mask, val; 267 268 if (is_mt7996(&dev->mt76)) { 269 l1_mask = MT_HIF_REMAP_L1_MASK_7996; 270 val = FIELD_PREP(MT_HIF_REMAP_L1_MASK_7996, base); 271 } else { 272 l1_mask = MT_HIF_REMAP_L1_MASK; 273 val = FIELD_PREP(MT_HIF_REMAP_L1_MASK, base); 274 } 275 276 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L1, l1_mask, val); 277 /* use read to push write */ 278 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L1); 279 280 return MT_HIF_REMAP_BASE_L1 + offset; 281 } 282 283 static u32 mt7996_reg_map_l2(struct mt7996_dev *dev, u32 addr) 284 { 285 u32 offset, base, l2_mask, val; 286 287 if (is_mt7990(&dev->mt76)) { 288 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET_7990, addr); 289 base = FIELD_GET(MT_HIF_REMAP_L2_BASE_7990, addr); 290 l2_mask = MT_HIF_REMAP_L2_MASK_7990; 291 val = FIELD_PREP(MT_HIF_REMAP_L2_MASK_7990, base); 292 } else { 293 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr); 294 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr); 295 l2_mask = MT_HIF_REMAP_L2_MASK; 296 val = FIELD_PREP(MT_HIF_REMAP_L2_MASK, base); 297 } 298 299 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2, l2_mask, val); 300 /* use read to push write */ 301 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2); 302 303 return MT_HIF_REMAP_BASE_L2 + offset; 304 } 305 306 static u32 mt7996_reg_map_cbtop(struct mt7996_dev *dev, u32 addr) 307 { 308 u32 offset = FIELD_GET(MT_HIF_REMAP_CBTOP_OFFSET, addr); 309 u32 base = FIELD_GET(MT_HIF_REMAP_CBTOP_BASE, addr); 310 311 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_CBTOP, 312 MT_HIF_REMAP_CBTOP_MASK, 313 FIELD_PREP(MT_HIF_REMAP_CBTOP_MASK, base)); 314 /* use read to push write */ 315 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_CBTOP); 316 317 return MT_HIF_REMAP_BASE_CBTOP + offset; 318 } 319 320 static u32 __mt7996_reg_addr(struct mt7996_dev *dev, u32 addr) 321 { 322 int i; 323 324 if (addr < 0x100000) 325 return addr; 326 327 for (i = 0; i < dev->reg.map_size; i++) { 328 u32 ofs; 329 330 if (addr < dev->reg.map[i].phys) 331 continue; 332 333 ofs = addr - dev->reg.map[i].phys; 334 if (ofs >= dev->reg.map[i].size) 335 continue; 336 337 return dev->reg.map[i].mapped + ofs; 338 } 339 340 return 0; 341 } 342 343 static u32 __mt7996_reg_remap_addr(struct mt7996_dev *dev, u32 addr) 344 { 345 if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) || 346 (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) || 347 (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END)) 348 return mt7996_reg_map_l1(dev, addr); 349 350 /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */ 351 if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) { 352 addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE; 353 return mt7996_reg_map_l1(dev, addr); 354 } 355 356 if (dev_is_pci(dev->mt76.dev) && 357 ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) || 358 addr >= MT_CBTOP2_PHY_START)) { 359 if (is_mt7990(&dev->mt76)) 360 return mt7996_reg_map_cbtop(dev, addr); 361 return mt7996_reg_map_l1(dev, addr); 362 } 363 364 return mt7996_reg_map_l2(dev, addr); 365 } 366 367 void mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset, 368 size_t len) 369 { 370 u32 addr = __mt7996_reg_addr(dev, offset); 371 372 if (addr) { 373 #if defined(__linux__) 374 memcpy_fromio(buf, dev->mt76.mmio.regs + addr, len); 375 #elif defined(__FreeBSD__) 376 memcpy_fromio(buf, (u8 *)dev->mt76.mmio.regs + addr, len); 377 #endif 378 return; 379 } 380 381 spin_lock_bh(&dev->reg_lock); 382 #if defined(__linux__) 383 memcpy_fromio(buf, dev->mt76.mmio.regs + 384 #elif defined(__FreeBSD__) 385 memcpy_fromio(buf, (u8 *)dev->mt76.mmio.regs + 386 #endif 387 __mt7996_reg_remap_addr(dev, offset), len); 388 spin_unlock_bh(&dev->reg_lock); 389 } 390 391 static u32 mt7996_rr(struct mt76_dev *mdev, u32 offset) 392 { 393 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 394 u32 addr = __mt7996_reg_addr(dev, offset), val; 395 396 if (addr) 397 return dev->bus_ops->rr(mdev, addr); 398 399 spin_lock_bh(&dev->reg_lock); 400 val = dev->bus_ops->rr(mdev, __mt7996_reg_remap_addr(dev, offset)); 401 spin_unlock_bh(&dev->reg_lock); 402 403 return val; 404 } 405 406 static void mt7996_wr(struct mt76_dev *mdev, u32 offset, u32 val) 407 { 408 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 409 u32 addr = __mt7996_reg_addr(dev, offset); 410 411 if (addr) { 412 dev->bus_ops->wr(mdev, addr, val); 413 return; 414 } 415 416 spin_lock_bh(&dev->reg_lock); 417 dev->bus_ops->wr(mdev, __mt7996_reg_remap_addr(dev, offset), val); 418 spin_unlock_bh(&dev->reg_lock); 419 } 420 421 static u32 mt7996_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 422 { 423 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 424 u32 addr = __mt7996_reg_addr(dev, offset); 425 426 if (addr) 427 return dev->bus_ops->rmw(mdev, addr, mask, val); 428 429 spin_lock_bh(&dev->reg_lock); 430 val = dev->bus_ops->rmw(mdev, __mt7996_reg_remap_addr(dev, offset), mask, val); 431 spin_unlock_bh(&dev->reg_lock); 432 433 return val; 434 } 435 436 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 437 static int mt7996_mmio_wed_reset(struct mtk_wed_device *wed) 438 { 439 struct mt76_dev *mdev = container_of(wed, struct mt76_dev, mmio.wed); 440 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 441 struct mt76_phy *mphy = &dev->mphy; 442 int ret; 443 444 ASSERT_RTNL(); 445 446 if (test_and_set_bit(MT76_STATE_WED_RESET, &mphy->state)) 447 return -EBUSY; 448 449 ret = mt7996_mcu_set_ser(dev, UNI_CMD_SER_TRIGGER, UNI_CMD_SER_SET_RECOVER_FROM_ETH, 450 mphy->band_idx); 451 if (ret) 452 goto out; 453 454 rtnl_unlock(); 455 if (!wait_for_completion_timeout(&mdev->mmio.wed_reset, 20 * HZ)) { 456 dev_err(mdev->dev, "wed reset timeout\n"); 457 ret = -ETIMEDOUT; 458 } 459 rtnl_lock(); 460 out: 461 clear_bit(MT76_STATE_WED_RESET, &mphy->state); 462 463 return ret; 464 } 465 #endif 466 467 int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr, 468 bool hif2, int *irq) 469 { 470 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 471 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 472 struct pci_dev *pci_dev = pdev_ptr; 473 u32 hif1_ofs = 0; 474 475 if (!wed_enable) 476 return 0; 477 478 dev->has_rro = true; 479 480 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 481 482 if (hif2) 483 wed = &dev->mt76.mmio.wed_hif2; 484 485 wed->wlan.pci_dev = pci_dev; 486 wed->wlan.bus_type = MTK_WED_BUS_PCIE; 487 488 wed->wlan.base = devm_ioremap(dev->mt76.dev, 489 pci_resource_start(pci_dev, 0), 490 pci_resource_len(pci_dev, 0)); 491 if (!wed->wlan.base) 492 return -ENOMEM; 493 494 wed->wlan.phy_base = pci_resource_start(pci_dev, 0); 495 496 if (hif2) { 497 wed->wlan.wpdma_int = wed->wlan.phy_base + 498 MT_INT_PCIE1_SOURCE_CSR_EXT; 499 wed->wlan.wpdma_mask = wed->wlan.phy_base + 500 MT_INT_PCIE1_MASK_CSR; 501 wed->wlan.wpdma_tx = wed->wlan.phy_base + hif1_ofs + 502 MT_TXQ_RING_BASE(0) + 503 MT7996_TXQ_BAND2 * MT_RING_SIZE; 504 if (dev->has_rro) { 505 wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs + 506 MT_RXQ_RING_BASE(0) + 507 MT7996_RXQ_TXFREE2 * MT_RING_SIZE; 508 wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_EXT) - 1; 509 } else { 510 wed->wlan.wpdma_txfree = wed->wlan.phy_base + hif1_ofs + 511 MT_RXQ_RING_BASE(0) + 512 MT7996_RXQ_MCU_WA_TRI * MT_RING_SIZE; 513 wed->wlan.txfree_tbit = ffs(MT_INT_RX_DONE_WA_TRI) - 1; 514 } 515 516 wed->wlan.wpdma_rx_glo = wed->wlan.phy_base + hif1_ofs + MT_WFDMA0_GLO_CFG; 517 wed->wlan.wpdma_rx = wed->wlan.phy_base + hif1_ofs + 518 MT_RXQ_RING_BASE(MT7996_RXQ_BAND0) + 519 MT7996_RXQ_BAND0 * MT_RING_SIZE; 520 521 wed->wlan.id = MT7996_DEVICE_ID_2; 522 wed->wlan.tx_tbit[0] = ffs(MT_INT_TX_DONE_BAND2) - 1; 523 } else { 524 wed->wlan.hw_rro = dev->has_rro; /* default on */ 525 wed->wlan.wpdma_int = wed->wlan.phy_base + MT_INT_SOURCE_CSR; 526 wed->wlan.wpdma_mask = wed->wlan.phy_base + MT_INT_MASK_CSR; 527 wed->wlan.wpdma_tx = wed->wlan.phy_base + MT_TXQ_RING_BASE(0) + 528 MT7996_TXQ_BAND0 * MT_RING_SIZE; 529 530 wed->wlan.wpdma_rx_glo = wed->wlan.phy_base + MT_WFDMA0_GLO_CFG; 531 532 wed->wlan.wpdma_rx = wed->wlan.phy_base + 533 MT_RXQ_RING_BASE(MT7996_RXQ_BAND0) + 534 MT7996_RXQ_BAND0 * MT_RING_SIZE; 535 536 wed->wlan.wpdma_rx_rro[0] = wed->wlan.phy_base + 537 MT_RXQ_RING_BASE(MT7996_RXQ_RRO_BAND0) + 538 MT7996_RXQ_RRO_BAND0 * MT_RING_SIZE; 539 wed->wlan.wpdma_rx_rro[1] = wed->wlan.phy_base + hif1_ofs + 540 MT_RXQ_RING_BASE(MT7996_RXQ_RRO_BAND2) + 541 MT7996_RXQ_RRO_BAND2 * MT_RING_SIZE; 542 wed->wlan.wpdma_rx_pg = wed->wlan.phy_base + 543 MT_RXQ_RING_BASE(MT7996_RXQ_MSDU_PG_BAND0) + 544 MT7996_RXQ_MSDU_PG_BAND0 * MT_RING_SIZE; 545 546 wed->wlan.rx_nbuf = 65536; 547 wed->wlan.rx_npkt = dev->hif2 ? 32768 : 24576; 548 wed->wlan.rx_size = SKB_WITH_OVERHEAD(MT_RX_BUF_SIZE); 549 550 wed->wlan.rx_tbit[0] = ffs(MT_INT_RX_DONE_BAND0) - 1; 551 wed->wlan.rx_tbit[1] = ffs(MT_INT_RX_DONE_BAND2) - 1; 552 553 wed->wlan.rro_rx_tbit[0] = ffs(MT_INT_RX_DONE_RRO_BAND0) - 1; 554 wed->wlan.rro_rx_tbit[1] = ffs(MT_INT_RX_DONE_RRO_BAND2) - 1; 555 556 wed->wlan.rx_pg_tbit[0] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND0) - 1; 557 wed->wlan.rx_pg_tbit[1] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND1) - 1; 558 wed->wlan.rx_pg_tbit[2] = ffs(MT_INT_RX_DONE_MSDU_PG_BAND2) - 1; 559 560 wed->wlan.tx_tbit[0] = ffs(MT_INT_TX_DONE_BAND0) - 1; 561 wed->wlan.tx_tbit[1] = ffs(MT_INT_TX_DONE_BAND1) - 1; 562 if (dev->has_rro) { 563 wed->wlan.wpdma_txfree = wed->wlan.phy_base + MT_RXQ_RING_BASE(0) + 564 MT7996_RXQ_TXFREE0 * MT_RING_SIZE; 565 wed->wlan.txfree_tbit = ffs(MT_INT_RX_TXFREE_MAIN) - 1; 566 } else { 567 wed->wlan.txfree_tbit = ffs(MT_INT_RX_DONE_WA_MAIN) - 1; 568 wed->wlan.wpdma_txfree = wed->wlan.phy_base + MT_RXQ_RING_BASE(0) + 569 MT7996_RXQ_MCU_WA_MAIN * MT_RING_SIZE; 570 } 571 dev->mt76.rx_token_size = MT7996_TOKEN_SIZE + wed->wlan.rx_npkt; 572 } 573 574 wed->wlan.nbuf = MT7996_HW_TOKEN_SIZE; 575 wed->wlan.token_start = MT7996_TOKEN_SIZE - wed->wlan.nbuf; 576 577 wed->wlan.amsdu_max_subframes = 8; 578 wed->wlan.amsdu_max_len = 1536; 579 580 wed->wlan.init_buf = mt7996_wed_init_buf; 581 wed->wlan.init_rx_buf = mt76_wed_init_rx_buf; 582 wed->wlan.release_rx_buf = mt76_wed_release_rx_buf; 583 wed->wlan.offload_enable = mt76_wed_offload_enable; 584 wed->wlan.offload_disable = mt76_wed_offload_disable; 585 if (!hif2) { 586 wed->wlan.reset = mt7996_mmio_wed_reset; 587 wed->wlan.reset_complete = mt76_wed_reset_complete; 588 } 589 590 if (mtk_wed_device_attach(wed)) 591 return 0; 592 593 *irq = wed->irq; 594 dev->mt76.dma_dev = wed->dev; 595 596 return 1; 597 #else 598 return 0; 599 #endif 600 } 601 602 static int mt7996_mmio_init(struct mt76_dev *mdev, 603 void __iomem *mem_base, 604 u32 device_id) 605 { 606 struct mt76_bus_ops *bus_ops; 607 struct mt7996_dev *dev; 608 609 dev = container_of(mdev, struct mt7996_dev, mt76); 610 mt76_mmio_init(&dev->mt76, mem_base); 611 spin_lock_init(&dev->reg_lock); 612 613 switch (device_id) { 614 case MT7996_DEVICE_ID: 615 dev->reg.base = mt7996_reg_base; 616 dev->reg.offs_rev = mt7996_offs; 617 dev->reg.map = mt7996_reg_map; 618 dev->reg.map_size = ARRAY_SIZE(mt7996_reg_map); 619 break; 620 case MT7992_DEVICE_ID: 621 dev->reg.base = mt7996_reg_base; 622 dev->reg.offs_rev = mt7992_offs; 623 dev->reg.map = mt7996_reg_map; 624 dev->reg.map_size = ARRAY_SIZE(mt7996_reg_map); 625 break; 626 case MT7990_DEVICE_ID: 627 dev->reg.base = mt7996_reg_base; 628 dev->reg.offs_rev = mt7990_offs; 629 dev->reg.map = mt7990_reg_map; 630 dev->reg.map_size = ARRAY_SIZE(mt7990_reg_map); 631 break; 632 default: 633 return -EINVAL; 634 } 635 636 dev->bus_ops = dev->mt76.bus; 637 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 638 GFP_KERNEL); 639 if (!bus_ops) 640 return -ENOMEM; 641 642 bus_ops->rr = mt7996_rr; 643 bus_ops->wr = mt7996_wr; 644 bus_ops->rmw = mt7996_rmw; 645 dev->mt76.bus = bus_ops; 646 647 mdev->rev = (device_id << 16) | (mt76_rr(dev, MT_HW_REV) & 0xff); 648 649 dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev); 650 651 return 0; 652 } 653 654 void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg, 655 u32 clear, u32 set) 656 { 657 struct mt76_dev *mdev = &dev->mt76; 658 unsigned long flags; 659 660 spin_lock_irqsave(&mdev->mmio.irq_lock, flags); 661 662 mdev->mmio.irqmask &= ~clear; 663 mdev->mmio.irqmask |= set; 664 665 if (write_reg) { 666 if (mtk_wed_device_active(&mdev->mmio.wed)) { 667 mtk_wed_device_irq_set_mask(&mdev->mmio.wed, 668 mdev->mmio.irqmask); 669 if (mtk_wed_device_active(&mdev->mmio.wed_hif2)) { 670 mtk_wed_device_irq_set_mask(&mdev->mmio.wed_hif2, 671 mdev->mmio.irqmask); 672 } 673 } else { 674 mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask); 675 mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask); 676 } 677 } 678 679 spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags); 680 } 681 682 static void mt7996_rx_poll_complete(struct mt76_dev *mdev, 683 enum mt76_rxq_id q) 684 { 685 struct mt7996_dev *dev = container_of(mdev, struct mt7996_dev, mt76); 686 687 mt7996_irq_enable(dev, MT_INT_RX(q)); 688 } 689 690 /* TODO: support 2/4/6/8 MSI-X vectors */ 691 static void mt7996_irq_tasklet(struct tasklet_struct *t) 692 { 693 struct mt7996_dev *dev = from_tasklet(dev, t, mt76.irq_tasklet); 694 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 695 struct mtk_wed_device *wed_hif2 = &dev->mt76.mmio.wed_hif2; 696 u32 i, intr, mask, intr1 = 0; 697 698 if (dev->hif2 && mtk_wed_device_active(wed_hif2)) { 699 mtk_wed_device_irq_set_mask(wed_hif2, 0); 700 intr1 = mtk_wed_device_irq_get(wed_hif2, 701 dev->mt76.mmio.irqmask); 702 if (intr1 & MT_INT_RX_TXFREE_EXT) 703 napi_schedule(&dev->mt76.napi[MT_RXQ_TXFREE_BAND2]); 704 } 705 706 if (mtk_wed_device_active(wed)) { 707 mtk_wed_device_irq_set_mask(wed, 0); 708 intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask); 709 intr |= (intr1 & ~MT_INT_RX_TXFREE_EXT); 710 } else { 711 mt76_wr(dev, MT_INT_MASK_CSR, 0); 712 if (dev->hif2) 713 mt76_wr(dev, MT_INT1_MASK_CSR, 0); 714 715 intr = mt76_rr(dev, MT_INT_SOURCE_CSR); 716 intr &= dev->mt76.mmio.irqmask; 717 mt76_wr(dev, MT_INT_SOURCE_CSR, intr); 718 if (dev->hif2) { 719 intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR); 720 intr1 &= dev->mt76.mmio.irqmask; 721 mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1); 722 intr |= intr1; 723 } 724 } 725 726 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); 727 728 mask = intr & MT_INT_RX_DONE_ALL; 729 if (intr & MT_INT_TX_DONE_MCU) 730 mask |= MT_INT_TX_DONE_MCU; 731 mt7996_irq_disable(dev, mask); 732 733 if (intr & MT_INT_TX_DONE_MCU) 734 napi_schedule(&dev->mt76.tx_napi); 735 736 for (i = 0; i < __MT_RXQ_MAX; i++) { 737 if ((intr & MT_INT_RX(i))) 738 napi_schedule(&dev->mt76.napi[i]); 739 } 740 741 if (intr & MT_INT_MCU_CMD) { 742 u32 val = mt76_rr(dev, MT_MCU_CMD); 743 744 mt76_wr(dev, MT_MCU_CMD, val); 745 if (val & (MT_MCU_CMD_ERROR_MASK | MT_MCU_CMD_WDT_MASK)) { 746 dev->recovery.state = val; 747 mt7996_reset(dev); 748 } 749 } 750 } 751 752 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance) 753 { 754 struct mt7996_dev *dev = dev_instance; 755 756 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) 757 mtk_wed_device_irq_set_mask(&dev->mt76.mmio.wed, 0); 758 else 759 mt76_wr(dev, MT_INT_MASK_CSR, 0); 760 761 if (dev->hif2) { 762 if (mtk_wed_device_active(&dev->mt76.mmio.wed_hif2)) 763 mtk_wed_device_irq_set_mask(&dev->mt76.mmio.wed_hif2, 0); 764 else 765 mt76_wr(dev, MT_INT1_MASK_CSR, 0); 766 } 767 768 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) 769 return IRQ_NONE; 770 771 tasklet_schedule(&dev->mt76.irq_tasklet); 772 773 return IRQ_HANDLED; 774 } 775 776 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev, 777 void __iomem *mem_base, u32 device_id) 778 { 779 static const struct mt76_driver_ops drv_ops = { 780 /* txwi_size = txd size + txp size */ 781 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_fw_txp), 782 .link_data_size = sizeof(struct mt7996_vif_link), 783 .drv_flags = MT_DRV_TXWI_NO_FREE | 784 MT_DRV_AMSDU_OFFLOAD | 785 MT_DRV_HW_MGMT_TXQ, 786 .survey_flags = SURVEY_INFO_TIME_TX | 787 SURVEY_INFO_TIME_RX | 788 SURVEY_INFO_TIME_BSS_RX, 789 .token_size = MT7996_TOKEN_SIZE, 790 .tx_prepare_skb = mt7996_tx_prepare_skb, 791 .tx_complete_skb = mt76_connac_tx_complete_skb, 792 .rx_skb = mt7996_queue_rx_skb, 793 .rx_check = mt7996_rx_check, 794 .rx_poll_complete = mt7996_rx_poll_complete, 795 .update_survey = mt7996_update_channel, 796 .set_channel = mt7996_set_channel, 797 .vif_link_add = mt7996_vif_link_add, 798 .vif_link_remove = mt7996_vif_link_remove, 799 }; 800 struct mt7996_dev *dev; 801 struct mt76_dev *mdev; 802 int ret; 803 804 mdev = mt76_alloc_device(pdev, sizeof(*dev), &mt7996_ops, &drv_ops); 805 if (!mdev) 806 return ERR_PTR(-ENOMEM); 807 808 dev = container_of(mdev, struct mt7996_dev, mt76); 809 810 ret = mt7996_mmio_init(mdev, mem_base, device_id); 811 if (ret) 812 goto error; 813 814 tasklet_setup(&mdev->irq_tasklet, mt7996_irq_tasklet); 815 816 mt76_wr(dev, MT_INT_MASK_CSR, 0); 817 818 return dev; 819 820 error: 821 mt76_free_device(&dev->mt76); 822 823 return ERR_PTR(ret); 824 } 825 826 static int __init mt7996_init(void) 827 { 828 int ret; 829 830 ret = pci_register_driver(&mt7996_hif_driver); 831 if (ret) 832 return ret; 833 834 ret = pci_register_driver(&mt7996_pci_driver); 835 if (ret) 836 pci_unregister_driver(&mt7996_hif_driver); 837 838 return ret; 839 } 840 841 static void __exit mt7996_exit(void) 842 { 843 pci_unregister_driver(&mt7996_pci_driver); 844 pci_unregister_driver(&mt7996_hif_driver); 845 } 846 847 module_init(mt7996_init); 848 module_exit(mt7996_exit); 849 MODULE_DESCRIPTION("MediaTek MT7996 MMIO helpers"); 850 MODULE_LICENSE("Dual BSD/GPL"); 851