1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2022 MediaTek Inc. 4 */ 5 6 #include <linux/etherdevice.h> 7 #include <linux/of.h> 8 #include <linux/hwmon.h> 9 #include <linux/hwmon-sysfs.h> 10 #include <linux/thermal.h> 11 #include "mt7996.h" 12 #include "mac.h" 13 #include "mcu.h" 14 #include "coredump.h" 15 #include "eeprom.h" 16 #if defined(__FreeBSD__) 17 #include <linux/delay.h> 18 #endif 19 20 static const struct ieee80211_iface_limit if_limits_global = { 21 .max = MT7996_MAX_INTERFACES * MT7996_MAX_RADIOS, 22 .types = BIT(NL80211_IFTYPE_STATION) 23 | BIT(NL80211_IFTYPE_ADHOC) 24 | BIT(NL80211_IFTYPE_AP) 25 #ifdef CONFIG_MAC80211_MESH 26 | BIT(NL80211_IFTYPE_MESH_POINT) 27 #endif 28 }; 29 30 static const struct ieee80211_iface_combination if_comb_global = { 31 .limits = &if_limits_global, 32 .n_limits = 1, 33 .max_interfaces = MT7996_MAX_INTERFACES * MT7996_MAX_RADIOS, 34 .num_different_channels = MT7996_MAX_RADIOS, 35 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 36 BIT(NL80211_CHAN_WIDTH_20) | 37 BIT(NL80211_CHAN_WIDTH_40) | 38 BIT(NL80211_CHAN_WIDTH_80) | 39 BIT(NL80211_CHAN_WIDTH_160), 40 }; 41 42 static const struct ieee80211_iface_limit if_limits[] = { 43 { 44 .max = 16, 45 .types = BIT(NL80211_IFTYPE_AP) 46 #ifdef CONFIG_MAC80211_MESH 47 | BIT(NL80211_IFTYPE_MESH_POINT) 48 #endif 49 }, { 50 .max = MT7996_MAX_INTERFACES, 51 .types = BIT(NL80211_IFTYPE_STATION) 52 } 53 }; 54 55 static const struct ieee80211_iface_combination if_comb = { 56 .limits = if_limits, 57 .n_limits = ARRAY_SIZE(if_limits), 58 .max_interfaces = MT7996_MAX_INTERFACES, 59 .num_different_channels = 1, 60 .beacon_int_infra_match = true, 61 .radar_detect_widths = BIT(NL80211_CHAN_WIDTH_20_NOHT) | 62 BIT(NL80211_CHAN_WIDTH_20) | 63 BIT(NL80211_CHAN_WIDTH_40) | 64 BIT(NL80211_CHAN_WIDTH_80) | 65 BIT(NL80211_CHAN_WIDTH_160), 66 .beacon_int_min_gcd = 100, 67 }; 68 69 #if defined(CONFIG_HWMON) 70 static ssize_t mt7996_thermal_temp_show(struct device *dev, 71 struct device_attribute *attr, 72 char *buf) 73 { 74 struct mt7996_phy *phy = dev_get_drvdata(dev); 75 int i = to_sensor_dev_attr(attr)->index; 76 int temperature; 77 78 switch (i) { 79 case 0: 80 temperature = mt7996_mcu_get_temperature(phy); 81 if (temperature < 0) 82 return temperature; 83 /* display in millidegree celcius */ 84 return sprintf(buf, "%u\n", temperature * 1000); 85 case 1: 86 case 2: 87 return sprintf(buf, "%u\n", 88 phy->throttle_temp[i - 1] * 1000); 89 case 3: 90 return sprintf(buf, "%hhu\n", phy->throttle_state); 91 default: 92 return -EINVAL; 93 } 94 } 95 96 static ssize_t mt7996_thermal_temp_store(struct device *dev, 97 struct device_attribute *attr, 98 const char *buf, size_t count) 99 { 100 struct mt7996_phy *phy = dev_get_drvdata(dev); 101 int ret, i = to_sensor_dev_attr(attr)->index; 102 long val; 103 104 ret = kstrtol(buf, 10, &val); 105 if (ret < 0) 106 return ret; 107 108 mutex_lock(&phy->dev->mt76.mutex); 109 val = DIV_ROUND_CLOSEST(clamp_val(val, 40 * 1000, 130 * 1000), 1000); 110 111 /* add a safety margin ~10 */ 112 if ((i - 1 == MT7996_CRIT_TEMP_IDX && 113 val > phy->throttle_temp[MT7996_MAX_TEMP_IDX] - 10) || 114 (i - 1 == MT7996_MAX_TEMP_IDX && 115 val - 10 < phy->throttle_temp[MT7996_CRIT_TEMP_IDX])) { 116 dev_err(phy->dev->mt76.dev, 117 "temp1_max shall be 10 degrees higher than temp1_crit."); 118 mutex_unlock(&phy->dev->mt76.mutex); 119 return -EINVAL; 120 } 121 122 phy->throttle_temp[i - 1] = val; 123 mutex_unlock(&phy->dev->mt76.mutex); 124 125 ret = mt7996_mcu_set_thermal_protect(phy, true); 126 if (ret) 127 return ret; 128 129 return count; 130 } 131 132 static SENSOR_DEVICE_ATTR_RO(temp1_input, mt7996_thermal_temp, 0); 133 static SENSOR_DEVICE_ATTR_RW(temp1_crit, mt7996_thermal_temp, 1); 134 static SENSOR_DEVICE_ATTR_RW(temp1_max, mt7996_thermal_temp, 2); 135 static SENSOR_DEVICE_ATTR_RO(throttle1, mt7996_thermal_temp, 3); 136 137 static struct attribute *mt7996_hwmon_attrs[] = { 138 &sensor_dev_attr_temp1_input.dev_attr.attr, 139 &sensor_dev_attr_temp1_crit.dev_attr.attr, 140 &sensor_dev_attr_temp1_max.dev_attr.attr, 141 &sensor_dev_attr_throttle1.dev_attr.attr, 142 NULL, 143 }; 144 ATTRIBUTE_GROUPS(mt7996_hwmon); 145 146 static int 147 mt7996_thermal_get_max_throttle_state(struct thermal_cooling_device *cdev, 148 unsigned long *state) 149 { 150 *state = MT7996_CDEV_THROTTLE_MAX; 151 152 return 0; 153 } 154 155 static int 156 mt7996_thermal_get_cur_throttle_state(struct thermal_cooling_device *cdev, 157 unsigned long *state) 158 { 159 struct mt7996_phy *phy = cdev->devdata; 160 161 *state = phy->cdev_state; 162 163 return 0; 164 } 165 166 static int 167 mt7996_thermal_set_cur_throttle_state(struct thermal_cooling_device *cdev, 168 unsigned long state) 169 { 170 struct mt7996_phy *phy = cdev->devdata; 171 u8 throttling = MT7996_THERMAL_THROTTLE_MAX - state; 172 int ret; 173 174 if (state > MT7996_CDEV_THROTTLE_MAX) { 175 dev_err(phy->dev->mt76.dev, 176 "please specify a valid throttling state\n"); 177 return -EINVAL; 178 } 179 180 if (state == phy->cdev_state) 181 return 0; 182 183 /* cooling_device convention: 0 = no cooling, more = more cooling 184 * mcu convention: 1 = max cooling, more = less cooling 185 */ 186 ret = mt7996_mcu_set_thermal_throttling(phy, throttling); 187 if (ret) 188 return ret; 189 190 phy->cdev_state = state; 191 192 return 0; 193 } 194 195 static const struct thermal_cooling_device_ops mt7996_thermal_ops = { 196 .get_max_state = mt7996_thermal_get_max_throttle_state, 197 .get_cur_state = mt7996_thermal_get_cur_throttle_state, 198 .set_cur_state = mt7996_thermal_set_cur_throttle_state, 199 }; 200 201 static void mt7996_unregister_thermal(struct mt7996_phy *phy) 202 { 203 struct wiphy *wiphy = phy->mt76->hw->wiphy; 204 char name[sizeof("cooling_deviceXXX")]; 205 206 if (!phy->cdev) 207 return; 208 209 snprintf(name, sizeof(name), "cooling_device%d", phy->mt76->band_idx); 210 sysfs_remove_link(&wiphy->dev.kobj, name); 211 thermal_cooling_device_unregister(phy->cdev); 212 } 213 214 static int mt7996_thermal_init(struct mt7996_phy *phy) 215 { 216 struct wiphy *wiphy = phy->mt76->hw->wiphy; 217 char cname[sizeof("cooling_deviceXXX")]; 218 struct thermal_cooling_device *cdev; 219 struct device *hwmon; 220 const char *name; 221 222 name = devm_kasprintf(&wiphy->dev, GFP_KERNEL, "mt7996_%s.%d", 223 wiphy_name(wiphy), phy->mt76->band_idx); 224 if (!name) 225 return -ENOMEM; 226 227 snprintf(cname, sizeof(cname), "cooling_device%d", phy->mt76->band_idx); 228 229 cdev = thermal_cooling_device_register(name, phy, &mt7996_thermal_ops); 230 if (!IS_ERR(cdev)) { 231 if (sysfs_create_link(&wiphy->dev.kobj, &cdev->device.kobj, 232 cname) < 0) 233 thermal_cooling_device_unregister(cdev); 234 else 235 phy->cdev = cdev; 236 } 237 238 /* initialize critical/maximum high temperature */ 239 phy->throttle_temp[MT7996_CRIT_TEMP_IDX] = MT7996_CRIT_TEMP; 240 phy->throttle_temp[MT7996_MAX_TEMP_IDX] = MT7996_MAX_TEMP; 241 242 if (!IS_REACHABLE(CONFIG_HWMON)) 243 return 0; 244 245 hwmon = devm_hwmon_device_register_with_groups(&wiphy->dev, name, phy, 246 mt7996_hwmon_groups); 247 248 if (IS_ERR(hwmon)) 249 return PTR_ERR(hwmon); 250 251 return 0; 252 } 253 #endif 254 255 static void mt7996_led_set_config(struct led_classdev *led_cdev, 256 u8 delay_on, u8 delay_off) 257 { 258 struct mt7996_dev *dev; 259 struct mt76_phy *mphy; 260 u32 val; 261 262 mphy = container_of(led_cdev, struct mt76_phy, leds.cdev); 263 dev = container_of(mphy->dev, struct mt7996_dev, mt76); 264 265 /* select TX blink mode, 2: only data frames */ 266 mt76_rmw_field(dev, MT_TMAC_TCR0(mphy->band_idx), MT_TMAC_TCR0_TX_BLINK, 2); 267 268 /* enable LED */ 269 mt76_wr(dev, MT_LED_EN(mphy->band_idx), 1); 270 271 /* set LED Tx blink on/off time */ 272 val = FIELD_PREP(MT_LED_TX_BLINK_ON_MASK, delay_on) | 273 FIELD_PREP(MT_LED_TX_BLINK_OFF_MASK, delay_off); 274 mt76_wr(dev, MT_LED_TX_BLINK(mphy->band_idx), val); 275 276 /* turn LED off */ 277 if (delay_off == 0xff && delay_on == 0x0) { 278 val = MT_LED_CTRL_POLARITY | MT_LED_CTRL_KICK; 279 } else { 280 /* control LED */ 281 val = MT_LED_CTRL_BLINK_MODE | MT_LED_CTRL_KICK; 282 if (mphy->band_idx == MT_BAND1) 283 val |= MT_LED_CTRL_BLINK_BAND_SEL; 284 } 285 286 if (mphy->leds.al) 287 val |= MT_LED_CTRL_POLARITY; 288 289 mt76_wr(dev, MT_LED_CTRL(mphy->band_idx), val); 290 mt76_clear(dev, MT_LED_CTRL(mphy->band_idx), MT_LED_CTRL_KICK); 291 } 292 293 static int mt7996_led_set_blink(struct led_classdev *led_cdev, 294 unsigned long *delay_on, 295 unsigned long *delay_off) 296 { 297 u16 delta_on = 0, delta_off = 0; 298 299 #define HW_TICK 10 300 #define TO_HW_TICK(_t) (((_t) > HW_TICK) ? ((_t) / HW_TICK) : HW_TICK) 301 302 if (*delay_on) 303 delta_on = TO_HW_TICK(*delay_on); 304 if (*delay_off) 305 delta_off = TO_HW_TICK(*delay_off); 306 307 mt7996_led_set_config(led_cdev, delta_on, delta_off); 308 309 return 0; 310 } 311 312 static void mt7996_led_set_brightness(struct led_classdev *led_cdev, 313 enum led_brightness brightness) 314 { 315 if (!brightness) 316 mt7996_led_set_config(led_cdev, 0, 0xff); 317 else 318 mt7996_led_set_config(led_cdev, 0xff, 0); 319 } 320 321 static void __mt7996_init_txpower(struct mt7996_phy *phy, 322 struct ieee80211_supported_band *sband) 323 { 324 struct mt7996_dev *dev = phy->dev; 325 int i, n_chains = hweight16(phy->mt76->chainmask); 326 int path_delta = mt76_tx_power_path_delta(n_chains); 327 int pwr_delta = mt7996_eeprom_get_power_delta(dev, sband->band); 328 struct mt76_power_limits limits; 329 330 for (i = 0; i < sband->n_channels; i++) { 331 struct ieee80211_channel *chan = &sband->channels[i]; 332 int target_power = mt7996_eeprom_get_target_power(dev, chan); 333 334 target_power += pwr_delta; 335 target_power = mt76_get_rate_power_limits(phy->mt76, chan, 336 &limits, 337 target_power); 338 target_power += path_delta; 339 target_power = DIV_ROUND_UP(target_power, 2); 340 chan->max_power = min_t(int, chan->max_reg_power, 341 target_power); 342 chan->orig_mpwr = target_power; 343 } 344 } 345 346 void mt7996_init_txpower(struct mt7996_phy *phy) 347 { 348 if (!phy) 349 return; 350 351 if (phy->mt76->cap.has_2ghz) 352 __mt7996_init_txpower(phy, &phy->mt76->sband_2g.sband); 353 if (phy->mt76->cap.has_5ghz) 354 __mt7996_init_txpower(phy, &phy->mt76->sband_5g.sband); 355 if (phy->mt76->cap.has_6ghz) 356 __mt7996_init_txpower(phy, &phy->mt76->sband_6g.sband); 357 } 358 359 static void 360 mt7996_regd_notifier(struct wiphy *wiphy, 361 struct regulatory_request *request) 362 { 363 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 364 struct mt7996_dev *dev = mt7996_hw_dev(hw); 365 struct mt7996_phy *phy; 366 367 memcpy(dev->mt76.alpha2, request->alpha2, sizeof(dev->mt76.alpha2)); 368 dev->mt76.region = request->dfs_region; 369 370 mt7996_for_each_phy(dev, phy) { 371 if (dev->mt76.region == NL80211_DFS_UNSET) 372 mt7996_mcu_rdd_background_enable(phy, NULL); 373 374 mt7996_init_txpower(phy); 375 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 376 mt7996_dfs_init_radar_detector(phy); 377 } 378 } 379 380 static void 381 mt7996_init_wiphy_band(struct ieee80211_hw *hw, struct mt7996_phy *phy) 382 { 383 struct mt7996_dev *dev = phy->dev; 384 struct wiphy *wiphy = hw->wiphy; 385 int n_radios = hw->wiphy->n_radio; 386 struct wiphy_radio_freq_range *freq = &dev->radio_freqs[n_radios]; 387 struct wiphy_radio *radio = &dev->radios[n_radios]; 388 389 phy->slottime = 9; 390 phy->beacon_rate = -1; 391 392 if (phy->mt76->cap.has_2ghz) { 393 phy->mt76->sband_2g.sband.ht_cap.cap |= 394 IEEE80211_HT_CAP_LDPC_CODING | 395 IEEE80211_HT_CAP_MAX_AMSDU; 396 phy->mt76->sband_2g.sband.ht_cap.ampdu_density = 397 IEEE80211_HT_MPDU_DENSITY_2; 398 freq->start_freq = 2400000; 399 freq->end_freq = 2500000; 400 } else if (phy->mt76->cap.has_5ghz) { 401 phy->mt76->sband_5g.sband.ht_cap.cap |= 402 IEEE80211_HT_CAP_LDPC_CODING | 403 IEEE80211_HT_CAP_MAX_AMSDU; 404 405 phy->mt76->sband_5g.sband.vht_cap.cap |= 406 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 407 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 408 IEEE80211_VHT_CAP_SHORT_GI_160 | 409 IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ; 410 phy->mt76->sband_5g.sband.ht_cap.ampdu_density = 411 IEEE80211_HT_MPDU_DENSITY_1; 412 413 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 414 freq->start_freq = 5000000; 415 freq->end_freq = 5900000; 416 } else if (phy->mt76->cap.has_6ghz) { 417 freq->start_freq = 5900000; 418 freq->end_freq = 7200000; 419 } else { 420 return; 421 } 422 423 dev->radio_phy[n_radios] = phy; 424 radio->freq_range = freq; 425 radio->n_freq_range = 1; 426 radio->iface_combinations = &if_comb; 427 radio->n_iface_combinations = 1; 428 hw->wiphy->n_radio++; 429 430 wiphy->available_antennas_rx |= phy->mt76->chainmask; 431 wiphy->available_antennas_tx |= phy->mt76->chainmask; 432 433 mt76_set_stream_caps(phy->mt76, true); 434 mt7996_set_stream_vht_txbf_caps(phy); 435 mt7996_set_stream_he_eht_caps(phy); 436 mt7996_init_txpower(phy); 437 } 438 439 static void 440 mt7996_init_wiphy(struct ieee80211_hw *hw, struct mtk_wed_device *wed) 441 { 442 struct mt7996_dev *dev = mt7996_hw_dev(hw); 443 struct mt76_dev *mdev = &dev->mt76; 444 struct wiphy *wiphy = hw->wiphy; 445 u16 max_subframes = dev->has_eht ? IEEE80211_MAX_AMPDU_BUF_EHT : 446 IEEE80211_MAX_AMPDU_BUF_HE; 447 448 hw->queues = 4; 449 hw->max_rx_aggregation_subframes = max_subframes; 450 hw->max_tx_aggregation_subframes = max_subframes; 451 if (is_mt7990(mdev) && dev->has_eht) 452 hw->max_tx_aggregation_subframes = 512; 453 454 hw->netdev_features = NETIF_F_RXCSUM; 455 if (mtk_wed_device_active(wed)) 456 hw->netdev_features |= NETIF_F_HW_TC; 457 458 hw->radiotap_timestamp.units_pos = 459 IEEE80211_RADIOTAP_TIMESTAMP_UNIT_US; 460 461 hw->sta_data_size = sizeof(struct mt7996_sta); 462 hw->vif_data_size = sizeof(struct mt7996_vif); 463 hw->chanctx_data_size = sizeof(struct mt76_chanctx); 464 465 wiphy->iface_combinations = &if_comb_global; 466 wiphy->n_iface_combinations = 1; 467 468 wiphy->radio = dev->radios; 469 470 wiphy->reg_notifier = mt7996_regd_notifier; 471 wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH; 472 wiphy->mbssid_max_interfaces = 16; 473 474 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BSS_COLOR); 475 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_VHT_IBSS); 476 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_LEGACY); 477 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HT); 478 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_VHT); 479 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_BEACON_RATE_HE); 480 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_UNSOL_BCAST_PROBE_RESP); 481 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_FILS_DISCOVERY); 482 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_ACK_SIGNAL_SUPPORT); 483 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 484 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_MU_MIMO_AIR_SNIFFER); 485 486 if (mt7996_eeprom_has_background_radar(dev) && 487 #if defined(CONFIG_OF) 488 (!mdev->dev->of_node || 489 !of_property_read_bool(mdev->dev->of_node, 490 "mediatek,disable-radar-background"))) 491 #else 492 1) 493 #endif 494 wiphy_ext_feature_set(wiphy, 495 NL80211_EXT_FEATURE_RADAR_BACKGROUND); 496 497 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 498 ieee80211_hw_set(hw, SUPPORTS_TX_ENCAP_OFFLOAD); 499 ieee80211_hw_set(hw, SUPPORTS_RX_DECAP_OFFLOAD); 500 ieee80211_hw_set(hw, NO_VIRTUAL_MONITOR); 501 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 502 503 hw->max_tx_fragments = 4; 504 505 /* init led callbacks */ 506 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 507 dev->mphy.leds.cdev.brightness_set = mt7996_led_set_brightness; 508 dev->mphy.leds.cdev.blink_set = mt7996_led_set_blink; 509 } 510 511 wiphy->max_scan_ssids = 4; 512 wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; 513 514 mt7996_init_wiphy_band(hw, &dev->phy); 515 } 516 517 static void 518 mt7996_mac_init_band(struct mt7996_dev *dev, u8 band) 519 { 520 u32 mask, set; 521 522 /* clear estimated value of EIFS for Rx duration & OBSS time */ 523 mt76_wr(dev, MT_WF_RMAC_RSVD0(band), MT_WF_RMAC_RSVD0_EIFS_CLR); 524 525 /* clear backoff time for Rx duration */ 526 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME1(band), 527 MT_WF_RMAC_MIB_NONQOSD_BACKOFF); 528 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME3(band), 529 MT_WF_RMAC_MIB_QOS01_BACKOFF); 530 mt76_clear(dev, MT_WF_RMAC_MIB_AIRTIME4(band), 531 MT_WF_RMAC_MIB_QOS23_BACKOFF); 532 533 /* clear backoff time for Tx duration */ 534 mt76_clear(dev, MT_WTBLOFF_ACR(band), 535 MT_WTBLOFF_ADM_BACKOFFTIME); 536 537 /* clear backoff time and set software compensation for OBSS time */ 538 mask = MT_WF_RMAC_MIB_OBSS_BACKOFF | MT_WF_RMAC_MIB_ED_OFFSET; 539 set = FIELD_PREP(MT_WF_RMAC_MIB_OBSS_BACKOFF, 0) | 540 FIELD_PREP(MT_WF_RMAC_MIB_ED_OFFSET, 4); 541 mt76_rmw(dev, MT_WF_RMAC_MIB_AIRTIME0(band), mask, set); 542 543 /* filter out non-resp frames and get instanstaeous signal reporting */ 544 mask = MT_WTBLOFF_RSCR_RCPI_MODE | MT_WTBLOFF_RSCR_RCPI_PARAM; 545 set = FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_MODE, 0) | 546 FIELD_PREP(MT_WTBLOFF_RSCR_RCPI_PARAM, 0x3); 547 mt76_rmw(dev, MT_WTBLOFF_RSCR(band), mask, set); 548 549 /* MT_TXD5_TX_STATUS_HOST (MPDU format) has higher priority than 550 * MT_AGG_ACR_PPDU_TXS2H (PPDU format) even though ACR bit is set. 551 */ 552 mt76_set(dev, MT_AGG_ACR4(band), MT_AGG_ACR_PPDU_TXS2H); 553 } 554 555 static void mt7996_mac_init_basic_rates(struct mt7996_dev *dev) 556 { 557 int i; 558 559 for (i = 0; i < ARRAY_SIZE(mt76_rates); i++) { 560 u16 rate = mt76_rates[i].hw_value; 561 /* odd index for driver, even index for firmware */ 562 u16 idx = MT7996_BASIC_RATES_TBL + 2 * i; 563 564 rate = FIELD_PREP(MT_TX_RATE_MODE, rate >> 8) | 565 FIELD_PREP(MT_TX_RATE_IDX, rate & GENMASK(7, 0)); 566 mt7996_mcu_set_fixed_rate_table(&dev->phy, idx, rate, false); 567 } 568 } 569 570 void mt7996_mac_init(struct mt7996_dev *dev) 571 { 572 #define HIF_TXD_V2_1 0x21 573 int i; 574 575 mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); 576 577 for (i = 0; i < mt7996_wtbl_size(dev); i++) 578 mt7996_mac_wtbl_update(dev, i, 579 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 580 581 if (IS_ENABLED(CONFIG_MT76_LEDS)) { 582 i = dev->mphy.leds.pin ? MT_LED_GPIO_MUX3 : MT_LED_GPIO_MUX2; 583 mt76_rmw_field(dev, i, MT_LED_GPIO_SEL_MASK, 4); 584 } 585 586 /* rro module init */ 587 if (is_mt7996(&dev->mt76)) 588 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 2); 589 else 590 mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 591 dev->hif2 ? 7 : 0); 592 593 if (dev->has_rro) { 594 u16 timeout; 595 596 timeout = mt76_rr(dev, MT_HW_REV) == MT_HW_REV1 ? 512 : 128; 597 mt7996_mcu_set_rro(dev, UNI_RRO_SET_FLUSH_TIMEOUT, timeout); 598 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 1); 599 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 0); 600 } else { 601 mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 3); 602 mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 1); 603 } 604 605 mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), 606 MCU_WA_PARAM_HW_PATH_HIF_VER, 607 HIF_TXD_V2_1, 0); 608 609 for (i = MT_BAND0; i <= MT_BAND2; i++) 610 mt7996_mac_init_band(dev, i); 611 612 mt7996_mac_init_basic_rates(dev); 613 } 614 615 int mt7996_txbf_init(struct mt7996_dev *dev) 616 { 617 int ret; 618 619 if (mt7996_band_valid(dev, MT_BAND1) || 620 mt7996_band_valid(dev, MT_BAND2)) { 621 ret = mt7996_mcu_set_txbf(dev, BF_MOD_EN_CTRL); 622 if (ret) 623 return ret; 624 } 625 626 /* trigger sounding packets */ 627 ret = mt7996_mcu_set_txbf(dev, BF_SOUNDING_ON); 628 if (ret) 629 return ret; 630 631 /* enable eBF */ 632 return mt7996_mcu_set_txbf(dev, BF_HW_EN_UPDATE); 633 } 634 635 static int mt7996_register_phy(struct mt7996_dev *dev, enum mt76_band_id band) 636 { 637 struct mt7996_phy *phy; 638 struct mt76_phy *mphy; 639 u32 mac_ofs, hif1_ofs = 0; 640 int ret; 641 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 642 643 if (!mt7996_band_valid(dev, band)) 644 return 0; 645 646 if (is_mt7996(&dev->mt76) && band == MT_BAND2 && dev->hif2) { 647 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); 648 wed = &dev->mt76.mmio.wed_hif2; 649 } 650 651 mphy = mt76_alloc_radio_phy(&dev->mt76, sizeof(*phy), band); 652 if (!mphy) 653 return -ENOMEM; 654 655 phy = mphy->priv; 656 phy->dev = dev; 657 phy->mt76 = mphy; 658 mphy->dev->phys[band] = mphy; 659 660 INIT_DELAYED_WORK(&mphy->mac_work, mt7996_mac_work); 661 662 ret = mt7996_eeprom_parse_hw_cap(dev, phy); 663 if (ret) 664 goto error; 665 666 mac_ofs = band == MT_BAND2 ? MT_EE_MAC_ADDR3 : MT_EE_MAC_ADDR2; 667 #if defined(__linux__) 668 memcpy(mphy->macaddr, dev->mt76.eeprom.data + mac_ofs, ETH_ALEN); 669 #elif defined(__FreeBSD__) 670 memcpy(mphy->macaddr, (u8 *)dev->mt76.eeprom.data + mac_ofs, ETH_ALEN); 671 #endif 672 /* Make the extra PHY MAC address local without overlapping with 673 * the usual MAC address allocation scheme on multiple virtual interfaces 674 */ 675 if (!is_valid_ether_addr(mphy->macaddr)) { 676 #if defined(__linux__) 677 memcpy(mphy->macaddr, dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 678 #elif defined(__FreeBSD__) 679 memcpy(mphy->macaddr, (u8 *)dev->mt76.eeprom.data + MT_EE_MAC_ADDR, 680 #endif 681 ETH_ALEN); 682 mphy->macaddr[0] |= 2; 683 mphy->macaddr[0] ^= BIT(7); 684 if (band == MT_BAND2) 685 mphy->macaddr[0] ^= BIT(6); 686 } 687 mt76_eeprom_override(mphy); 688 689 /* init wiphy according to mphy and phy */ 690 mt7996_init_wiphy_band(mphy->hw, phy); 691 ret = mt7996_init_tx_queues(mphy->priv, 692 MT_TXQ_ID(band), 693 MT7996_TX_RING_SIZE, 694 MT_TXQ_RING_BASE(band) + hif1_ofs, 695 wed); 696 if (ret) 697 goto error; 698 699 ret = mt76_register_phy(mphy, true, mt76_rates, 700 ARRAY_SIZE(mt76_rates)); 701 if (ret) 702 goto error; 703 704 if (wed == &dev->mt76.mmio.wed_hif2 && mtk_wed_device_active(wed)) { 705 u32 irq_mask = dev->mt76.mmio.irqmask | MT_INT_TX_DONE_BAND2; 706 707 mt76_wr(dev, MT_INT1_MASK_CSR, irq_mask); 708 mtk_wed_device_start(&dev->mt76.mmio.wed_hif2, irq_mask); 709 } 710 711 return 0; 712 713 error: 714 mphy->dev->phys[band] = NULL; 715 return ret; 716 } 717 718 static void 719 mt7996_unregister_phy(struct mt7996_phy *phy) 720 { 721 #if defined(CONFIG_HWMON) 722 if (phy) 723 mt7996_unregister_thermal(phy); 724 #endif 725 } 726 727 static void mt7996_init_work(struct work_struct *work) 728 { 729 struct mt7996_dev *dev = container_of(work, struct mt7996_dev, 730 init_work); 731 732 mt7996_mcu_set_eeprom(dev); 733 mt7996_mac_init(dev); 734 mt7996_txbf_init(dev); 735 } 736 737 void mt7996_wfsys_reset(struct mt7996_dev *dev) 738 { 739 mt76_set(dev, MT_WF_SUBSYS_RST, 0x1); 740 msleep(20); 741 742 mt76_clear(dev, MT_WF_SUBSYS_RST, 0x1); 743 msleep(20); 744 } 745 746 static int mt7996_wed_rro_init(struct mt7996_dev *dev) 747 { 748 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 749 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; 750 u32 reg = MT_RRO_ADDR_ELEM_SEG_ADDR0; 751 struct mt7996_wed_rro_addr *addr; 752 void *ptr; 753 int i; 754 755 if (!dev->has_rro) 756 return 0; 757 758 if (!mtk_wed_device_active(wed)) 759 return 0; 760 761 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) { 762 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 763 MT7996_RRO_BA_BITMAP_CR_SIZE, 764 &dev->wed_rro.ba_bitmap[i].phy_addr, 765 GFP_KERNEL); 766 if (!ptr) 767 return -ENOMEM; 768 769 dev->wed_rro.ba_bitmap[i].ptr = ptr; 770 } 771 772 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 773 int j; 774 775 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 776 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr), 777 &dev->wed_rro.addr_elem[i].phy_addr, 778 GFP_KERNEL); 779 if (!ptr) 780 return -ENOMEM; 781 782 dev->wed_rro.addr_elem[i].ptr = ptr; 783 memset(dev->wed_rro.addr_elem[i].ptr, 0, 784 MT7996_RRO_WINDOW_MAX_SIZE * sizeof(*addr)); 785 786 addr = dev->wed_rro.addr_elem[i].ptr; 787 for (j = 0; j < MT7996_RRO_WINDOW_MAX_SIZE; j++) { 788 addr->signature = 0xff; 789 addr++; 790 } 791 792 wed->wlan.ind_cmd.addr_elem_phys[i] = 793 dev->wed_rro.addr_elem[i].phy_addr; 794 } 795 796 ptr = dmam_alloc_coherent(dev->mt76.dma_dev, 797 MT7996_RRO_WINDOW_MAX_LEN * sizeof(*addr), 798 &dev->wed_rro.session.phy_addr, 799 GFP_KERNEL); 800 if (!ptr) 801 return -ENOMEM; 802 803 dev->wed_rro.session.ptr = ptr; 804 addr = dev->wed_rro.session.ptr; 805 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) { 806 addr->signature = 0xff; 807 addr++; 808 } 809 810 /* rro hw init */ 811 /* TODO: remove line after WM has set */ 812 mt76_clear(dev, WF_RRO_AXI_MST_CFG, WF_RRO_AXI_MST_CFG_DIDX_OK); 813 814 /* setup BA bitmap cache address */ 815 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE0, 816 dev->wed_rro.ba_bitmap[0].phy_addr); 817 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE1, 0); 818 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT0, 819 dev->wed_rro.ba_bitmap[1].phy_addr); 820 mt76_wr(dev, MT_RRO_BA_BITMAP_BASE_EXT1, 0); 821 822 /* setup Address element address */ 823 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 824 mt76_wr(dev, reg, dev->wed_rro.addr_elem[i].phy_addr >> 4); 825 reg += 4; 826 } 827 828 /* setup Address element address - separate address segment mode */ 829 mt76_wr(dev, MT_RRO_ADDR_ARRAY_BASE1, 830 MT_RRO_ADDR_ARRAY_ELEM_ADDR_SEG_MODE); 831 832 wed->wlan.ind_cmd.win_size = ffs(MT7996_RRO_WINDOW_MAX_LEN) - 6; 833 wed->wlan.ind_cmd.particular_sid = MT7996_RRO_MAX_SESSION; 834 wed->wlan.ind_cmd.particular_se_phys = dev->wed_rro.session.phy_addr; 835 wed->wlan.ind_cmd.se_group_nums = MT7996_RRO_ADDR_ELEM_LEN; 836 wed->wlan.ind_cmd.ack_sn_addr = MT_RRO_ACK_SN_CTRL; 837 838 mt76_wr(dev, MT_RRO_IND_CMD_SIGNATURE_BASE0, 0x15010e00); 839 mt76_set(dev, MT_RRO_IND_CMD_SIGNATURE_BASE1, 840 MT_RRO_IND_CMD_SIGNATURE_BASE1_EN); 841 842 /* particular session configure */ 843 /* use max session idx + 1 as particular session id */ 844 mt76_wr(dev, MT_RRO_PARTICULAR_CFG0, dev->wed_rro.session.phy_addr); 845 mt76_wr(dev, MT_RRO_PARTICULAR_CFG1, 846 MT_RRO_PARTICULAR_CONFG_EN | 847 FIELD_PREP(MT_RRO_PARTICULAR_SID, MT7996_RRO_MAX_SESSION)); 848 849 /* interrupt enable */ 850 mt76_wr(dev, MT_RRO_HOST_INT_ENA, 851 MT_RRO_HOST_INT_ENA_HOST_RRO_DONE_ENA); 852 853 /* rro ind cmd queue init */ 854 return mt7996_dma_rro_init(dev); 855 #else 856 return 0; 857 #endif 858 } 859 860 static void mt7996_wed_rro_free(struct mt7996_dev *dev) 861 { 862 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 863 int i; 864 865 if (!dev->has_rro) 866 return; 867 868 if (!mtk_wed_device_active(&dev->mt76.mmio.wed)) 869 return; 870 871 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.ba_bitmap); i++) { 872 if (!dev->wed_rro.ba_bitmap[i].ptr) 873 continue; 874 875 dmam_free_coherent(dev->mt76.dma_dev, 876 MT7996_RRO_BA_BITMAP_CR_SIZE, 877 dev->wed_rro.ba_bitmap[i].ptr, 878 dev->wed_rro.ba_bitmap[i].phy_addr); 879 } 880 881 for (i = 0; i < ARRAY_SIZE(dev->wed_rro.addr_elem); i++) { 882 if (!dev->wed_rro.addr_elem[i].ptr) 883 continue; 884 885 dmam_free_coherent(dev->mt76.dma_dev, 886 MT7996_RRO_WINDOW_MAX_SIZE * 887 sizeof(struct mt7996_wed_rro_addr), 888 dev->wed_rro.addr_elem[i].ptr, 889 dev->wed_rro.addr_elem[i].phy_addr); 890 } 891 892 if (!dev->wed_rro.session.ptr) 893 return; 894 895 dmam_free_coherent(dev->mt76.dma_dev, 896 MT7996_RRO_WINDOW_MAX_LEN * 897 sizeof(struct mt7996_wed_rro_addr), 898 dev->wed_rro.session.ptr, 899 dev->wed_rro.session.phy_addr); 900 #endif 901 } 902 903 static void mt7996_wed_rro_work(struct work_struct *work) 904 { 905 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 906 struct mt7996_dev *dev; 907 LIST_HEAD(list); 908 909 dev = (struct mt7996_dev *)container_of(work, struct mt7996_dev, 910 wed_rro.work); 911 912 spin_lock_bh(&dev->wed_rro.lock); 913 list_splice_init(&dev->wed_rro.poll_list, &list); 914 spin_unlock_bh(&dev->wed_rro.lock); 915 916 while (!list_empty(&list)) { 917 struct mt7996_wed_rro_session_id *e; 918 int i; 919 920 e = list_first_entry(&list, struct mt7996_wed_rro_session_id, 921 list); 922 list_del_init(&e->list); 923 924 for (i = 0; i < MT7996_RRO_WINDOW_MAX_LEN; i++) { 925 void *ptr = dev->wed_rro.session.ptr; 926 struct mt7996_wed_rro_addr *elem; 927 u32 idx, elem_id = i; 928 929 if (e->id == MT7996_RRO_MAX_SESSION) 930 goto reset; 931 932 idx = e->id / MT7996_RRO_BA_BITMAP_SESSION_SIZE; 933 if (idx >= ARRAY_SIZE(dev->wed_rro.addr_elem)) 934 goto out; 935 936 ptr = dev->wed_rro.addr_elem[idx].ptr; 937 elem_id += 938 (e->id % MT7996_RRO_BA_BITMAP_SESSION_SIZE) * 939 MT7996_RRO_WINDOW_MAX_LEN; 940 reset: 941 elem = ptr + elem_id * sizeof(*elem); 942 elem->signature = 0xff; 943 } 944 mt7996_mcu_wed_rro_reset_sessions(dev, e->id); 945 out: 946 kfree(e); 947 } 948 #endif 949 } 950 951 static int mt7996_variant_type_init(struct mt7996_dev *dev) 952 { 953 u32 val = mt76_rr(dev, MT_PAD_GPIO); 954 u8 var_type; 955 956 switch (mt76_chip(&dev->mt76)) { 957 case MT7996_DEVICE_ID: 958 if (val & MT_PAD_GPIO_2ADIE_TBTC) 959 var_type = MT7996_VAR_TYPE_233; 960 else 961 var_type = MT7996_VAR_TYPE_444; 962 break; 963 case MT7992_DEVICE_ID: 964 if (val & MT_PAD_GPIO_ADIE_SINGLE) 965 var_type = MT7992_VAR_TYPE_23; 966 else if (u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB_7992)) 967 var_type = MT7992_VAR_TYPE_44; 968 else 969 return -EINVAL; 970 break; 971 case MT7990_DEVICE_ID: 972 var_type = MT7990_VAR_TYPE_23; 973 break; 974 default: 975 return -EINVAL; 976 } 977 978 dev->var.type = var_type; 979 return 0; 980 } 981 982 static int mt7996_variant_fem_init(struct mt7996_dev *dev) 983 { 984 #define MT7976C_EFUSE_OFFSET 0x470 985 u8 buf[MT7996_EEPROM_BLOCK_SIZE], idx, adie_idx, adie_comb; 986 u32 regval, val = mt76_rr(dev, MT_PAD_GPIO); 987 u16 adie_id, adie_ver; 988 bool is_7976c; 989 int ret; 990 991 if (is_mt7992(&dev->mt76)) { 992 adie_idx = (val & MT_PAD_GPIO_ADIE_SINGLE) ? 0 : 1; 993 adie_comb = u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB_7992); 994 } else { 995 adie_idx = 0; 996 adie_comb = u32_get_bits(val, MT_PAD_GPIO_ADIE_COMB); 997 } 998 999 ret = mt7996_mcu_rf_regval(dev, MT_ADIE_CHIP_ID(adie_idx), ®val, false); 1000 if (ret) 1001 return ret; 1002 1003 ret = mt7996_mcu_get_eeprom(dev, MT7976C_EFUSE_OFFSET, buf, sizeof(buf)); 1004 if (ret && ret != -EINVAL) 1005 return ret; 1006 1007 adie_ver = u32_get_bits(regval, MT_ADIE_VERSION_MASK); 1008 idx = MT7976C_EFUSE_OFFSET % MT7996_EEPROM_BLOCK_SIZE; 1009 is_7976c = adie_ver == 0x8a10 || adie_ver == 0x8b00 || 1010 adie_ver == 0x8c10 || buf[idx] == 0xc; 1011 1012 adie_id = u32_get_bits(regval, MT_ADIE_CHIP_ID_MASK); 1013 if (adie_id == 0x7975 || adie_id == 0x7979 || 1014 (adie_id == 0x7976 && is_7976c)) 1015 dev->var.fem = MT7996_FEM_INT; 1016 else if (adie_id == 0x7977 && adie_comb == 1) 1017 dev->var.fem = MT7996_FEM_MIX; 1018 else 1019 dev->var.fem = MT7996_FEM_EXT; 1020 1021 return 0; 1022 } 1023 1024 static int mt7996_init_hardware(struct mt7996_dev *dev) 1025 { 1026 int ret, idx; 1027 1028 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 1029 if (is_mt7992(&dev->mt76)) { 1030 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND0), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0); 1031 mt76_rmw(dev, MT_AFE_CTL_BAND_PLL_03(MT_BAND1), MT_AFE_CTL_BAND_PLL_03_MSB_EN, 0); 1032 } 1033 1034 INIT_WORK(&dev->init_work, mt7996_init_work); 1035 INIT_WORK(&dev->wed_rro.work, mt7996_wed_rro_work); 1036 INIT_LIST_HEAD(&dev->wed_rro.poll_list); 1037 spin_lock_init(&dev->wed_rro.lock); 1038 1039 ret = mt7996_variant_type_init(dev); 1040 if (ret) 1041 return ret; 1042 1043 ret = mt7996_dma_init(dev); 1044 if (ret) 1045 return ret; 1046 1047 set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state); 1048 1049 ret = mt7996_mcu_init(dev); 1050 if (ret) 1051 return ret; 1052 1053 ret = mt7996_wed_rro_init(dev); 1054 if (ret) 1055 return ret; 1056 1057 ret = mt7996_variant_fem_init(dev); 1058 if (ret) 1059 return ret; 1060 1061 ret = mt7996_eeprom_init(dev); 1062 if (ret < 0) 1063 return ret; 1064 1065 /* Beacon and mgmt frames should occupy wcid 0 */ 1066 idx = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7996_WTBL_STA); 1067 if (idx) 1068 return -ENOSPC; 1069 1070 dev->mt76.global_wcid.idx = idx; 1071 dev->mt76.global_wcid.hw_key_idx = -1; 1072 dev->mt76.global_wcid.tx_info |= MT_WCID_TX_INFO_SET; 1073 rcu_assign_pointer(dev->mt76.wcid[idx], &dev->mt76.global_wcid); 1074 1075 return 0; 1076 } 1077 1078 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy) 1079 { 1080 int sts; 1081 u32 *cap; 1082 1083 if (!phy->mt76->cap.has_5ghz) 1084 return; 1085 1086 sts = hweight16(phy->mt76->chainmask); 1087 cap = &phy->mt76->sband_5g.sband.vht_cap.cap; 1088 1089 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE | 1090 IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE; 1091 1092 if (is_mt7992(phy->mt76->dev)) 1093 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 4); 1094 else 1095 *cap |= FIELD_PREP(IEEE80211_VHT_CAP_BEAMFORMEE_STS_MASK, 3); 1096 1097 *cap &= ~(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK | 1098 IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 1099 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE); 1100 1101 if (sts < 2) 1102 return; 1103 1104 *cap |= IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE | 1105 IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE | 1106 FIELD_PREP(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, sts - 1); 1107 } 1108 1109 static void 1110 mt7996_set_stream_he_txbf_caps(struct mt7996_phy *phy, 1111 struct ieee80211_sta_he_cap *he_cap, int vif, 1112 enum nl80211_band band) 1113 { 1114 struct ieee80211_he_cap_elem *elem = &he_cap->he_cap_elem; 1115 int sts = hweight16(phy->mt76->chainmask); 1116 bool non_2g = band != NL80211_BAND_2GHZ; 1117 u8 c; 1118 1119 #ifdef CONFIG_MAC80211_MESH 1120 if (vif == NL80211_IFTYPE_MESH_POINT) 1121 return; 1122 #endif 1123 1124 elem->phy_cap_info[3] &= ~IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 1125 elem->phy_cap_info[4] &= ~IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 1126 1127 c = IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK | 1128 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK; 1129 elem->phy_cap_info[5] &= ~c; 1130 1131 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 1132 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 1133 elem->phy_cap_info[6] &= ~c; 1134 1135 elem->phy_cap_info[7] &= ~IEEE80211_HE_PHY_CAP7_MAX_NC_MASK; 1136 1137 c = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 1138 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO; 1139 elem->phy_cap_info[2] |= c; 1140 1141 c = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE; 1142 1143 if (is_mt7992(phy->mt76->dev)) 1144 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_5 | 1145 (IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_5 * non_2g); 1146 else 1147 c |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4 | 1148 (IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4 * non_2g); 1149 1150 elem->phy_cap_info[4] |= c; 1151 1152 /* do not support NG16 due to spec D4.0 changes subcarrier idx */ 1153 c = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 1154 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU; 1155 1156 if (vif == NL80211_IFTYPE_STATION) 1157 c |= IEEE80211_HE_PHY_CAP6_PARTIAL_BANDWIDTH_DL_MUMIMO; 1158 1159 elem->phy_cap_info[6] |= c; 1160 1161 if (sts < 2) 1162 return; 1163 1164 /* the maximum cap is 4 x 3, (Nr, Nc) = (3, 2) */ 1165 elem->phy_cap_info[7] |= min_t(int, sts - 1, 2) << 3; 1166 1167 if (!(vif == NL80211_IFTYPE_AP || vif == NL80211_IFTYPE_STATION)) 1168 return; 1169 1170 elem->phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER; 1171 1172 c = FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 1173 sts - 1) | 1174 (FIELD_PREP(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_MASK, 1175 sts - 1) * non_2g); 1176 1177 elem->phy_cap_info[5] |= c; 1178 1179 if (vif != NL80211_IFTYPE_AP) 1180 return; 1181 1182 elem->phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER; 1183 1184 c = IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 1185 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB; 1186 elem->phy_cap_info[6] |= c; 1187 1188 c = 0; 1189 if (non_2g) 1190 c |= IEEE80211_HE_PHY_CAP7_STBC_TX_ABOVE_80MHZ | 1191 IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ; 1192 elem->phy_cap_info[7] |= c; 1193 } 1194 1195 static void 1196 mt7996_init_he_caps(struct mt7996_phy *phy, enum nl80211_band band, 1197 struct ieee80211_sband_iftype_data *data, 1198 enum nl80211_iftype iftype) 1199 { 1200 struct ieee80211_sta_he_cap *he_cap = &data->he_cap; 1201 struct ieee80211_he_cap_elem *he_cap_elem = &he_cap->he_cap_elem; 1202 struct ieee80211_he_mcs_nss_supp *he_mcs = &he_cap->he_mcs_nss_supp; 1203 int i, nss = hweight8(phy->mt76->antenna_mask); 1204 u16 mcs_map = 0; 1205 1206 for (i = 0; i < 8; i++) { 1207 if (i < nss) 1208 mcs_map |= (IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2)); 1209 else 1210 mcs_map |= (IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2)); 1211 } 1212 1213 he_cap->has_he = true; 1214 1215 he_cap_elem->mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 1216 he_cap_elem->mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_OMI_CONTROL | 1217 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3; 1218 he_cap_elem->mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 1219 1220 if (band == NL80211_BAND_2GHZ) 1221 he_cap_elem->phy_cap_info[0] = 1222 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 1223 else 1224 he_cap_elem->phy_cap_info[0] = 1225 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G | 1226 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 1227 1228 he_cap_elem->phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD; 1229 he_cap_elem->phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 1230 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ; 1231 1232 he_cap_elem->phy_cap_info[7] = 1233 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI; 1234 1235 switch (iftype) { 1236 case NL80211_IFTYPE_AP: 1237 he_cap_elem->mac_cap_info[0] |= IEEE80211_HE_MAC_CAP0_TWT_RES; 1238 he_cap_elem->mac_cap_info[2] |= IEEE80211_HE_MAC_CAP2_BSR; 1239 he_cap_elem->mac_cap_info[4] |= IEEE80211_HE_MAC_CAP4_BQR; 1240 he_cap_elem->mac_cap_info[5] |= 1241 IEEE80211_HE_MAC_CAP5_OM_CTRL_UL_MU_DATA_DIS_RX; 1242 he_cap_elem->phy_cap_info[3] |= 1243 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1244 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1245 he_cap_elem->phy_cap_info[6] |= 1246 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1247 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1248 he_cap_elem->phy_cap_info[9] |= 1249 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1250 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU; 1251 break; 1252 case NL80211_IFTYPE_STATION: 1253 he_cap_elem->mac_cap_info[1] |= 1254 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 1255 1256 if (band == NL80211_BAND_2GHZ) 1257 he_cap_elem->phy_cap_info[0] |= 1258 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_2G; 1259 else 1260 he_cap_elem->phy_cap_info[0] |= 1261 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_RU_MAPPING_IN_5G; 1262 1263 he_cap_elem->phy_cap_info[1] |= 1264 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 1265 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 1266 he_cap_elem->phy_cap_info[3] |= 1267 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_QPSK | 1268 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_QPSK; 1269 he_cap_elem->phy_cap_info[6] |= 1270 IEEE80211_HE_PHY_CAP6_TRIG_CQI_FB | 1271 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE | 1272 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT; 1273 he_cap_elem->phy_cap_info[7] |= 1274 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP; 1275 he_cap_elem->phy_cap_info[8] |= 1276 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G | 1277 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 1278 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU | 1279 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_484; 1280 he_cap_elem->phy_cap_info[9] |= 1281 IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 1282 IEEE80211_HE_PHY_CAP9_NON_TRIGGERED_CQI_FEEDBACK | 1283 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU | 1284 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 1285 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 1286 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB; 1287 break; 1288 default: 1289 break; 1290 } 1291 1292 he_mcs->rx_mcs_80 = cpu_to_le16(mcs_map); 1293 he_mcs->tx_mcs_80 = cpu_to_le16(mcs_map); 1294 he_mcs->rx_mcs_160 = cpu_to_le16(mcs_map); 1295 he_mcs->tx_mcs_160 = cpu_to_le16(mcs_map); 1296 1297 mt7996_set_stream_he_txbf_caps(phy, he_cap, iftype, band); 1298 1299 memset(he_cap->ppe_thres, 0, sizeof(he_cap->ppe_thres)); 1300 if (he_cap_elem->phy_cap_info[6] & 1301 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT) { 1302 mt76_connac_gen_ppe_thresh(he_cap->ppe_thres, nss, band); 1303 } else { 1304 he_cap_elem->phy_cap_info[9] |= 1305 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 1306 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 1307 } 1308 1309 if (band == NL80211_BAND_6GHZ) { 1310 u16 cap = IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS | 1311 IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS; 1312 1313 cap |= u16_encode_bits(IEEE80211_HT_MPDU_DENSITY_0_5, 1314 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 1315 u16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 1316 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 1317 u16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 1318 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 1319 1320 data->he_6ghz_capa.capa = cpu_to_le16(cap); 1321 } 1322 } 1323 1324 static void 1325 mt7996_init_eht_caps(struct mt7996_phy *phy, enum nl80211_band band, 1326 struct ieee80211_sband_iftype_data *data, 1327 enum nl80211_iftype iftype) 1328 { 1329 struct ieee80211_sta_eht_cap *eht_cap = &data->eht_cap; 1330 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem = &eht_cap->eht_cap_elem; 1331 struct ieee80211_eht_mcs_nss_supp *eht_nss = &eht_cap->eht_mcs_nss_supp; 1332 enum nl80211_chan_width width = phy->mt76->chandef.width; 1333 int nss = hweight8(phy->mt76->antenna_mask); 1334 int sts = hweight16(phy->mt76->chainmask); 1335 u8 val; 1336 1337 if (!phy->dev->has_eht) 1338 return; 1339 1340 eht_cap->has_eht = true; 1341 1342 eht_cap_elem->mac_cap_info[0] = 1343 IEEE80211_EHT_MAC_CAP0_EPCS_PRIO_ACCESS | 1344 IEEE80211_EHT_MAC_CAP0_OM_CONTROL | 1345 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454, 1346 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); 1347 1348 eht_cap_elem->mac_cap_info[1] |= 1349 IEEE80211_EHT_MAC_CAP1_MAX_AMPDU_LEN_MASK; 1350 1351 eht_cap_elem->phy_cap_info[0] = 1352 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 1353 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMER | 1354 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 1355 1356 /* Set the maximum capability regardless of the antenna configuration. */ 1357 val = is_mt7992(phy->mt76->dev) ? 4 : 3; 1358 eht_cap_elem->phy_cap_info[0] |= 1359 u8_encode_bits(u8_get_bits(val, BIT(0)), 1360 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 1361 1362 eht_cap_elem->phy_cap_info[1] = 1363 u8_encode_bits(u8_get_bits(val, GENMASK(2, 1)), 1364 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK); 1365 1366 eht_cap_elem->phy_cap_info[2] = 1367 u8_encode_bits(sts - 1, IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_80MHZ_MASK); 1368 1369 if (band != NL80211_BAND_2GHZ) { 1370 eht_cap_elem->phy_cap_info[1] |= 1371 u8_encode_bits(val, 1372 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK); 1373 1374 eht_cap_elem->phy_cap_info[2] |= 1375 u8_encode_bits(sts - 1, 1376 IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_160MHZ_MASK); 1377 } 1378 1379 if (band == NL80211_BAND_6GHZ) { 1380 eht_cap_elem->phy_cap_info[0] |= 1381 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 1382 1383 eht_cap_elem->phy_cap_info[1] |= 1384 u8_encode_bits(val, 1385 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 1386 1387 eht_cap_elem->phy_cap_info[2] |= 1388 u8_encode_bits(sts - 1, 1389 IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_320MHZ_MASK); 1390 } 1391 1392 eht_cap_elem->phy_cap_info[3] = 1393 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK | 1394 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK | 1395 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 1396 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK; 1397 1398 eht_cap_elem->phy_cap_info[4] = 1399 IEEE80211_EHT_PHY_CAP4_EHT_MU_PPDU_4_EHT_LTF_08_GI | 1400 u8_encode_bits(min_t(int, sts - 1, 2), 1401 IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 1402 1403 eht_cap_elem->phy_cap_info[5] = 1404 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US, 1405 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK) | 1406 u8_encode_bits(u8_get_bits(1, GENMASK(1, 0)), 1407 IEEE80211_EHT_PHY_CAP5_MAX_NUM_SUPP_EHT_LTF_MASK); 1408 1409 val = width == NL80211_CHAN_WIDTH_320 ? 0xf : 1410 width == NL80211_CHAN_WIDTH_160 ? 0x7 : 1411 width == NL80211_CHAN_WIDTH_80 ? 0x3 : 0x1; 1412 eht_cap_elem->phy_cap_info[6] = 1413 u8_encode_bits(val, IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK); 1414 1415 val = u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_RX) | 1416 u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_TX); 1417 #define SET_EHT_MAX_NSS(_bw, _val) do { \ 1418 eht_nss->bw._##_bw.rx_tx_mcs9_max_nss = _val; \ 1419 eht_nss->bw._##_bw.rx_tx_mcs11_max_nss = _val; \ 1420 eht_nss->bw._##_bw.rx_tx_mcs13_max_nss = _val; \ 1421 } while (0) 1422 1423 SET_EHT_MAX_NSS(80, val); 1424 SET_EHT_MAX_NSS(160, val); 1425 if (band == NL80211_BAND_6GHZ) 1426 SET_EHT_MAX_NSS(320, val); 1427 #undef SET_EHT_MAX_NSS 1428 1429 if (iftype != NL80211_IFTYPE_AP) 1430 return; 1431 1432 eht_cap_elem->phy_cap_info[3] |= 1433 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 1434 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK; 1435 1436 eht_cap_elem->phy_cap_info[7] = 1437 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_80MHZ | 1438 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_80MHZ; 1439 1440 if (band == NL80211_BAND_2GHZ) 1441 return; 1442 1443 eht_cap_elem->phy_cap_info[7] |= 1444 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_160MHZ | 1445 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_160MHZ; 1446 1447 if (band != NL80211_BAND_6GHZ) 1448 return; 1449 1450 eht_cap_elem->phy_cap_info[7] |= 1451 IEEE80211_EHT_PHY_CAP7_NON_OFDMA_UL_MU_MIMO_320MHZ | 1452 IEEE80211_EHT_PHY_CAP7_MU_BEAMFORMER_320MHZ; 1453 } 1454 1455 static void 1456 __mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy, 1457 struct ieee80211_supported_band *sband, 1458 enum nl80211_band band) 1459 { 1460 struct ieee80211_sband_iftype_data *data = phy->iftype[band]; 1461 int i, n = 0; 1462 1463 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 1464 switch (i) { 1465 case NL80211_IFTYPE_STATION: 1466 case NL80211_IFTYPE_AP: 1467 #ifdef CONFIG_MAC80211_MESH 1468 case NL80211_IFTYPE_MESH_POINT: 1469 #endif 1470 break; 1471 default: 1472 continue; 1473 } 1474 1475 data[n].types_mask = BIT(i); 1476 mt7996_init_he_caps(phy, band, &data[n], i); 1477 mt7996_init_eht_caps(phy, band, &data[n], i); 1478 1479 n++; 1480 } 1481 1482 _ieee80211_set_sband_iftype_data(sband, data, n); 1483 } 1484 1485 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy) 1486 { 1487 if (phy->mt76->cap.has_2ghz) 1488 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_2g.sband, 1489 NL80211_BAND_2GHZ); 1490 1491 if (phy->mt76->cap.has_5ghz) 1492 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_5g.sband, 1493 NL80211_BAND_5GHZ); 1494 1495 if (phy->mt76->cap.has_6ghz) 1496 __mt7996_set_stream_he_eht_caps(phy, &phy->mt76->sband_6g.sband, 1497 NL80211_BAND_6GHZ); 1498 } 1499 1500 int mt7996_register_device(struct mt7996_dev *dev) 1501 { 1502 struct ieee80211_hw *hw = mt76_hw(dev); 1503 #if defined(CONFIG_HWMON) 1504 struct mt7996_phy *phy; 1505 #endif 1506 int ret; 1507 1508 dev->phy.dev = dev; 1509 dev->phy.mt76 = &dev->mt76.phy; 1510 dev->mt76.phy.priv = &dev->phy; 1511 INIT_WORK(&dev->rc_work, mt7996_mac_sta_rc_work); 1512 INIT_DELAYED_WORK(&dev->mphy.mac_work, mt7996_mac_work); 1513 INIT_LIST_HEAD(&dev->sta_rc_list); 1514 INIT_LIST_HEAD(&dev->twt_list); 1515 1516 init_waitqueue_head(&dev->reset_wait); 1517 INIT_WORK(&dev->reset_work, mt7996_mac_reset_work); 1518 INIT_WORK(&dev->dump_work, mt7996_mac_dump_work); 1519 mutex_init(&dev->dump_mutex); 1520 1521 ret = mt7996_init_hardware(dev); 1522 if (ret) 1523 return ret; 1524 1525 mt7996_init_wiphy(hw, &dev->mt76.mmio.wed); 1526 1527 ret = mt7996_register_phy(dev, MT_BAND1); 1528 if (ret) 1529 return ret; 1530 1531 ret = mt7996_register_phy(dev, MT_BAND2); 1532 if (ret) 1533 return ret; 1534 1535 ret = mt76_register_device(&dev->mt76, true, mt76_rates, 1536 ARRAY_SIZE(mt76_rates)); 1537 if (ret) 1538 return ret; 1539 1540 #if defined(CONFIG_HWMON) 1541 mt7996_for_each_phy(dev, phy) 1542 mt7996_thermal_init(phy); 1543 #endif 1544 1545 ieee80211_queue_work(mt76_hw(dev), &dev->init_work); 1546 1547 dev->recovery.hw_init_done = true; 1548 1549 #if defined(CONFIG_MT7996_DEBUGFS) 1550 ret = mt7996_init_debugfs(dev); 1551 if (ret) 1552 goto error; 1553 #endif 1554 1555 ret = mt7996_coredump_register(dev); 1556 if (ret) 1557 goto error; 1558 1559 return 0; 1560 1561 error: 1562 cancel_work_sync(&dev->init_work); 1563 1564 return ret; 1565 } 1566 1567 void mt7996_unregister_device(struct mt7996_dev *dev) 1568 { 1569 cancel_work_sync(&dev->wed_rro.work); 1570 mt7996_unregister_phy(mt7996_phy3(dev)); 1571 mt7996_unregister_phy(mt7996_phy2(dev)); 1572 #if defined(CONFIG_HWMON) 1573 mt7996_unregister_thermal(&dev->phy); 1574 #endif 1575 mt7996_coredump_unregister(dev); 1576 mt76_unregister_device(&dev->mt76); 1577 mt7996_wed_rro_free(dev); 1578 mt7996_mcu_exit(dev); 1579 mt7996_tx_token_put(dev); 1580 mt7996_dma_cleanup(dev); 1581 tasklet_disable(&dev->mt76.irq_tasklet); 1582 1583 mt76_free_device(&dev->mt76); 1584 } 1585