xref: /freebsd/sys/contrib/dev/mediatek/mt76/mt7921/pci.c (revision 7fdf597e96a02165cfe22ff357b857d5fa15ed8a)
1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2020 MediaTek Inc.
3  *
4  */
5 
6 #if defined(__FreeBSD__)
7 #define	LINUXKPI_PARAM_PREFIX	mt7921_pci_
8 #endif
9 
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 
14 #include "mt7921.h"
15 #include "../mt76_connac2_mac.h"
16 #include "../dma.h"
17 #include "mcu.h"
18 
19 static const struct pci_device_id mt7921_pci_device_table[] = {
20 	{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961),
21 		.driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM },
22 	{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922),
23 		.driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM },
24 	{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608),
25 		.driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM },
26 	{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616),
27 		.driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM },
28 	{ },
29 };
30 
31 static bool mt7921_disable_aspm;
32 module_param_named(disable_aspm, mt7921_disable_aspm, bool, 0644);
33 MODULE_PARM_DESC(disable_aspm, "disable PCI ASPM support");
34 
35 static int mt7921e_init_reset(struct mt792x_dev *dev)
36 {
37 	return mt792x_wpdma_reset(dev, true);
38 }
39 
40 static void mt7921e_unregister_device(struct mt792x_dev *dev)
41 {
42 	int i;
43 	struct mt76_connac_pm *pm = &dev->pm;
44 
45 	cancel_work_sync(&dev->init_work);
46 	mt76_unregister_device(&dev->mt76);
47 	mt76_for_each_q_rx(&dev->mt76, i)
48 		napi_disable(&dev->mt76.napi[i]);
49 	cancel_delayed_work_sync(&pm->ps_work);
50 	cancel_work_sync(&pm->wake_work);
51 	cancel_work_sync(&dev->reset_work);
52 
53 	mt76_connac2_tx_token_put(&dev->mt76);
54 	__mt792x_mcu_drv_pmctrl(dev);
55 	mt792x_dma_cleanup(dev);
56 	mt792x_wfsys_reset(dev);
57 	skb_queue_purge(&dev->mt76.mcu.res_q);
58 
59 	tasklet_disable(&dev->mt76.irq_tasklet);
60 }
61 
62 static u32 __mt7921_reg_addr(struct mt792x_dev *dev, u32 addr)
63 {
64 	static const struct mt76_connac_reg_map fixed_map[] = {
65 		{ 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
66 		{ 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
67 		{ 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
68 		{ 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
69 		{ 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
70 		{ 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
71 		{ 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
72 		{ 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
73 		{ 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
74 		{ 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
75 		{ 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
76 		{ 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */
77 		{ 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */
78 		{ 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
79 		{ 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */
80 		{ 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
81 		{ 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
82 		{ 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
83 		{ 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
84 		{ 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
85 		{ 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */
86 		{ 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */
87 		{ 0x820cc000, 0x0e000, 0x01000 }, /* WF_UMAC_TOP (PP) */
88 		{ 0x820cd000, 0x0f000, 0x01000 }, /* WF_MDP_TOP */
89 		{ 0x74030000, 0x10000, 0x10000 }, /* PCIE_MAC_IREG */
90 		{ 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */
91 		{ 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */
92 		{ 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
93 		{ 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
94 		{ 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
95 		{ 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
96 		{ 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
97 		{ 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
98 		{ 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
99 		{ 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
100 		{ 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
101 		{ 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
102 		{ 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
103 		{ 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
104 		{ 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
105 		{ 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
106 		{ 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
107 		{ 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
108 		{ 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
109 	};
110 	int i;
111 
112 	if (addr < 0x100000)
113 		return addr;
114 
115 	for (i = 0; i < ARRAY_SIZE(fixed_map); i++) {
116 		u32 ofs;
117 
118 		if (addr < fixed_map[i].phys)
119 			continue;
120 
121 		ofs = addr - fixed_map[i].phys;
122 		if (ofs > fixed_map[i].size)
123 			continue;
124 
125 		return fixed_map[i].maps + ofs;
126 	}
127 
128 	if ((addr >= 0x18000000 && addr < 0x18c00000) ||
129 	    (addr >= 0x70000000 && addr < 0x78000000) ||
130 	    (addr >= 0x7c000000 && addr < 0x7c400000))
131 		return mt7921_reg_map_l1(dev, addr);
132 
133 	dev_err(dev->mt76.dev, "Access currently unsupported address %08x\n",
134 		addr);
135 
136 	return 0;
137 }
138 
139 static u32 mt7921_rr(struct mt76_dev *mdev, u32 offset)
140 {
141 	struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
142 	u32 addr = __mt7921_reg_addr(dev, offset);
143 
144 	return dev->bus_ops->rr(mdev, addr);
145 }
146 
147 static void mt7921_wr(struct mt76_dev *mdev, u32 offset, u32 val)
148 {
149 	struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
150 	u32 addr = __mt7921_reg_addr(dev, offset);
151 
152 	dev->bus_ops->wr(mdev, addr, val);
153 }
154 
155 static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
156 {
157 	struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
158 	u32 addr = __mt7921_reg_addr(dev, offset);
159 
160 	return dev->bus_ops->rmw(mdev, addr, mask, val);
161 }
162 
163 static int mt7921_dma_init(struct mt792x_dev *dev)
164 {
165 	int ret;
166 
167 	mt76_dma_attach(&dev->mt76);
168 
169 	ret = mt792x_dma_disable(dev, true);
170 	if (ret)
171 		return ret;
172 
173 	/* init tx queue */
174 	ret = mt76_connac_init_tx_queues(dev->phy.mt76, MT7921_TXQ_BAND0,
175 					 MT7921_TX_RING_SIZE,
176 					 MT_TX_RING_BASE, 0);
177 	if (ret)
178 		return ret;
179 
180 	mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, 0x4);
181 
182 	/* command to WM */
183 	ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7921_TXQ_MCU_WM,
184 				  MT7921_TX_MCU_RING_SIZE, MT_TX_RING_BASE);
185 	if (ret)
186 		return ret;
187 
188 	/* firmware download */
189 	ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7921_TXQ_FWDL,
190 				  MT7921_TX_FWDL_RING_SIZE, MT_TX_RING_BASE);
191 	if (ret)
192 		return ret;
193 
194 	/* event from WM before firmware download */
195 	ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU],
196 			       MT7921_RXQ_MCU_WM,
197 			       MT7921_RX_MCU_RING_SIZE,
198 			       MT_RX_BUF_SIZE, MT_RX_EVENT_RING_BASE);
199 	if (ret)
200 		return ret;
201 
202 	/* Change mcu queue after firmware download */
203 	ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],
204 			       MT7921_RXQ_MCU_WM,
205 			       MT7921_RX_MCU_RING_SIZE,
206 			       MT_RX_BUF_SIZE, MT_WFDMA0(0x540));
207 	if (ret)
208 		return ret;
209 
210 	/* rx data */
211 	ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],
212 			       MT7921_RXQ_BAND0, MT7921_RX_RING_SIZE,
213 			       MT_RX_BUF_SIZE, MT_RX_DATA_RING_BASE);
214 	if (ret)
215 		return ret;
216 
217 	ret = mt76_init_queues(dev, mt792x_poll_rx);
218 	if (ret < 0)
219 		return ret;
220 
221 	netif_napi_add_tx(&dev->mt76.tx_napi_dev, &dev->mt76.tx_napi,
222 			  mt792x_poll_tx);
223 	napi_enable(&dev->mt76.tx_napi);
224 
225 	return mt792x_dma_enable(dev);
226 }
227 
228 static int mt7921_pci_probe(struct pci_dev *pdev,
229 			    const struct pci_device_id *id)
230 {
231 	static const struct mt76_driver_ops drv_ops = {
232 		/* txwi_size = txd size + txp size */
233 		.txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_hw_txp),
234 		.drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ |
235 			     MT_DRV_AMSDU_OFFLOAD,
236 		.survey_flags = SURVEY_INFO_TIME_TX |
237 				SURVEY_INFO_TIME_RX |
238 				SURVEY_INFO_TIME_BSS_RX,
239 		.token_size = MT7921_TOKEN_SIZE,
240 		.tx_prepare_skb = mt7921e_tx_prepare_skb,
241 		.tx_complete_skb = mt76_connac_tx_complete_skb,
242 		.rx_check = mt7921_rx_check,
243 		.rx_skb = mt7921_queue_rx_skb,
244 		.rx_poll_complete = mt792x_rx_poll_complete,
245 		.sta_add = mt7921_mac_sta_add,
246 		.sta_assoc = mt7921_mac_sta_assoc,
247 		.sta_remove = mt7921_mac_sta_remove,
248 		.update_survey = mt792x_update_channel,
249 	};
250 	static const struct mt792x_hif_ops mt7921_pcie_ops = {
251 		.init_reset = mt7921e_init_reset,
252 		.reset = mt7921e_mac_reset,
253 		.mcu_init = mt7921e_mcu_init,
254 		.drv_own = mt792xe_mcu_drv_pmctrl,
255 		.fw_own = mt792xe_mcu_fw_pmctrl,
256 	};
257 	static const struct mt792x_irq_map irq_map = {
258 		.host_irq_enable = MT_WFDMA0_HOST_INT_ENA,
259 		.tx = {
260 			.all_complete_mask = MT_INT_TX_DONE_ALL,
261 			.mcu_complete_mask = MT_INT_TX_DONE_MCU,
262 		},
263 		.rx = {
264 			.data_complete_mask = MT_INT_RX_DONE_DATA,
265 			.wm_complete_mask = MT_INT_RX_DONE_WM,
266 			.wm2_complete_mask = MT_INT_RX_DONE_WM2,
267 		},
268 	};
269 	struct ieee80211_ops *ops;
270 	struct mt76_bus_ops *bus_ops;
271 	struct mt792x_dev *dev;
272 	struct mt76_dev *mdev;
273 	u8 features;
274 	int ret;
275 	u16 cmd;
276 
277 	ret = pcim_enable_device(pdev);
278 	if (ret)
279 		return ret;
280 
281 	ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
282 	if (ret)
283 		return ret;
284 
285 	pci_read_config_word(pdev, PCI_COMMAND, &cmd);
286 	if (!(cmd & PCI_COMMAND_MEMORY)) {
287 		cmd |= PCI_COMMAND_MEMORY;
288 		pci_write_config_word(pdev, PCI_COMMAND, cmd);
289 	}
290 	pci_set_master(pdev);
291 
292 	ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
293 	if (ret < 0)
294 		return ret;
295 
296 	ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
297 	if (ret)
298 		goto err_free_pci_vec;
299 
300 	if (mt7921_disable_aspm)
301 		mt76_pci_disable_aspm(pdev);
302 
303 	ops = mt792x_get_mac80211_ops(&pdev->dev, &mt7921_ops,
304 				      (void *)id->driver_data, &features);
305 	if (!ops) {
306 		ret = -ENOMEM;
307 		goto err_free_pci_vec;
308 	}
309 
310 	mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), ops, &drv_ops);
311 	if (!mdev) {
312 		ret = -ENOMEM;
313 		goto err_free_pci_vec;
314 	}
315 
316 	pci_set_drvdata(pdev, mdev);
317 
318 	dev = container_of(mdev, struct mt792x_dev, mt76);
319 	dev->fw_features = features;
320 	dev->hif_ops = &mt7921_pcie_ops;
321 	dev->irq_map = &irq_map;
322 	mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]);
323 	tasklet_init(&mdev->irq_tasklet, mt792x_irq_tasklet, (unsigned long)dev);
324 
325 	dev->phy.dev = dev;
326 	dev->phy.mt76 = &dev->mt76.phy;
327 	dev->mt76.phy.priv = &dev->phy;
328 	dev->bus_ops = dev->mt76.bus;
329 	bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
330 			       GFP_KERNEL);
331 	if (!bus_ops) {
332 		ret = -ENOMEM;
333 		goto err_free_dev;
334 	}
335 
336 	bus_ops->rr = mt7921_rr;
337 	bus_ops->wr = mt7921_wr;
338 	bus_ops->rmw = mt7921_rmw;
339 	dev->mt76.bus = bus_ops;
340 
341 	ret = mt792xe_mcu_fw_pmctrl(dev);
342 	if (ret)
343 		goto err_free_dev;
344 
345 	ret = __mt792xe_mcu_drv_pmctrl(dev);
346 	if (ret)
347 		goto err_free_dev;
348 
349 	mdev->rev = (mt7921_l1_rr(dev, MT_HW_CHIPID) << 16) |
350 		    (mt7921_l1_rr(dev, MT_HW_REV) & 0xff);
351 	dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
352 
353 	ret = mt792x_wfsys_reset(dev);
354 	if (ret)
355 		goto err_free_dev;
356 
357 	mt76_wr(dev, irq_map.host_irq_enable, 0);
358 
359 	mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
360 
361 	ret = devm_request_irq(mdev->dev, pdev->irq, mt792x_irq_handler,
362 			       IRQF_SHARED, KBUILD_MODNAME, dev);
363 	if (ret)
364 		goto err_free_dev;
365 
366 	ret = mt7921_dma_init(dev);
367 	if (ret)
368 		goto err_free_irq;
369 
370 	ret = mt7921_register_device(dev);
371 	if (ret)
372 		goto err_free_irq;
373 
374 	return 0;
375 
376 err_free_irq:
377 	devm_free_irq(&pdev->dev, pdev->irq, dev);
378 err_free_dev:
379 	mt76_free_device(&dev->mt76);
380 err_free_pci_vec:
381 	pci_free_irq_vectors(pdev);
382 
383 	return ret;
384 }
385 
386 static void mt7921_pci_remove(struct pci_dev *pdev)
387 {
388 	struct mt76_dev *mdev = pci_get_drvdata(pdev);
389 	struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
390 
391 	mt7921e_unregister_device(dev);
392 	devm_free_irq(&pdev->dev, pdev->irq, dev);
393 	mt76_free_device(&dev->mt76);
394 	pci_free_irq_vectors(pdev);
395 }
396 
397 #if !defined(__FreeBSD__) || defined(CONFIG_PM_SLEEP)
398 static int mt7921_pci_suspend(struct device *device)
399 {
400 	struct pci_dev *pdev = to_pci_dev(device);
401 	struct mt76_dev *mdev = pci_get_drvdata(pdev);
402 	struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
403 	struct mt76_connac_pm *pm = &dev->pm;
404 	int i, err;
405 
406 	pm->suspended = true;
407 	flush_work(&dev->reset_work);
408 	cancel_delayed_work_sync(&pm->ps_work);
409 	cancel_work_sync(&pm->wake_work);
410 
411 	err = mt792x_mcu_drv_pmctrl(dev);
412 	if (err < 0)
413 		goto restore_suspend;
414 
415 	err = mt76_connac_mcu_set_hif_suspend(mdev, true);
416 	if (err)
417 		goto restore_suspend;
418 
419 	/* always enable deep sleep during suspend to reduce
420 	 * power consumption
421 	 */
422 	mt76_connac_mcu_set_deep_sleep(&dev->mt76, true);
423 
424 	napi_disable(&mdev->tx_napi);
425 	mt76_worker_disable(&mdev->tx_worker);
426 
427 	mt76_for_each_q_rx(mdev, i) {
428 		napi_disable(&mdev->napi[i]);
429 	}
430 
431 	/* wait until dma is idle  */
432 	mt76_poll(dev, MT_WFDMA0_GLO_CFG,
433 		  MT_WFDMA0_GLO_CFG_TX_DMA_BUSY |
434 		  MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000);
435 
436 	/* put dma disabled */
437 	mt76_clear(dev, MT_WFDMA0_GLO_CFG,
438 		   MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
439 
440 	/* disable interrupt */
441 	mt76_wr(dev, dev->irq_map->host_irq_enable, 0);
442 	mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0);
443 	synchronize_irq(pdev->irq);
444 	tasklet_kill(&mdev->irq_tasklet);
445 
446 	err = mt792x_mcu_fw_pmctrl(dev);
447 	if (err)
448 		goto restore_napi;
449 
450 	return 0;
451 
452 restore_napi:
453 	mt76_for_each_q_rx(mdev, i) {
454 		napi_enable(&mdev->napi[i]);
455 	}
456 	napi_enable(&mdev->tx_napi);
457 
458 	if (!pm->ds_enable)
459 		mt76_connac_mcu_set_deep_sleep(&dev->mt76, false);
460 
461 	mt76_connac_mcu_set_hif_suspend(mdev, false);
462 
463 restore_suspend:
464 	pm->suspended = false;
465 
466 	if (err < 0)
467 		mt792x_reset(&dev->mt76);
468 
469 	return err;
470 }
471 
472 static int mt7921_pci_resume(struct device *device)
473 {
474 	struct pci_dev *pdev = to_pci_dev(device);
475 	struct mt76_dev *mdev = pci_get_drvdata(pdev);
476 	struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76);
477 	struct mt76_connac_pm *pm = &dev->pm;
478 	int i, err;
479 
480 	err = mt792x_mcu_drv_pmctrl(dev);
481 	if (err < 0)
482 		goto failed;
483 
484 	mt792x_wpdma_reinit_cond(dev);
485 
486 	/* enable interrupt */
487 	mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff);
488 	mt76_connac_irq_enable(&dev->mt76,
489 			       dev->irq_map->tx.all_complete_mask |
490 			       MT_INT_RX_DONE_ALL | MT_INT_MCU_CMD);
491 	mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE);
492 
493 	/* put dma enabled */
494 	mt76_set(dev, MT_WFDMA0_GLO_CFG,
495 		 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN);
496 
497 	mt76_worker_enable(&mdev->tx_worker);
498 
499 	local_bh_disable();
500 	mt76_for_each_q_rx(mdev, i) {
501 		napi_enable(&mdev->napi[i]);
502 		napi_schedule(&mdev->napi[i]);
503 	}
504 	napi_enable(&mdev->tx_napi);
505 	napi_schedule(&mdev->tx_napi);
506 	local_bh_enable();
507 
508 	/* restore previous ds setting */
509 	if (!pm->ds_enable)
510 		mt76_connac_mcu_set_deep_sleep(&dev->mt76, false);
511 
512 	err = mt76_connac_mcu_set_hif_suspend(mdev, false);
513 failed:
514 	pm->suspended = false;
515 
516 	if (err < 0)
517 		mt792x_reset(&dev->mt76);
518 
519 	return err;
520 }
521 #endif
522 
523 static void mt7921_pci_shutdown(struct pci_dev *pdev)
524 {
525 	mt7921_pci_remove(pdev);
526 }
527 
528 static DEFINE_SIMPLE_DEV_PM_OPS(mt7921_pm_ops, mt7921_pci_suspend, mt7921_pci_resume);
529 
530 static struct pci_driver mt7921_pci_driver = {
531 	.name		= KBUILD_MODNAME,
532 	.id_table	= mt7921_pci_device_table,
533 	.probe		= mt7921_pci_probe,
534 	.remove		= mt7921_pci_remove,
535 	.shutdown	= mt7921_pci_shutdown,
536 	.driver.pm	= pm_sleep_ptr(&mt7921_pm_ops),
537 };
538 
539 module_pci_driver(mt7921_pci_driver);
540 
541 MODULE_DEVICE_TABLE(pci, mt7921_pci_device_table);
542 MODULE_FIRMWARE(MT7921_FIRMWARE_WM);
543 MODULE_FIRMWARE(MT7921_ROM_PATCH);
544 MODULE_FIRMWARE(MT7922_FIRMWARE_WM);
545 MODULE_FIRMWARE(MT7922_ROM_PATCH);
546 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
547 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
548 MODULE_LICENSE("Dual BSD/GPL");
549 #if defined(__FreeBSD__)
550 MODULE_VERSION(mt7921_pci, 1);
551 MODULE_DEPEND(mt7921_pci, linuxkpi, 1, 1, 1);
552 MODULE_DEPEND(mt7921_pci, linuxkpi_wlan, 1, 1, 1);
553 MODULE_DEPEND(mt7921_pci, mt76_core, 1, 1, 1);
554 #endif
555