1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. 3 * 4 */ 5 6 #if defined(__FreeBSD__) 7 #define LINUXKPI_PARAM_PREFIX mt7921_pci_ 8 #endif 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/pci.h> 13 #include <linux/of.h> 14 15 #include "mt7921.h" 16 #include "../mt76_connac2_mac.h" 17 #include "../dma.h" 18 #include "mcu.h" 19 20 static const struct pci_device_id mt7921_pci_device_table[] = { 21 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961), 22 .driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM }, 23 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922), 24 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM }, 25 { PCI_DEVICE(PCI_VENDOR_ID_ITTIM, 0x7922), 26 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM }, 27 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608), 28 .driver_data = (kernel_ulong_t)MT7921_FIRMWARE_WM }, 29 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616), 30 .driver_data = (kernel_ulong_t)MT7922_FIRMWARE_WM }, 31 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7920), 32 .driver_data = (kernel_ulong_t)MT7920_FIRMWARE_WM }, 33 { }, 34 }; 35 36 static bool mt7921_disable_aspm; 37 module_param_named(disable_aspm, mt7921_disable_aspm, bool, 0644); 38 MODULE_PARM_DESC(disable_aspm, "disable PCI ASPM support"); 39 40 static int mt7921e_init_reset(struct mt792x_dev *dev) 41 { 42 return mt792x_wpdma_reset(dev, true); 43 } 44 45 static void mt7921e_unregister_device(struct mt792x_dev *dev) 46 { 47 int i; 48 struct mt76_connac_pm *pm = &dev->pm; 49 struct ieee80211_hw *hw = mt76_hw(dev); 50 51 if (dev->phy.chip_cap & MT792x_CHIP_CAP_WF_RF_PIN_CTRL_EVT_EN) 52 wiphy_rfkill_stop_polling(hw->wiphy); 53 54 cancel_work_sync(&dev->init_work); 55 mt76_unregister_device(&dev->mt76); 56 mt76_for_each_q_rx(&dev->mt76, i) 57 napi_disable(&dev->mt76.napi[i]); 58 cancel_delayed_work_sync(&pm->ps_work); 59 cancel_work_sync(&pm->wake_work); 60 cancel_work_sync(&dev->reset_work); 61 62 mt76_connac2_tx_token_put(&dev->mt76); 63 __mt792x_mcu_drv_pmctrl(dev); 64 mt792x_dma_cleanup(dev); 65 mt792x_wfsys_reset(dev); 66 skb_queue_purge(&dev->mt76.mcu.res_q); 67 68 tasklet_disable(&dev->mt76.irq_tasklet); 69 } 70 71 static u32 __mt7921_reg_addr(struct mt792x_dev *dev, u32 addr) 72 { 73 static const struct mt76_connac_reg_map fixed_map[] = { 74 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ 75 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ 76 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ 77 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ 78 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ 79 { 0x820e2000, 0x20800, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */ 80 { 0x820e3000, 0x20c00, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */ 81 { 0x820e5000, 0x21400, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */ 82 { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */ 83 { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */ 84 { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */ 85 { 0x54000000, 0x02000, 0x01000 }, /* WFDMA PCIE0 MCU DMA0 */ 86 { 0x55000000, 0x03000, 0x01000 }, /* WFDMA PCIE0 MCU DMA1 */ 87 { 0x58000000, 0x06000, 0x01000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */ 88 { 0x59000000, 0x07000, 0x01000 }, /* WFDMA PCIE1 MCU DMA1 */ 89 { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */ 90 { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */ 91 { 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */ 92 { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */ 93 { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */ 94 { 0x820c0000, 0x08000, 0x04000 }, /* WF_UMAC_TOP (PLE) */ 95 { 0x820c8000, 0x0c000, 0x02000 }, /* WF_UMAC_TOP (PSE) */ 96 { 0x820cc000, 0x0e000, 0x01000 }, /* WF_UMAC_TOP (PP) */ 97 { 0x820cd000, 0x0f000, 0x01000 }, /* WF_MDP_TOP */ 98 { 0x74030000, 0x10000, 0x10000 }, /* PCIE_MAC_IREG */ 99 { 0x820ce000, 0x21c00, 0x00200 }, /* WF_LMAC_TOP (WF_SEC) */ 100 { 0x820cf000, 0x22000, 0x01000 }, /* WF_LMAC_TOP (WF_PF) */ 101 { 0x820e0000, 0x20000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */ 102 { 0x820e1000, 0x20400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */ 103 { 0x820e9000, 0x23400, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */ 104 { 0x820ea000, 0x24000, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */ 105 { 0x820ec000, 0x24600, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_INT) */ 106 { 0x820f0000, 0xa0000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */ 107 { 0x820f1000, 0xa0600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */ 108 { 0x820f2000, 0xa0800, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */ 109 { 0x820f3000, 0xa0c00, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */ 110 { 0x820f4000, 0xa1000, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */ 111 { 0x820f5000, 0xa1400, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */ 112 { 0x820f7000, 0xa1e00, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */ 113 { 0x820f9000, 0xa3400, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */ 114 { 0x820fa000, 0xa4000, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */ 115 { 0x820fb000, 0xa4200, 0x00400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */ 116 { 0x820fc000, 0xa4600, 0x00200 }, /* WF_LMAC_TOP BN1 (WF_INT) */ 117 { 0x820fd000, 0xa4800, 0x00800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */ 118 }; 119 int i; 120 121 if (addr < 0x100000) 122 return addr; 123 124 for (i = 0; i < ARRAY_SIZE(fixed_map); i++) { 125 u32 ofs; 126 127 if (addr < fixed_map[i].phys) 128 continue; 129 130 ofs = addr - fixed_map[i].phys; 131 if (ofs > fixed_map[i].size) 132 continue; 133 134 return fixed_map[i].maps + ofs; 135 } 136 137 if ((addr >= 0x18000000 && addr < 0x18c00000) || 138 (addr >= 0x70000000 && addr < 0x78000000) || 139 (addr >= 0x7c000000 && addr < 0x7c400000)) 140 return mt7921_reg_map_l1(dev, addr); 141 142 dev_err(dev->mt76.dev, "Access currently unsupported address %08x\n", 143 addr); 144 145 return 0; 146 } 147 148 static u32 mt7921_rr(struct mt76_dev *mdev, u32 offset) 149 { 150 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 151 u32 addr = __mt7921_reg_addr(dev, offset); 152 153 return dev->bus_ops->rr(mdev, addr); 154 } 155 156 static void mt7921_wr(struct mt76_dev *mdev, u32 offset, u32 val) 157 { 158 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 159 u32 addr = __mt7921_reg_addr(dev, offset); 160 161 dev->bus_ops->wr(mdev, addr, val); 162 } 163 164 static u32 mt7921_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val) 165 { 166 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 167 u32 addr = __mt7921_reg_addr(dev, offset); 168 169 return dev->bus_ops->rmw(mdev, addr, mask, val); 170 } 171 172 static int mt7921_dma_init(struct mt792x_dev *dev) 173 { 174 int ret; 175 176 mt76_dma_attach(&dev->mt76); 177 178 ret = mt792x_dma_disable(dev, true); 179 if (ret) 180 return ret; 181 182 /* init tx queue */ 183 ret = mt76_connac_init_tx_queues(dev->phy.mt76, MT7921_TXQ_BAND0, 184 MT7921_TX_RING_SIZE, 185 MT_TX_RING_BASE, NULL, 0); 186 if (ret) 187 return ret; 188 189 mt76_wr(dev, MT_WFDMA0_TX_RING0_EXT_CTRL, 0x4); 190 191 /* command to WM */ 192 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_WM, MT7921_TXQ_MCU_WM, 193 MT7921_TX_MCU_RING_SIZE, MT_TX_RING_BASE); 194 if (ret) 195 return ret; 196 197 /* firmware download */ 198 ret = mt76_init_mcu_queue(&dev->mt76, MT_MCUQ_FWDL, MT7921_TXQ_FWDL, 199 MT7921_TX_FWDL_RING_SIZE, MT_TX_RING_BASE); 200 if (ret) 201 return ret; 202 203 /* event from WM before firmware download */ 204 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU], 205 MT7921_RXQ_MCU_WM, 206 MT7921_RX_MCU_RING_SIZE, 207 MT_RX_BUF_SIZE, MT_RX_EVENT_RING_BASE); 208 if (ret) 209 return ret; 210 211 /* Change mcu queue after firmware download */ 212 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA], 213 MT7921_RXQ_MCU_WM, 214 MT7921_RX_MCU_WA_RING_SIZE, 215 MT_RX_BUF_SIZE, MT_WFDMA0(0x540)); 216 if (ret) 217 return ret; 218 219 /* rx data */ 220 ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], 221 MT7921_RXQ_BAND0, MT7921_RX_RING_SIZE, 222 MT_RX_BUF_SIZE, MT_RX_DATA_RING_BASE); 223 if (ret) 224 return ret; 225 226 ret = mt76_init_queues(dev, mt792x_poll_rx); 227 if (ret < 0) 228 return ret; 229 230 netif_napi_add_tx(dev->mt76.tx_napi_dev, &dev->mt76.tx_napi, 231 mt792x_poll_tx); 232 napi_enable(&dev->mt76.tx_napi); 233 234 return mt792x_dma_enable(dev); 235 } 236 237 static int mt7921_pci_probe(struct pci_dev *pdev, 238 const struct pci_device_id *id) 239 { 240 static const struct mt76_driver_ops drv_ops = { 241 /* txwi_size = txd size + txp size */ 242 .txwi_size = MT_TXD_SIZE + sizeof(struct mt76_connac_hw_txp), 243 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ | 244 MT_DRV_AMSDU_OFFLOAD, 245 .survey_flags = SURVEY_INFO_TIME_TX | 246 SURVEY_INFO_TIME_RX | 247 SURVEY_INFO_TIME_BSS_RX, 248 .token_size = MT7921_TOKEN_SIZE, 249 .tx_prepare_skb = mt7921e_tx_prepare_skb, 250 .tx_complete_skb = mt76_connac_tx_complete_skb, 251 .rx_check = mt7921_rx_check, 252 .rx_skb = mt7921_queue_rx_skb, 253 .rx_poll_complete = mt792x_rx_poll_complete, 254 .sta_add = mt7921_mac_sta_add, 255 .sta_event = mt7921_mac_sta_event, 256 .sta_remove = mt7921_mac_sta_remove, 257 .update_survey = mt792x_update_channel, 258 .set_channel = mt7921_set_channel, 259 }; 260 static const struct mt792x_hif_ops mt7921_pcie_ops = { 261 .init_reset = mt7921e_init_reset, 262 .reset = mt7921e_mac_reset, 263 .mcu_init = mt7921e_mcu_init, 264 .drv_own = mt792xe_mcu_drv_pmctrl, 265 .fw_own = mt792xe_mcu_fw_pmctrl, 266 }; 267 static const struct mt792x_irq_map irq_map = { 268 .host_irq_enable = MT_WFDMA0_HOST_INT_ENA, 269 .tx = { 270 .all_complete_mask = MT_INT_TX_DONE_ALL, 271 .mcu_complete_mask = MT_INT_TX_DONE_MCU, 272 }, 273 .rx = { 274 .data_complete_mask = MT_INT_RX_DONE_DATA, 275 .wm_complete_mask = MT_INT_RX_DONE_WM, 276 .wm2_complete_mask = MT_INT_RX_DONE_WM2, 277 }, 278 }; 279 struct ieee80211_ops *ops; 280 struct mt76_bus_ops *bus_ops; 281 struct mt792x_dev *dev; 282 struct mt76_dev *mdev; 283 u16 cmd, chipid; 284 u8 features; 285 int ret; 286 287 ret = pcim_enable_device(pdev); 288 if (ret) 289 return ret; 290 291 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); 292 if (ret) 293 return ret; 294 295 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 296 if (!(cmd & PCI_COMMAND_MEMORY)) { 297 cmd |= PCI_COMMAND_MEMORY; 298 pci_write_config_word(pdev, PCI_COMMAND, cmd); 299 } 300 pci_set_master(pdev); 301 302 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 303 if (ret < 0) 304 return ret; 305 306 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 307 if (ret) 308 goto err_free_pci_vec; 309 310 if (mt7921_disable_aspm) 311 mt76_pci_disable_aspm(pdev); 312 313 ops = mt792x_get_mac80211_ops(&pdev->dev, &mt7921_ops, 314 (void *)id->driver_data, &features); 315 if (!ops) { 316 ret = -ENOMEM; 317 goto err_free_pci_vec; 318 } 319 320 mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), ops, &drv_ops); 321 if (!mdev) { 322 ret = -ENOMEM; 323 goto err_free_pci_vec; 324 } 325 326 pci_set_drvdata(pdev, mdev); 327 328 dev = container_of(mdev, struct mt792x_dev, mt76); 329 dev->fw_features = features; 330 dev->hif_ops = &mt7921_pcie_ops; 331 dev->irq_map = &irq_map; 332 mt76_mmio_init(&dev->mt76, pcim_iomap_table(pdev)[0]); 333 tasklet_init(&mdev->irq_tasklet, mt792x_irq_tasklet, (unsigned long)dev); 334 335 dev->phy.dev = dev; 336 dev->phy.mt76 = &dev->mt76.phy; 337 dev->mt76.phy.priv = &dev->phy; 338 dev->bus_ops = dev->mt76.bus; 339 bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops), 340 GFP_KERNEL); 341 if (!bus_ops) { 342 ret = -ENOMEM; 343 goto err_free_dev; 344 } 345 346 bus_ops->rr = mt7921_rr; 347 bus_ops->wr = mt7921_wr; 348 bus_ops->rmw = mt7921_rmw; 349 dev->mt76.bus = bus_ops; 350 351 if (!mt7921_disable_aspm && mt76_pci_aspm_supported(pdev)) 352 dev->aspm_supported = true; 353 354 ret = mt792xe_mcu_fw_pmctrl(dev); 355 if (ret) 356 goto err_free_dev; 357 358 ret = __mt792xe_mcu_drv_pmctrl(dev); 359 if (ret) 360 goto err_free_dev; 361 362 chipid = mt7921_l1_rr(dev, MT_HW_CHIPID); 363 if (chipid == 0x7961 && (mt7921_l1_rr(dev, MT_HW_BOUND) & BIT(7))) 364 chipid = 0x7920; 365 mdev->rev = (chipid << 16) | 366 (mt7921_l1_rr(dev, MT_HW_REV) & 0xff); 367 dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev); 368 369 ret = mt792x_wfsys_reset(dev); 370 if (ret) 371 goto err_free_dev; 372 373 mt76_wr(dev, irq_map.host_irq_enable, 0); 374 375 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 376 377 ret = devm_request_irq(mdev->dev, pdev->irq, mt792x_irq_handler, 378 IRQF_SHARED, KBUILD_MODNAME, dev); 379 if (ret) 380 goto err_free_dev; 381 382 ret = mt7921_dma_init(dev); 383 if (ret) 384 goto err_free_irq; 385 386 ret = mt7921_register_device(dev); 387 if (ret) 388 goto err_free_irq; 389 390 #if defined(CONFIG_OF) 391 if (of_property_read_bool(dev->mt76.dev->of_node, "wakeup-source")) 392 device_init_wakeup(dev->mt76.dev, true); 393 #endif 394 395 return 0; 396 397 err_free_irq: 398 devm_free_irq(&pdev->dev, pdev->irq, dev); 399 err_free_dev: 400 mt76_free_device(&dev->mt76); 401 err_free_pci_vec: 402 pci_free_irq_vectors(pdev); 403 404 return ret; 405 } 406 407 static void mt7921_pci_remove(struct pci_dev *pdev) 408 { 409 struct mt76_dev *mdev = pci_get_drvdata(pdev); 410 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 411 412 #if defined(CONFIG_OF) 413 if (of_property_read_bool(dev->mt76.dev->of_node, "wakeup-source")) 414 device_init_wakeup(dev->mt76.dev, false); 415 #endif 416 417 mt7921e_unregister_device(dev); 418 set_bit(MT76_REMOVED, &mdev->phy.state); 419 devm_free_irq(&pdev->dev, pdev->irq, dev); 420 mt76_free_device(&dev->mt76); 421 pci_free_irq_vectors(pdev); 422 } 423 424 #if !defined(__FreeBSD__) || defined(CONFIG_PM_SLEEP) 425 static int mt7921_pci_suspend(struct device *device) 426 { 427 struct pci_dev *pdev = to_pci_dev(device); 428 struct mt76_dev *mdev = pci_get_drvdata(pdev); 429 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 430 struct mt76_connac_pm *pm = &dev->pm; 431 int i, err; 432 433 pm->suspended = true; 434 flush_work(&dev->reset_work); 435 cancel_delayed_work_sync(&pm->ps_work); 436 cancel_work_sync(&pm->wake_work); 437 438 mt7921_roc_abort_sync(dev); 439 440 err = mt792x_mcu_drv_pmctrl(dev); 441 if (err < 0) 442 goto restore_suspend; 443 444 wait_event_timeout(dev->wait, 445 !dev->regd_in_progress, 5 * HZ); 446 447 err = mt7921_mcu_radio_led_ctrl(dev, EXT_CMD_RADIO_OFF_LED); 448 if (err < 0) 449 goto restore_suspend; 450 451 err = mt76_connac_mcu_set_hif_suspend(mdev, true, true); 452 if (err) 453 goto restore_suspend; 454 455 /* always enable deep sleep during suspend to reduce 456 * power consumption 457 */ 458 mt76_connac_mcu_set_deep_sleep(&dev->mt76, true); 459 460 napi_disable(&mdev->tx_napi); 461 mt76_worker_disable(&mdev->tx_worker); 462 463 mt76_for_each_q_rx(mdev, i) { 464 napi_disable(&mdev->napi[i]); 465 } 466 467 /* wait until dma is idle */ 468 mt76_poll(dev, MT_WFDMA0_GLO_CFG, 469 MT_WFDMA0_GLO_CFG_TX_DMA_BUSY | 470 MT_WFDMA0_GLO_CFG_RX_DMA_BUSY, 0, 1000); 471 472 /* put dma disabled */ 473 mt76_clear(dev, MT_WFDMA0_GLO_CFG, 474 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 475 476 /* disable interrupt */ 477 mt76_wr(dev, dev->irq_map->host_irq_enable, 0); 478 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0); 479 synchronize_irq(pdev->irq); 480 tasklet_kill(&mdev->irq_tasklet); 481 482 err = mt792x_mcu_fw_pmctrl(dev); 483 if (err) 484 goto restore_napi; 485 486 return 0; 487 488 restore_napi: 489 mt76_for_each_q_rx(mdev, i) { 490 napi_enable(&mdev->napi[i]); 491 } 492 napi_enable(&mdev->tx_napi); 493 494 if (!pm->ds_enable) 495 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false); 496 497 mt76_connac_mcu_set_hif_suspend(mdev, false, true); 498 499 restore_suspend: 500 pm->suspended = false; 501 502 if (err < 0) 503 mt792x_reset(&dev->mt76); 504 505 return err; 506 } 507 508 static int mt7921_pci_resume(struct device *device) 509 { 510 struct pci_dev *pdev = to_pci_dev(device); 511 struct mt76_dev *mdev = pci_get_drvdata(pdev); 512 struct mt792x_dev *dev = container_of(mdev, struct mt792x_dev, mt76); 513 struct mt76_connac_pm *pm = &dev->pm; 514 int i, err; 515 516 err = mt792x_mcu_drv_pmctrl(dev); 517 if (err < 0) 518 goto failed; 519 520 mt792x_wpdma_reinit_cond(dev); 521 522 /* enable interrupt */ 523 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 524 mt76_connac_irq_enable(&dev->mt76, 525 dev->irq_map->tx.all_complete_mask | 526 MT_INT_RX_DONE_ALL | MT_INT_MCU_CMD); 527 mt76_set(dev, MT_MCU2HOST_SW_INT_ENA, MT_MCU_CMD_WAKE_RX_PCIE); 528 529 /* put dma enabled */ 530 mt76_set(dev, MT_WFDMA0_GLO_CFG, 531 MT_WFDMA0_GLO_CFG_TX_DMA_EN | MT_WFDMA0_GLO_CFG_RX_DMA_EN); 532 533 mt76_worker_enable(&mdev->tx_worker); 534 535 mt76_for_each_q_rx(mdev, i) { 536 napi_enable(&mdev->napi[i]); 537 } 538 napi_enable(&mdev->tx_napi); 539 540 local_bh_disable(); 541 mt76_for_each_q_rx(mdev, i) { 542 napi_schedule(&mdev->napi[i]); 543 } 544 napi_schedule(&mdev->tx_napi); 545 local_bh_enable(); 546 547 /* restore previous ds setting */ 548 if (!pm->ds_enable) 549 mt76_connac_mcu_set_deep_sleep(&dev->mt76, false); 550 551 err = mt76_connac_mcu_set_hif_suspend(mdev, false, true); 552 if (err < 0) 553 goto failed; 554 555 mt7921_regd_update(dev); 556 err = mt7921_mcu_radio_led_ctrl(dev, EXT_CMD_RADIO_ON_LED); 557 failed: 558 pm->suspended = false; 559 560 if (err < 0) 561 mt792x_reset(&dev->mt76); 562 563 return err; 564 } 565 #endif 566 567 static void mt7921_pci_shutdown(struct pci_dev *pdev) 568 { 569 mt7921_pci_remove(pdev); 570 } 571 572 static DEFINE_SIMPLE_DEV_PM_OPS(mt7921_pm_ops, mt7921_pci_suspend, mt7921_pci_resume); 573 574 static struct pci_driver mt7921_pci_driver = { 575 .name = KBUILD_MODNAME, 576 .id_table = mt7921_pci_device_table, 577 .probe = mt7921_pci_probe, 578 .remove = mt7921_pci_remove, 579 .shutdown = mt7921_pci_shutdown, 580 .driver.pm = pm_sleep_ptr(&mt7921_pm_ops), 581 }; 582 583 module_pci_driver(mt7921_pci_driver); 584 585 MODULE_DEVICE_TABLE(pci, mt7921_pci_device_table); 586 MODULE_FIRMWARE(MT7920_FIRMWARE_WM); 587 MODULE_FIRMWARE(MT7920_ROM_PATCH); 588 MODULE_FIRMWARE(MT7921_FIRMWARE_WM); 589 MODULE_FIRMWARE(MT7921_ROM_PATCH); 590 MODULE_FIRMWARE(MT7922_FIRMWARE_WM); 591 MODULE_FIRMWARE(MT7922_ROM_PATCH); 592 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 593 MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 594 MODULE_DESCRIPTION("MediaTek MT7921E (PCIe) wireless driver"); 595 MODULE_LICENSE("Dual BSD/GPL"); 596 #if defined(__FreeBSD__) 597 MODULE_VERSION(mt7921_pci, 1); 598 MODULE_DEPEND(mt7921_pci, linuxkpi, 1, 1, 1); 599 MODULE_DEPEND(mt7921_pci, linuxkpi_wlan, 1, 1, 1); 600 MODULE_DEPEND(mt7921_pci, mt76_core, 1, 1, 1); 601 #endif 602