1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/timekeeping.h> 6 #if defined(__FreeBSD__) 7 #include <linux/delay.h> 8 #include <linux/math64.h> 9 #endif 10 #include "coredump.h" 11 #include "mt7915.h" 12 #include "../dma.h" 13 #include "mac.h" 14 #include "mcu.h" 15 16 #define to_rssi(field, rcpi) ((FIELD_GET(field, rcpi) - 220) / 2) 17 18 static const struct mt7915_dfs_radar_spec etsi_radar_specs = { 19 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 20 .radar_pattern = { 21 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 }, 22 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 }, 23 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 }, 24 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 }, 25 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 }, 26 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 }, 27 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 }, 28 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 }, 29 }, 30 }; 31 32 static const struct mt7915_dfs_radar_spec fcc_radar_specs = { 33 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 34 .radar_pattern = { 35 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 36 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 37 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 38 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 39 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 40 }, 41 }; 42 43 static const struct mt7915_dfs_radar_spec jp_radar_specs = { 44 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 45 .radar_pattern = { 46 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 47 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 48 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 49 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 50 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 51 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 }, 52 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 }, 53 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 }, 54 }, 55 }; 56 57 static struct mt76_wcid *mt7915_rx_get_wcid(struct mt7915_dev *dev, 58 u16 idx, bool unicast) 59 { 60 struct mt7915_sta *sta; 61 struct mt76_wcid *wcid; 62 63 if (idx >= ARRAY_SIZE(dev->mt76.wcid)) 64 return NULL; 65 66 wcid = rcu_dereference(dev->mt76.wcid[idx]); 67 if (unicast || !wcid) 68 return wcid; 69 70 if (!wcid->sta) 71 return NULL; 72 73 sta = container_of(wcid, struct mt7915_sta, wcid); 74 if (!sta->vif) 75 return NULL; 76 77 return &sta->vif->sta.wcid; 78 } 79 80 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask) 81 { 82 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 83 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 84 85 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 86 0, 5000); 87 } 88 89 u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw) 90 { 91 mt76_wr(dev, MT_WTBLON_TOP_WDUCR, 92 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7))); 93 94 return MT_WTBL_LMAC_OFFS(wcid, dw); 95 } 96 97 static void mt7915_mac_sta_poll(struct mt7915_dev *dev) 98 { 99 static const u8 ac_to_tid[] = { 100 [IEEE80211_AC_BE] = 0, 101 [IEEE80211_AC_BK] = 1, 102 [IEEE80211_AC_VI] = 4, 103 [IEEE80211_AC_VO] = 6 104 }; 105 struct ieee80211_sta *sta; 106 struct mt7915_sta *msta; 107 struct rate_info *rate; 108 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS]; 109 #if defined(__linux__) 110 LIST_HEAD(sta_poll_list); 111 #elif defined(__FreeBSD__) 112 LINUX_LIST_HEAD(sta_poll_list); 113 #endif 114 int i; 115 116 spin_lock_bh(&dev->mt76.sta_poll_lock); 117 list_splice_init(&dev->mt76.sta_poll_list, &sta_poll_list); 118 spin_unlock_bh(&dev->mt76.sta_poll_lock); 119 120 rcu_read_lock(); 121 122 while (true) { 123 bool clear = false; 124 u32 addr, val; 125 u16 idx; 126 s8 rssi[4]; 127 u8 bw; 128 129 spin_lock_bh(&dev->mt76.sta_poll_lock); 130 if (list_empty(&sta_poll_list)) { 131 spin_unlock_bh(&dev->mt76.sta_poll_lock); 132 break; 133 } 134 msta = list_first_entry(&sta_poll_list, 135 struct mt7915_sta, wcid.poll_list); 136 list_del_init(&msta->wcid.poll_list); 137 spin_unlock_bh(&dev->mt76.sta_poll_lock); 138 139 idx = msta->wcid.idx; 140 141 /* refresh peer's airtime reporting */ 142 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 20); 143 144 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 145 u32 tx_last = msta->airtime_ac[i]; 146 u32 rx_last = msta->airtime_ac[i + 4]; 147 148 msta->airtime_ac[i] = mt76_rr(dev, addr); 149 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 150 151 if (msta->airtime_ac[i] <= tx_last) 152 tx_time[i] = 0; 153 else 154 tx_time[i] = msta->airtime_ac[i] - tx_last; 155 156 if (msta->airtime_ac[i + 4] <= rx_last) 157 rx_time[i] = 0; 158 else 159 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 160 161 if ((tx_last | rx_last) & BIT(30)) 162 clear = true; 163 164 addr += 8; 165 } 166 167 if (clear) { 168 mt7915_mac_wtbl_update(dev, idx, 169 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 170 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 171 } 172 173 if (!msta->wcid.sta) 174 continue; 175 176 sta = container_of((void *)msta, struct ieee80211_sta, 177 drv_priv); 178 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 179 u8 queue = mt76_connac_lmac_mapping(i); 180 u32 tx_cur = tx_time[queue]; 181 u32 rx_cur = rx_time[queue]; 182 u8 tid = ac_to_tid[i]; 183 184 if (!tx_cur && !rx_cur) 185 continue; 186 187 ieee80211_sta_register_airtime(sta, tid, tx_cur, 188 rx_cur); 189 } 190 191 /* 192 * We don't support reading GI info from txs packets. 193 * For accurate tx status reporting and AQL improvement, 194 * we need to make sure that flags match so polling GI 195 * from per-sta counters directly. 196 */ 197 rate = &msta->wcid.rate; 198 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 7); 199 val = mt76_rr(dev, addr); 200 201 switch (rate->bw) { 202 case RATE_INFO_BW_160: 203 bw = IEEE80211_STA_RX_BW_160; 204 break; 205 case RATE_INFO_BW_80: 206 bw = IEEE80211_STA_RX_BW_80; 207 break; 208 case RATE_INFO_BW_40: 209 bw = IEEE80211_STA_RX_BW_40; 210 break; 211 default: 212 bw = IEEE80211_STA_RX_BW_20; 213 break; 214 } 215 216 if (rate->flags & RATE_INFO_FLAGS_HE_MCS) { 217 u8 offs = 24 + 2 * bw; 218 219 rate->he_gi = (val & (0x3 << offs)) >> offs; 220 } else if (rate->flags & 221 (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) { 222 if (val & BIT(12 + bw)) 223 rate->flags |= RATE_INFO_FLAGS_SHORT_GI; 224 else 225 rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI; 226 } 227 228 /* get signal strength of resp frames (CTS/BA/ACK) */ 229 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 30); 230 val = mt76_rr(dev, addr); 231 232 rssi[0] = to_rssi(GENMASK(7, 0), val); 233 rssi[1] = to_rssi(GENMASK(15, 8), val); 234 rssi[2] = to_rssi(GENMASK(23, 16), val); 235 rssi[3] = to_rssi(GENMASK(31, 14), val); 236 237 msta->ack_signal = 238 mt76_rx_signal(msta->vif->phy->mt76->antenna_mask, rssi); 239 240 ewma_avg_signal_add(&msta->avg_ack_signal, -msta->ack_signal); 241 } 242 243 rcu_read_unlock(); 244 } 245 246 void mt7915_mac_enable_rtscts(struct mt7915_dev *dev, 247 struct ieee80211_vif *vif, bool enable) 248 { 249 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 250 u32 addr; 251 252 addr = mt7915_mac_wtbl_lmac_addr(dev, mvif->sta.wcid.idx, 5); 253 if (enable) 254 mt76_set(dev, addr, BIT(5)); 255 else 256 mt76_clear(dev, addr, BIT(5)); 257 } 258 259 static void 260 mt7915_wed_check_ppe(struct mt7915_dev *dev, struct mt76_queue *q, 261 struct mt7915_sta *msta, struct sk_buff *skb, 262 u32 info) 263 { 264 struct ieee80211_vif *vif; 265 struct wireless_dev *wdev; 266 267 if (!msta || !msta->vif) 268 return; 269 270 if (!mt76_queue_is_wed_rx(q)) 271 return; 272 273 if (!(info & MT_DMA_INFO_PPE_VLD)) 274 return; 275 276 vif = container_of((void *)msta->vif, struct ieee80211_vif, 277 drv_priv); 278 wdev = ieee80211_vif_to_wdev(vif); 279 skb->dev = wdev->netdev; 280 281 mtk_wed_device_ppe_check(&dev->mt76.mmio.wed, skb, 282 FIELD_GET(MT_DMA_PPE_CPU_REASON, info), 283 FIELD_GET(MT_DMA_PPE_ENTRY, info)); 284 } 285 286 static int 287 mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb, 288 enum mt76_rxq_id q, u32 *info) 289 { 290 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 291 struct mt76_phy *mphy = &dev->mt76.phy; 292 struct mt7915_phy *phy = &dev->phy; 293 struct ieee80211_supported_band *sband; 294 __le32 *rxd = (__le32 *)skb->data; 295 __le32 *rxv = NULL; 296 u32 rxd0 = le32_to_cpu(rxd[0]); 297 u32 rxd1 = le32_to_cpu(rxd[1]); 298 u32 rxd2 = le32_to_cpu(rxd[2]); 299 u32 rxd3 = le32_to_cpu(rxd[3]); 300 u32 rxd4 = le32_to_cpu(rxd[4]); 301 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 302 bool unicast, insert_ccmp_hdr = false; 303 u8 remove_pad, amsdu_info; 304 u8 mode = 0, qos_ctl = 0; 305 struct mt7915_sta *msta = NULL; 306 u32 csum_status = *(u32 *)skb->cb; 307 bool hdr_trans; 308 u16 hdr_gap; 309 u16 seq_ctrl = 0; 310 __le16 fc = 0; 311 int idx; 312 313 memset(status, 0, sizeof(*status)); 314 315 if ((rxd1 & MT_RXD1_NORMAL_BAND_IDX) && !phy->mt76->band_idx) { 316 mphy = dev->mt76.phys[MT_BAND1]; 317 if (!mphy) 318 return -EINVAL; 319 320 phy = mphy->priv; 321 status->phy_idx = 1; 322 } 323 324 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 325 return -EINVAL; 326 327 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 328 return -EINVAL; 329 330 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS; 331 if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM)) 332 return -EINVAL; 333 334 /* ICV error or CCMP/BIP/WPI MIC error */ 335 if (rxd1 & MT_RXD1_NORMAL_ICV_ERR) 336 status->flag |= RX_FLAG_ONLY_MONITOR; 337 338 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M; 339 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1); 340 status->wcid = mt7915_rx_get_wcid(dev, idx, unicast); 341 342 if (status->wcid) { 343 msta = container_of(status->wcid, struct mt7915_sta, wcid); 344 mt76_wcid_add_poll(&dev->mt76, &msta->wcid); 345 } 346 347 status->freq = mphy->chandef.chan->center_freq; 348 status->band = mphy->chandef.chan->band; 349 if (status->band == NL80211_BAND_5GHZ) 350 sband = &mphy->sband_5g.sband; 351 else if (status->band == NL80211_BAND_6GHZ) 352 sband = &mphy->sband_6g.sband; 353 else 354 sband = &mphy->sband_2g.sband; 355 356 if (!sband->channels) 357 return -EINVAL; 358 359 if ((rxd0 & csum_mask) == csum_mask && 360 !(csum_status & (BIT(0) | BIT(2) | BIT(3)))) 361 skb->ip_summed = CHECKSUM_UNNECESSARY; 362 363 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR) 364 status->flag |= RX_FLAG_FAILED_FCS_CRC; 365 366 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR) 367 status->flag |= RX_FLAG_MMIC_ERROR; 368 369 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 && 370 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) { 371 status->flag |= RX_FLAG_DECRYPTED; 372 status->flag |= RX_FLAG_IV_STRIPPED; 373 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 374 } 375 376 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2); 377 378 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 379 return -EINVAL; 380 381 rxd += 6; 382 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { 383 u32 v0 = le32_to_cpu(rxd[0]); 384 u32 v2 = le32_to_cpu(rxd[2]); 385 386 fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0)); 387 qos_ctl = FIELD_GET(MT_RXD8_QOS_CTL, v2); 388 seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2); 389 390 rxd += 4; 391 if ((u8 *)rxd - skb->data >= skb->len) 392 return -EINVAL; 393 } 394 395 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { 396 u8 *data = (u8 *)rxd; 397 398 if (status->flag & RX_FLAG_DECRYPTED) { 399 switch (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1)) { 400 case MT_CIPHER_AES_CCMP: 401 case MT_CIPHER_CCMP_CCX: 402 case MT_CIPHER_CCMP_256: 403 insert_ccmp_hdr = 404 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 405 fallthrough; 406 case MT_CIPHER_TKIP: 407 case MT_CIPHER_TKIP_NO_MIC: 408 case MT_CIPHER_GCMP: 409 case MT_CIPHER_GCMP_256: 410 status->iv[0] = data[5]; 411 status->iv[1] = data[4]; 412 status->iv[2] = data[3]; 413 status->iv[3] = data[2]; 414 status->iv[4] = data[1]; 415 status->iv[5] = data[0]; 416 break; 417 default: 418 break; 419 } 420 } 421 rxd += 4; 422 if ((u8 *)rxd - skb->data >= skb->len) 423 return -EINVAL; 424 } 425 426 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { 427 status->timestamp = le32_to_cpu(rxd[0]); 428 status->flag |= RX_FLAG_MACTIME_START; 429 430 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) { 431 status->flag |= RX_FLAG_AMPDU_DETAILS; 432 433 /* all subframes of an A-MPDU have the same timestamp */ 434 if (phy->rx_ampdu_ts != status->timestamp) { 435 if (!++phy->ampdu_ref) 436 phy->ampdu_ref++; 437 } 438 phy->rx_ampdu_ts = status->timestamp; 439 440 status->ampdu_ref = phy->ampdu_ref; 441 } 442 443 rxd += 2; 444 if ((u8 *)rxd - skb->data >= skb->len) 445 return -EINVAL; 446 } 447 448 /* RXD Group 3 - P-RXV */ 449 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { 450 u32 v0, v1; 451 int ret; 452 453 rxv = rxd; 454 rxd += 2; 455 if ((u8 *)rxd - skb->data >= skb->len) 456 return -EINVAL; 457 458 v0 = le32_to_cpu(rxv[0]); 459 v1 = le32_to_cpu(rxv[1]); 460 461 if (v0 & MT_PRXV_HT_AD_CODE) 462 status->enc_flags |= RX_ENC_FLAG_LDPC; 463 464 status->chains = mphy->antenna_mask; 465 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1); 466 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1); 467 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1); 468 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1); 469 470 /* RXD Group 5 - C-RXV */ 471 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { 472 rxd += 18; 473 if ((u8 *)rxd - skb->data >= skb->len) 474 return -EINVAL; 475 } 476 477 if (!is_mt7915(&dev->mt76) || (rxd1 & MT_RXD1_NORMAL_GROUP_5)) { 478 ret = mt76_connac2_mac_fill_rx_rate(&dev->mt76, status, 479 sband, rxv, &mode); 480 if (ret < 0) 481 return ret; 482 } 483 } 484 485 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4); 486 status->amsdu = !!amsdu_info; 487 if (status->amsdu) { 488 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME; 489 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME; 490 } 491 492 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; 493 if (hdr_trans && ieee80211_has_morefrags(fc)) { 494 struct ieee80211_vif *vif; 495 int err; 496 497 if (!msta || !msta->vif) 498 return -EINVAL; 499 500 vif = container_of((void *)msta->vif, struct ieee80211_vif, 501 drv_priv); 502 err = mt76_connac2_reverse_frag0_hdr_trans(vif, skb, hdr_gap); 503 if (err) 504 return err; 505 506 hdr_trans = false; 507 } else { 508 int pad_start = 0; 509 510 skb_pull(skb, hdr_gap); 511 if (!hdr_trans && status->amsdu) { 512 pad_start = ieee80211_get_hdrlen_from_skb(skb); 513 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) { 514 /* 515 * When header translation failure is indicated, 516 * the hardware will insert an extra 2-byte field 517 * containing the data length after the protocol 518 * type field. This happens either when the LLC-SNAP 519 * pattern did not match, or if a VLAN header was 520 * detected. 521 */ 522 pad_start = 12; 523 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q) 524 pad_start += 4; 525 else 526 pad_start = 0; 527 } 528 529 if (pad_start) { 530 memmove(skb->data + 2, skb->data, pad_start); 531 skb_pull(skb, 2); 532 } 533 } 534 535 if (!hdr_trans) { 536 struct ieee80211_hdr *hdr; 537 538 if (insert_ccmp_hdr) { 539 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 540 541 mt76_insert_ccmp_hdr(skb, key_id); 542 } 543 544 hdr = mt76_skb_get_hdr(skb); 545 fc = hdr->frame_control; 546 if (ieee80211_is_data_qos(fc)) { 547 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 548 qos_ctl = *ieee80211_get_qos_ctl(hdr); 549 } 550 } else { 551 status->flag |= RX_FLAG_8023; 552 mt7915_wed_check_ppe(dev, &dev->mt76.q_rx[q], msta, skb, 553 *info); 554 } 555 556 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023)) 557 mt76_connac2_mac_decode_he_radiotap(&dev->mt76, skb, rxv, mode); 558 559 if (!status->wcid || !ieee80211_is_data_qos(fc)) 560 return 0; 561 562 status->aggr = unicast && 563 !ieee80211_is_qos_nullfunc(fc); 564 status->qos_ctl = qos_ctl; 565 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 566 567 return 0; 568 } 569 570 static void 571 mt7915_mac_fill_rx_vector(struct mt7915_dev *dev, struct sk_buff *skb) 572 { 573 #ifdef CONFIG_NL80211_TESTMODE 574 struct mt7915_phy *phy = &dev->phy; 575 __le32 *rxd = (__le32 *)skb->data; 576 __le32 *rxv_hdr = rxd + 2; 577 __le32 *rxv = rxd + 4; 578 u32 rcpi, ib_rssi, wb_rssi, v20, v21; 579 u8 band_idx; 580 s32 foe; 581 u8 snr; 582 int i; 583 584 band_idx = le32_get_bits(rxv_hdr[1], MT_RXV_HDR_BAND_IDX); 585 if (band_idx && !phy->mt76->band_idx) { 586 phy = mt7915_ext_phy(dev); 587 if (!phy) 588 goto out; 589 } 590 591 rcpi = le32_to_cpu(rxv[6]); 592 ib_rssi = le32_to_cpu(rxv[7]); 593 wb_rssi = le32_to_cpu(rxv[8]) >> 5; 594 595 for (i = 0; i < 4; i++, rcpi >>= 8, ib_rssi >>= 8, wb_rssi >>= 9) { 596 if (i == 3) 597 wb_rssi = le32_to_cpu(rxv[9]); 598 599 phy->test.last_rcpi[i] = rcpi & 0xff; 600 phy->test.last_ib_rssi[i] = ib_rssi & 0xff; 601 phy->test.last_wb_rssi[i] = wb_rssi & 0xff; 602 } 603 604 v20 = le32_to_cpu(rxv[20]); 605 v21 = le32_to_cpu(rxv[21]); 606 607 foe = FIELD_GET(MT_CRXV_FOE_LO, v20) | 608 (FIELD_GET(MT_CRXV_FOE_HI, v21) << MT_CRXV_FOE_SHIFT); 609 610 snr = FIELD_GET(MT_CRXV_SNR, v20) - 16; 611 612 phy->test.last_freq_offset = foe; 613 phy->test.last_snr = snr; 614 out: 615 #endif 616 dev_kfree_skb(skb); 617 } 618 619 static void 620 mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi, 621 struct sk_buff *skb) 622 { 623 #ifdef CONFIG_NL80211_TESTMODE 624 struct mt76_testmode_data *td = &phy->mt76->test; 625 const struct ieee80211_rate *r; 626 u8 bw, mode, nss = td->tx_rate_nss; 627 u8 rate_idx = td->tx_rate_idx; 628 u16 rateval = 0; 629 u32 val; 630 bool cck = false; 631 int band; 632 633 if (skb != phy->mt76->test.tx_skb) 634 return; 635 636 switch (td->tx_rate_mode) { 637 case MT76_TM_TX_MODE_HT: 638 nss = 1 + (rate_idx >> 3); 639 mode = MT_PHY_TYPE_HT; 640 break; 641 case MT76_TM_TX_MODE_VHT: 642 mode = MT_PHY_TYPE_VHT; 643 break; 644 case MT76_TM_TX_MODE_HE_SU: 645 mode = MT_PHY_TYPE_HE_SU; 646 break; 647 case MT76_TM_TX_MODE_HE_EXT_SU: 648 mode = MT_PHY_TYPE_HE_EXT_SU; 649 break; 650 case MT76_TM_TX_MODE_HE_TB: 651 mode = MT_PHY_TYPE_HE_TB; 652 break; 653 case MT76_TM_TX_MODE_HE_MU: 654 mode = MT_PHY_TYPE_HE_MU; 655 break; 656 case MT76_TM_TX_MODE_CCK: 657 cck = true; 658 fallthrough; 659 case MT76_TM_TX_MODE_OFDM: 660 band = phy->mt76->chandef.chan->band; 661 if (band == NL80211_BAND_2GHZ && !cck) 662 rate_idx += 4; 663 664 r = &phy->mt76->hw->wiphy->bands[band]->bitrates[rate_idx]; 665 val = cck ? r->hw_value_short : r->hw_value; 666 667 mode = val >> 8; 668 rate_idx = val & 0xff; 669 break; 670 default: 671 mode = MT_PHY_TYPE_OFDM; 672 break; 673 } 674 675 switch (phy->mt76->chandef.width) { 676 case NL80211_CHAN_WIDTH_40: 677 bw = 1; 678 break; 679 case NL80211_CHAN_WIDTH_80: 680 bw = 2; 681 break; 682 case NL80211_CHAN_WIDTH_80P80: 683 case NL80211_CHAN_WIDTH_160: 684 bw = 3; 685 break; 686 default: 687 bw = 0; 688 break; 689 } 690 691 if (td->tx_rate_stbc && nss == 1) { 692 nss++; 693 rateval |= MT_TX_RATE_STBC; 694 } 695 696 rateval |= FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | 697 FIELD_PREP(MT_TX_RATE_MODE, mode) | 698 FIELD_PREP(MT_TX_RATE_NSS, nss - 1); 699 700 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); 701 702 le32p_replace_bits(&txwi[3], 1, MT_TXD3_REM_TX_COUNT); 703 if (td->tx_rate_mode < MT76_TM_TX_MODE_HT) 704 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 705 706 val = MT_TXD6_FIXED_BW | 707 FIELD_PREP(MT_TXD6_BW, bw) | 708 FIELD_PREP(MT_TXD6_TX_RATE, rateval) | 709 FIELD_PREP(MT_TXD6_SGI, td->tx_rate_sgi); 710 711 /* for HE_SU/HE_EXT_SU PPDU 712 * - 1x, 2x, 4x LTF + 0.8us GI 713 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 714 * for HE_MU PPDU 715 * - 2x, 4x LTF + 0.8us GI 716 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 717 * for HE_TB PPDU 718 * - 1x, 2x LTF + 1.6us GI 719 * - 4x LTF + 3.2us GI 720 */ 721 if (mode >= MT_PHY_TYPE_HE_SU) 722 val |= FIELD_PREP(MT_TXD6_HELTF, td->tx_ltf); 723 724 if (td->tx_rate_ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU)) 725 val |= MT_TXD6_LDPC; 726 727 txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID); 728 txwi[6] |= cpu_to_le32(val); 729 txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX, 730 phy->test.spe_idx)); 731 #endif 732 } 733 734 void mt7915_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi, 735 struct sk_buff *skb, struct mt76_wcid *wcid, int pid, 736 struct ieee80211_key_conf *key, 737 enum mt76_txq_id qid, u32 changed) 738 { 739 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 740 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 741 struct mt76_phy *mphy = &dev->phy; 742 743 if (phy_idx && dev->phys[MT_BAND1]) 744 mphy = dev->phys[MT_BAND1]; 745 746 mt76_connac2_mac_write_txwi(dev, txwi, skb, wcid, key, pid, qid, changed); 747 748 if (mt76_testmode_enabled(mphy)) 749 mt7915_mac_write_txwi_tm(mphy->priv, txwi, skb); 750 } 751 752 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 753 enum mt76_txq_id qid, struct mt76_wcid *wcid, 754 struct ieee80211_sta *sta, 755 struct mt76_tx_info *tx_info) 756 { 757 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data; 758 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 759 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 760 struct ieee80211_key_conf *key = info->control.hw_key; 761 struct ieee80211_vif *vif = info->control.vif; 762 struct mt76_connac_fw_txp *txp; 763 struct mt76_txwi_cache *t; 764 int id, i, nbuf = tx_info->nbuf - 1; 765 u8 *txwi = (u8 *)txwi_ptr; 766 int pid; 767 768 if (unlikely(tx_info->skb->len <= ETH_HLEN)) 769 return -EINVAL; 770 771 if (!wcid) 772 wcid = &dev->mt76.global_wcid; 773 774 if (sta) { 775 struct mt7915_sta *msta; 776 777 msta = (struct mt7915_sta *)sta->drv_priv; 778 779 if (time_after(jiffies, msta->jiffies + HZ / 4)) { 780 info->flags |= IEEE80211_TX_CTL_REQ_TX_STATUS; 781 msta->jiffies = jiffies; 782 } 783 } 784 785 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size); 786 t->skb = tx_info->skb; 787 788 id = mt76_token_consume(mdev, &t); 789 if (id < 0) 790 return id; 791 792 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); 793 mt7915_mac_write_txwi(mdev, txwi_ptr, tx_info->skb, wcid, pid, key, 794 qid, 0); 795 796 txp = (struct mt76_connac_fw_txp *)(txwi + MT_TXD_SIZE); 797 for (i = 0; i < nbuf; i++) { 798 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr); 799 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len); 800 } 801 txp->nbuf = nbuf; 802 803 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD | MT_CT_INFO_FROM_HOST); 804 805 if (!key) 806 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME); 807 808 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 809 ieee80211_is_mgmt(hdr->frame_control)) 810 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME); 811 812 if (vif) { 813 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 814 815 txp->bss_idx = mvif->mt76.idx; 816 } 817 818 txp->token = cpu_to_le16(id); 819 if (test_bit(MT_WCID_FLAG_4ADDR, &wcid->flags)) 820 txp->rept_wds_wcid = cpu_to_le16(wcid->idx); 821 else 822 txp->rept_wds_wcid = cpu_to_le16(0x3ff); 823 tx_info->skb = NULL; 824 825 /* pass partial skb header to fw */ 826 tx_info->buf[1].len = MT_CT_PARSE_LEN; 827 tx_info->buf[1].skip_unmap = true; 828 tx_info->nbuf = MT_CT_DMA_BUF_NUM; 829 830 return 0; 831 } 832 833 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id) 834 { 835 #if defined(__linux__) 836 struct mt76_connac_fw_txp *txp = ptr + MT_TXD_SIZE; 837 #elif defined(__FreeBSD__) 838 struct mt76_connac_fw_txp *txp = (void *)((u8 *)ptr + MT_TXD_SIZE); 839 #endif 840 __le32 *txwi = ptr; 841 u32 val; 842 843 memset(ptr, 0, MT_TXD_SIZE + sizeof(*txp)); 844 845 val = FIELD_PREP(MT_TXD0_TX_BYTES, MT_TXD_SIZE) | 846 FIELD_PREP(MT_TXD0_PKT_FMT, MT_TX_TYPE_CT); 847 txwi[0] = cpu_to_le32(val); 848 849 val = MT_TXD1_LONG_FORMAT | 850 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3); 851 txwi[1] = cpu_to_le32(val); 852 853 txp->token = cpu_to_le16(token_id); 854 txp->nbuf = 1; 855 txp->buf[0] = cpu_to_le32(phys + MT_TXD_SIZE + sizeof(*txp)); 856 857 return MT_TXD_SIZE + sizeof(*txp); 858 } 859 860 static void 861 mt7915_mac_tx_free_prepare(struct mt7915_dev *dev) 862 { 863 struct mt76_dev *mdev = &dev->mt76; 864 struct mt76_phy *mphy_ext = mdev->phys[MT_BAND1]; 865 866 /* clean DMA queues and unmap buffers first */ 867 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 868 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 869 if (mphy_ext) { 870 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_PSD], false); 871 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false); 872 } 873 } 874 875 static void 876 mt7915_mac_tx_free_done(struct mt7915_dev *dev, 877 struct list_head *free_list, bool wake) 878 { 879 struct sk_buff *skb, *tmp; 880 881 mt7915_mac_sta_poll(dev); 882 883 if (wake) 884 mt76_set_tx_blocked(&dev->mt76, false); 885 886 mt76_worker_schedule(&dev->mt76.tx_worker); 887 888 list_for_each_entry_safe(skb, tmp, free_list, list) { 889 skb_list_del_init(skb); 890 napi_consume_skb(skb, 1); 891 } 892 } 893 894 static void 895 mt7915_mac_tx_free(struct mt7915_dev *dev, void *data, int len) 896 { 897 struct mt76_connac_tx_free *free = data; 898 #if defined(__linux__) 899 __le32 *tx_info = (__le32 *)(data + sizeof(*free)); 900 #elif defined(__FreeBSD__) 901 __le32 *tx_info = (__le32 *)((u8 *)data + sizeof(*free)); 902 #endif 903 struct mt76_dev *mdev = &dev->mt76; 904 struct mt76_txwi_cache *txwi; 905 struct ieee80211_sta *sta = NULL; 906 struct mt76_wcid *wcid = NULL; 907 #if defined(__linux__) 908 LIST_HEAD(free_list); 909 void *end = data + len; 910 #elif defined(__FreeBSD__) 911 LINUX_LIST_HEAD(free_list); 912 void *end = (u8 *)data + len; 913 #endif 914 bool v3, wake = false; 915 u16 total, count = 0; 916 u32 txd = le32_to_cpu(free->txd); 917 __le32 *cur_info; 918 919 mt7915_mac_tx_free_prepare(dev); 920 921 total = le16_get_bits(free->ctrl, MT_TX_FREE_MSDU_CNT); 922 v3 = (FIELD_GET(MT_TX_FREE_VER, txd) == 0x4); 923 924 for (cur_info = tx_info; count < total; cur_info++) { 925 u32 msdu, info; 926 u8 i; 927 928 if (WARN_ON_ONCE((void *)cur_info >= end)) 929 return; 930 931 /* 932 * 1'b1: new wcid pair. 933 * 1'b0: msdu_id with the same 'wcid pair' as above. 934 */ 935 info = le32_to_cpu(*cur_info); 936 if (info & MT_TX_FREE_PAIR) { 937 struct mt7915_sta *msta; 938 u16 idx; 939 940 idx = FIELD_GET(MT_TX_FREE_WLAN_ID, info); 941 wcid = rcu_dereference(dev->mt76.wcid[idx]); 942 sta = wcid_to_sta(wcid); 943 if (!sta) 944 continue; 945 946 msta = container_of(wcid, struct mt7915_sta, wcid); 947 mt76_wcid_add_poll(&dev->mt76, &msta->wcid); 948 continue; 949 } 950 951 if (!mtk_wed_device_active(&mdev->mmio.wed) && wcid) { 952 u32 tx_retries = 0, tx_failed = 0; 953 954 if (v3 && (info & MT_TX_FREE_MPDU_HEADER_V3)) { 955 tx_retries = 956 FIELD_GET(MT_TX_FREE_COUNT_V3, info) - 1; 957 tx_failed = tx_retries + 958 !!FIELD_GET(MT_TX_FREE_STAT_V3, info); 959 } else if (!v3 && (info & MT_TX_FREE_MPDU_HEADER)) { 960 tx_retries = 961 FIELD_GET(MT_TX_FREE_COUNT, info) - 1; 962 tx_failed = tx_retries + 963 !!FIELD_GET(MT_TX_FREE_STAT, info); 964 } 965 wcid->stats.tx_retries += tx_retries; 966 wcid->stats.tx_failed += tx_failed; 967 } 968 969 if (v3 && (info & MT_TX_FREE_MPDU_HEADER_V3)) 970 continue; 971 972 for (i = 0; i < 1 + v3; i++) { 973 if (v3) { 974 msdu = (info >> (15 * i)) & MT_TX_FREE_MSDU_ID_V3; 975 if (msdu == MT_TX_FREE_MSDU_ID_V3) 976 continue; 977 } else { 978 msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info); 979 } 980 count++; 981 txwi = mt76_token_release(mdev, msdu, &wake); 982 if (!txwi) 983 continue; 984 985 mt76_connac2_txwi_free(mdev, txwi, sta, &free_list); 986 } 987 } 988 989 mt7915_mac_tx_free_done(dev, &free_list, wake); 990 } 991 992 static void 993 mt7915_mac_tx_free_v0(struct mt7915_dev *dev, void *data, int len) 994 { 995 struct mt76_connac_tx_free *free = data; 996 #if defined(__linux__) 997 __le16 *info = (__le16 *)(data + sizeof(*free)); 998 #elif defined(__FreeBSD__) 999 __le16 *info = (__le16 *)((u8 *)data + sizeof(*free)); 1000 #endif 1001 struct mt76_dev *mdev = &dev->mt76; 1002 #if defined(__linux__) 1003 void *end = data + len; 1004 LIST_HEAD(free_list); 1005 #elif defined(__FreeBSD__) 1006 void *end = (u8 *)data + len; 1007 LINUX_LIST_HEAD(free_list); 1008 #endif 1009 bool wake = false; 1010 u8 i, count; 1011 1012 mt7915_mac_tx_free_prepare(dev); 1013 1014 count = FIELD_GET(MT_TX_FREE_MSDU_CNT_V0, le16_to_cpu(free->ctrl)); 1015 if (WARN_ON_ONCE((void *)&info[count] > end)) 1016 return; 1017 1018 for (i = 0; i < count; i++) { 1019 struct mt76_txwi_cache *txwi; 1020 u16 msdu = le16_to_cpu(info[i]); 1021 1022 txwi = mt76_token_release(mdev, msdu, &wake); 1023 if (!txwi) 1024 continue; 1025 1026 mt76_connac2_txwi_free(mdev, txwi, NULL, &free_list); 1027 } 1028 1029 mt7915_mac_tx_free_done(dev, &free_list, wake); 1030 } 1031 1032 static void mt7915_mac_add_txs(struct mt7915_dev *dev, void *data) 1033 { 1034 struct mt7915_sta *msta = NULL; 1035 struct mt76_wcid *wcid; 1036 __le32 *txs_data = data; 1037 u16 wcidx; 1038 u8 pid; 1039 1040 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID); 1041 pid = le32_get_bits(txs_data[3], MT_TXS3_PID); 1042 1043 if (pid < MT_PACKET_ID_WED) 1044 return; 1045 1046 if (wcidx >= mt7915_wtbl_size(dev)) 1047 return; 1048 1049 rcu_read_lock(); 1050 1051 wcid = rcu_dereference(dev->mt76.wcid[wcidx]); 1052 if (!wcid) 1053 goto out; 1054 1055 msta = container_of(wcid, struct mt7915_sta, wcid); 1056 1057 if (pid == MT_PACKET_ID_WED) 1058 mt76_connac2_mac_fill_txs(&dev->mt76, wcid, txs_data); 1059 else 1060 mt76_connac2_mac_add_txs_skb(&dev->mt76, wcid, pid, txs_data); 1061 1062 if (!wcid->sta) 1063 goto out; 1064 1065 mt76_wcid_add_poll(&dev->mt76, &msta->wcid); 1066 1067 out: 1068 rcu_read_unlock(); 1069 } 1070 1071 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len) 1072 { 1073 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1074 __le32 *rxd = (__le32 *)data; 1075 __le32 *end = (__le32 *)&rxd[len / 4]; 1076 enum rx_pkt_type type; 1077 1078 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1079 1080 switch (type) { 1081 case PKT_TYPE_TXRX_NOTIFY: 1082 mt7915_mac_tx_free(dev, data, len); 1083 return false; 1084 case PKT_TYPE_TXRX_NOTIFY_V0: 1085 mt7915_mac_tx_free_v0(dev, data, len); 1086 return false; 1087 case PKT_TYPE_TXS: 1088 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1089 mt7915_mac_add_txs(dev, rxd); 1090 return false; 1091 case PKT_TYPE_RX_FW_MONITOR: 1092 #if !defined(__FreeBSD__) || defined(CONFIG_MT7915_DEBUGFS) 1093 mt7915_debugfs_rx_fw_monitor(dev, data, len); 1094 #endif 1095 return false; 1096 default: 1097 return true; 1098 } 1099 } 1100 1101 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1102 struct sk_buff *skb, u32 *info) 1103 { 1104 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1105 __le32 *rxd = (__le32 *)skb->data; 1106 __le32 *end = (__le32 *)&skb->data[skb->len]; 1107 enum rx_pkt_type type; 1108 1109 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1110 1111 switch (type) { 1112 case PKT_TYPE_TXRX_NOTIFY: 1113 mt7915_mac_tx_free(dev, skb->data, skb->len); 1114 napi_consume_skb(skb, 1); 1115 break; 1116 case PKT_TYPE_TXRX_NOTIFY_V0: 1117 mt7915_mac_tx_free_v0(dev, skb->data, skb->len); 1118 napi_consume_skb(skb, 1); 1119 break; 1120 case PKT_TYPE_RX_EVENT: 1121 mt7915_mcu_rx_event(dev, skb); 1122 break; 1123 case PKT_TYPE_TXRXV: 1124 mt7915_mac_fill_rx_vector(dev, skb); 1125 break; 1126 case PKT_TYPE_TXS: 1127 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1128 mt7915_mac_add_txs(dev, rxd); 1129 dev_kfree_skb(skb); 1130 break; 1131 case PKT_TYPE_RX_FW_MONITOR: 1132 #if !defined(__FreeBSD__) || defined(CONFIG_MT7915_DEBUGFS) 1133 mt7915_debugfs_rx_fw_monitor(dev, skb->data, skb->len); 1134 #endif 1135 dev_kfree_skb(skb); 1136 break; 1137 case PKT_TYPE_NORMAL: 1138 if (!mt7915_mac_fill_rx(dev, skb, q, info)) { 1139 mt76_rx(&dev->mt76, q, skb); 1140 return; 1141 } 1142 fallthrough; 1143 default: 1144 dev_kfree_skb(skb); 1145 break; 1146 } 1147 } 1148 1149 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy) 1150 { 1151 struct mt7915_dev *dev = phy->dev; 1152 u32 reg = MT_WF_PHY_RX_CTRL1(phy->mt76->band_idx); 1153 1154 mt76_clear(dev, reg, MT_WF_PHY_RX_CTRL1_STSCNT_EN); 1155 mt76_set(dev, reg, BIT(11) | BIT(9)); 1156 } 1157 1158 void mt7915_mac_reset_counters(struct mt7915_phy *phy) 1159 { 1160 struct mt7915_dev *dev = phy->dev; 1161 int i; 1162 1163 for (i = 0; i < 4; i++) { 1164 mt76_rr(dev, MT_TX_AGG_CNT(phy->mt76->band_idx, i)); 1165 mt76_rr(dev, MT_TX_AGG_CNT2(phy->mt76->band_idx, i)); 1166 } 1167 1168 phy->mt76->survey_time = ktime_get_boottime(); 1169 memset(phy->mt76->aggr_stats, 0, sizeof(phy->mt76->aggr_stats)); 1170 1171 /* reset airtime counters */ 1172 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(phy->mt76->band_idx), 1173 MT_WF_RMAC_MIB_RXTIME_CLR); 1174 1175 mt7915_mcu_get_chan_mib_info(phy, true); 1176 } 1177 1178 void mt7915_mac_set_timing(struct mt7915_phy *phy) 1179 { 1180 s16 coverage_class = phy->coverage_class; 1181 struct mt7915_dev *dev = phy->dev; 1182 struct mt7915_phy *ext_phy = mt7915_ext_phy(dev); 1183 u32 val, reg_offset; 1184 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 1185 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 1186 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 1187 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 1188 u8 band = phy->mt76->band_idx; 1189 int eifs_ofdm = 84, sifs = 10, offset; 1190 bool a_band = !(phy->mt76->chandef.chan->band == NL80211_BAND_2GHZ); 1191 1192 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 1193 return; 1194 1195 if (ext_phy) 1196 coverage_class = max_t(s16, dev->phy.coverage_class, 1197 ext_phy->coverage_class); 1198 1199 mt76_set(dev, MT_ARB_SCR(band), 1200 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1201 udelay(1); 1202 1203 offset = 3 * coverage_class; 1204 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 1205 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 1206 1207 if (!is_mt7915(&dev->mt76)) { 1208 if (!a_band) { 1209 mt76_wr(dev, MT_TMAC_ICR1(band), 1210 FIELD_PREP(MT_IFS_EIFS_CCK, 314)); 1211 eifs_ofdm = 78; 1212 } else { 1213 eifs_ofdm = 84; 1214 } 1215 } else if (a_band) { 1216 sifs = 16; 1217 } 1218 1219 mt76_wr(dev, MT_TMAC_CDTR(band), cck + reg_offset); 1220 mt76_wr(dev, MT_TMAC_ODTR(band), ofdm + reg_offset); 1221 mt76_wr(dev, MT_TMAC_ICR0(band), 1222 FIELD_PREP(MT_IFS_EIFS_OFDM, eifs_ofdm) | 1223 FIELD_PREP(MT_IFS_RIFS, 2) | 1224 FIELD_PREP(MT_IFS_SIFS, sifs) | 1225 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); 1226 1227 if (phy->slottime < 20 || a_band) 1228 val = MT7915_CFEND_RATE_DEFAULT; 1229 else 1230 val = MT7915_CFEND_RATE_11B; 1231 1232 mt76_rmw_field(dev, MT_AGG_ACR0(band), MT_AGG_ACR_CFEND_RATE, val); 1233 mt76_clear(dev, MT_ARB_SCR(band), 1234 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1235 } 1236 1237 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool band) 1238 { 1239 u32 reg; 1240 1241 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RXTD12(band) : 1242 MT_WF_PHY_RXTD12_MT7916(band); 1243 mt76_set(dev, reg, 1244 MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY | 1245 MT_WF_PHY_RXTD12_IRPI_SW_CLR); 1246 1247 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RX_CTRL1(band) : 1248 MT_WF_PHY_RX_CTRL1_MT7916(band); 1249 mt76_set(dev, reg, FIELD_PREP(MT_WF_PHY_RX_CTRL1_IPI_EN, 0x5)); 1250 } 1251 1252 static u8 1253 mt7915_phy_get_nf(struct mt7915_phy *phy, int idx) 1254 { 1255 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; 1256 struct mt7915_dev *dev = phy->dev; 1257 u32 val, sum = 0, n = 0; 1258 int nss, i; 1259 1260 for (nss = 0; nss < hweight8(phy->mt76->chainmask); nss++) { 1261 u32 reg = is_mt7915(&dev->mt76) ? 1262 MT_WF_IRPI_NSS(0, nss + (idx << dev->dbdc_support)) : 1263 MT_WF_IRPI_NSS_MT7916(idx, nss); 1264 1265 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { 1266 val = mt76_rr(dev, reg); 1267 sum += val * nf_power[i]; 1268 n += val; 1269 } 1270 } 1271 1272 if (!n) 1273 return 0; 1274 1275 return sum / n; 1276 } 1277 1278 void mt7915_update_channel(struct mt76_phy *mphy) 1279 { 1280 struct mt7915_phy *phy = mphy->priv; 1281 struct mt76_channel_state *state = mphy->chan_state; 1282 int nf; 1283 1284 mt7915_mcu_get_chan_mib_info(phy, false); 1285 1286 nf = mt7915_phy_get_nf(phy, phy->mt76->band_idx); 1287 if (!phy->noise) 1288 phy->noise = nf << 4; 1289 else if (nf) 1290 phy->noise += nf - (phy->noise >> 4); 1291 1292 state->noise = -(phy->noise >> 4); 1293 } 1294 1295 static bool 1296 mt7915_wait_reset_state(struct mt7915_dev *dev, u32 state) 1297 { 1298 bool ret; 1299 1300 ret = wait_event_timeout(dev->reset_wait, 1301 (READ_ONCE(dev->recovery.state) & state), 1302 MT7915_RESET_TIMEOUT); 1303 1304 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state); 1305 return ret; 1306 } 1307 1308 static void 1309 mt7915_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif) 1310 { 1311 struct ieee80211_hw *hw = priv; 1312 1313 switch (vif->type) { 1314 case NL80211_IFTYPE_MESH_POINT: 1315 case NL80211_IFTYPE_ADHOC: 1316 case NL80211_IFTYPE_AP: 1317 mt7915_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon, 1318 BSS_CHANGED_BEACON_ENABLED); 1319 break; 1320 default: 1321 break; 1322 } 1323 } 1324 1325 static void 1326 mt7915_update_beacons(struct mt7915_dev *dev) 1327 { 1328 struct mt76_phy *mphy_ext = dev->mt76.phys[MT_BAND1]; 1329 1330 ieee80211_iterate_active_interfaces(dev->mt76.hw, 1331 IEEE80211_IFACE_ITER_RESUME_ALL, 1332 mt7915_update_vif_beacon, dev->mt76.hw); 1333 1334 if (!mphy_ext) 1335 return; 1336 1337 ieee80211_iterate_active_interfaces(mphy_ext->hw, 1338 IEEE80211_IFACE_ITER_RESUME_ALL, 1339 mt7915_update_vif_beacon, mphy_ext->hw); 1340 } 1341 1342 static int 1343 mt7915_mac_restart(struct mt7915_dev *dev) 1344 { 1345 struct mt7915_phy *phy2; 1346 struct mt76_phy *ext_phy; 1347 struct mt76_dev *mdev = &dev->mt76; 1348 int i, ret; 1349 1350 ext_phy = dev->mt76.phys[MT_BAND1]; 1351 phy2 = ext_phy ? ext_phy->priv : NULL; 1352 1353 if (dev->hif2) { 1354 mt76_wr(dev, MT_INT1_MASK_CSR, 0x0); 1355 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1356 } 1357 1358 if (dev_is_pci(mdev->dev)) { 1359 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0); 1360 if (dev->hif2) { 1361 if (is_mt7915(mdev)) 1362 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0x0); 1363 else 1364 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE_MT7916, 0x0); 1365 } 1366 } 1367 1368 set_bit(MT76_RESET, &dev->mphy.state); 1369 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1370 wake_up(&dev->mt76.mcu.wait); 1371 if (ext_phy) 1372 set_bit(MT76_RESET, &ext_phy->state); 1373 1374 /* lock/unlock all queues to ensure that no tx is pending */ 1375 mt76_txq_schedule_all(&dev->mphy); 1376 if (ext_phy) 1377 mt76_txq_schedule_all(ext_phy); 1378 1379 /* disable all tx/rx napi */ 1380 mt76_worker_disable(&dev->mt76.tx_worker); 1381 mt76_for_each_q_rx(mdev, i) { 1382 if (mdev->q_rx[i].ndesc) 1383 napi_disable(&dev->mt76.napi[i]); 1384 } 1385 napi_disable(&dev->mt76.tx_napi); 1386 1387 /* token reinit */ 1388 mt76_connac2_tx_token_put(&dev->mt76); 1389 idr_init(&dev->mt76.token); 1390 1391 mt7915_dma_reset(dev, true); 1392 1393 mt76_for_each_q_rx(mdev, i) { 1394 if (mdev->q_rx[i].ndesc) { 1395 napi_enable(&dev->mt76.napi[i]); 1396 } 1397 } 1398 1399 local_bh_disable(); 1400 mt76_for_each_q_rx(mdev, i) { 1401 if (mdev->q_rx[i].ndesc) { 1402 napi_schedule(&dev->mt76.napi[i]); 1403 } 1404 } 1405 local_bh_enable(); 1406 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1407 clear_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state); 1408 1409 mt76_wr(dev, MT_INT_MASK_CSR, dev->mt76.mmio.irqmask); 1410 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 1411 1412 if (dev->hif2) { 1413 mt76_wr(dev, MT_INT1_MASK_CSR, dev->mt76.mmio.irqmask); 1414 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1415 } 1416 if (dev_is_pci(mdev->dev)) { 1417 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 1418 if (dev->hif2) { 1419 mt76_wr(dev, MT_PCIE_RECOG_ID, 1420 dev->hif2->index | MT_PCIE_RECOG_ID_SEM); 1421 if (is_mt7915(mdev)) 1422 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0xff); 1423 else 1424 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE_MT7916, 0xff); 1425 } 1426 } 1427 1428 /* load firmware */ 1429 ret = mt7915_mcu_init_firmware(dev); 1430 if (ret) 1431 goto out; 1432 1433 /* set the necessary init items */ 1434 ret = mt7915_mcu_set_eeprom(dev); 1435 if (ret) 1436 goto out; 1437 1438 mt7915_mac_init(dev); 1439 mt7915_init_txpower(&dev->phy); 1440 mt7915_init_txpower(phy2); 1441 ret = mt7915_txbf_init(dev); 1442 1443 if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state)) { 1444 ret = mt7915_run(dev->mphy.hw); 1445 if (ret) 1446 goto out; 1447 } 1448 1449 if (ext_phy && test_bit(MT76_STATE_RUNNING, &ext_phy->state)) { 1450 ret = mt7915_run(ext_phy->hw); 1451 if (ret) 1452 goto out; 1453 } 1454 1455 out: 1456 /* reset done */ 1457 clear_bit(MT76_RESET, &dev->mphy.state); 1458 if (phy2) 1459 clear_bit(MT76_RESET, &phy2->mt76->state); 1460 1461 napi_enable(&dev->mt76.tx_napi); 1462 1463 local_bh_disable(); 1464 napi_schedule(&dev->mt76.tx_napi); 1465 local_bh_enable(); 1466 1467 mt76_worker_enable(&dev->mt76.tx_worker); 1468 1469 return ret; 1470 } 1471 1472 static void 1473 mt7915_mac_full_reset(struct mt7915_dev *dev) 1474 { 1475 struct mt76_phy *ext_phy; 1476 struct mt7915_phy *phy2; 1477 int i; 1478 1479 ext_phy = dev->mt76.phys[MT_BAND1]; 1480 phy2 = ext_phy ? ext_phy->priv : NULL; 1481 1482 dev->recovery.hw_full_reset = true; 1483 1484 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1485 wake_up(&dev->mt76.mcu.wait); 1486 ieee80211_stop_queues(mt76_hw(dev)); 1487 if (ext_phy) 1488 ieee80211_stop_queues(ext_phy->hw); 1489 1490 cancel_delayed_work_sync(&dev->mphy.mac_work); 1491 if (ext_phy) 1492 cancel_delayed_work_sync(&ext_phy->mac_work); 1493 1494 mutex_lock(&dev->mt76.mutex); 1495 for (i = 0; i < 10; i++) { 1496 if (!mt7915_mac_restart(dev)) 1497 break; 1498 } 1499 1500 if (i == 10) 1501 dev_err(dev->mt76.dev, "chip full reset failed\n"); 1502 1503 spin_lock_bh(&dev->mt76.sta_poll_lock); 1504 while (!list_empty(&dev->mt76.sta_poll_list)) 1505 list_del_init(dev->mt76.sta_poll_list.next); 1506 spin_unlock_bh(&dev->mt76.sta_poll_lock); 1507 1508 memset(dev->mt76.wcid_mask, 0, sizeof(dev->mt76.wcid_mask)); 1509 dev->mt76.vif_mask = 0; 1510 dev->phy.omac_mask = 0; 1511 if (phy2) 1512 phy2->omac_mask = 0; 1513 1514 i = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA); 1515 dev->mt76.global_wcid.idx = i; 1516 dev->recovery.hw_full_reset = false; 1517 1518 mutex_unlock(&dev->mt76.mutex); 1519 1520 ieee80211_restart_hw(mt76_hw(dev)); 1521 if (ext_phy) 1522 ieee80211_restart_hw(ext_phy->hw); 1523 } 1524 1525 /* system error recovery */ 1526 void mt7915_mac_reset_work(struct work_struct *work) 1527 { 1528 struct mt7915_phy *phy2; 1529 struct mt76_phy *ext_phy; 1530 struct mt7915_dev *dev; 1531 int i; 1532 1533 dev = container_of(work, struct mt7915_dev, reset_work); 1534 ext_phy = dev->mt76.phys[MT_BAND1]; 1535 phy2 = ext_phy ? ext_phy->priv : NULL; 1536 1537 /* chip full reset */ 1538 if (dev->recovery.restart) { 1539 /* disable WA/WM WDT */ 1540 mt76_clear(dev, MT_WFDMA0_MCU_HOST_INT_ENA, 1541 MT_MCU_CMD_WDT_MASK); 1542 1543 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WA_WDT) 1544 dev->recovery.wa_reset_count++; 1545 else 1546 dev->recovery.wm_reset_count++; 1547 1548 mt7915_mac_full_reset(dev); 1549 1550 /* enable mcu irq */ 1551 mt7915_irq_enable(dev, MT_INT_MCU_CMD); 1552 mt7915_irq_disable(dev, 0); 1553 1554 /* enable WA/WM WDT */ 1555 mt76_set(dev, MT_WFDMA0_MCU_HOST_INT_ENA, MT_MCU_CMD_WDT_MASK); 1556 1557 dev->recovery.state = MT_MCU_CMD_NORMAL_STATE; 1558 dev->recovery.restart = false; 1559 return; 1560 } 1561 1562 /* chip partial reset */ 1563 if (!(READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA)) 1564 return; 1565 1566 ieee80211_stop_queues(mt76_hw(dev)); 1567 if (ext_phy) 1568 ieee80211_stop_queues(ext_phy->hw); 1569 1570 set_bit(MT76_RESET, &dev->mphy.state); 1571 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1572 wake_up(&dev->mt76.mcu.wait); 1573 cancel_delayed_work_sync(&dev->mphy.mac_work); 1574 if (phy2) { 1575 set_bit(MT76_RESET, &phy2->mt76->state); 1576 cancel_delayed_work_sync(&phy2->mt76->mac_work); 1577 } 1578 1579 mutex_lock(&dev->mt76.mutex); 1580 1581 mt76_worker_disable(&dev->mt76.tx_worker); 1582 mt76_for_each_q_rx(&dev->mt76, i) 1583 napi_disable(&dev->mt76.napi[i]); 1584 napi_disable(&dev->mt76.tx_napi); 1585 1586 1587 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) 1588 mtk_wed_device_stop(&dev->mt76.mmio.wed); 1589 1590 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED); 1591 1592 if (mt7915_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) { 1593 mt7915_dma_reset(dev, false); 1594 1595 mt76_connac2_tx_token_put(&dev->mt76); 1596 idr_init(&dev->mt76.token); 1597 1598 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT); 1599 mt7915_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE); 1600 } 1601 1602 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE); 1603 mt7915_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE); 1604 1605 /* enable DMA Tx/Rx and interrupt */ 1606 mt7915_dma_start(dev, false, false); 1607 1608 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1609 clear_bit(MT76_RESET, &dev->mphy.state); 1610 if (phy2) 1611 clear_bit(MT76_RESET, &phy2->mt76->state); 1612 1613 mt76_for_each_q_rx(&dev->mt76, i) { 1614 napi_enable(&dev->mt76.napi[i]); 1615 } 1616 1617 local_bh_disable(); 1618 mt76_for_each_q_rx(&dev->mt76, i) { 1619 napi_schedule(&dev->mt76.napi[i]); 1620 } 1621 local_bh_enable(); 1622 1623 tasklet_schedule(&dev->mt76.irq_tasklet); 1624 1625 mt76_worker_enable(&dev->mt76.tx_worker); 1626 1627 napi_enable(&dev->mt76.tx_napi); 1628 local_bh_disable(); 1629 napi_schedule(&dev->mt76.tx_napi); 1630 local_bh_enable(); 1631 1632 ieee80211_wake_queues(mt76_hw(dev)); 1633 if (ext_phy) 1634 ieee80211_wake_queues(ext_phy->hw); 1635 1636 mutex_unlock(&dev->mt76.mutex); 1637 1638 mt7915_update_beacons(dev); 1639 1640 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 1641 MT7915_WATCHDOG_TIME); 1642 if (phy2) 1643 ieee80211_queue_delayed_work(ext_phy->hw, 1644 &phy2->mt76->mac_work, 1645 MT7915_WATCHDOG_TIME); 1646 } 1647 1648 /* firmware coredump */ 1649 void mt7915_mac_dump_work(struct work_struct *work) 1650 { 1651 const struct mt7915_mem_region *mem_region; 1652 struct mt7915_crash_data *crash_data; 1653 struct mt7915_dev *dev; 1654 struct mt7915_mem_hdr *hdr; 1655 size_t buf_len; 1656 int i; 1657 u32 num; 1658 u8 *buf; 1659 1660 dev = container_of(work, struct mt7915_dev, dump_work); 1661 1662 mutex_lock(&dev->dump_mutex); 1663 1664 crash_data = mt7915_coredump_new(dev); 1665 if (!crash_data) { 1666 mutex_unlock(&dev->dump_mutex); 1667 goto skip_coredump; 1668 } 1669 1670 mem_region = mt7915_coredump_get_mem_layout(dev, &num); 1671 if (!mem_region || !crash_data->memdump_buf_len) { 1672 mutex_unlock(&dev->dump_mutex); 1673 goto skip_memdump; 1674 } 1675 1676 buf = crash_data->memdump_buf; 1677 buf_len = crash_data->memdump_buf_len; 1678 1679 /* dumping memory content... */ 1680 memset(buf, 0, buf_len); 1681 for (i = 0; i < num; i++) { 1682 if (mem_region->len > buf_len) { 1683 dev_warn(dev->mt76.dev, "%s len %lu is too large\n", 1684 mem_region->name, 1685 (unsigned long)mem_region->len); 1686 break; 1687 } 1688 1689 /* reserve space for the header */ 1690 hdr = (void *)buf; 1691 buf += sizeof(*hdr); 1692 buf_len -= sizeof(*hdr); 1693 1694 mt7915_memcpy_fromio(dev, buf, mem_region->start, 1695 mem_region->len); 1696 1697 hdr->start = mem_region->start; 1698 hdr->len = mem_region->len; 1699 1700 if (!mem_region->len) 1701 /* note: the header remains, just with zero length */ 1702 break; 1703 1704 buf += mem_region->len; 1705 buf_len -= mem_region->len; 1706 1707 mem_region++; 1708 } 1709 1710 mutex_unlock(&dev->dump_mutex); 1711 1712 skip_memdump: 1713 mt7915_coredump_submit(dev); 1714 skip_coredump: 1715 queue_work(dev->mt76.wq, &dev->reset_work); 1716 } 1717 1718 void mt7915_reset(struct mt7915_dev *dev) 1719 { 1720 if (!dev->recovery.hw_init_done) 1721 return; 1722 1723 if (dev->recovery.hw_full_reset) 1724 return; 1725 1726 /* wm/wa exception: do full recovery */ 1727 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WDT_MASK) { 1728 dev->recovery.restart = true; 1729 dev_info(dev->mt76.dev, 1730 "%s indicated firmware crash, attempting recovery\n", 1731 wiphy_name(dev->mt76.hw->wiphy)); 1732 1733 mt7915_irq_disable(dev, MT_INT_MCU_CMD); 1734 queue_work(dev->mt76.wq, &dev->dump_work); 1735 return; 1736 } 1737 1738 if ((READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA)) { 1739 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1740 wake_up(&dev->mt76.mcu.wait); 1741 } 1742 1743 queue_work(dev->mt76.wq, &dev->reset_work); 1744 wake_up(&dev->reset_wait); 1745 } 1746 1747 void mt7915_mac_update_stats(struct mt7915_phy *phy) 1748 { 1749 struct mt76_mib_stats *mib = &phy->mib; 1750 struct mt7915_dev *dev = phy->dev; 1751 int i, aggr0 = 0, aggr1, cnt; 1752 u8 band = phy->mt76->band_idx; 1753 u32 val; 1754 1755 cnt = mt76_rr(dev, MT_MIB_SDR3(band)); 1756 mib->fcs_err_cnt += is_mt7915(&dev->mt76) ? 1757 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK, cnt) : 1758 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK_MT7916, cnt); 1759 1760 cnt = mt76_rr(dev, MT_MIB_SDR4(band)); 1761 mib->rx_fifo_full_cnt += FIELD_GET(MT_MIB_SDR4_RX_FIFO_FULL_MASK, cnt); 1762 1763 cnt = mt76_rr(dev, MT_MIB_SDR5(band)); 1764 mib->rx_mpdu_cnt += cnt; 1765 1766 cnt = mt76_rr(dev, MT_MIB_SDR6(band)); 1767 mib->channel_idle_cnt += FIELD_GET(MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK, cnt); 1768 1769 cnt = mt76_rr(dev, MT_MIB_SDR7(band)); 1770 mib->rx_vector_mismatch_cnt += 1771 FIELD_GET(MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK, cnt); 1772 1773 cnt = mt76_rr(dev, MT_MIB_SDR8(band)); 1774 mib->rx_delimiter_fail_cnt += 1775 FIELD_GET(MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK, cnt); 1776 1777 cnt = mt76_rr(dev, MT_MIB_SDR10(band)); 1778 mib->rx_mrdy_cnt += is_mt7915(&dev->mt76) ? 1779 FIELD_GET(MT_MIB_SDR10_MRDY_COUNT_MASK, cnt) : 1780 FIELD_GET(MT_MIB_SDR10_MRDY_COUNT_MASK_MT7916, cnt); 1781 1782 cnt = mt76_rr(dev, MT_MIB_SDR11(band)); 1783 mib->rx_len_mismatch_cnt += 1784 FIELD_GET(MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK, cnt); 1785 1786 cnt = mt76_rr(dev, MT_MIB_SDR12(band)); 1787 mib->tx_ampdu_cnt += cnt; 1788 1789 cnt = mt76_rr(dev, MT_MIB_SDR13(band)); 1790 mib->tx_stop_q_empty_cnt += 1791 FIELD_GET(MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK, cnt); 1792 1793 cnt = mt76_rr(dev, MT_MIB_SDR14(band)); 1794 mib->tx_mpdu_attempts_cnt += is_mt7915(&dev->mt76) ? 1795 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK, cnt) : 1796 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916, cnt); 1797 1798 cnt = mt76_rr(dev, MT_MIB_SDR15(band)); 1799 mib->tx_mpdu_success_cnt += is_mt7915(&dev->mt76) ? 1800 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK, cnt) : 1801 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916, cnt); 1802 1803 cnt = mt76_rr(dev, MT_MIB_SDR16(band)); 1804 mib->primary_cca_busy_time += 1805 FIELD_GET(MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK, cnt); 1806 1807 cnt = mt76_rr(dev, MT_MIB_SDR17(band)); 1808 mib->secondary_cca_busy_time += 1809 FIELD_GET(MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK, cnt); 1810 1811 cnt = mt76_rr(dev, MT_MIB_SDR18(band)); 1812 mib->primary_energy_detect_time += 1813 FIELD_GET(MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK, cnt); 1814 1815 cnt = mt76_rr(dev, MT_MIB_SDR19(band)); 1816 mib->cck_mdrdy_time += FIELD_GET(MT_MIB_SDR19_CCK_MDRDY_TIME_MASK, cnt); 1817 1818 cnt = mt76_rr(dev, MT_MIB_SDR20(band)); 1819 mib->ofdm_mdrdy_time += 1820 FIELD_GET(MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK, cnt); 1821 1822 cnt = mt76_rr(dev, MT_MIB_SDR21(band)); 1823 mib->green_mdrdy_time += 1824 FIELD_GET(MT_MIB_SDR21_GREEN_MDRDY_TIME_MASK, cnt); 1825 1826 cnt = mt76_rr(dev, MT_MIB_SDR22(band)); 1827 mib->rx_ampdu_cnt += cnt; 1828 1829 cnt = mt76_rr(dev, MT_MIB_SDR23(band)); 1830 mib->rx_ampdu_bytes_cnt += cnt; 1831 1832 cnt = mt76_rr(dev, MT_MIB_SDR24(band)); 1833 mib->rx_ampdu_valid_subframe_cnt += is_mt7915(&dev->mt76) ? 1834 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK, cnt) : 1835 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916, cnt); 1836 1837 cnt = mt76_rr(dev, MT_MIB_SDR25(band)); 1838 mib->rx_ampdu_valid_subframe_bytes_cnt += cnt; 1839 1840 cnt = mt76_rr(dev, MT_MIB_SDR27(band)); 1841 mib->tx_rwp_fail_cnt += 1842 FIELD_GET(MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK, cnt); 1843 1844 cnt = mt76_rr(dev, MT_MIB_SDR28(band)); 1845 mib->tx_rwp_need_cnt += 1846 FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK, cnt); 1847 1848 cnt = mt76_rr(dev, MT_MIB_SDR29(band)); 1849 mib->rx_pfdrop_cnt += is_mt7915(&dev->mt76) ? 1850 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK, cnt) : 1851 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916, cnt); 1852 1853 cnt = mt76_rr(dev, MT_MIB_SDRVEC(band)); 1854 mib->rx_vec_queue_overflow_drop_cnt += is_mt7915(&dev->mt76) ? 1855 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK, cnt) : 1856 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916, cnt); 1857 1858 cnt = mt76_rr(dev, MT_MIB_SDR31(band)); 1859 mib->rx_ba_cnt += cnt; 1860 1861 cnt = mt76_rr(dev, MT_MIB_SDRMUBF(band)); 1862 mib->tx_bf_cnt += FIELD_GET(MT_MIB_MU_BF_TX_CNT, cnt); 1863 1864 cnt = mt76_rr(dev, MT_MIB_DR8(band)); 1865 mib->tx_mu_mpdu_cnt += cnt; 1866 1867 cnt = mt76_rr(dev, MT_MIB_DR9(band)); 1868 mib->tx_mu_acked_mpdu_cnt += cnt; 1869 1870 cnt = mt76_rr(dev, MT_MIB_DR11(band)); 1871 mib->tx_su_acked_mpdu_cnt += cnt; 1872 1873 cnt = mt76_rr(dev, MT_ETBF_PAR_RPT0(band)); 1874 mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_PAR_RPT0_FB_BW, cnt); 1875 mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NC, cnt); 1876 mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NR, cnt); 1877 1878 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 1879 cnt = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i)); 1880 mib->tx_amsdu[i] += cnt; 1881 mib->tx_amsdu_cnt += cnt; 1882 } 1883 1884 if (is_mt7915(&dev->mt76)) { 1885 for (i = 0, aggr1 = aggr0 + 8; i < 4; i++) { 1886 val = mt76_rr(dev, MT_MIB_MB_SDR1(band, (i << 4))); 1887 mib->ba_miss_cnt += 1888 FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val); 1889 mib->ack_fail_cnt += 1890 FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val); 1891 1892 val = mt76_rr(dev, MT_MIB_MB_SDR0(band, (i << 4))); 1893 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val); 1894 mib->rts_retries_cnt += 1895 FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val); 1896 1897 val = mt76_rr(dev, MT_TX_AGG_CNT(band, i)); 1898 phy->mt76->aggr_stats[aggr0++] += val & 0xffff; 1899 phy->mt76->aggr_stats[aggr0++] += val >> 16; 1900 1901 val = mt76_rr(dev, MT_TX_AGG_CNT2(band, i)); 1902 phy->mt76->aggr_stats[aggr1++] += val & 0xffff; 1903 phy->mt76->aggr_stats[aggr1++] += val >> 16; 1904 } 1905 1906 cnt = mt76_rr(dev, MT_MIB_SDR32(band)); 1907 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1908 1909 cnt = mt76_rr(dev, MT_MIB_SDR33(band)); 1910 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR33_TX_PKT_IBF_CNT, cnt); 1911 1912 cnt = mt76_rr(dev, MT_ETBF_TX_APP_CNT(band)); 1913 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_IBF_CNT, cnt); 1914 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_EBF_CNT, cnt); 1915 1916 cnt = mt76_rr(dev, MT_ETBF_TX_NDP_BFRP(band)); 1917 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_ETBF_TX_FB_CPL, cnt); 1918 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_ETBF_TX_FB_TRI, cnt); 1919 1920 cnt = mt76_rr(dev, MT_ETBF_RX_FB_CNT(band)); 1921 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_ETBF_RX_FB_ALL, cnt); 1922 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_ETBF_RX_FB_HE, cnt); 1923 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_ETBF_RX_FB_VHT, cnt); 1924 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_ETBF_RX_FB_HT, cnt); 1925 } else { 1926 for (i = 0; i < 2; i++) { 1927 /* rts count */ 1928 val = mt76_rr(dev, MT_MIB_MB_SDR0(band, (i << 2))); 1929 mib->rts_cnt += FIELD_GET(GENMASK(15, 0), val); 1930 mib->rts_cnt += FIELD_GET(GENMASK(31, 16), val); 1931 1932 /* rts retry count */ 1933 val = mt76_rr(dev, MT_MIB_MB_SDR1(band, (i << 2))); 1934 mib->rts_retries_cnt += FIELD_GET(GENMASK(15, 0), val); 1935 mib->rts_retries_cnt += FIELD_GET(GENMASK(31, 16), val); 1936 1937 /* ba miss count */ 1938 val = mt76_rr(dev, MT_MIB_MB_SDR2(band, (i << 2))); 1939 mib->ba_miss_cnt += FIELD_GET(GENMASK(15, 0), val); 1940 mib->ba_miss_cnt += FIELD_GET(GENMASK(31, 16), val); 1941 1942 /* ack fail count */ 1943 val = mt76_rr(dev, MT_MIB_MB_BFTF(band, (i << 2))); 1944 mib->ack_fail_cnt += FIELD_GET(GENMASK(15, 0), val); 1945 mib->ack_fail_cnt += FIELD_GET(GENMASK(31, 16), val); 1946 } 1947 1948 for (i = 0; i < 8; i++) { 1949 val = mt76_rr(dev, MT_TX_AGG_CNT(band, i)); 1950 phy->mt76->aggr_stats[aggr0++] += FIELD_GET(GENMASK(15, 0), val); 1951 phy->mt76->aggr_stats[aggr0++] += FIELD_GET(GENMASK(31, 16), val); 1952 } 1953 1954 cnt = mt76_rr(dev, MT_MIB_SDR32(band)); 1955 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt); 1956 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt); 1957 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1958 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1959 1960 cnt = mt76_rr(dev, MT_MIB_BFCR7(band)); 1961 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_MIB_BFCR7_BFEE_TX_FB_CPL, cnt); 1962 1963 cnt = mt76_rr(dev, MT_MIB_BFCR2(band)); 1964 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_MIB_BFCR2_BFEE_TX_FB_TRIG, cnt); 1965 1966 cnt = mt76_rr(dev, MT_MIB_BFCR0(band)); 1967 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt); 1968 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt); 1969 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt); 1970 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt); 1971 1972 cnt = mt76_rr(dev, MT_MIB_BFCR1(band)); 1973 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt); 1974 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt); 1975 } 1976 } 1977 1978 static void mt7915_mac_severe_check(struct mt7915_phy *phy) 1979 { 1980 struct mt7915_dev *dev = phy->dev; 1981 u32 trb; 1982 1983 if (!phy->omac_mask) 1984 return; 1985 1986 /* In rare cases, TRB pointers might be out of sync leads to RMAC 1987 * stopping Rx, so check status periodically to see if TRB hardware 1988 * requires minimal recovery. 1989 */ 1990 trb = mt76_rr(dev, MT_TRB_RXPSR0(phy->mt76->band_idx)); 1991 1992 if ((FIELD_GET(MT_TRB_RXPSR0_RX_RMAC_PTR, trb) != 1993 FIELD_GET(MT_TRB_RXPSR0_RX_WTBL_PTR, trb)) && 1994 (FIELD_GET(MT_TRB_RXPSR0_RX_RMAC_PTR, phy->trb_ts) != 1995 FIELD_GET(MT_TRB_RXPSR0_RX_WTBL_PTR, phy->trb_ts)) && 1996 trb == phy->trb_ts) 1997 mt7915_mcu_set_ser(dev, SER_RECOVER, SER_SET_RECOVER_L3_RX_ABORT, 1998 phy->mt76->band_idx); 1999 2000 phy->trb_ts = trb; 2001 } 2002 2003 void mt7915_mac_sta_rc_work(struct work_struct *work) 2004 { 2005 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, rc_work); 2006 struct ieee80211_sta *sta; 2007 struct ieee80211_vif *vif; 2008 struct mt7915_sta *msta; 2009 u32 changed; 2010 #if defined(__linux__) 2011 LIST_HEAD(list); 2012 #elif defined(__FreeBSD__) 2013 LINUX_LIST_HEAD(list); 2014 #endif 2015 2016 spin_lock_bh(&dev->mt76.sta_poll_lock); 2017 list_splice_init(&dev->sta_rc_list, &list); 2018 2019 while (!list_empty(&list)) { 2020 msta = list_first_entry(&list, struct mt7915_sta, rc_list); 2021 list_del_init(&msta->rc_list); 2022 changed = msta->changed; 2023 msta->changed = 0; 2024 spin_unlock_bh(&dev->mt76.sta_poll_lock); 2025 2026 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 2027 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 2028 2029 if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED | 2030 IEEE80211_RC_NSS_CHANGED | 2031 IEEE80211_RC_BW_CHANGED)) 2032 mt7915_mcu_add_rate_ctrl(dev, vif, sta, true); 2033 2034 if (changed & IEEE80211_RC_SMPS_CHANGED) 2035 mt7915_mcu_add_smps(dev, vif, sta); 2036 2037 spin_lock_bh(&dev->mt76.sta_poll_lock); 2038 } 2039 2040 spin_unlock_bh(&dev->mt76.sta_poll_lock); 2041 } 2042 2043 void mt7915_mac_work(struct work_struct *work) 2044 { 2045 struct mt7915_phy *phy; 2046 struct mt76_phy *mphy; 2047 2048 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 2049 mac_work.work); 2050 phy = mphy->priv; 2051 2052 mutex_lock(&mphy->dev->mutex); 2053 2054 mt76_update_survey(mphy); 2055 if (++mphy->mac_work_count == 5) { 2056 mphy->mac_work_count = 0; 2057 2058 mt7915_mac_update_stats(phy); 2059 mt7915_mac_severe_check(phy); 2060 2061 if (phy->dev->muru_debug) 2062 mt7915_mcu_muru_debug_get(phy); 2063 } 2064 2065 mutex_unlock(&mphy->dev->mutex); 2066 2067 mt76_tx_status_check(mphy->dev, false); 2068 2069 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 2070 MT7915_WATCHDOG_TIME); 2071 } 2072 2073 static void mt7915_dfs_stop_radar_detector(struct mt7915_phy *phy) 2074 { 2075 struct mt7915_dev *dev = phy->dev; 2076 2077 if (phy->rdd_state & BIT(0)) 2078 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 0, 2079 MT_RX_SEL0, 0); 2080 if (phy->rdd_state & BIT(1)) 2081 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, 1, 2082 MT_RX_SEL0, 0); 2083 } 2084 2085 static int mt7915_dfs_start_rdd(struct mt7915_dev *dev, int chain) 2086 { 2087 int err, region; 2088 2089 switch (dev->mt76.region) { 2090 case NL80211_DFS_ETSI: 2091 region = 0; 2092 break; 2093 case NL80211_DFS_JP: 2094 region = 2; 2095 break; 2096 case NL80211_DFS_FCC: 2097 default: 2098 region = 1; 2099 break; 2100 } 2101 2102 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_START, chain, 2103 MT_RX_SEL0, region); 2104 if (err < 0) 2105 return err; 2106 2107 if (is_mt7915(&dev->mt76)) { 2108 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_SET_WF_ANT, chain, 2109 0, dev->dbdc_support ? 2 : 0); 2110 if (err < 0) 2111 return err; 2112 } 2113 2114 return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_DET_MODE, chain, 2115 MT_RX_SEL0, 1); 2116 } 2117 2118 static int mt7915_dfs_start_radar_detector(struct mt7915_phy *phy) 2119 { 2120 struct cfg80211_chan_def *chandef = &phy->mt76->chandef; 2121 struct mt7915_dev *dev = phy->dev; 2122 int err; 2123 2124 /* start CAC */ 2125 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_START, 2126 phy->mt76->band_idx, MT_RX_SEL0, 0); 2127 if (err < 0) 2128 return err; 2129 2130 err = mt7915_dfs_start_rdd(dev, phy->mt76->band_idx); 2131 if (err < 0) 2132 return err; 2133 2134 phy->rdd_state |= BIT(phy->mt76->band_idx); 2135 2136 if (!is_mt7915(&dev->mt76)) 2137 return 0; 2138 2139 if (chandef->width == NL80211_CHAN_WIDTH_160 || 2140 chandef->width == NL80211_CHAN_WIDTH_80P80) { 2141 err = mt7915_dfs_start_rdd(dev, 1); 2142 if (err < 0) 2143 return err; 2144 2145 phy->rdd_state |= BIT(1); 2146 } 2147 2148 return 0; 2149 } 2150 2151 static int 2152 mt7915_dfs_init_radar_specs(struct mt7915_phy *phy) 2153 { 2154 const struct mt7915_dfs_radar_spec *radar_specs; 2155 struct mt7915_dev *dev = phy->dev; 2156 int err, i; 2157 2158 switch (dev->mt76.region) { 2159 case NL80211_DFS_FCC: 2160 radar_specs = &fcc_radar_specs; 2161 err = mt7915_mcu_set_fcc5_lpn(dev, 8); 2162 if (err < 0) 2163 return err; 2164 break; 2165 case NL80211_DFS_ETSI: 2166 radar_specs = &etsi_radar_specs; 2167 break; 2168 case NL80211_DFS_JP: 2169 radar_specs = &jp_radar_specs; 2170 break; 2171 default: 2172 return -EINVAL; 2173 } 2174 2175 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { 2176 err = mt7915_mcu_set_radar_th(dev, i, 2177 &radar_specs->radar_pattern[i]); 2178 if (err < 0) 2179 return err; 2180 } 2181 2182 return mt7915_mcu_set_pulse_th(dev, &radar_specs->pulse_th); 2183 } 2184 2185 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy) 2186 { 2187 struct mt7915_dev *dev = phy->dev; 2188 enum mt76_dfs_state dfs_state, prev_state; 2189 int err; 2190 2191 prev_state = phy->mt76->dfs_state; 2192 dfs_state = mt76_phy_dfs_state(phy->mt76); 2193 2194 if (prev_state == dfs_state) 2195 return 0; 2196 2197 if (prev_state == MT_DFS_STATE_UNKNOWN) 2198 mt7915_dfs_stop_radar_detector(phy); 2199 2200 if (dfs_state == MT_DFS_STATE_DISABLED) 2201 goto stop; 2202 2203 if (prev_state <= MT_DFS_STATE_DISABLED) { 2204 err = mt7915_dfs_init_radar_specs(phy); 2205 if (err < 0) 2206 return err; 2207 2208 err = mt7915_dfs_start_radar_detector(phy); 2209 if (err < 0) 2210 return err; 2211 2212 phy->mt76->dfs_state = MT_DFS_STATE_CAC; 2213 } 2214 2215 if (dfs_state == MT_DFS_STATE_CAC) 2216 return 0; 2217 2218 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_END, 2219 phy->mt76->band_idx, MT_RX_SEL0, 0); 2220 if (err < 0) { 2221 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 2222 return err; 2223 } 2224 2225 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE; 2226 return 0; 2227 2228 stop: 2229 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_NORMAL_START, 2230 phy->mt76->band_idx, MT_RX_SEL0, 0); 2231 if (err < 0) 2232 return err; 2233 2234 if (is_mt7915(&dev->mt76)) { 2235 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_SET_WF_ANT, 2236 phy->mt76->band_idx, 0, 2237 dev->dbdc_support ? 2 : 0); 2238 if (err < 0) 2239 return err; 2240 } 2241 2242 mt7915_dfs_stop_radar_detector(phy); 2243 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED; 2244 2245 return 0; 2246 } 2247 2248 static int 2249 mt7915_mac_twt_duration_align(int duration) 2250 { 2251 return duration << 8; 2252 } 2253 2254 static u64 2255 mt7915_mac_twt_sched_list_add(struct mt7915_dev *dev, 2256 struct mt7915_twt_flow *flow) 2257 { 2258 struct mt7915_twt_flow *iter, *iter_next; 2259 u32 duration = flow->duration << 8; 2260 u64 start_tsf; 2261 2262 iter = list_first_entry_or_null(&dev->twt_list, 2263 struct mt7915_twt_flow, list); 2264 if (!iter || !iter->sched || iter->start_tsf > duration) { 2265 /* add flow as first entry in the list */ 2266 list_add(&flow->list, &dev->twt_list); 2267 return 0; 2268 } 2269 2270 list_for_each_entry_safe(iter, iter_next, &dev->twt_list, list) { 2271 start_tsf = iter->start_tsf + 2272 mt7915_mac_twt_duration_align(iter->duration); 2273 if (list_is_last(&iter->list, &dev->twt_list)) 2274 break; 2275 2276 if (!iter_next->sched || 2277 iter_next->start_tsf > start_tsf + duration) { 2278 list_add(&flow->list, &iter->list); 2279 goto out; 2280 } 2281 } 2282 2283 /* add flow as last entry in the list */ 2284 list_add_tail(&flow->list, &dev->twt_list); 2285 out: 2286 return start_tsf; 2287 } 2288 2289 static int mt7915_mac_check_twt_req(struct ieee80211_twt_setup *twt) 2290 { 2291 struct ieee80211_twt_params *twt_agrt; 2292 u64 interval, duration; 2293 u16 mantissa; 2294 u8 exp; 2295 2296 /* only individual agreement supported */ 2297 if (twt->control & IEEE80211_TWT_CONTROL_NEG_TYPE_BROADCAST) 2298 return -EOPNOTSUPP; 2299 2300 /* only 256us unit supported */ 2301 if (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) 2302 return -EOPNOTSUPP; 2303 2304 twt_agrt = (struct ieee80211_twt_params *)twt->params; 2305 2306 /* explicit agreement not supported */ 2307 if (!(twt_agrt->req_type & cpu_to_le16(IEEE80211_TWT_REQTYPE_IMPLICIT))) 2308 return -EOPNOTSUPP; 2309 2310 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, 2311 le16_to_cpu(twt_agrt->req_type)); 2312 mantissa = le16_to_cpu(twt_agrt->mantissa); 2313 duration = twt_agrt->min_twt_dur << 8; 2314 2315 interval = (u64)mantissa << exp; 2316 if (interval < duration) 2317 return -EOPNOTSUPP; 2318 2319 return 0; 2320 } 2321 2322 static bool 2323 mt7915_mac_twt_param_equal(struct mt7915_sta *msta, 2324 struct ieee80211_twt_params *twt_agrt) 2325 { 2326 u16 type = le16_to_cpu(twt_agrt->req_type); 2327 u8 exp; 2328 int i; 2329 2330 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, type); 2331 for (i = 0; i < MT7915_MAX_STA_TWT_AGRT; i++) { 2332 struct mt7915_twt_flow *f; 2333 2334 if (!(msta->twt.flowid_mask & BIT(i))) 2335 continue; 2336 2337 f = &msta->twt.flow[i]; 2338 if (f->duration == twt_agrt->min_twt_dur && 2339 f->mantissa == twt_agrt->mantissa && 2340 f->exp == exp && 2341 f->protection == !!(type & IEEE80211_TWT_REQTYPE_PROTECTION) && 2342 f->flowtype == !!(type & IEEE80211_TWT_REQTYPE_FLOWTYPE) && 2343 f->trigger == !!(type & IEEE80211_TWT_REQTYPE_TRIGGER)) 2344 return true; 2345 } 2346 2347 return false; 2348 } 2349 2350 void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw, 2351 struct ieee80211_sta *sta, 2352 struct ieee80211_twt_setup *twt) 2353 { 2354 enum ieee80211_twt_setup_cmd setup_cmd = TWT_SETUP_CMD_REJECT; 2355 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv; 2356 struct ieee80211_twt_params *twt_agrt = (void *)twt->params; 2357 u16 req_type = le16_to_cpu(twt_agrt->req_type); 2358 enum ieee80211_twt_setup_cmd sta_setup_cmd; 2359 struct mt7915_dev *dev = mt7915_hw_dev(hw); 2360 struct mt7915_twt_flow *flow; 2361 int flowid, table_id; 2362 u8 exp; 2363 2364 if (mt7915_mac_check_twt_req(twt)) 2365 goto out; 2366 2367 mutex_lock(&dev->mt76.mutex); 2368 2369 if (dev->twt.n_agrt == MT7915_MAX_TWT_AGRT) 2370 goto unlock; 2371 2372 if (hweight8(msta->twt.flowid_mask) == ARRAY_SIZE(msta->twt.flow)) 2373 goto unlock; 2374 2375 if (twt_agrt->min_twt_dur < MT7915_MIN_TWT_DUR) { 2376 setup_cmd = TWT_SETUP_CMD_DICTATE; 2377 twt_agrt->min_twt_dur = MT7915_MIN_TWT_DUR; 2378 goto unlock; 2379 } 2380 2381 flowid = ffs(~msta->twt.flowid_mask) - 1; 2382 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_FLOWID); 2383 twt_agrt->req_type |= le16_encode_bits(flowid, 2384 IEEE80211_TWT_REQTYPE_FLOWID); 2385 2386 table_id = ffs(~dev->twt.table_mask) - 1; 2387 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, req_type); 2388 sta_setup_cmd = FIELD_GET(IEEE80211_TWT_REQTYPE_SETUP_CMD, req_type); 2389 2390 if (mt7915_mac_twt_param_equal(msta, twt_agrt)) 2391 goto unlock; 2392 2393 flow = &msta->twt.flow[flowid]; 2394 memset(flow, 0, sizeof(*flow)); 2395 INIT_LIST_HEAD(&flow->list); 2396 flow->wcid = msta->wcid.idx; 2397 flow->table_id = table_id; 2398 flow->id = flowid; 2399 flow->duration = twt_agrt->min_twt_dur; 2400 flow->mantissa = twt_agrt->mantissa; 2401 flow->exp = exp; 2402 flow->protection = !!(req_type & IEEE80211_TWT_REQTYPE_PROTECTION); 2403 flow->flowtype = !!(req_type & IEEE80211_TWT_REQTYPE_FLOWTYPE); 2404 flow->trigger = !!(req_type & IEEE80211_TWT_REQTYPE_TRIGGER); 2405 2406 if (sta_setup_cmd == TWT_SETUP_CMD_REQUEST || 2407 sta_setup_cmd == TWT_SETUP_CMD_SUGGEST) { 2408 u64 interval = (u64)le16_to_cpu(twt_agrt->mantissa) << exp; 2409 u64 flow_tsf, curr_tsf; 2410 u32 rem; 2411 2412 flow->sched = true; 2413 flow->start_tsf = mt7915_mac_twt_sched_list_add(dev, flow); 2414 curr_tsf = __mt7915_get_tsf(hw, msta->vif); 2415 div_u64_rem(curr_tsf - flow->start_tsf, interval, &rem); 2416 flow_tsf = curr_tsf + interval - rem; 2417 twt_agrt->twt = cpu_to_le64(flow_tsf); 2418 } else { 2419 list_add_tail(&flow->list, &dev->twt_list); 2420 } 2421 flow->tsf = le64_to_cpu(twt_agrt->twt); 2422 2423 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, MCU_TWT_AGRT_ADD)) 2424 goto unlock; 2425 2426 setup_cmd = TWT_SETUP_CMD_ACCEPT; 2427 dev->twt.table_mask |= BIT(table_id); 2428 msta->twt.flowid_mask |= BIT(flowid); 2429 dev->twt.n_agrt++; 2430 2431 unlock: 2432 mutex_unlock(&dev->mt76.mutex); 2433 out: 2434 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_SETUP_CMD); 2435 twt_agrt->req_type |= 2436 le16_encode_bits(setup_cmd, IEEE80211_TWT_REQTYPE_SETUP_CMD); 2437 twt->control = (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) | 2438 (twt->control & IEEE80211_TWT_CONTROL_RX_DISABLED); 2439 } 2440 2441 void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev, 2442 struct mt7915_sta *msta, 2443 u8 flowid) 2444 { 2445 struct mt7915_twt_flow *flow; 2446 2447 lockdep_assert_held(&dev->mt76.mutex); 2448 2449 if (flowid >= ARRAY_SIZE(msta->twt.flow)) 2450 return; 2451 2452 if (!(msta->twt.flowid_mask & BIT(flowid))) 2453 return; 2454 2455 flow = &msta->twt.flow[flowid]; 2456 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, 2457 MCU_TWT_AGRT_DELETE)) 2458 return; 2459 2460 list_del_init(&flow->list); 2461 msta->twt.flowid_mask &= ~BIT(flowid); 2462 dev->twt.table_mask &= ~BIT(flow->table_id); 2463 dev->twt.n_agrt--; 2464 } 2465