1 // SPDX-License-Identifier: ISC 2 /* Copyright (C) 2020 MediaTek Inc. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/timekeeping.h> 6 #if defined(__FreeBSD__) 7 #include <linux/delay.h> 8 #include <linux/math64.h> 9 #endif 10 #include "coredump.h" 11 #include "mt7915.h" 12 #include "../dma.h" 13 #include "mac.h" 14 #include "mcu.h" 15 16 #define to_rssi(field, rcpi) ((FIELD_GET(field, rcpi) - 220) / 2) 17 18 static const struct mt7915_dfs_radar_spec etsi_radar_specs = { 19 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 20 .radar_pattern = { 21 [5] = { 1, 0, 6, 32, 28, 0, 990, 5010, 17, 1, 1 }, 22 [6] = { 1, 0, 9, 32, 28, 0, 615, 5010, 27, 1, 1 }, 23 [7] = { 1, 0, 15, 32, 28, 0, 240, 445, 27, 1, 1 }, 24 [8] = { 1, 0, 12, 32, 28, 0, 240, 510, 42, 1, 1 }, 25 [9] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 12, 32, 28, { }, 126 }, 26 [10] = { 1, 1, 0, 0, 0, 0, 2490, 3343, 14, 0, 0, 15, 32, 24, { }, 126 }, 27 [11] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 18, 32, 28, { }, 54 }, 28 [12] = { 1, 1, 0, 0, 0, 0, 823, 2510, 14, 0, 0, 27, 32, 24, { }, 54 }, 29 }, 30 }; 31 32 static const struct mt7915_dfs_radar_spec fcc_radar_specs = { 33 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 34 .radar_pattern = { 35 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 36 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 37 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 38 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 39 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 40 }, 41 }; 42 43 static const struct mt7915_dfs_radar_spec jp_radar_specs = { 44 .pulse_th = { 110, -10, -80, 40, 5200, 128, 5200 }, 45 .radar_pattern = { 46 [0] = { 1, 0, 8, 32, 28, 0, 508, 3076, 13, 1, 1 }, 47 [1] = { 1, 0, 12, 32, 28, 0, 140, 240, 17, 1, 1 }, 48 [2] = { 1, 0, 8, 32, 28, 0, 190, 510, 22, 1, 1 }, 49 [3] = { 1, 0, 6, 32, 28, 0, 190, 510, 32, 1, 1 }, 50 [4] = { 1, 0, 9, 255, 28, 0, 323, 343, 13, 1, 32 }, 51 [13] = { 1, 0, 7, 32, 28, 0, 3836, 3856, 14, 1, 1 }, 52 [14] = { 1, 0, 6, 32, 28, 0, 615, 5010, 110, 1, 1 }, 53 [15] = { 1, 1, 0, 0, 0, 0, 15, 5010, 110, 0, 0, 12, 32, 28 }, 54 }, 55 }; 56 57 static struct mt76_wcid *mt7915_rx_get_wcid(struct mt7915_dev *dev, 58 u16 idx, bool unicast) 59 { 60 struct mt7915_sta *sta; 61 struct mt76_wcid *wcid; 62 63 wcid = mt76_wcid_ptr(dev, idx); 64 if (unicast || !wcid) 65 return wcid; 66 67 if (!wcid->sta) 68 return NULL; 69 70 sta = container_of(wcid, struct mt7915_sta, wcid); 71 if (!sta->vif) 72 return NULL; 73 74 return &sta->vif->sta.wcid; 75 } 76 77 bool mt7915_mac_wtbl_update(struct mt7915_dev *dev, int idx, u32 mask) 78 { 79 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX, 80 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask); 81 82 return mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 83 0, 5000); 84 } 85 86 u32 mt7915_mac_wtbl_lmac_addr(struct mt7915_dev *dev, u16 wcid, u8 dw) 87 { 88 mt76_wr(dev, MT_WTBLON_TOP_WDUCR, 89 FIELD_PREP(MT_WTBLON_TOP_WDUCR_GROUP, (wcid >> 7))); 90 91 return MT_WTBL_LMAC_OFFS(wcid, dw); 92 } 93 94 static void mt7915_mac_sta_poll(struct mt7915_dev *dev) 95 { 96 static const u8 ac_to_tid[] = { 97 [IEEE80211_AC_BE] = 0, 98 [IEEE80211_AC_BK] = 1, 99 [IEEE80211_AC_VI] = 4, 100 [IEEE80211_AC_VO] = 6 101 }; 102 struct ieee80211_sta *sta; 103 struct mt7915_sta *msta; 104 struct rate_info *rate; 105 u32 tx_time[IEEE80211_NUM_ACS], rx_time[IEEE80211_NUM_ACS]; 106 #if defined(__linux__) 107 LIST_HEAD(sta_poll_list); 108 #elif defined(__FreeBSD__) 109 LINUX_LIST_HEAD(sta_poll_list); 110 #endif 111 int i; 112 113 spin_lock_bh(&dev->mt76.sta_poll_lock); 114 list_splice_init(&dev->mt76.sta_poll_list, &sta_poll_list); 115 spin_unlock_bh(&dev->mt76.sta_poll_lock); 116 117 rcu_read_lock(); 118 119 while (true) { 120 bool clear = false; 121 u32 addr, val; 122 u16 idx; 123 s8 rssi[4]; 124 u8 bw; 125 126 spin_lock_bh(&dev->mt76.sta_poll_lock); 127 if (list_empty(&sta_poll_list)) { 128 spin_unlock_bh(&dev->mt76.sta_poll_lock); 129 break; 130 } 131 msta = list_first_entry(&sta_poll_list, 132 struct mt7915_sta, wcid.poll_list); 133 list_del_init(&msta->wcid.poll_list); 134 spin_unlock_bh(&dev->mt76.sta_poll_lock); 135 136 idx = msta->wcid.idx; 137 138 /* refresh peer's airtime reporting */ 139 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 20); 140 141 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 142 u32 tx_last = msta->airtime_ac[i]; 143 u32 rx_last = msta->airtime_ac[i + 4]; 144 145 msta->airtime_ac[i] = mt76_rr(dev, addr); 146 msta->airtime_ac[i + 4] = mt76_rr(dev, addr + 4); 147 148 if (msta->airtime_ac[i] <= tx_last) 149 tx_time[i] = 0; 150 else 151 tx_time[i] = msta->airtime_ac[i] - tx_last; 152 153 if (msta->airtime_ac[i + 4] <= rx_last) 154 rx_time[i] = 0; 155 else 156 rx_time[i] = msta->airtime_ac[i + 4] - rx_last; 157 158 if ((tx_last | rx_last) & BIT(30)) 159 clear = true; 160 161 addr += 8; 162 } 163 164 if (clear) { 165 mt7915_mac_wtbl_update(dev, idx, 166 MT_WTBL_UPDATE_ADM_COUNT_CLEAR); 167 memset(msta->airtime_ac, 0, sizeof(msta->airtime_ac)); 168 } 169 170 if (!msta->wcid.sta) 171 continue; 172 173 sta = container_of((void *)msta, struct ieee80211_sta, 174 drv_priv); 175 for (i = 0; i < IEEE80211_NUM_ACS; i++) { 176 u8 queue = mt76_connac_lmac_mapping(i); 177 u32 tx_cur = tx_time[queue]; 178 u32 rx_cur = rx_time[queue]; 179 u8 tid = ac_to_tid[i]; 180 181 if (!tx_cur && !rx_cur) 182 continue; 183 184 ieee80211_sta_register_airtime(sta, tid, tx_cur, 185 rx_cur); 186 } 187 188 /* 189 * We don't support reading GI info from txs packets. 190 * For accurate tx status reporting and AQL improvement, 191 * we need to make sure that flags match so polling GI 192 * from per-sta counters directly. 193 */ 194 rate = &msta->wcid.rate; 195 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 7); 196 val = mt76_rr(dev, addr); 197 198 switch (rate->bw) { 199 case RATE_INFO_BW_160: 200 bw = IEEE80211_STA_RX_BW_160; 201 break; 202 case RATE_INFO_BW_80: 203 bw = IEEE80211_STA_RX_BW_80; 204 break; 205 case RATE_INFO_BW_40: 206 bw = IEEE80211_STA_RX_BW_40; 207 break; 208 default: 209 bw = IEEE80211_STA_RX_BW_20; 210 break; 211 } 212 213 if (rate->flags & RATE_INFO_FLAGS_HE_MCS) { 214 u8 offs = 24 + 2 * bw; 215 216 rate->he_gi = (val & (0x3 << offs)) >> offs; 217 } else if (rate->flags & 218 (RATE_INFO_FLAGS_VHT_MCS | RATE_INFO_FLAGS_MCS)) { 219 if (val & BIT(12 + bw)) 220 rate->flags |= RATE_INFO_FLAGS_SHORT_GI; 221 else 222 rate->flags &= ~RATE_INFO_FLAGS_SHORT_GI; 223 } 224 225 /* get signal strength of resp frames (CTS/BA/ACK) */ 226 addr = mt7915_mac_wtbl_lmac_addr(dev, idx, 30); 227 val = mt76_rr(dev, addr); 228 229 rssi[0] = to_rssi(GENMASK(7, 0), val); 230 rssi[1] = to_rssi(GENMASK(15, 8), val); 231 rssi[2] = to_rssi(GENMASK(23, 16), val); 232 rssi[3] = to_rssi(GENMASK(31, 14), val); 233 234 msta->ack_signal = 235 mt76_rx_signal(msta->vif->phy->mt76->antenna_mask, rssi); 236 237 ewma_avg_signal_add(&msta->avg_ack_signal, -msta->ack_signal); 238 } 239 240 rcu_read_unlock(); 241 } 242 243 void mt7915_mac_enable_rtscts(struct mt7915_dev *dev, 244 struct ieee80211_vif *vif, bool enable) 245 { 246 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 247 u32 addr; 248 249 addr = mt7915_mac_wtbl_lmac_addr(dev, mvif->sta.wcid.idx, 5); 250 if (enable) 251 mt76_set(dev, addr, BIT(5)); 252 else 253 mt76_clear(dev, addr, BIT(5)); 254 } 255 256 static void 257 mt7915_wed_check_ppe(struct mt7915_dev *dev, struct mt76_queue *q, 258 struct mt7915_sta *msta, struct sk_buff *skb, 259 u32 info) 260 { 261 struct ieee80211_vif *vif; 262 struct wireless_dev *wdev; 263 264 if (!msta || !msta->vif) 265 return; 266 267 if (!mt76_queue_is_wed_rx(q)) 268 return; 269 270 if (!(info & MT_DMA_INFO_PPE_VLD)) 271 return; 272 273 vif = container_of((void *)msta->vif, struct ieee80211_vif, 274 drv_priv); 275 wdev = ieee80211_vif_to_wdev(vif); 276 skb->dev = wdev->netdev; 277 278 mtk_wed_device_ppe_check(&dev->mt76.mmio.wed, skb, 279 FIELD_GET(MT_DMA_PPE_CPU_REASON, info), 280 FIELD_GET(MT_DMA_PPE_ENTRY, info)); 281 } 282 283 static int 284 mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb, 285 enum mt76_rxq_id q, u32 *info) 286 { 287 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb; 288 struct mt76_phy *mphy = &dev->mt76.phy; 289 struct mt7915_phy *phy = &dev->phy; 290 struct ieee80211_supported_band *sband; 291 __le32 *rxd = (__le32 *)skb->data; 292 __le32 *rxv = NULL; 293 u32 rxd0 = le32_to_cpu(rxd[0]); 294 u32 rxd1 = le32_to_cpu(rxd[1]); 295 u32 rxd2 = le32_to_cpu(rxd[2]); 296 u32 rxd3 = le32_to_cpu(rxd[3]); 297 u32 rxd4 = le32_to_cpu(rxd[4]); 298 u32 csum_mask = MT_RXD0_NORMAL_IP_SUM | MT_RXD0_NORMAL_UDP_TCP_SUM; 299 bool unicast, insert_ccmp_hdr = false; 300 u8 remove_pad, amsdu_info; 301 u8 mode = 0, qos_ctl = 0; 302 struct mt7915_sta *msta = NULL; 303 u32 csum_status = *(u32 *)skb->cb; 304 bool hdr_trans; 305 u16 hdr_gap; 306 u16 seq_ctrl = 0; 307 __le16 fc = 0; 308 int idx; 309 310 memset(status, 0, sizeof(*status)); 311 312 if ((rxd1 & MT_RXD1_NORMAL_BAND_IDX) && !phy->mt76->band_idx) { 313 mphy = dev->mt76.phys[MT_BAND1]; 314 if (!mphy) 315 return -EINVAL; 316 317 phy = mphy->priv; 318 status->phy_idx = 1; 319 } 320 321 if (!test_bit(MT76_STATE_RUNNING, &mphy->state)) 322 return -EINVAL; 323 324 if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) 325 return -EINVAL; 326 327 hdr_trans = rxd2 & MT_RXD2_NORMAL_HDR_TRANS; 328 if (hdr_trans && (rxd1 & MT_RXD1_NORMAL_CM)) 329 return -EINVAL; 330 331 /* ICV error or CCMP/BIP/WPI MIC error */ 332 if (rxd1 & MT_RXD1_NORMAL_ICV_ERR) 333 status->flag |= RX_FLAG_ONLY_MONITOR; 334 335 unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M; 336 idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1); 337 status->wcid = mt7915_rx_get_wcid(dev, idx, unicast); 338 339 if (status->wcid) { 340 msta = container_of(status->wcid, struct mt7915_sta, wcid); 341 mt76_wcid_add_poll(&dev->mt76, &msta->wcid); 342 } 343 344 status->freq = mphy->chandef.chan->center_freq; 345 status->band = mphy->chandef.chan->band; 346 if (status->band == NL80211_BAND_5GHZ) 347 sband = &mphy->sband_5g.sband; 348 else if (status->band == NL80211_BAND_6GHZ) 349 sband = &mphy->sband_6g.sband; 350 else 351 sband = &mphy->sband_2g.sband; 352 353 if (!sband->channels) 354 return -EINVAL; 355 356 if ((rxd0 & csum_mask) == csum_mask && 357 !(csum_status & (BIT(0) | BIT(2) | BIT(3)))) 358 skb->ip_summed = CHECKSUM_UNNECESSARY; 359 360 if (rxd1 & MT_RXD1_NORMAL_FCS_ERR) 361 status->flag |= RX_FLAG_FAILED_FCS_CRC; 362 363 if (rxd1 & MT_RXD1_NORMAL_TKIP_MIC_ERR) 364 status->flag |= RX_FLAG_MMIC_ERROR; 365 366 if (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1) != 0 && 367 !(rxd1 & (MT_RXD1_NORMAL_CLM | MT_RXD1_NORMAL_CM))) { 368 status->flag |= RX_FLAG_DECRYPTED; 369 status->flag |= RX_FLAG_IV_STRIPPED; 370 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED; 371 } 372 373 remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2); 374 375 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) 376 return -EINVAL; 377 378 rxd += 6; 379 if (rxd1 & MT_RXD1_NORMAL_GROUP_4) { 380 u32 v0 = le32_to_cpu(rxd[0]); 381 u32 v2 = le32_to_cpu(rxd[2]); 382 383 fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0)); 384 qos_ctl = FIELD_GET(MT_RXD8_QOS_CTL, v2); 385 seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2); 386 387 rxd += 4; 388 if ((u8 *)rxd - skb->data >= skb->len) 389 return -EINVAL; 390 } 391 392 if (rxd1 & MT_RXD1_NORMAL_GROUP_1) { 393 u8 *data = (u8 *)rxd; 394 395 if (status->flag & RX_FLAG_DECRYPTED) { 396 switch (FIELD_GET(MT_RXD1_NORMAL_SEC_MODE, rxd1)) { 397 case MT_CIPHER_AES_CCMP: 398 case MT_CIPHER_CCMP_CCX: 399 case MT_CIPHER_CCMP_256: 400 insert_ccmp_hdr = 401 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2); 402 fallthrough; 403 case MT_CIPHER_TKIP: 404 case MT_CIPHER_TKIP_NO_MIC: 405 case MT_CIPHER_GCMP: 406 case MT_CIPHER_GCMP_256: 407 status->iv[0] = data[5]; 408 status->iv[1] = data[4]; 409 status->iv[2] = data[3]; 410 status->iv[3] = data[2]; 411 status->iv[4] = data[1]; 412 status->iv[5] = data[0]; 413 break; 414 default: 415 break; 416 } 417 } 418 rxd += 4; 419 if ((u8 *)rxd - skb->data >= skb->len) 420 return -EINVAL; 421 } 422 423 if (rxd1 & MT_RXD1_NORMAL_GROUP_2) { 424 status->timestamp = le32_to_cpu(rxd[0]); 425 status->flag |= RX_FLAG_MACTIME_START; 426 427 if (!(rxd2 & MT_RXD2_NORMAL_NON_AMPDU)) { 428 status->flag |= RX_FLAG_AMPDU_DETAILS; 429 430 /* all subframes of an A-MPDU have the same timestamp */ 431 if (phy->rx_ampdu_ts != status->timestamp) { 432 if (!++phy->ampdu_ref) 433 phy->ampdu_ref++; 434 } 435 phy->rx_ampdu_ts = status->timestamp; 436 437 status->ampdu_ref = phy->ampdu_ref; 438 } 439 440 rxd += 2; 441 if ((u8 *)rxd - skb->data >= skb->len) 442 return -EINVAL; 443 } 444 445 /* RXD Group 3 - P-RXV */ 446 if (rxd1 & MT_RXD1_NORMAL_GROUP_3) { 447 u32 v0, v1; 448 int ret; 449 450 rxv = rxd; 451 rxd += 2; 452 if ((u8 *)rxd - skb->data >= skb->len) 453 return -EINVAL; 454 455 v0 = le32_to_cpu(rxv[0]); 456 v1 = le32_to_cpu(rxv[1]); 457 458 if (v0 & MT_PRXV_HT_AD_CODE) 459 status->enc_flags |= RX_ENC_FLAG_LDPC; 460 461 status->chains = mphy->antenna_mask; 462 status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1); 463 status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1); 464 status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1); 465 status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1); 466 467 /* RXD Group 5 - C-RXV */ 468 if (rxd1 & MT_RXD1_NORMAL_GROUP_5) { 469 rxd += 18; 470 if ((u8 *)rxd - skb->data >= skb->len) 471 return -EINVAL; 472 } 473 474 if (!is_mt7915(&dev->mt76) || (rxd1 & MT_RXD1_NORMAL_GROUP_5)) { 475 ret = mt76_connac2_mac_fill_rx_rate(&dev->mt76, status, 476 sband, rxv, &mode); 477 if (ret < 0) 478 return ret; 479 } 480 } 481 482 amsdu_info = FIELD_GET(MT_RXD4_NORMAL_PAYLOAD_FORMAT, rxd4); 483 status->amsdu = !!amsdu_info; 484 if (status->amsdu) { 485 status->first_amsdu = amsdu_info == MT_RXD4_FIRST_AMSDU_FRAME; 486 status->last_amsdu = amsdu_info == MT_RXD4_LAST_AMSDU_FRAME; 487 } 488 489 hdr_gap = (u8 *)rxd - skb->data + 2 * remove_pad; 490 if (hdr_trans && ieee80211_has_morefrags(fc)) { 491 struct ieee80211_vif *vif; 492 int err; 493 494 if (!msta || !msta->vif) 495 return -EINVAL; 496 497 vif = container_of((void *)msta->vif, struct ieee80211_vif, 498 drv_priv); 499 err = mt76_connac2_reverse_frag0_hdr_trans(vif, skb, hdr_gap); 500 if (err) 501 return err; 502 503 hdr_trans = false; 504 } else { 505 int pad_start = 0; 506 507 skb_pull(skb, hdr_gap); 508 if (!hdr_trans && status->amsdu) { 509 pad_start = ieee80211_get_hdrlen_from_skb(skb); 510 } else if (hdr_trans && (rxd2 & MT_RXD2_NORMAL_HDR_TRANS_ERROR)) { 511 /* 512 * When header translation failure is indicated, 513 * the hardware will insert an extra 2-byte field 514 * containing the data length after the protocol 515 * type field. This happens either when the LLC-SNAP 516 * pattern did not match, or if a VLAN header was 517 * detected. 518 */ 519 pad_start = 12; 520 if (get_unaligned_be16(skb->data + pad_start) == ETH_P_8021Q) 521 pad_start += 4; 522 else 523 pad_start = 0; 524 } 525 526 if (pad_start) { 527 memmove(skb->data + 2, skb->data, pad_start); 528 skb_pull(skb, 2); 529 } 530 } 531 532 if (!hdr_trans) { 533 struct ieee80211_hdr *hdr; 534 535 if (insert_ccmp_hdr) { 536 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1); 537 538 mt76_insert_ccmp_hdr(skb, key_id); 539 } 540 541 hdr = mt76_skb_get_hdr(skb); 542 fc = hdr->frame_control; 543 if (ieee80211_is_data_qos(fc)) { 544 seq_ctrl = le16_to_cpu(hdr->seq_ctrl); 545 qos_ctl = *ieee80211_get_qos_ctl(hdr); 546 } 547 } else { 548 status->flag |= RX_FLAG_8023; 549 mt7915_wed_check_ppe(dev, &dev->mt76.q_rx[q], msta, skb, 550 *info); 551 } 552 553 if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023)) 554 mt76_connac2_mac_decode_he_radiotap(&dev->mt76, skb, rxv, mode); 555 556 if (!status->wcid || !ieee80211_is_data_qos(fc)) 557 return 0; 558 559 status->aggr = unicast && 560 !ieee80211_is_qos_nullfunc(fc); 561 status->qos_ctl = qos_ctl; 562 status->seqno = IEEE80211_SEQ_TO_SN(seq_ctrl); 563 564 return 0; 565 } 566 567 static void 568 mt7915_mac_fill_rx_vector(struct mt7915_dev *dev, struct sk_buff *skb) 569 { 570 #ifdef CONFIG_NL80211_TESTMODE 571 struct mt7915_phy *phy = &dev->phy; 572 __le32 *rxd = (__le32 *)skb->data; 573 __le32 *rxv_hdr = rxd + 2; 574 __le32 *rxv = rxd + 4; 575 u32 rcpi, ib_rssi, wb_rssi, v20, v21; 576 u8 band_idx; 577 s32 foe; 578 u8 snr; 579 int i; 580 581 band_idx = le32_get_bits(rxv_hdr[1], MT_RXV_HDR_BAND_IDX); 582 if (band_idx && !phy->mt76->band_idx) { 583 phy = mt7915_ext_phy(dev); 584 if (!phy) 585 goto out; 586 } 587 588 rcpi = le32_to_cpu(rxv[6]); 589 ib_rssi = le32_to_cpu(rxv[7]); 590 wb_rssi = le32_to_cpu(rxv[8]) >> 5; 591 592 for (i = 0; i < 4; i++, rcpi >>= 8, ib_rssi >>= 8, wb_rssi >>= 9) { 593 if (i == 3) 594 wb_rssi = le32_to_cpu(rxv[9]); 595 596 phy->test.last_rcpi[i] = rcpi & 0xff; 597 phy->test.last_ib_rssi[i] = ib_rssi & 0xff; 598 phy->test.last_wb_rssi[i] = wb_rssi & 0xff; 599 } 600 601 v20 = le32_to_cpu(rxv[20]); 602 v21 = le32_to_cpu(rxv[21]); 603 604 foe = FIELD_GET(MT_CRXV_FOE_LO, v20) | 605 (FIELD_GET(MT_CRXV_FOE_HI, v21) << MT_CRXV_FOE_SHIFT); 606 607 snr = FIELD_GET(MT_CRXV_SNR, v20) - 16; 608 609 phy->test.last_freq_offset = foe; 610 phy->test.last_snr = snr; 611 out: 612 #endif 613 dev_kfree_skb(skb); 614 } 615 616 static void 617 mt7915_mac_write_txwi_tm(struct mt7915_phy *phy, __le32 *txwi, 618 struct sk_buff *skb) 619 { 620 #ifdef CONFIG_NL80211_TESTMODE 621 struct mt76_testmode_data *td = &phy->mt76->test; 622 const struct ieee80211_rate *r; 623 u8 bw, mode, nss = td->tx_rate_nss; 624 u8 rate_idx = td->tx_rate_idx; 625 u16 rateval = 0; 626 u32 val; 627 bool cck = false; 628 int band; 629 630 if (skb != phy->mt76->test.tx_skb) 631 return; 632 633 switch (td->tx_rate_mode) { 634 case MT76_TM_TX_MODE_HT: 635 nss = 1 + (rate_idx >> 3); 636 mode = MT_PHY_TYPE_HT; 637 break; 638 case MT76_TM_TX_MODE_VHT: 639 mode = MT_PHY_TYPE_VHT; 640 break; 641 case MT76_TM_TX_MODE_HE_SU: 642 mode = MT_PHY_TYPE_HE_SU; 643 break; 644 case MT76_TM_TX_MODE_HE_EXT_SU: 645 mode = MT_PHY_TYPE_HE_EXT_SU; 646 break; 647 case MT76_TM_TX_MODE_HE_TB: 648 mode = MT_PHY_TYPE_HE_TB; 649 break; 650 case MT76_TM_TX_MODE_HE_MU: 651 mode = MT_PHY_TYPE_HE_MU; 652 break; 653 case MT76_TM_TX_MODE_CCK: 654 cck = true; 655 fallthrough; 656 case MT76_TM_TX_MODE_OFDM: 657 band = phy->mt76->chandef.chan->band; 658 if (band == NL80211_BAND_2GHZ && !cck) 659 rate_idx += 4; 660 661 r = &phy->mt76->hw->wiphy->bands[band]->bitrates[rate_idx]; 662 val = cck ? r->hw_value_short : r->hw_value; 663 664 mode = val >> 8; 665 rate_idx = val & 0xff; 666 break; 667 default: 668 mode = MT_PHY_TYPE_OFDM; 669 break; 670 } 671 672 switch (phy->mt76->chandef.width) { 673 case NL80211_CHAN_WIDTH_40: 674 bw = 1; 675 break; 676 case NL80211_CHAN_WIDTH_80: 677 bw = 2; 678 break; 679 case NL80211_CHAN_WIDTH_80P80: 680 case NL80211_CHAN_WIDTH_160: 681 bw = 3; 682 break; 683 default: 684 bw = 0; 685 break; 686 } 687 688 if (td->tx_rate_stbc && nss == 1) { 689 nss++; 690 rateval |= MT_TX_RATE_STBC; 691 } 692 693 rateval |= FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | 694 FIELD_PREP(MT_TX_RATE_MODE, mode) | 695 FIELD_PREP(MT_TX_RATE_NSS, nss - 1); 696 697 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE); 698 699 le32p_replace_bits(&txwi[3], 1, MT_TXD3_REM_TX_COUNT); 700 if (td->tx_rate_mode < MT76_TM_TX_MODE_HT) 701 txwi[3] |= cpu_to_le32(MT_TXD3_BA_DISABLE); 702 703 val = MT_TXD6_FIXED_BW | 704 FIELD_PREP(MT_TXD6_BW, bw) | 705 FIELD_PREP(MT_TXD6_TX_RATE, rateval) | 706 FIELD_PREP(MT_TXD6_SGI, td->tx_rate_sgi); 707 708 /* for HE_SU/HE_EXT_SU PPDU 709 * - 1x, 2x, 4x LTF + 0.8us GI 710 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 711 * for HE_MU PPDU 712 * - 2x, 4x LTF + 0.8us GI 713 * - 2x LTF + 1.6us GI, 4x LTF + 3.2us GI 714 * for HE_TB PPDU 715 * - 1x, 2x LTF + 1.6us GI 716 * - 4x LTF + 3.2us GI 717 */ 718 if (mode >= MT_PHY_TYPE_HE_SU) 719 val |= FIELD_PREP(MT_TXD6_HELTF, td->tx_ltf); 720 721 if (td->tx_rate_ldpc || (bw > 0 && mode >= MT_PHY_TYPE_HE_SU)) 722 val |= MT_TXD6_LDPC; 723 724 txwi[3] &= ~cpu_to_le32(MT_TXD3_SN_VALID); 725 txwi[6] |= cpu_to_le32(val); 726 txwi[7] |= cpu_to_le32(FIELD_PREP(MT_TXD7_SPE_IDX, 727 phy->test.spe_idx)); 728 #endif 729 } 730 731 void mt7915_mac_write_txwi(struct mt76_dev *dev, __le32 *txwi, 732 struct sk_buff *skb, struct mt76_wcid *wcid, int pid, 733 struct ieee80211_key_conf *key, 734 enum mt76_txq_id qid, u32 changed) 735 { 736 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 737 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 738 struct mt76_phy *mphy = &dev->phy; 739 740 if (phy_idx && dev->phys[MT_BAND1]) 741 mphy = dev->phys[MT_BAND1]; 742 743 mt76_connac2_mac_write_txwi(dev, txwi, skb, wcid, key, pid, qid, changed); 744 745 if (mt76_testmode_enabled(mphy)) 746 mt7915_mac_write_txwi_tm(mphy->priv, txwi, skb); 747 } 748 749 int mt7915_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr, 750 enum mt76_txq_id qid, struct mt76_wcid *wcid, 751 struct ieee80211_sta *sta, 752 struct mt76_tx_info *tx_info) 753 { 754 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)tx_info->skb->data; 755 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 756 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb); 757 struct ieee80211_key_conf *key = info->control.hw_key; 758 struct ieee80211_vif *vif = info->control.vif; 759 struct mt76_connac_fw_txp *txp; 760 struct mt76_txwi_cache *t; 761 int id, i, nbuf = tx_info->nbuf - 1; 762 u8 *txwi = (u8 *)txwi_ptr; 763 int pid; 764 765 if (unlikely(tx_info->skb->len <= ETH_HLEN)) 766 return -EINVAL; 767 768 if (!wcid) 769 wcid = &dev->mt76.global_wcid; 770 771 if (sta) { 772 struct mt7915_sta *msta; 773 774 msta = (struct mt7915_sta *)sta->drv_priv; 775 776 if (time_after(jiffies, msta->jiffies + HZ / 4)) { 777 info->flags |= IEEE80211_TX_CTL_REQ_TX_STATUS; 778 msta->jiffies = jiffies; 779 } 780 } 781 782 t = (struct mt76_txwi_cache *)(txwi + mdev->drv->txwi_size); 783 t->skb = tx_info->skb; 784 785 id = mt76_token_consume(mdev, &t); 786 if (id < 0) 787 return id; 788 789 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); 790 mt7915_mac_write_txwi(mdev, txwi_ptr, tx_info->skb, wcid, pid, key, 791 qid, 0); 792 793 txp = (struct mt76_connac_fw_txp *)(txwi + MT_TXD_SIZE); 794 for (i = 0; i < nbuf; i++) { 795 txp->buf[i] = cpu_to_le32(tx_info->buf[i + 1].addr); 796 txp->len[i] = cpu_to_le16(tx_info->buf[i + 1].len); 797 } 798 txp->nbuf = nbuf; 799 800 txp->flags = cpu_to_le16(MT_CT_INFO_APPLY_TXD | MT_CT_INFO_FROM_HOST); 801 802 if (!key) 803 txp->flags |= cpu_to_le16(MT_CT_INFO_NONE_CIPHER_FRAME); 804 805 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 806 ieee80211_is_mgmt(hdr->frame_control)) 807 txp->flags |= cpu_to_le16(MT_CT_INFO_MGMT_FRAME); 808 809 if (vif) { 810 struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; 811 812 txp->bss_idx = mvif->mt76.idx; 813 } 814 815 txp->token = cpu_to_le16(id); 816 if (test_bit(MT_WCID_FLAG_4ADDR, &wcid->flags)) 817 txp->rept_wds_wcid = cpu_to_le16(wcid->idx); 818 else 819 txp->rept_wds_wcid = cpu_to_le16(0x3ff); 820 tx_info->skb = NULL; 821 822 /* pass partial skb header to fw */ 823 tx_info->buf[1].len = MT_CT_PARSE_LEN; 824 tx_info->buf[1].skip_unmap = true; 825 tx_info->nbuf = MT_CT_DMA_BUF_NUM; 826 827 return 0; 828 } 829 830 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id) 831 { 832 #if defined(__linux__) 833 struct mt76_connac_fw_txp *txp = ptr + MT_TXD_SIZE; 834 #elif defined(__FreeBSD__) 835 struct mt76_connac_fw_txp *txp = (void *)((u8 *)ptr + MT_TXD_SIZE); 836 #endif 837 __le32 *txwi = ptr; 838 u32 val; 839 840 memset(ptr, 0, MT_TXD_SIZE + sizeof(*txp)); 841 842 val = FIELD_PREP(MT_TXD0_TX_BYTES, MT_TXD_SIZE) | 843 FIELD_PREP(MT_TXD0_PKT_FMT, MT_TX_TYPE_CT); 844 txwi[0] = cpu_to_le32(val); 845 846 val = MT_TXD1_LONG_FORMAT | 847 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_3); 848 txwi[1] = cpu_to_le32(val); 849 850 txp->token = cpu_to_le16(token_id); 851 txp->nbuf = 1; 852 txp->buf[0] = cpu_to_le32(phys + MT_TXD_SIZE + sizeof(*txp)); 853 854 return MT_TXD_SIZE + sizeof(*txp); 855 } 856 857 static void 858 mt7915_mac_tx_free_prepare(struct mt7915_dev *dev) 859 { 860 struct mt76_dev *mdev = &dev->mt76; 861 struct mt76_phy *mphy_ext = mdev->phys[MT_BAND1]; 862 863 /* clean DMA queues and unmap buffers first */ 864 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_PSD], false); 865 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[MT_TXQ_BE], false); 866 if (mphy_ext) { 867 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_PSD], false); 868 mt76_queue_tx_cleanup(dev, mphy_ext->q_tx[MT_TXQ_BE], false); 869 } 870 } 871 872 static void 873 mt7915_mac_tx_free_done(struct mt7915_dev *dev, 874 struct list_head *free_list, bool wake) 875 { 876 struct sk_buff *skb, *tmp; 877 878 mt7915_mac_sta_poll(dev); 879 880 if (wake) 881 mt76_set_tx_blocked(&dev->mt76, false); 882 883 mt76_worker_schedule(&dev->mt76.tx_worker); 884 885 list_for_each_entry_safe(skb, tmp, free_list, list) { 886 skb_list_del_init(skb); 887 napi_consume_skb(skb, 1); 888 } 889 } 890 891 static void 892 mt7915_mac_tx_free(struct mt7915_dev *dev, void *data, int len) 893 { 894 struct mt76_connac_tx_free *free = data; 895 #if defined(__linux__) 896 __le32 *tx_info = (__le32 *)(data + sizeof(*free)); 897 #elif defined(__FreeBSD__) 898 __le32 *tx_info = (__le32 *)((u8 *)data + sizeof(*free)); 899 #endif 900 struct mt76_dev *mdev = &dev->mt76; 901 struct mt76_txwi_cache *txwi; 902 struct ieee80211_sta *sta = NULL; 903 struct mt76_wcid *wcid = NULL; 904 #if defined(__linux__) 905 LIST_HEAD(free_list); 906 void *end = data + len; 907 #elif defined(__FreeBSD__) 908 LINUX_LIST_HEAD(free_list); 909 void *end = (u8 *)data + len; 910 #endif 911 bool v3, wake = false; 912 u16 total, count = 0; 913 u32 txd = le32_to_cpu(free->txd); 914 __le32 *cur_info; 915 916 mt7915_mac_tx_free_prepare(dev); 917 918 total = le16_get_bits(free->ctrl, MT_TX_FREE_MSDU_CNT); 919 v3 = (FIELD_GET(MT_TX_FREE_VER, txd) == 0x4); 920 921 for (cur_info = tx_info; count < total; cur_info++) { 922 u32 msdu, info; 923 u8 i; 924 925 if (WARN_ON_ONCE((void *)cur_info >= end)) 926 return; 927 928 /* 929 * 1'b1: new wcid pair. 930 * 1'b0: msdu_id with the same 'wcid pair' as above. 931 */ 932 info = le32_to_cpu(*cur_info); 933 if (info & MT_TX_FREE_PAIR) { 934 struct mt7915_sta *msta; 935 u16 idx; 936 937 idx = FIELD_GET(MT_TX_FREE_WLAN_ID, info); 938 wcid = mt76_wcid_ptr(dev, idx); 939 sta = wcid_to_sta(wcid); 940 if (!sta) 941 continue; 942 943 msta = container_of(wcid, struct mt7915_sta, wcid); 944 mt76_wcid_add_poll(&dev->mt76, &msta->wcid); 945 continue; 946 } 947 948 if (!mtk_wed_device_active(&mdev->mmio.wed) && wcid) { 949 u32 tx_retries = 0, tx_failed = 0; 950 951 if (v3 && (info & MT_TX_FREE_MPDU_HEADER_V3)) { 952 tx_retries = 953 FIELD_GET(MT_TX_FREE_COUNT_V3, info) - 1; 954 tx_failed = tx_retries + 955 !!FIELD_GET(MT_TX_FREE_STAT_V3, info); 956 } else if (!v3 && (info & MT_TX_FREE_MPDU_HEADER)) { 957 tx_retries = 958 FIELD_GET(MT_TX_FREE_COUNT, info) - 1; 959 tx_failed = tx_retries + 960 !!FIELD_GET(MT_TX_FREE_STAT, info); 961 } 962 wcid->stats.tx_retries += tx_retries; 963 wcid->stats.tx_failed += tx_failed; 964 } 965 966 if (v3 && (info & MT_TX_FREE_MPDU_HEADER_V3)) 967 continue; 968 969 for (i = 0; i < 1 + v3; i++) { 970 if (v3) { 971 msdu = (info >> (15 * i)) & MT_TX_FREE_MSDU_ID_V3; 972 if (msdu == MT_TX_FREE_MSDU_ID_V3) 973 continue; 974 } else { 975 msdu = FIELD_GET(MT_TX_FREE_MSDU_ID, info); 976 } 977 count++; 978 txwi = mt76_token_release(mdev, msdu, &wake); 979 if (!txwi) 980 continue; 981 982 mt76_connac2_txwi_free(mdev, txwi, sta, &free_list); 983 } 984 } 985 986 mt7915_mac_tx_free_done(dev, &free_list, wake); 987 } 988 989 static void 990 mt7915_mac_tx_free_v0(struct mt7915_dev *dev, void *data, int len) 991 { 992 struct mt76_connac_tx_free *free = data; 993 #if defined(__linux__) 994 __le16 *info = (__le16 *)(data + sizeof(*free)); 995 #elif defined(__FreeBSD__) 996 __le16 *info = (__le16 *)((u8 *)data + sizeof(*free)); 997 #endif 998 struct mt76_dev *mdev = &dev->mt76; 999 #if defined(__linux__) 1000 void *end = data + len; 1001 LIST_HEAD(free_list); 1002 #elif defined(__FreeBSD__) 1003 void *end = (u8 *)data + len; 1004 LINUX_LIST_HEAD(free_list); 1005 #endif 1006 bool wake = false; 1007 u8 i, count; 1008 1009 mt7915_mac_tx_free_prepare(dev); 1010 1011 count = FIELD_GET(MT_TX_FREE_MSDU_CNT_V0, le16_to_cpu(free->ctrl)); 1012 if (WARN_ON_ONCE((void *)&info[count] > end)) 1013 return; 1014 1015 for (i = 0; i < count; i++) { 1016 struct mt76_txwi_cache *txwi; 1017 u16 msdu = le16_to_cpu(info[i]); 1018 1019 txwi = mt76_token_release(mdev, msdu, &wake); 1020 if (!txwi) 1021 continue; 1022 1023 mt76_connac2_txwi_free(mdev, txwi, NULL, &free_list); 1024 } 1025 1026 mt7915_mac_tx_free_done(dev, &free_list, wake); 1027 } 1028 1029 static void mt7915_mac_add_txs(struct mt7915_dev *dev, void *data) 1030 { 1031 struct mt7915_sta *msta = NULL; 1032 struct mt76_wcid *wcid; 1033 __le32 *txs_data = data; 1034 u16 wcidx; 1035 u8 pid; 1036 1037 wcidx = le32_get_bits(txs_data[2], MT_TXS2_WCID); 1038 pid = le32_get_bits(txs_data[3], MT_TXS3_PID); 1039 1040 if (pid < MT_PACKET_ID_WED) 1041 return; 1042 1043 rcu_read_lock(); 1044 1045 wcid = mt76_wcid_ptr(dev, wcidx); 1046 if (!wcid) 1047 goto out; 1048 1049 msta = container_of(wcid, struct mt7915_sta, wcid); 1050 1051 if (pid == MT_PACKET_ID_WED) 1052 mt76_connac2_mac_fill_txs(&dev->mt76, wcid, txs_data); 1053 else 1054 mt76_connac2_mac_add_txs_skb(&dev->mt76, wcid, pid, txs_data); 1055 1056 if (!wcid->sta) 1057 goto out; 1058 1059 mt76_wcid_add_poll(&dev->mt76, &msta->wcid); 1060 1061 out: 1062 rcu_read_unlock(); 1063 } 1064 1065 bool mt7915_rx_check(struct mt76_dev *mdev, void *data, int len) 1066 { 1067 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1068 __le32 *rxd = (__le32 *)data; 1069 __le32 *end = (__le32 *)&rxd[len / 4]; 1070 enum rx_pkt_type type; 1071 1072 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1073 1074 switch (type) { 1075 case PKT_TYPE_TXRX_NOTIFY: 1076 mt7915_mac_tx_free(dev, data, len); 1077 return false; 1078 case PKT_TYPE_TXRX_NOTIFY_V0: 1079 mt7915_mac_tx_free_v0(dev, data, len); 1080 return false; 1081 case PKT_TYPE_TXS: 1082 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1083 mt7915_mac_add_txs(dev, rxd); 1084 return false; 1085 case PKT_TYPE_RX_FW_MONITOR: 1086 #if !defined(__FreeBSD__) || defined(CONFIG_MT7915_DEBUGFS) 1087 mt7915_debugfs_rx_fw_monitor(dev, data, len); 1088 #endif 1089 return false; 1090 default: 1091 return true; 1092 } 1093 } 1094 1095 void mt7915_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q, 1096 struct sk_buff *skb, u32 *info) 1097 { 1098 struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); 1099 __le32 *rxd = (__le32 *)skb->data; 1100 __le32 *end = (__le32 *)&skb->data[skb->len]; 1101 enum rx_pkt_type type; 1102 1103 type = le32_get_bits(rxd[0], MT_RXD0_PKT_TYPE); 1104 1105 switch (type) { 1106 case PKT_TYPE_TXRX_NOTIFY: 1107 mt7915_mac_tx_free(dev, skb->data, skb->len); 1108 napi_consume_skb(skb, 1); 1109 break; 1110 case PKT_TYPE_TXRX_NOTIFY_V0: 1111 mt7915_mac_tx_free_v0(dev, skb->data, skb->len); 1112 napi_consume_skb(skb, 1); 1113 break; 1114 case PKT_TYPE_RX_EVENT: 1115 mt7915_mcu_rx_event(dev, skb); 1116 break; 1117 case PKT_TYPE_TXRXV: 1118 mt7915_mac_fill_rx_vector(dev, skb); 1119 break; 1120 case PKT_TYPE_TXS: 1121 for (rxd += 2; rxd + 8 <= end; rxd += 8) 1122 mt7915_mac_add_txs(dev, rxd); 1123 dev_kfree_skb(skb); 1124 break; 1125 case PKT_TYPE_RX_FW_MONITOR: 1126 #if !defined(__FreeBSD__) || defined(CONFIG_MT7915_DEBUGFS) 1127 mt7915_debugfs_rx_fw_monitor(dev, skb->data, skb->len); 1128 #endif 1129 dev_kfree_skb(skb); 1130 break; 1131 case PKT_TYPE_NORMAL: 1132 if (!mt7915_mac_fill_rx(dev, skb, q, info)) { 1133 mt76_rx(&dev->mt76, q, skb); 1134 return; 1135 } 1136 fallthrough; 1137 default: 1138 dev_kfree_skb(skb); 1139 break; 1140 } 1141 } 1142 1143 void mt7915_mac_cca_stats_reset(struct mt7915_phy *phy) 1144 { 1145 struct mt7915_dev *dev = phy->dev; 1146 u32 reg = MT_WF_PHY_RX_CTRL1(phy->mt76->band_idx); 1147 1148 mt76_clear(dev, reg, MT_WF_PHY_RX_CTRL1_STSCNT_EN); 1149 mt76_set(dev, reg, BIT(11) | BIT(9)); 1150 } 1151 1152 void mt7915_mac_reset_counters(struct mt7915_phy *phy) 1153 { 1154 struct mt7915_dev *dev = phy->dev; 1155 int i; 1156 1157 for (i = 0; i < 4; i++) { 1158 mt76_rr(dev, MT_TX_AGG_CNT(phy->mt76->band_idx, i)); 1159 mt76_rr(dev, MT_TX_AGG_CNT2(phy->mt76->band_idx, i)); 1160 } 1161 1162 phy->mt76->survey_time = ktime_get_boottime(); 1163 memset(phy->mt76->aggr_stats, 0, sizeof(phy->mt76->aggr_stats)); 1164 1165 /* reset airtime counters */ 1166 mt76_set(dev, MT_WF_RMAC_MIB_AIRTIME0(phy->mt76->band_idx), 1167 MT_WF_RMAC_MIB_RXTIME_CLR); 1168 1169 mt7915_mcu_get_chan_mib_info(phy, true); 1170 } 1171 1172 void mt7915_mac_set_timing(struct mt7915_phy *phy) 1173 { 1174 s16 coverage_class = phy->coverage_class; 1175 struct mt7915_dev *dev = phy->dev; 1176 struct mt7915_phy *ext_phy = mt7915_ext_phy(dev); 1177 u32 val, reg_offset; 1178 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | 1179 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); 1180 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | 1181 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 28); 1182 u8 band = phy->mt76->band_idx; 1183 int eifs_ofdm = 84, sifs = 10, offset; 1184 bool a_band = !(phy->mt76->chandef.chan->band == NL80211_BAND_2GHZ); 1185 1186 if (!test_bit(MT76_STATE_RUNNING, &phy->mt76->state)) 1187 return; 1188 1189 if (ext_phy) 1190 coverage_class = max_t(s16, dev->phy.coverage_class, 1191 ext_phy->coverage_class); 1192 1193 mt76_set(dev, MT_ARB_SCR(band), 1194 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1195 udelay(1); 1196 1197 offset = 3 * coverage_class; 1198 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | 1199 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); 1200 1201 if (!is_mt7915(&dev->mt76)) { 1202 if (!a_band) { 1203 mt76_wr(dev, MT_TMAC_ICR1(band), 1204 FIELD_PREP(MT_IFS_EIFS_CCK, 314)); 1205 eifs_ofdm = 78; 1206 } else { 1207 eifs_ofdm = 84; 1208 } 1209 } else if (a_band) { 1210 sifs = 16; 1211 } 1212 1213 mt76_wr(dev, MT_TMAC_CDTR(band), cck + reg_offset); 1214 mt76_wr(dev, MT_TMAC_ODTR(band), ofdm + reg_offset); 1215 mt76_wr(dev, MT_TMAC_ICR0(band), 1216 FIELD_PREP(MT_IFS_EIFS_OFDM, eifs_ofdm) | 1217 FIELD_PREP(MT_IFS_RIFS, 2) | 1218 FIELD_PREP(MT_IFS_SIFS, sifs) | 1219 FIELD_PREP(MT_IFS_SLOT, phy->slottime)); 1220 1221 if (phy->slottime < 20 || a_band) 1222 val = MT7915_CFEND_RATE_DEFAULT; 1223 else 1224 val = MT7915_CFEND_RATE_11B; 1225 1226 mt76_rmw_field(dev, MT_AGG_ACR0(band), MT_AGG_ACR_CFEND_RATE, val); 1227 mt76_clear(dev, MT_ARB_SCR(band), 1228 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE); 1229 } 1230 1231 void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool band) 1232 { 1233 u32 reg; 1234 1235 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RXTD12(band) : 1236 MT_WF_PHY_RXTD12_MT7916(band); 1237 mt76_set(dev, reg, 1238 MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY | 1239 MT_WF_PHY_RXTD12_IRPI_SW_CLR); 1240 1241 reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RX_CTRL1(band) : 1242 MT_WF_PHY_RX_CTRL1_MT7916(band); 1243 mt76_set(dev, reg, FIELD_PREP(MT_WF_PHY_RX_CTRL1_IPI_EN, 0x5)); 1244 } 1245 1246 static u8 1247 mt7915_phy_get_nf(struct mt7915_phy *phy, int idx) 1248 { 1249 static const u8 nf_power[] = { 92, 89, 86, 83, 80, 75, 70, 65, 60, 55, 52 }; 1250 struct mt7915_dev *dev = phy->dev; 1251 u32 val, sum = 0, n = 0; 1252 int nss, i; 1253 1254 for (nss = 0; nss < hweight8(phy->mt76->chainmask); nss++) { 1255 u32 reg = is_mt7915(&dev->mt76) ? 1256 MT_WF_IRPI_NSS(0, nss + (idx << dev->dbdc_support)) : 1257 MT_WF_IRPI_NSS_MT7916(idx, nss); 1258 1259 for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) { 1260 val = mt76_rr(dev, reg); 1261 sum += val * nf_power[i]; 1262 n += val; 1263 } 1264 } 1265 1266 if (!n) 1267 return 0; 1268 1269 return sum / n; 1270 } 1271 1272 void mt7915_update_channel(struct mt76_phy *mphy) 1273 { 1274 struct mt7915_phy *phy = mphy->priv; 1275 struct mt76_channel_state *state = mphy->chan_state; 1276 int nf; 1277 1278 mt7915_mcu_get_chan_mib_info(phy, false); 1279 1280 nf = mt7915_phy_get_nf(phy, phy->mt76->band_idx); 1281 if (!phy->noise) 1282 phy->noise = nf << 4; 1283 else if (nf) 1284 phy->noise += nf - (phy->noise >> 4); 1285 1286 state->noise = -(phy->noise >> 4); 1287 } 1288 1289 static bool 1290 mt7915_wait_reset_state(struct mt7915_dev *dev, u32 state) 1291 { 1292 bool ret; 1293 1294 ret = wait_event_timeout(dev->reset_wait, 1295 (READ_ONCE(dev->recovery.state) & state), 1296 MT7915_RESET_TIMEOUT); 1297 1298 WARN(!ret, "Timeout waiting for MCU reset state %x\n", state); 1299 return ret; 1300 } 1301 1302 static void 1303 mt7915_update_vif_beacon(void *priv, u8 *mac, struct ieee80211_vif *vif) 1304 { 1305 struct ieee80211_hw *hw = priv; 1306 1307 switch (vif->type) { 1308 case NL80211_IFTYPE_MESH_POINT: 1309 case NL80211_IFTYPE_ADHOC: 1310 case NL80211_IFTYPE_AP: 1311 mt7915_mcu_add_beacon(hw, vif, vif->bss_conf.enable_beacon, 1312 BSS_CHANGED_BEACON_ENABLED); 1313 break; 1314 default: 1315 break; 1316 } 1317 } 1318 1319 static void 1320 mt7915_update_beacons(struct mt7915_dev *dev) 1321 { 1322 struct mt76_phy *mphy_ext = dev->mt76.phys[MT_BAND1]; 1323 1324 ieee80211_iterate_active_interfaces(dev->mt76.hw, 1325 IEEE80211_IFACE_ITER_RESUME_ALL, 1326 mt7915_update_vif_beacon, dev->mt76.hw); 1327 1328 if (!mphy_ext) 1329 return; 1330 1331 ieee80211_iterate_active_interfaces(mphy_ext->hw, 1332 IEEE80211_IFACE_ITER_RESUME_ALL, 1333 mt7915_update_vif_beacon, mphy_ext->hw); 1334 } 1335 1336 static int 1337 mt7915_mac_restart(struct mt7915_dev *dev) 1338 { 1339 struct mt7915_phy *phy2; 1340 struct mt76_phy *ext_phy; 1341 struct mt76_dev *mdev = &dev->mt76; 1342 int i, ret; 1343 1344 ext_phy = dev->mt76.phys[MT_BAND1]; 1345 phy2 = ext_phy ? ext_phy->priv : NULL; 1346 1347 if (dev->hif2) { 1348 mt76_wr(dev, MT_INT1_MASK_CSR, 0x0); 1349 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1350 } 1351 1352 if (dev_is_pci(mdev->dev)) { 1353 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0x0); 1354 if (dev->hif2) { 1355 if (is_mt7915(mdev)) 1356 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0x0); 1357 else 1358 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE_MT7916, 0x0); 1359 } 1360 } 1361 1362 set_bit(MT76_RESET, &dev->mphy.state); 1363 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1364 wake_up(&dev->mt76.mcu.wait); 1365 if (ext_phy) 1366 set_bit(MT76_RESET, &ext_phy->state); 1367 1368 /* lock/unlock all queues to ensure that no tx is pending */ 1369 mt76_txq_schedule_all(&dev->mphy); 1370 if (ext_phy) 1371 mt76_txq_schedule_all(ext_phy); 1372 1373 /* disable all tx/rx napi */ 1374 mt76_worker_disable(&dev->mt76.tx_worker); 1375 mt76_for_each_q_rx(mdev, i) { 1376 if (mdev->q_rx[i].ndesc) 1377 napi_disable(&dev->mt76.napi[i]); 1378 } 1379 napi_disable(&dev->mt76.tx_napi); 1380 1381 /* token reinit */ 1382 mt76_connac2_tx_token_put(&dev->mt76); 1383 idr_init(&dev->mt76.token); 1384 1385 mt7915_dma_reset(dev, true); 1386 1387 mt76_for_each_q_rx(mdev, i) { 1388 if (mdev->q_rx[i].ndesc) { 1389 napi_enable(&dev->mt76.napi[i]); 1390 } 1391 } 1392 1393 local_bh_disable(); 1394 mt76_for_each_q_rx(mdev, i) { 1395 if (mdev->q_rx[i].ndesc) { 1396 napi_schedule(&dev->mt76.napi[i]); 1397 } 1398 } 1399 local_bh_enable(); 1400 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1401 clear_bit(MT76_STATE_MCU_RUNNING, &dev->mphy.state); 1402 1403 mt76_wr(dev, MT_INT_MASK_CSR, dev->mt76.mmio.irqmask); 1404 mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); 1405 1406 if (dev->hif2) { 1407 mt76_wr(dev, MT_INT1_MASK_CSR, dev->mt76.mmio.irqmask); 1408 mt76_wr(dev, MT_INT1_SOURCE_CSR, ~0); 1409 } 1410 if (dev_is_pci(mdev->dev)) { 1411 mt76_wr(dev, MT_PCIE_MAC_INT_ENABLE, 0xff); 1412 if (dev->hif2) { 1413 mt76_wr(dev, MT_PCIE_RECOG_ID, 1414 dev->hif2->index | MT_PCIE_RECOG_ID_SEM); 1415 if (is_mt7915(mdev)) 1416 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE, 0xff); 1417 else 1418 mt76_wr(dev, MT_PCIE1_MAC_INT_ENABLE_MT7916, 0xff); 1419 } 1420 } 1421 1422 /* load firmware */ 1423 ret = mt7915_mcu_init_firmware(dev); 1424 if (ret) 1425 goto out; 1426 1427 /* set the necessary init items */ 1428 ret = mt7915_mcu_set_eeprom(dev); 1429 if (ret) 1430 goto out; 1431 1432 mt7915_mac_init(dev); 1433 mt7915_init_txpower(&dev->phy); 1434 mt7915_init_txpower(phy2); 1435 ret = mt7915_txbf_init(dev); 1436 1437 if (test_bit(MT76_STATE_RUNNING, &dev->mphy.state)) { 1438 ret = mt7915_run(dev->mphy.hw); 1439 if (ret) 1440 goto out; 1441 } 1442 1443 if (ext_phy && test_bit(MT76_STATE_RUNNING, &ext_phy->state)) { 1444 ret = mt7915_run(ext_phy->hw); 1445 if (ret) 1446 goto out; 1447 } 1448 1449 out: 1450 /* reset done */ 1451 clear_bit(MT76_RESET, &dev->mphy.state); 1452 if (phy2) 1453 clear_bit(MT76_RESET, &phy2->mt76->state); 1454 1455 napi_enable(&dev->mt76.tx_napi); 1456 1457 local_bh_disable(); 1458 napi_schedule(&dev->mt76.tx_napi); 1459 local_bh_enable(); 1460 1461 mt76_worker_enable(&dev->mt76.tx_worker); 1462 1463 return ret; 1464 } 1465 1466 static void 1467 mt7915_mac_full_reset(struct mt7915_dev *dev) 1468 { 1469 struct mt76_phy *ext_phy; 1470 struct mt7915_phy *phy2; 1471 int i; 1472 1473 ext_phy = dev->mt76.phys[MT_BAND1]; 1474 phy2 = ext_phy ? ext_phy->priv : NULL; 1475 1476 dev->recovery.hw_full_reset = true; 1477 1478 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1479 wake_up(&dev->mt76.mcu.wait); 1480 ieee80211_stop_queues(mt76_hw(dev)); 1481 if (ext_phy) 1482 ieee80211_stop_queues(ext_phy->hw); 1483 1484 cancel_delayed_work_sync(&dev->mphy.mac_work); 1485 if (ext_phy) 1486 cancel_delayed_work_sync(&ext_phy->mac_work); 1487 1488 mutex_lock(&dev->mt76.mutex); 1489 for (i = 0; i < 10; i++) { 1490 if (!mt7915_mac_restart(dev)) 1491 break; 1492 } 1493 1494 if (i == 10) 1495 dev_err(dev->mt76.dev, "chip full reset failed\n"); 1496 1497 dev->phy.omac_mask = 0; 1498 if (phy2) 1499 phy2->omac_mask = 0; 1500 1501 mt76_reset_device(&dev->mt76); 1502 1503 INIT_LIST_HEAD(&dev->sta_rc_list); 1504 INIT_LIST_HEAD(&dev->twt_list); 1505 1506 i = mt76_wcid_alloc(dev->mt76.wcid_mask, MT7915_WTBL_STA); 1507 dev->mt76.global_wcid.idx = i; 1508 dev->recovery.hw_full_reset = false; 1509 1510 mutex_unlock(&dev->mt76.mutex); 1511 1512 ieee80211_restart_hw(mt76_hw(dev)); 1513 if (ext_phy) 1514 ieee80211_restart_hw(ext_phy->hw); 1515 } 1516 1517 /* system error recovery */ 1518 void mt7915_mac_reset_work(struct work_struct *work) 1519 { 1520 struct mt7915_phy *phy2; 1521 struct mt76_phy *ext_phy; 1522 struct mt7915_dev *dev; 1523 int i; 1524 1525 dev = container_of(work, struct mt7915_dev, reset_work); 1526 ext_phy = dev->mt76.phys[MT_BAND1]; 1527 phy2 = ext_phy ? ext_phy->priv : NULL; 1528 1529 /* chip full reset */ 1530 if (dev->recovery.restart) { 1531 /* disable WA/WM WDT */ 1532 mt76_clear(dev, MT_WFDMA0_MCU_HOST_INT_ENA, 1533 MT_MCU_CMD_WDT_MASK); 1534 1535 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WA_WDT) 1536 dev->recovery.wa_reset_count++; 1537 else 1538 dev->recovery.wm_reset_count++; 1539 1540 mt7915_mac_full_reset(dev); 1541 1542 /* enable mcu irq */ 1543 mt7915_irq_enable(dev, MT_INT_MCU_CMD); 1544 mt7915_irq_disable(dev, 0); 1545 1546 /* enable WA/WM WDT */ 1547 mt76_set(dev, MT_WFDMA0_MCU_HOST_INT_ENA, MT_MCU_CMD_WDT_MASK); 1548 1549 dev->recovery.state = MT_MCU_CMD_NORMAL_STATE; 1550 dev->recovery.restart = false; 1551 return; 1552 } 1553 1554 /* chip partial reset */ 1555 if (!(READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA)) 1556 return; 1557 1558 ieee80211_stop_queues(mt76_hw(dev)); 1559 if (ext_phy) 1560 ieee80211_stop_queues(ext_phy->hw); 1561 1562 set_bit(MT76_RESET, &dev->mphy.state); 1563 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1564 wake_up(&dev->mt76.mcu.wait); 1565 cancel_delayed_work_sync(&dev->mphy.mac_work); 1566 if (phy2) { 1567 set_bit(MT76_RESET, &phy2->mt76->state); 1568 cancel_delayed_work_sync(&phy2->mt76->mac_work); 1569 } 1570 1571 mutex_lock(&dev->mt76.mutex); 1572 1573 mt76_worker_disable(&dev->mt76.tx_worker); 1574 mt76_for_each_q_rx(&dev->mt76, i) 1575 napi_disable(&dev->mt76.napi[i]); 1576 napi_disable(&dev->mt76.tx_napi); 1577 1578 1579 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) 1580 mtk_wed_device_stop(&dev->mt76.mmio.wed); 1581 1582 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_STOPPED); 1583 1584 if (mt7915_wait_reset_state(dev, MT_MCU_CMD_RESET_DONE)) { 1585 mt7915_dma_reset(dev, false); 1586 1587 mt76_connac2_tx_token_put(&dev->mt76); 1588 idr_init(&dev->mt76.token); 1589 1590 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_DMA_INIT); 1591 mt7915_wait_reset_state(dev, MT_MCU_CMD_RECOVERY_DONE); 1592 } 1593 1594 mt76_wr(dev, MT_MCU_INT_EVENT, MT_MCU_INT_EVENT_RESET_DONE); 1595 mt7915_wait_reset_state(dev, MT_MCU_CMD_NORMAL_STATE); 1596 1597 /* enable DMA Tx/Rx and interrupt */ 1598 mt7915_dma_start(dev, false, false); 1599 1600 clear_bit(MT76_MCU_RESET, &dev->mphy.state); 1601 clear_bit(MT76_RESET, &dev->mphy.state); 1602 if (phy2) 1603 clear_bit(MT76_RESET, &phy2->mt76->state); 1604 1605 mt76_for_each_q_rx(&dev->mt76, i) { 1606 napi_enable(&dev->mt76.napi[i]); 1607 } 1608 1609 local_bh_disable(); 1610 mt76_for_each_q_rx(&dev->mt76, i) { 1611 napi_schedule(&dev->mt76.napi[i]); 1612 } 1613 local_bh_enable(); 1614 1615 tasklet_schedule(&dev->mt76.irq_tasklet); 1616 1617 mt76_worker_enable(&dev->mt76.tx_worker); 1618 1619 napi_enable(&dev->mt76.tx_napi); 1620 local_bh_disable(); 1621 napi_schedule(&dev->mt76.tx_napi); 1622 local_bh_enable(); 1623 1624 ieee80211_wake_queues(mt76_hw(dev)); 1625 if (ext_phy) 1626 ieee80211_wake_queues(ext_phy->hw); 1627 1628 mutex_unlock(&dev->mt76.mutex); 1629 1630 mt7915_update_beacons(dev); 1631 1632 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work, 1633 MT7915_WATCHDOG_TIME); 1634 if (phy2) 1635 ieee80211_queue_delayed_work(ext_phy->hw, 1636 &phy2->mt76->mac_work, 1637 MT7915_WATCHDOG_TIME); 1638 } 1639 1640 /* firmware coredump */ 1641 void mt7915_mac_dump_work(struct work_struct *work) 1642 { 1643 const struct mt7915_mem_region *mem_region; 1644 struct mt7915_crash_data *crash_data; 1645 struct mt7915_dev *dev; 1646 struct mt7915_mem_hdr *hdr; 1647 size_t buf_len; 1648 int i; 1649 u32 num; 1650 u8 *buf; 1651 1652 dev = container_of(work, struct mt7915_dev, dump_work); 1653 1654 mutex_lock(&dev->dump_mutex); 1655 1656 crash_data = mt7915_coredump_new(dev); 1657 if (!crash_data) { 1658 mutex_unlock(&dev->dump_mutex); 1659 goto skip_coredump; 1660 } 1661 1662 mem_region = mt7915_coredump_get_mem_layout(dev, &num); 1663 if (!mem_region || !crash_data->memdump_buf_len) { 1664 mutex_unlock(&dev->dump_mutex); 1665 goto skip_memdump; 1666 } 1667 1668 buf = crash_data->memdump_buf; 1669 buf_len = crash_data->memdump_buf_len; 1670 1671 /* dumping memory content... */ 1672 memset(buf, 0, buf_len); 1673 for (i = 0; i < num; i++) { 1674 if (mem_region->len > buf_len) { 1675 dev_warn(dev->mt76.dev, "%s len %lu is too large\n", 1676 mem_region->name, 1677 (unsigned long)mem_region->len); 1678 break; 1679 } 1680 1681 /* reserve space for the header */ 1682 hdr = (void *)buf; 1683 buf += sizeof(*hdr); 1684 buf_len -= sizeof(*hdr); 1685 1686 mt7915_memcpy_fromio(dev, buf, mem_region->start, 1687 mem_region->len); 1688 1689 hdr->start = mem_region->start; 1690 hdr->len = mem_region->len; 1691 1692 if (!mem_region->len) 1693 /* note: the header remains, just with zero length */ 1694 break; 1695 1696 buf += mem_region->len; 1697 buf_len -= mem_region->len; 1698 1699 mem_region++; 1700 } 1701 1702 mutex_unlock(&dev->dump_mutex); 1703 1704 skip_memdump: 1705 mt7915_coredump_submit(dev); 1706 skip_coredump: 1707 queue_work(dev->mt76.wq, &dev->reset_work); 1708 } 1709 1710 void mt7915_reset(struct mt7915_dev *dev) 1711 { 1712 if (!dev->recovery.hw_init_done) 1713 return; 1714 1715 if (dev->recovery.hw_full_reset) 1716 return; 1717 1718 /* wm/wa exception: do full recovery */ 1719 if (READ_ONCE(dev->recovery.state) & MT_MCU_CMD_WDT_MASK) { 1720 dev->recovery.restart = true; 1721 dev_info(dev->mt76.dev, 1722 "%s indicated firmware crash, attempting recovery\n", 1723 wiphy_name(dev->mt76.hw->wiphy)); 1724 1725 mt7915_irq_disable(dev, MT_INT_MCU_CMD); 1726 queue_work(dev->mt76.wq, &dev->dump_work); 1727 return; 1728 } 1729 1730 if ((READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA)) { 1731 set_bit(MT76_MCU_RESET, &dev->mphy.state); 1732 wake_up(&dev->mt76.mcu.wait); 1733 } 1734 1735 queue_work(dev->mt76.wq, &dev->reset_work); 1736 wake_up(&dev->reset_wait); 1737 } 1738 1739 void mt7915_mac_update_stats(struct mt7915_phy *phy) 1740 { 1741 struct mt76_mib_stats *mib = &phy->mib; 1742 struct mt7915_dev *dev = phy->dev; 1743 int i, aggr0 = 0, aggr1, cnt; 1744 u8 band = phy->mt76->band_idx; 1745 u32 val; 1746 1747 cnt = mt76_rr(dev, MT_MIB_SDR3(band)); 1748 mib->fcs_err_cnt += is_mt7915(&dev->mt76) ? 1749 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK, cnt) : 1750 FIELD_GET(MT_MIB_SDR3_FCS_ERR_MASK_MT7916, cnt); 1751 1752 cnt = mt76_rr(dev, MT_MIB_SDR4(band)); 1753 mib->rx_fifo_full_cnt += FIELD_GET(MT_MIB_SDR4_RX_FIFO_FULL_MASK, cnt); 1754 1755 cnt = mt76_rr(dev, MT_MIB_SDR5(band)); 1756 mib->rx_mpdu_cnt += cnt; 1757 1758 cnt = mt76_rr(dev, MT_MIB_SDR6(band)); 1759 mib->channel_idle_cnt += FIELD_GET(MT_MIB_SDR6_CHANNEL_IDL_CNT_MASK, cnt); 1760 1761 cnt = mt76_rr(dev, MT_MIB_SDR7(band)); 1762 mib->rx_vector_mismatch_cnt += 1763 FIELD_GET(MT_MIB_SDR7_RX_VECTOR_MISMATCH_CNT_MASK, cnt); 1764 1765 cnt = mt76_rr(dev, MT_MIB_SDR8(band)); 1766 mib->rx_delimiter_fail_cnt += 1767 FIELD_GET(MT_MIB_SDR8_RX_DELIMITER_FAIL_CNT_MASK, cnt); 1768 1769 cnt = mt76_rr(dev, MT_MIB_SDR10(band)); 1770 mib->rx_mrdy_cnt += is_mt7915(&dev->mt76) ? 1771 FIELD_GET(MT_MIB_SDR10_MRDY_COUNT_MASK, cnt) : 1772 FIELD_GET(MT_MIB_SDR10_MRDY_COUNT_MASK_MT7916, cnt); 1773 1774 cnt = mt76_rr(dev, MT_MIB_SDR11(band)); 1775 mib->rx_len_mismatch_cnt += 1776 FIELD_GET(MT_MIB_SDR11_RX_LEN_MISMATCH_CNT_MASK, cnt); 1777 1778 cnt = mt76_rr(dev, MT_MIB_SDR12(band)); 1779 mib->tx_ampdu_cnt += cnt; 1780 1781 cnt = mt76_rr(dev, MT_MIB_SDR13(band)); 1782 mib->tx_stop_q_empty_cnt += 1783 FIELD_GET(MT_MIB_SDR13_TX_STOP_Q_EMPTY_CNT_MASK, cnt); 1784 1785 cnt = mt76_rr(dev, MT_MIB_SDR14(band)); 1786 mib->tx_mpdu_attempts_cnt += is_mt7915(&dev->mt76) ? 1787 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK, cnt) : 1788 FIELD_GET(MT_MIB_SDR14_TX_MPDU_ATTEMPTS_CNT_MASK_MT7916, cnt); 1789 1790 cnt = mt76_rr(dev, MT_MIB_SDR15(band)); 1791 mib->tx_mpdu_success_cnt += is_mt7915(&dev->mt76) ? 1792 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK, cnt) : 1793 FIELD_GET(MT_MIB_SDR15_TX_MPDU_SUCCESS_CNT_MASK_MT7916, cnt); 1794 1795 cnt = mt76_rr(dev, MT_MIB_SDR16(band)); 1796 mib->primary_cca_busy_time += 1797 FIELD_GET(MT_MIB_SDR16_PRIMARY_CCA_BUSY_TIME_MASK, cnt); 1798 1799 cnt = mt76_rr(dev, MT_MIB_SDR17(band)); 1800 mib->secondary_cca_busy_time += 1801 FIELD_GET(MT_MIB_SDR17_SECONDARY_CCA_BUSY_TIME_MASK, cnt); 1802 1803 cnt = mt76_rr(dev, MT_MIB_SDR18(band)); 1804 mib->primary_energy_detect_time += 1805 FIELD_GET(MT_MIB_SDR18_PRIMARY_ENERGY_DETECT_TIME_MASK, cnt); 1806 1807 cnt = mt76_rr(dev, MT_MIB_SDR19(band)); 1808 mib->cck_mdrdy_time += FIELD_GET(MT_MIB_SDR19_CCK_MDRDY_TIME_MASK, cnt); 1809 1810 cnt = mt76_rr(dev, MT_MIB_SDR20(band)); 1811 mib->ofdm_mdrdy_time += 1812 FIELD_GET(MT_MIB_SDR20_OFDM_VHT_MDRDY_TIME_MASK, cnt); 1813 1814 cnt = mt76_rr(dev, MT_MIB_SDR21(band)); 1815 mib->green_mdrdy_time += 1816 FIELD_GET(MT_MIB_SDR21_GREEN_MDRDY_TIME_MASK, cnt); 1817 1818 cnt = mt76_rr(dev, MT_MIB_SDR22(band)); 1819 mib->rx_ampdu_cnt += cnt; 1820 1821 cnt = mt76_rr(dev, MT_MIB_SDR23(band)); 1822 mib->rx_ampdu_bytes_cnt += cnt; 1823 1824 cnt = mt76_rr(dev, MT_MIB_SDR24(band)); 1825 mib->rx_ampdu_valid_subframe_cnt += is_mt7915(&dev->mt76) ? 1826 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK, cnt) : 1827 FIELD_GET(MT_MIB_SDR24_RX_AMPDU_SF_CNT_MASK_MT7916, cnt); 1828 1829 cnt = mt76_rr(dev, MT_MIB_SDR25(band)); 1830 mib->rx_ampdu_valid_subframe_bytes_cnt += cnt; 1831 1832 cnt = mt76_rr(dev, MT_MIB_SDR27(band)); 1833 mib->tx_rwp_fail_cnt += 1834 FIELD_GET(MT_MIB_SDR27_TX_RWP_FAIL_CNT_MASK, cnt); 1835 1836 cnt = mt76_rr(dev, MT_MIB_SDR28(band)); 1837 mib->tx_rwp_need_cnt += 1838 FIELD_GET(MT_MIB_SDR28_TX_RWP_NEED_CNT_MASK, cnt); 1839 1840 cnt = mt76_rr(dev, MT_MIB_SDR29(band)); 1841 mib->rx_pfdrop_cnt += is_mt7915(&dev->mt76) ? 1842 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK, cnt) : 1843 FIELD_GET(MT_MIB_SDR29_RX_PFDROP_CNT_MASK_MT7916, cnt); 1844 1845 cnt = mt76_rr(dev, MT_MIB_SDRVEC(band)); 1846 mib->rx_vec_queue_overflow_drop_cnt += is_mt7915(&dev->mt76) ? 1847 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK, cnt) : 1848 FIELD_GET(MT_MIB_SDR30_RX_VEC_QUEUE_OVERFLOW_DROP_CNT_MASK_MT7916, cnt); 1849 1850 cnt = mt76_rr(dev, MT_MIB_SDR31(band)); 1851 mib->rx_ba_cnt += cnt; 1852 1853 cnt = mt76_rr(dev, MT_MIB_SDRMUBF(band)); 1854 mib->tx_bf_cnt += FIELD_GET(MT_MIB_MU_BF_TX_CNT, cnt); 1855 1856 cnt = mt76_rr(dev, MT_MIB_DR8(band)); 1857 mib->tx_mu_mpdu_cnt += cnt; 1858 1859 cnt = mt76_rr(dev, MT_MIB_DR9(band)); 1860 mib->tx_mu_acked_mpdu_cnt += cnt; 1861 1862 cnt = mt76_rr(dev, MT_MIB_DR11(band)); 1863 mib->tx_su_acked_mpdu_cnt += cnt; 1864 1865 cnt = mt76_rr(dev, MT_ETBF_PAR_RPT0(band)); 1866 mib->tx_bf_rx_fb_bw = FIELD_GET(MT_ETBF_PAR_RPT0_FB_BW, cnt); 1867 mib->tx_bf_rx_fb_nc_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NC, cnt); 1868 mib->tx_bf_rx_fb_nr_cnt += FIELD_GET(MT_ETBF_PAR_RPT0_FB_NR, cnt); 1869 1870 for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu); i++) { 1871 cnt = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i)); 1872 mib->tx_amsdu[i] += cnt; 1873 mib->tx_amsdu_cnt += cnt; 1874 } 1875 1876 if (is_mt7915(&dev->mt76)) { 1877 for (i = 0, aggr1 = aggr0 + 8; i < 4; i++) { 1878 val = mt76_rr(dev, MT_MIB_MB_SDR1(band, (i << 4))); 1879 mib->ba_miss_cnt += 1880 FIELD_GET(MT_MIB_BA_MISS_COUNT_MASK, val); 1881 mib->ack_fail_cnt += 1882 FIELD_GET(MT_MIB_ACK_FAIL_COUNT_MASK, val); 1883 1884 val = mt76_rr(dev, MT_MIB_MB_SDR0(band, (i << 4))); 1885 mib->rts_cnt += FIELD_GET(MT_MIB_RTS_COUNT_MASK, val); 1886 mib->rts_retries_cnt += 1887 FIELD_GET(MT_MIB_RTS_RETRIES_COUNT_MASK, val); 1888 1889 val = mt76_rr(dev, MT_TX_AGG_CNT(band, i)); 1890 phy->mt76->aggr_stats[aggr0++] += val & 0xffff; 1891 phy->mt76->aggr_stats[aggr0++] += val >> 16; 1892 1893 val = mt76_rr(dev, MT_TX_AGG_CNT2(band, i)); 1894 phy->mt76->aggr_stats[aggr1++] += val & 0xffff; 1895 phy->mt76->aggr_stats[aggr1++] += val >> 16; 1896 } 1897 1898 cnt = mt76_rr(dev, MT_MIB_SDR32(band)); 1899 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1900 1901 cnt = mt76_rr(dev, MT_MIB_SDR33(band)); 1902 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR33_TX_PKT_IBF_CNT, cnt); 1903 1904 cnt = mt76_rr(dev, MT_ETBF_TX_APP_CNT(band)); 1905 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_IBF_CNT, cnt); 1906 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_ETBF_TX_EBF_CNT, cnt); 1907 1908 cnt = mt76_rr(dev, MT_ETBF_TX_NDP_BFRP(band)); 1909 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_ETBF_TX_FB_CPL, cnt); 1910 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_ETBF_TX_FB_TRI, cnt); 1911 1912 cnt = mt76_rr(dev, MT_ETBF_RX_FB_CNT(band)); 1913 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_ETBF_RX_FB_ALL, cnt); 1914 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_ETBF_RX_FB_HE, cnt); 1915 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_ETBF_RX_FB_VHT, cnt); 1916 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_ETBF_RX_FB_HT, cnt); 1917 } else { 1918 for (i = 0; i < 2; i++) { 1919 /* rts count */ 1920 val = mt76_rr(dev, MT_MIB_MB_SDR0(band, (i << 2))); 1921 mib->rts_cnt += FIELD_GET(GENMASK(15, 0), val); 1922 mib->rts_cnt += FIELD_GET(GENMASK(31, 16), val); 1923 1924 /* rts retry count */ 1925 val = mt76_rr(dev, MT_MIB_MB_SDR1(band, (i << 2))); 1926 mib->rts_retries_cnt += FIELD_GET(GENMASK(15, 0), val); 1927 mib->rts_retries_cnt += FIELD_GET(GENMASK(31, 16), val); 1928 1929 /* ba miss count */ 1930 val = mt76_rr(dev, MT_MIB_MB_SDR2(band, (i << 2))); 1931 mib->ba_miss_cnt += FIELD_GET(GENMASK(15, 0), val); 1932 mib->ba_miss_cnt += FIELD_GET(GENMASK(31, 16), val); 1933 1934 /* ack fail count */ 1935 val = mt76_rr(dev, MT_MIB_MB_BFTF(band, (i << 2))); 1936 mib->ack_fail_cnt += FIELD_GET(GENMASK(15, 0), val); 1937 mib->ack_fail_cnt += FIELD_GET(GENMASK(31, 16), val); 1938 } 1939 1940 for (i = 0; i < 8; i++) { 1941 val = mt76_rr(dev, MT_TX_AGG_CNT(band, i)); 1942 phy->mt76->aggr_stats[aggr0++] += FIELD_GET(GENMASK(15, 0), val); 1943 phy->mt76->aggr_stats[aggr0++] += FIELD_GET(GENMASK(31, 16), val); 1944 } 1945 1946 cnt = mt76_rr(dev, MT_MIB_SDR32(band)); 1947 mib->tx_pkt_ibf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt); 1948 mib->tx_bf_ibf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_IBF_CNT, cnt); 1949 mib->tx_pkt_ebf_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1950 mib->tx_bf_ebf_ppdu_cnt += FIELD_GET(MT_MIB_SDR32_TX_PKT_EBF_CNT, cnt); 1951 1952 cnt = mt76_rr(dev, MT_MIB_BFCR7(band)); 1953 mib->tx_bf_fb_cpl_cnt += FIELD_GET(MT_MIB_BFCR7_BFEE_TX_FB_CPL, cnt); 1954 1955 cnt = mt76_rr(dev, MT_MIB_BFCR2(band)); 1956 mib->tx_bf_fb_trig_cnt += FIELD_GET(MT_MIB_BFCR2_BFEE_TX_FB_TRIG, cnt); 1957 1958 cnt = mt76_rr(dev, MT_MIB_BFCR0(band)); 1959 mib->tx_bf_rx_fb_vht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt); 1960 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_VHT, cnt); 1961 mib->tx_bf_rx_fb_ht_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt); 1962 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR0_RX_FB_HT, cnt); 1963 1964 cnt = mt76_rr(dev, MT_MIB_BFCR1(band)); 1965 mib->tx_bf_rx_fb_he_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt); 1966 mib->tx_bf_rx_fb_all_cnt += FIELD_GET(MT_MIB_BFCR1_RX_FB_HE, cnt); 1967 } 1968 } 1969 1970 static void mt7915_mac_severe_check(struct mt7915_phy *phy) 1971 { 1972 struct mt7915_dev *dev = phy->dev; 1973 u32 trb; 1974 1975 if (!phy->omac_mask) 1976 return; 1977 1978 /* In rare cases, TRB pointers might be out of sync leads to RMAC 1979 * stopping Rx, so check status periodically to see if TRB hardware 1980 * requires minimal recovery. 1981 */ 1982 trb = mt76_rr(dev, MT_TRB_RXPSR0(phy->mt76->band_idx)); 1983 1984 if ((FIELD_GET(MT_TRB_RXPSR0_RX_RMAC_PTR, trb) != 1985 FIELD_GET(MT_TRB_RXPSR0_RX_WTBL_PTR, trb)) && 1986 (FIELD_GET(MT_TRB_RXPSR0_RX_RMAC_PTR, phy->trb_ts) != 1987 FIELD_GET(MT_TRB_RXPSR0_RX_WTBL_PTR, phy->trb_ts)) && 1988 trb == phy->trb_ts) 1989 mt7915_mcu_set_ser(dev, SER_RECOVER, SER_SET_RECOVER_L3_RX_ABORT, 1990 phy->mt76->band_idx); 1991 1992 phy->trb_ts = trb; 1993 } 1994 1995 void mt7915_mac_sta_rc_work(struct work_struct *work) 1996 { 1997 struct mt7915_dev *dev = container_of(work, struct mt7915_dev, rc_work); 1998 struct ieee80211_sta *sta; 1999 struct ieee80211_vif *vif; 2000 struct mt7915_sta *msta; 2001 u32 changed; 2002 #if defined(__linux__) 2003 LIST_HEAD(list); 2004 #elif defined(__FreeBSD__) 2005 LINUX_LIST_HEAD(list); 2006 #endif 2007 2008 spin_lock_bh(&dev->mt76.sta_poll_lock); 2009 list_splice_init(&dev->sta_rc_list, &list); 2010 2011 while (!list_empty(&list)) { 2012 msta = list_first_entry(&list, struct mt7915_sta, rc_list); 2013 list_del_init(&msta->rc_list); 2014 changed = msta->changed; 2015 msta->changed = 0; 2016 spin_unlock_bh(&dev->mt76.sta_poll_lock); 2017 2018 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv); 2019 vif = container_of((void *)msta->vif, struct ieee80211_vif, drv_priv); 2020 2021 if (changed & (IEEE80211_RC_SUPP_RATES_CHANGED | 2022 IEEE80211_RC_NSS_CHANGED | 2023 IEEE80211_RC_BW_CHANGED)) 2024 mt7915_mcu_add_rate_ctrl(dev, vif, sta, true); 2025 2026 if (changed & IEEE80211_RC_SMPS_CHANGED) 2027 mt7915_mcu_add_smps(dev, vif, sta); 2028 2029 spin_lock_bh(&dev->mt76.sta_poll_lock); 2030 } 2031 2032 spin_unlock_bh(&dev->mt76.sta_poll_lock); 2033 } 2034 2035 void mt7915_mac_work(struct work_struct *work) 2036 { 2037 struct mt7915_phy *phy; 2038 struct mt76_phy *mphy; 2039 2040 mphy = (struct mt76_phy *)container_of(work, struct mt76_phy, 2041 mac_work.work); 2042 phy = mphy->priv; 2043 2044 mutex_lock(&mphy->dev->mutex); 2045 2046 mt76_update_survey(mphy); 2047 if (++mphy->mac_work_count == 5) { 2048 mphy->mac_work_count = 0; 2049 2050 mt7915_mac_update_stats(phy); 2051 mt7915_mac_severe_check(phy); 2052 2053 if (phy->dev->muru_debug) 2054 mt7915_mcu_muru_debug_get(phy); 2055 } 2056 2057 mutex_unlock(&mphy->dev->mutex); 2058 2059 mt76_tx_status_check(mphy->dev, false); 2060 2061 ieee80211_queue_delayed_work(mphy->hw, &mphy->mac_work, 2062 MT7915_WATCHDOG_TIME); 2063 } 2064 2065 static void mt7915_dfs_stop_radar_detector(struct mt7915_phy *phy) 2066 { 2067 struct mt7915_dev *dev = phy->dev; 2068 int rdd_idx = mt7915_get_rdd_idx(phy, false); 2069 2070 if (rdd_idx < 0) 2071 return; 2072 2073 mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_STOP, rdd_idx, 0, 0); 2074 } 2075 2076 static int mt7915_dfs_start_rdd(struct mt7915_dev *dev, int rdd_idx) 2077 { 2078 int err, region; 2079 2080 switch (dev->mt76.region) { 2081 case NL80211_DFS_ETSI: 2082 region = 0; 2083 break; 2084 case NL80211_DFS_JP: 2085 region = 2; 2086 break; 2087 case NL80211_DFS_FCC: 2088 default: 2089 region = 1; 2090 break; 2091 } 2092 2093 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_START, rdd_idx, 0, region); 2094 if (err < 0) 2095 return err; 2096 2097 if (is_mt7915(&dev->mt76)) { 2098 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_SET_WF_ANT, rdd_idx, 2099 0, dev->dbdc_support ? 2 : 0); 2100 if (err < 0) 2101 return err; 2102 } 2103 2104 return mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_DET_MODE, rdd_idx, 0, 1); 2105 } 2106 2107 static int mt7915_dfs_start_radar_detector(struct mt7915_phy *phy) 2108 { 2109 struct mt7915_dev *dev = phy->dev; 2110 int err, rdd_idx; 2111 2112 rdd_idx = mt7915_get_rdd_idx(phy, false); 2113 if (rdd_idx < 0) 2114 return -EINVAL; 2115 2116 /* start CAC */ 2117 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_START, rdd_idx, 0, 0); 2118 if (err < 0) 2119 return err; 2120 2121 err = mt7915_dfs_start_rdd(dev, rdd_idx); 2122 if (err < 0) 2123 return err; 2124 2125 return 0; 2126 } 2127 2128 static int 2129 mt7915_dfs_init_radar_specs(struct mt7915_phy *phy) 2130 { 2131 const struct mt7915_dfs_radar_spec *radar_specs; 2132 struct mt7915_dev *dev = phy->dev; 2133 int err, i; 2134 2135 switch (dev->mt76.region) { 2136 case NL80211_DFS_FCC: 2137 radar_specs = &fcc_radar_specs; 2138 err = mt7915_mcu_set_fcc5_lpn(dev, 8); 2139 if (err < 0) 2140 return err; 2141 break; 2142 case NL80211_DFS_ETSI: 2143 radar_specs = &etsi_radar_specs; 2144 break; 2145 case NL80211_DFS_JP: 2146 radar_specs = &jp_radar_specs; 2147 break; 2148 default: 2149 return -EINVAL; 2150 } 2151 2152 for (i = 0; i < ARRAY_SIZE(radar_specs->radar_pattern); i++) { 2153 err = mt7915_mcu_set_radar_th(dev, i, 2154 &radar_specs->radar_pattern[i]); 2155 if (err < 0) 2156 return err; 2157 } 2158 2159 return mt7915_mcu_set_pulse_th(dev, &radar_specs->pulse_th); 2160 } 2161 2162 int mt7915_dfs_init_radar_detector(struct mt7915_phy *phy) 2163 { 2164 struct mt7915_dev *dev = phy->dev; 2165 enum mt76_dfs_state dfs_state, prev_state; 2166 int err, rdd_idx = mt7915_get_rdd_idx(phy, false); 2167 2168 prev_state = phy->mt76->dfs_state; 2169 dfs_state = mt76_phy_dfs_state(phy->mt76); 2170 2171 if (prev_state == dfs_state || rdd_idx < 0) 2172 return 0; 2173 2174 if (prev_state == MT_DFS_STATE_UNKNOWN) 2175 mt7915_dfs_stop_radar_detector(phy); 2176 2177 if (dfs_state == MT_DFS_STATE_DISABLED) 2178 goto stop; 2179 2180 if (prev_state <= MT_DFS_STATE_DISABLED) { 2181 err = mt7915_dfs_init_radar_specs(phy); 2182 if (err < 0) 2183 return err; 2184 2185 err = mt7915_dfs_start_radar_detector(phy); 2186 if (err < 0) 2187 return err; 2188 2189 phy->mt76->dfs_state = MT_DFS_STATE_CAC; 2190 } 2191 2192 if (dfs_state == MT_DFS_STATE_CAC) 2193 return 0; 2194 2195 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_CAC_END, rdd_idx, 0, 0); 2196 if (err < 0) { 2197 phy->mt76->dfs_state = MT_DFS_STATE_UNKNOWN; 2198 return err; 2199 } 2200 2201 phy->mt76->dfs_state = MT_DFS_STATE_ACTIVE; 2202 return 0; 2203 2204 stop: 2205 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_NORMAL_START, rdd_idx, 0, 0); 2206 if (err < 0) 2207 return err; 2208 2209 if (is_mt7915(&dev->mt76)) { 2210 err = mt76_connac_mcu_rdd_cmd(&dev->mt76, RDD_SET_WF_ANT, 2211 rdd_idx, 0, dev->dbdc_support ? 2 : 0); 2212 if (err < 0) 2213 return err; 2214 } 2215 2216 mt7915_dfs_stop_radar_detector(phy); 2217 phy->mt76->dfs_state = MT_DFS_STATE_DISABLED; 2218 2219 return 0; 2220 } 2221 2222 static int 2223 mt7915_mac_twt_duration_align(int duration) 2224 { 2225 return duration << 8; 2226 } 2227 2228 static u64 2229 mt7915_mac_twt_sched_list_add(struct mt7915_dev *dev, 2230 struct mt7915_twt_flow *flow) 2231 { 2232 struct mt7915_twt_flow *iter, *iter_next; 2233 u32 duration = flow->duration << 8; 2234 u64 start_tsf; 2235 2236 iter = list_first_entry_or_null(&dev->twt_list, 2237 struct mt7915_twt_flow, list); 2238 if (!iter || !iter->sched || iter->start_tsf > duration) { 2239 /* add flow as first entry in the list */ 2240 list_add(&flow->list, &dev->twt_list); 2241 return 0; 2242 } 2243 2244 list_for_each_entry_safe(iter, iter_next, &dev->twt_list, list) { 2245 start_tsf = iter->start_tsf + 2246 mt7915_mac_twt_duration_align(iter->duration); 2247 if (list_is_last(&iter->list, &dev->twt_list)) 2248 break; 2249 2250 if (!iter_next->sched || 2251 iter_next->start_tsf > start_tsf + duration) { 2252 list_add(&flow->list, &iter->list); 2253 goto out; 2254 } 2255 } 2256 2257 /* add flow as last entry in the list */ 2258 list_add_tail(&flow->list, &dev->twt_list); 2259 out: 2260 return start_tsf; 2261 } 2262 2263 static int mt7915_mac_check_twt_req(struct ieee80211_twt_setup *twt) 2264 { 2265 struct ieee80211_twt_params *twt_agrt; 2266 u64 interval, duration; 2267 u16 mantissa; 2268 u8 exp; 2269 2270 /* only individual agreement supported */ 2271 if (twt->control & IEEE80211_TWT_CONTROL_NEG_TYPE_BROADCAST) 2272 return -EOPNOTSUPP; 2273 2274 /* only 256us unit supported */ 2275 if (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) 2276 return -EOPNOTSUPP; 2277 2278 twt_agrt = (struct ieee80211_twt_params *)twt->params; 2279 2280 /* explicit agreement not supported */ 2281 if (!(twt_agrt->req_type & cpu_to_le16(IEEE80211_TWT_REQTYPE_IMPLICIT))) 2282 return -EOPNOTSUPP; 2283 2284 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, 2285 le16_to_cpu(twt_agrt->req_type)); 2286 mantissa = le16_to_cpu(twt_agrt->mantissa); 2287 duration = twt_agrt->min_twt_dur << 8; 2288 2289 interval = (u64)mantissa << exp; 2290 if (interval < duration) 2291 return -EOPNOTSUPP; 2292 2293 return 0; 2294 } 2295 2296 static bool 2297 mt7915_mac_twt_param_equal(struct mt7915_sta *msta, 2298 struct ieee80211_twt_params *twt_agrt) 2299 { 2300 u16 type = le16_to_cpu(twt_agrt->req_type); 2301 u8 exp; 2302 int i; 2303 2304 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, type); 2305 for (i = 0; i < MT7915_MAX_STA_TWT_AGRT; i++) { 2306 struct mt7915_twt_flow *f; 2307 2308 if (!(msta->twt.flowid_mask & BIT(i))) 2309 continue; 2310 2311 f = &msta->twt.flow[i]; 2312 if (f->duration == twt_agrt->min_twt_dur && 2313 f->mantissa == twt_agrt->mantissa && 2314 f->exp == exp && 2315 f->protection == !!(type & IEEE80211_TWT_REQTYPE_PROTECTION) && 2316 f->flowtype == !!(type & IEEE80211_TWT_REQTYPE_FLOWTYPE) && 2317 f->trigger == !!(type & IEEE80211_TWT_REQTYPE_TRIGGER)) 2318 return true; 2319 } 2320 2321 return false; 2322 } 2323 2324 void mt7915_mac_add_twt_setup(struct ieee80211_hw *hw, 2325 struct ieee80211_sta *sta, 2326 struct ieee80211_twt_setup *twt) 2327 { 2328 enum ieee80211_twt_setup_cmd setup_cmd = TWT_SETUP_CMD_REJECT; 2329 struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv; 2330 struct ieee80211_twt_params *twt_agrt = (void *)twt->params; 2331 u16 req_type = le16_to_cpu(twt_agrt->req_type); 2332 enum ieee80211_twt_setup_cmd sta_setup_cmd; 2333 struct mt7915_dev *dev = mt7915_hw_dev(hw); 2334 struct mt7915_twt_flow *flow; 2335 int flowid, table_id; 2336 u8 exp; 2337 2338 if (mt7915_mac_check_twt_req(twt)) 2339 goto out; 2340 2341 mutex_lock(&dev->mt76.mutex); 2342 2343 if (dev->twt.n_agrt == MT7915_MAX_TWT_AGRT) 2344 goto unlock; 2345 2346 if (hweight8(msta->twt.flowid_mask) == ARRAY_SIZE(msta->twt.flow)) 2347 goto unlock; 2348 2349 if (twt_agrt->min_twt_dur < MT7915_MIN_TWT_DUR) { 2350 setup_cmd = TWT_SETUP_CMD_DICTATE; 2351 twt_agrt->min_twt_dur = MT7915_MIN_TWT_DUR; 2352 goto unlock; 2353 } 2354 2355 flowid = ffs(~msta->twt.flowid_mask) - 1; 2356 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_FLOWID); 2357 twt_agrt->req_type |= le16_encode_bits(flowid, 2358 IEEE80211_TWT_REQTYPE_FLOWID); 2359 2360 table_id = ffs(~dev->twt.table_mask) - 1; 2361 exp = FIELD_GET(IEEE80211_TWT_REQTYPE_WAKE_INT_EXP, req_type); 2362 sta_setup_cmd = FIELD_GET(IEEE80211_TWT_REQTYPE_SETUP_CMD, req_type); 2363 2364 if (mt7915_mac_twt_param_equal(msta, twt_agrt)) 2365 goto unlock; 2366 2367 flow = &msta->twt.flow[flowid]; 2368 memset(flow, 0, sizeof(*flow)); 2369 INIT_LIST_HEAD(&flow->list); 2370 flow->wcid = msta->wcid.idx; 2371 flow->table_id = table_id; 2372 flow->id = flowid; 2373 flow->duration = twt_agrt->min_twt_dur; 2374 flow->mantissa = twt_agrt->mantissa; 2375 flow->exp = exp; 2376 flow->protection = !!(req_type & IEEE80211_TWT_REQTYPE_PROTECTION); 2377 flow->flowtype = !!(req_type & IEEE80211_TWT_REQTYPE_FLOWTYPE); 2378 flow->trigger = !!(req_type & IEEE80211_TWT_REQTYPE_TRIGGER); 2379 2380 if (sta_setup_cmd == TWT_SETUP_CMD_REQUEST || 2381 sta_setup_cmd == TWT_SETUP_CMD_SUGGEST) { 2382 u64 interval = (u64)le16_to_cpu(twt_agrt->mantissa) << exp; 2383 u64 flow_tsf, curr_tsf; 2384 u32 rem; 2385 2386 flow->sched = true; 2387 flow->start_tsf = mt7915_mac_twt_sched_list_add(dev, flow); 2388 curr_tsf = __mt7915_get_tsf(hw, msta->vif); 2389 div_u64_rem(curr_tsf - flow->start_tsf, interval, &rem); 2390 flow_tsf = curr_tsf + interval - rem; 2391 twt_agrt->twt = cpu_to_le64(flow_tsf); 2392 } else { 2393 list_add_tail(&flow->list, &dev->twt_list); 2394 } 2395 flow->tsf = le64_to_cpu(twt_agrt->twt); 2396 2397 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, MCU_TWT_AGRT_ADD)) 2398 goto unlock; 2399 2400 setup_cmd = TWT_SETUP_CMD_ACCEPT; 2401 dev->twt.table_mask |= BIT(table_id); 2402 msta->twt.flowid_mask |= BIT(flowid); 2403 dev->twt.n_agrt++; 2404 2405 unlock: 2406 mutex_unlock(&dev->mt76.mutex); 2407 out: 2408 twt_agrt->req_type &= ~cpu_to_le16(IEEE80211_TWT_REQTYPE_SETUP_CMD); 2409 twt_agrt->req_type |= 2410 le16_encode_bits(setup_cmd, IEEE80211_TWT_REQTYPE_SETUP_CMD); 2411 twt->control = (twt->control & IEEE80211_TWT_CONTROL_WAKE_DUR_UNIT) | 2412 (twt->control & IEEE80211_TWT_CONTROL_RX_DISABLED); 2413 } 2414 2415 void mt7915_mac_twt_teardown_flow(struct mt7915_dev *dev, 2416 struct mt7915_sta *msta, 2417 u8 flowid) 2418 { 2419 struct mt7915_twt_flow *flow; 2420 2421 lockdep_assert_held(&dev->mt76.mutex); 2422 2423 if (flowid >= ARRAY_SIZE(msta->twt.flow)) 2424 return; 2425 2426 if (!(msta->twt.flowid_mask & BIT(flowid))) 2427 return; 2428 2429 flow = &msta->twt.flow[flowid]; 2430 if (mt7915_mcu_twt_agrt_update(dev, msta->vif, flow, 2431 MCU_TWT_AGRT_DELETE)) 2432 return; 2433 2434 list_del_init(&flow->list); 2435 msta->twt.flowid_mask &= ~BIT(flowid); 2436 dev->twt.table_mask &= ~BIT(flow->table_id); 2437 dev->twt.n_agrt--; 2438 } 2439