1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com> 4 */ 5 6 #ifndef __MT76x02_DFS_H 7 #define __MT76x02_DFS_H 8 9 #include <linux/types.h> 10 #include <linux/nl80211.h> 11 12 #define MT_DFS_GP_INTERVAL (10 << 4) /* 64 us unit */ 13 #define MT_DFS_NUM_ENGINES 4 14 15 /* bbp params */ 16 #define MT_DFS_SYM_ROUND 0 17 #define MT_DFS_DELTA_DELAY 2 18 #define MT_DFS_VGA_MASK 0 19 #define MT_DFS_PWR_GAIN_OFFSET 3 20 #define MT_DFS_PWR_DOWN_TIME 0xf 21 #define MT_DFS_RX_PE_MASK 0xff 22 #define MT_DFS_PKT_END_MASK 0 23 #define MT_DFS_CH_EN 0xf 24 25 /* sw detector params */ 26 #define MT_DFS_EVENT_LOOP 64 27 #define MT_DFS_SW_TIMEOUT (HZ / 20) 28 #define MT_DFS_EVENT_WINDOW (HZ / 5) 29 #define MT_DFS_SEQUENCE_WINDOW (200 * (1 << 20)) 30 #define MT_DFS_EVENT_TIME_MARGIN 2000 31 #define MT_DFS_PRI_MARGIN 4 32 #define MT_DFS_SEQUENCE_TH 6 33 34 #define MT_DFS_FCC_MAX_PRI ((28570 << 1) + 1000) 35 #define MT_DFS_FCC_MIN_PRI (3000 - 2) 36 #define MT_DFS_JP_MAX_PRI ((80000 << 1) + 1000) 37 #define MT_DFS_JP_MIN_PRI (28500 - 2) 38 #define MT_DFS_ETSI_MAX_PRI (133333 + 125000 + 117647 + 1000) 39 #define MT_DFS_ETSI_MIN_PRI (4500 - 20) 40 41 struct mt76x02_radar_specs { 42 u8 mode; 43 u16 avg_len; 44 u16 e_low; 45 u16 e_high; 46 u16 w_low; 47 u16 w_high; 48 u16 w_margin; 49 u32 t_low; 50 u32 t_high; 51 u16 t_margin; 52 u32 b_low; 53 u32 b_high; 54 u32 event_expiration; 55 u16 pwr_jmp; 56 }; 57 58 #define MT_DFS_CHECK_EVENT(x) ((x) != GENMASK(31, 0)) 59 #define MT_DFS_EVENT_ENGINE(x) (((x) & BIT(31)) ? 2 : 0) 60 #define MT_DFS_EVENT_TIMESTAMP(x) ((x) & GENMASK(21, 0)) 61 #define MT_DFS_EVENT_WIDTH(x) ((x) & GENMASK(11, 0)) 62 struct mt76x02_dfs_event { 63 unsigned long fetch_ts; 64 u32 ts; 65 u16 width; 66 u8 engine; 67 }; 68 69 #define MT_DFS_EVENT_BUFLEN 256 70 struct mt76x02_dfs_event_rb { 71 struct mt76x02_dfs_event data[MT_DFS_EVENT_BUFLEN]; 72 int h_rb, t_rb; 73 }; 74 75 struct mt76x02_dfs_sequence { 76 struct list_head head; 77 u32 first_ts; 78 u32 last_ts; 79 u32 pri; 80 u16 count; 81 u8 engine; 82 }; 83 84 struct mt76x02_dfs_hw_pulse { 85 u8 engine; 86 u32 period; 87 u32 w1; 88 u32 w2; 89 u32 burst; 90 }; 91 92 struct mt76x02_dfs_sw_detector_params { 93 u32 min_pri; 94 u32 max_pri; 95 u32 pri_margin; 96 }; 97 98 struct mt76x02_dfs_engine_stats { 99 u32 hw_pattern; 100 u32 hw_pulse_discarded; 101 u32 sw_pattern; 102 }; 103 104 struct mt76x02_dfs_seq_stats { 105 u32 seq_pool_len; 106 u32 seq_len; 107 }; 108 109 struct mt76x02_dfs_pattern_detector { 110 u8 chirp_pulse_cnt; 111 u32 chirp_pulse_ts; 112 113 struct mt76x02_dfs_sw_detector_params sw_dpd_params; 114 struct mt76x02_dfs_event_rb event_rb[2]; 115 116 struct list_head sequences; 117 struct list_head seq_pool; 118 struct mt76x02_dfs_seq_stats seq_stats; 119 120 unsigned long last_sw_check; 121 u32 last_event_ts; 122 123 struct mt76x02_dfs_engine_stats stats[MT_DFS_NUM_ENGINES]; 124 struct tasklet_struct dfs_tasklet; 125 }; 126 127 void mt76x02_dfs_init_params(struct mt76x02_dev *dev); 128 void mt76x02_dfs_init_detector(struct mt76x02_dev *dev); 129 void mt76x02_regd_notifier(struct wiphy *wiphy, 130 struct regulatory_request *request); 131 void mt76x02_phy_dfs_adjust_agc(struct mt76x02_dev *dev); 132 #endif /* __MT76x02_DFS_H */ 133