xref: /freebsd/sys/contrib/dev/mediatek/mt76/mt76x0/pci.c (revision 031beb4e239bfce798af17f5fe8dba8bcaf13d99)
1 // SPDX-License-Identifier: ISC
2 /*
3  * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4  */
5 
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/pci.h>
9 
10 #include "mt76x0.h"
11 #include "mcu.h"
12 
13 static int mt76x0e_start(struct ieee80211_hw *hw)
14 {
15 	struct mt76x02_dev *dev = hw->priv;
16 
17 	mt76x02_mac_start(dev);
18 	mt76x0_phy_calibrate(dev, true);
19 	ieee80211_queue_delayed_work(dev->mt76.hw, &dev->mphy.mac_work,
20 				     MT_MAC_WORK_INTERVAL);
21 	ieee80211_queue_delayed_work(dev->mt76.hw, &dev->cal_work,
22 				     MT_CALIBRATE_INTERVAL);
23 	set_bit(MT76_STATE_RUNNING, &dev->mphy.state);
24 
25 	return 0;
26 }
27 
28 static void mt76x0e_stop_hw(struct mt76x02_dev *dev)
29 {
30 	cancel_delayed_work_sync(&dev->cal_work);
31 	cancel_delayed_work_sync(&dev->mphy.mac_work);
32 	clear_bit(MT76_RESTART, &dev->mphy.state);
33 
34 	if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY,
35 		       0, 1000))
36 		dev_warn(dev->mt76.dev, "TX DMA did not stop\n");
37 	mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_EN);
38 
39 	mt76x0_mac_stop(dev);
40 
41 	if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_RX_DMA_BUSY,
42 		       0, 1000))
43 		dev_warn(dev->mt76.dev, "TX DMA did not stop\n");
44 	mt76_clear(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_RX_DMA_EN);
45 }
46 
47 static void mt76x0e_stop(struct ieee80211_hw *hw)
48 {
49 	struct mt76x02_dev *dev = hw->priv;
50 
51 	clear_bit(MT76_STATE_RUNNING, &dev->mphy.state);
52 	mt76x0e_stop_hw(dev);
53 }
54 
55 static void
56 mt76x0e_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
57 	      u32 queues, bool drop)
58 {
59 }
60 
61 static const struct ieee80211_ops mt76x0e_ops = {
62 	.tx = mt76x02_tx,
63 	.start = mt76x0e_start,
64 	.stop = mt76x0e_stop,
65 	.add_interface = mt76x02_add_interface,
66 	.remove_interface = mt76x02_remove_interface,
67 	.config = mt76x0_config,
68 	.configure_filter = mt76x02_configure_filter,
69 	.bss_info_changed = mt76x02_bss_info_changed,
70 	.sta_state = mt76_sta_state,
71 	.sta_pre_rcu_remove = mt76_sta_pre_rcu_remove,
72 	.set_key = mt76x02_set_key,
73 	.conf_tx = mt76x02_conf_tx,
74 	.sw_scan_start = mt76_sw_scan,
75 	.sw_scan_complete = mt76x02_sw_scan_complete,
76 	.ampdu_action = mt76x02_ampdu_action,
77 	.sta_rate_tbl_update = mt76x02_sta_rate_tbl_update,
78 	.wake_tx_queue = mt76_wake_tx_queue,
79 	.get_survey = mt76_get_survey,
80 	.get_txpower = mt76_get_txpower,
81 	.flush = mt76x0e_flush,
82 	.set_tim = mt76_set_tim,
83 	.release_buffered_frames = mt76_release_buffered_frames,
84 	.set_coverage_class = mt76x02_set_coverage_class,
85 	.set_rts_threshold = mt76x02_set_rts_threshold,
86 	.get_antenna = mt76_get_antenna,
87 	.reconfig_complete = mt76x02_reconfig_complete,
88 	.set_sar_specs = mt76x0_set_sar_specs,
89 };
90 
91 static int mt76x0e_init_hardware(struct mt76x02_dev *dev, bool resume)
92 {
93 	int err;
94 
95 	mt76x0_chip_onoff(dev, true, false);
96 	if (!mt76x02_wait_for_mac(&dev->mt76))
97 		return -ETIMEDOUT;
98 
99 	mt76x02_dma_disable(dev);
100 	err = mt76x0e_mcu_init(dev);
101 	if (err < 0)
102 		return err;
103 
104 	if (!resume) {
105 		err = mt76x02_dma_init(dev);
106 		if (err < 0)
107 			return err;
108 	}
109 
110 	err = mt76x0_init_hardware(dev);
111 	if (err < 0)
112 		return err;
113 
114 	mt76x02e_init_beacon_config(dev);
115 
116 	if (mt76_chip(&dev->mt76) == 0x7610) {
117 		u16 val;
118 
119 		mt76_clear(dev, MT_COEXCFG0, BIT(0));
120 
121 		val = mt76x02_eeprom_get(dev, MT_EE_NIC_CONF_0);
122 		if (!(val & MT_EE_NIC_CONF_0_PA_IO_CURRENT))
123 			mt76_set(dev, MT_XO_CTRL7, 0xc03);
124 	}
125 
126 	mt76_clear(dev, 0x110, BIT(9));
127 	mt76_set(dev, MT_MAX_LEN_CFG, BIT(13));
128 
129 	return 0;
130 }
131 
132 static int mt76x0e_register_device(struct mt76x02_dev *dev)
133 {
134 	int err;
135 
136 	err = mt76x0e_init_hardware(dev, false);
137 	if (err < 0)
138 		return err;
139 
140 	err = mt76x0_register_device(dev);
141 	if (err < 0)
142 		return err;
143 
144 	set_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
145 
146 	return 0;
147 }
148 
149 static int
150 mt76x0e_probe(struct pci_dev *pdev, const struct pci_device_id *id)
151 {
152 	static const struct mt76_driver_ops drv_ops = {
153 		.txwi_size = sizeof(struct mt76x02_txwi),
154 		.drv_flags = MT_DRV_TX_ALIGNED4_SKBS |
155 			     MT_DRV_SW_RX_AIRTIME,
156 		.survey_flags = SURVEY_INFO_TIME_TX,
157 		.update_survey = mt76x02_update_channel,
158 		.tx_prepare_skb = mt76x02_tx_prepare_skb,
159 		.tx_complete_skb = mt76x02_tx_complete_skb,
160 		.rx_skb = mt76x02_queue_rx_skb,
161 		.rx_poll_complete = mt76x02_rx_poll_complete,
162 		.sta_ps = mt76x02_sta_ps,
163 		.sta_add = mt76x02_sta_add,
164 		.sta_remove = mt76x02_sta_remove,
165 	};
166 	struct mt76x02_dev *dev;
167 	struct mt76_dev *mdev;
168 	int ret;
169 
170 	ret = pcim_enable_device(pdev);
171 	if (ret)
172 		return ret;
173 
174 	ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
175 	if (ret)
176 		return ret;
177 
178 	pci_set_master(pdev);
179 
180 	ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
181 	if (ret)
182 		return ret;
183 
184 	mt76_pci_disable_aspm(pdev);
185 
186 	mdev = mt76_alloc_device(&pdev->dev, sizeof(*dev), &mt76x0e_ops,
187 				 &drv_ops);
188 	if (!mdev)
189 		return -ENOMEM;
190 
191 	dev = container_of(mdev, struct mt76x02_dev, mt76);
192 	mutex_init(&dev->phy_mutex);
193 
194 	mt76_mmio_init(mdev, pcim_iomap_table(pdev)[0]);
195 
196 	mdev->rev = mt76_rr(dev, MT_ASIC_VERSION);
197 	dev_info(mdev->dev, "ASIC revision: %08x\n", mdev->rev);
198 
199 	mt76_wr(dev, MT_INT_MASK_CSR, 0);
200 
201 	ret = devm_request_irq(mdev->dev, pdev->irq, mt76x02_irq_handler,
202 			       IRQF_SHARED, KBUILD_MODNAME, dev);
203 	if (ret)
204 		goto error;
205 
206 	ret = mt76x0e_register_device(dev);
207 	if (ret < 0)
208 		goto error;
209 
210 	return 0;
211 
212 error:
213 	mt76_free_device(&dev->mt76);
214 
215 	return ret;
216 }
217 
218 static void mt76x0e_cleanup(struct mt76x02_dev *dev)
219 {
220 	clear_bit(MT76_STATE_INITIALIZED, &dev->mphy.state);
221 	tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
222 	mt76x0_chip_onoff(dev, false, false);
223 	mt76x0e_stop_hw(dev);
224 	mt76_dma_cleanup(&dev->mt76);
225 	mt76x02_mcu_cleanup(dev);
226 }
227 
228 static void
229 mt76x0e_remove(struct pci_dev *pdev)
230 {
231 	struct mt76_dev *mdev = pci_get_drvdata(pdev);
232 	struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
233 
234 	mt76_unregister_device(mdev);
235 	mt76x0e_cleanup(dev);
236 	mt76_free_device(mdev);
237 }
238 
239 #ifdef CONFIG_PM
240 static int mt76x0e_suspend(struct pci_dev *pdev, pm_message_t state)
241 {
242 	struct mt76_dev *mdev = pci_get_drvdata(pdev);
243 	struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
244 	int i;
245 
246 	mt76_worker_disable(&mdev->tx_worker);
247 	for (i = 0; i < ARRAY_SIZE(mdev->phy.q_tx); i++)
248 		mt76_queue_tx_cleanup(dev, mdev->phy.q_tx[i], true);
249 	for (i = 0; i < ARRAY_SIZE(mdev->q_mcu); i++)
250 		mt76_queue_tx_cleanup(dev, mdev->q_mcu[i], true);
251 	napi_disable(&mdev->tx_napi);
252 
253 	mt76_for_each_q_rx(mdev, i)
254 		napi_disable(&mdev->napi[i]);
255 
256 	mt76x02_dma_disable(dev);
257 	mt76x02_mcu_cleanup(dev);
258 	mt76x0_chip_onoff(dev, false, false);
259 
260 	pci_enable_wake(pdev, pci_choose_state(pdev, state), true);
261 	pci_save_state(pdev);
262 
263 	return pci_set_power_state(pdev, pci_choose_state(pdev, state));
264 }
265 
266 static int mt76x0e_resume(struct pci_dev *pdev)
267 {
268 	struct mt76_dev *mdev = pci_get_drvdata(pdev);
269 	struct mt76x02_dev *dev = container_of(mdev, struct mt76x02_dev, mt76);
270 	int err, i;
271 
272 	err = pci_set_power_state(pdev, PCI_D0);
273 	if (err)
274 		return err;
275 
276 	pci_restore_state(pdev);
277 
278 	mt76_worker_enable(&mdev->tx_worker);
279 
280 	local_bh_disable();
281 	mt76_for_each_q_rx(mdev, i) {
282 		mt76_queue_rx_reset(dev, i);
283 		napi_enable(&mdev->napi[i]);
284 		napi_schedule(&mdev->napi[i]);
285 	}
286 
287 	napi_enable(&mdev->tx_napi);
288 	napi_schedule(&mdev->tx_napi);
289 	local_bh_enable();
290 
291 	return mt76x0e_init_hardware(dev, true);
292 }
293 #endif /* CONFIG_PM */
294 
295 static const struct pci_device_id mt76x0e_device_table[] = {
296 	{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7610) },
297 	{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7630) },
298 	{ PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7650) },
299 	{ },
300 };
301 
302 MODULE_DEVICE_TABLE(pci, mt76x0e_device_table);
303 MODULE_FIRMWARE(MT7610E_FIRMWARE);
304 MODULE_FIRMWARE(MT7650E_FIRMWARE);
305 MODULE_LICENSE("Dual BSD/GPL");
306 
307 static struct pci_driver mt76x0e_driver = {
308 	.name		= KBUILD_MODNAME,
309 	.id_table	= mt76x0e_device_table,
310 	.probe		= mt76x0e_probe,
311 	.remove		= mt76x0e_remove,
312 #ifdef CONFIG_PM
313 	.suspend	= mt76x0e_suspend,
314 	.resume		= mt76x0e_resume,
315 #endif /* CONFIG_PM */
316 };
317 
318 module_pci_driver(mt76x0e_driver);
319