1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <linux/soc/mediatek/mtk_wed.h> 17 #if defined(__FreeBSD__) 18 #include <linux/wait.h> 19 #include <linux/bitfield.h> 20 #include <linux/debugfs.h> 21 #include <linux/pci.h> 22 #include <linux/interrupt.h> 23 #include <net/page_pool.h> 24 #endif 25 #include <net/mac80211.h> 26 #include <net/page_pool/helpers.h> 27 #include "util.h" 28 #include "testmode.h" 29 30 #define MT_MCU_RING_SIZE 32 31 #define MT_RX_BUF_SIZE 2048 32 #define MT_SKB_HEAD_LEN 256 33 34 #define MT_MAX_NON_AQL_PKT 16 35 #define MT_TXQ_FREE_THR 32 36 37 #define MT76_TOKEN_FREE_THR 64 38 39 #define MT_QFLAG_WED_RING GENMASK(1, 0) 40 #define MT_QFLAG_WED_TYPE GENMASK(4, 2) 41 #define MT_QFLAG_WED BIT(5) 42 #define MT_QFLAG_WED_RRO BIT(6) 43 #define MT_QFLAG_WED_RRO_EN BIT(7) 44 45 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ 46 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ 47 FIELD_PREP(MT_QFLAG_WED_RING, _n)) 48 #define __MT_WED_RRO_Q(_type, _n) (MT_QFLAG_WED_RRO | __MT_WED_Q(_type, _n)) 49 50 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n) 51 #define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n) 52 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0) 53 #define MT_WED_RRO_Q_DATA(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_DATA, _n) 54 #define MT_WED_RRO_Q_MSDU_PG(_n) __MT_WED_RRO_Q(MT76_WED_RRO_Q_MSDU_PG, _n) 55 #define MT_WED_RRO_Q_IND __MT_WED_RRO_Q(MT76_WED_RRO_Q_IND, 0) 56 57 struct mt76_dev; 58 struct mt76_phy; 59 struct mt76_wcid; 60 struct mt76s_intr; 61 struct mt76_chanctx; 62 struct mt76_vif_link; 63 64 struct mt76_reg_pair { 65 u32 reg; 66 u32 value; 67 }; 68 69 enum mt76_bus_type { 70 MT76_BUS_MMIO, 71 MT76_BUS_USB, 72 MT76_BUS_SDIO, 73 }; 74 75 enum mt76_wed_type { 76 MT76_WED_Q_TX, 77 MT76_WED_Q_TXFREE, 78 MT76_WED_Q_RX, 79 MT76_WED_RRO_Q_DATA, 80 MT76_WED_RRO_Q_MSDU_PG, 81 MT76_WED_RRO_Q_IND, 82 }; 83 84 struct mt76_bus_ops { 85 u32 (*rr)(struct mt76_dev *dev, u32 offset); 86 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 87 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 88 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 89 int len); 90 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 91 int len); 92 int (*wr_rp)(struct mt76_dev *dev, u32 base, 93 const struct mt76_reg_pair *rp, int len); 94 int (*rd_rp)(struct mt76_dev *dev, u32 base, 95 struct mt76_reg_pair *rp, int len); 96 enum mt76_bus_type type; 97 }; 98 99 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 100 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 101 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) 102 103 enum mt76_txq_id { 104 MT_TXQ_VO = IEEE80211_AC_VO, 105 MT_TXQ_VI = IEEE80211_AC_VI, 106 MT_TXQ_BE = IEEE80211_AC_BE, 107 MT_TXQ_BK = IEEE80211_AC_BK, 108 MT_TXQ_PSD, 109 MT_TXQ_BEACON, 110 MT_TXQ_CAB, 111 __MT_TXQ_MAX 112 }; 113 114 enum mt76_mcuq_id { 115 MT_MCUQ_WM, 116 MT_MCUQ_WA, 117 MT_MCUQ_FWDL, 118 __MT_MCUQ_MAX 119 }; 120 121 enum mt76_rxq_id { 122 MT_RXQ_MAIN, 123 MT_RXQ_MCU, 124 MT_RXQ_MCU_WA, 125 MT_RXQ_BAND1, 126 MT_RXQ_BAND1_WA, 127 MT_RXQ_MAIN_WA, 128 MT_RXQ_BAND2, 129 MT_RXQ_BAND2_WA, 130 MT_RXQ_RRO_BAND0, 131 MT_RXQ_RRO_BAND1, 132 MT_RXQ_RRO_BAND2, 133 MT_RXQ_MSDU_PAGE_BAND0, 134 MT_RXQ_MSDU_PAGE_BAND1, 135 MT_RXQ_MSDU_PAGE_BAND2, 136 MT_RXQ_TXFREE_BAND0, 137 MT_RXQ_TXFREE_BAND1, 138 MT_RXQ_TXFREE_BAND2, 139 MT_RXQ_RRO_IND, 140 __MT_RXQ_MAX 141 }; 142 143 enum mt76_band_id { 144 MT_BAND0, 145 MT_BAND1, 146 MT_BAND2, 147 __MT_MAX_BAND 148 }; 149 150 enum mt76_cipher_type { 151 MT_CIPHER_NONE, 152 MT_CIPHER_WEP40, 153 MT_CIPHER_TKIP, 154 MT_CIPHER_TKIP_NO_MIC, 155 MT_CIPHER_AES_CCMP, 156 MT_CIPHER_WEP104, 157 MT_CIPHER_BIP_CMAC_128, 158 MT_CIPHER_WEP128, 159 MT_CIPHER_WAPI, 160 MT_CIPHER_CCMP_CCX, 161 MT_CIPHER_CCMP_256, 162 MT_CIPHER_GCMP, 163 MT_CIPHER_GCMP_256, 164 }; 165 166 enum mt76_dfs_state { 167 MT_DFS_STATE_UNKNOWN, 168 MT_DFS_STATE_DISABLED, 169 MT_DFS_STATE_CAC, 170 MT_DFS_STATE_ACTIVE, 171 }; 172 173 struct mt76_queue_buf { 174 dma_addr_t addr; 175 u16 len:15, 176 skip_unmap:1; 177 }; 178 179 struct mt76_tx_info { 180 struct mt76_queue_buf buf[32]; 181 struct sk_buff *skb; 182 int nbuf; 183 u32 info; 184 }; 185 186 struct mt76_queue_entry { 187 union { 188 void *buf; 189 struct sk_buff *skb; 190 }; 191 union { 192 struct mt76_txwi_cache *txwi; 193 struct urb *urb; 194 int buf_sz; 195 }; 196 dma_addr_t dma_addr[2]; 197 u16 dma_len[2]; 198 u16 wcid; 199 bool skip_buf0:1; 200 bool skip_buf1:1; 201 bool done:1; 202 }; 203 204 struct mt76_queue_regs { 205 u32 desc_base; 206 u32 ring_size; 207 u32 cpu_idx; 208 u32 dma_idx; 209 } __packed __aligned(4); 210 211 struct mt76_queue { 212 struct mt76_queue_regs __iomem *regs; 213 214 spinlock_t lock; 215 spinlock_t cleanup_lock; 216 struct mt76_queue_entry *entry; 217 struct mt76_rro_desc *rro_desc; 218 struct mt76_desc *desc; 219 220 u16 first; 221 u16 head; 222 u16 tail; 223 u8 hw_idx; 224 u8 ep; 225 int ndesc; 226 int queued; 227 int buf_size; 228 bool stopped; 229 bool blocked; 230 231 u8 buf_offset; 232 u16 flags; 233 234 struct mtk_wed_device *wed; 235 u32 wed_regs; 236 237 dma_addr_t desc_dma; 238 struct sk_buff *rx_head; 239 struct page_pool *page_pool; 240 }; 241 242 struct mt76_mcu_ops { 243 unsigned int max_retry; 244 u32 headroom; 245 u32 tailroom; 246 247 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 248 int len, bool wait_resp); 249 int (*mcu_skb_prepare_msg)(struct mt76_dev *dev, struct sk_buff *skb, 250 int cmd, int *seq); 251 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 252 int cmd, int *seq); 253 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, 254 struct sk_buff *skb, int seq); 255 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); 256 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); 257 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 258 const struct mt76_reg_pair *rp, int len); 259 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 260 struct mt76_reg_pair *rp, int len); 261 int (*mcu_restart)(struct mt76_dev *dev); 262 }; 263 264 struct mt76_queue_ops { 265 int (*init)(struct mt76_dev *dev, 266 int (*poll)(struct napi_struct *napi, int budget)); 267 268 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 269 int idx, int n_desc, int bufsize, 270 u32 ring_base); 271 272 int (*tx_queue_skb)(struct mt76_phy *phy, struct mt76_queue *q, 273 enum mt76_txq_id qid, struct sk_buff *skb, 274 struct mt76_wcid *wcid, struct ieee80211_sta *sta); 275 276 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, 277 struct sk_buff *skb, u32 tx_info); 278 279 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 280 int *len, u32 *info, bool *more); 281 282 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 283 284 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 285 bool flush); 286 287 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); 288 289 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 290 291 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q); 292 }; 293 294 enum mt76_phy_type { 295 MT_PHY_TYPE_CCK, 296 MT_PHY_TYPE_OFDM, 297 MT_PHY_TYPE_HT, 298 MT_PHY_TYPE_HT_GF, 299 MT_PHY_TYPE_VHT, 300 MT_PHY_TYPE_HE_SU = 8, 301 MT_PHY_TYPE_HE_EXT_SU, 302 MT_PHY_TYPE_HE_TB, 303 MT_PHY_TYPE_HE_MU, 304 MT_PHY_TYPE_EHT_SU = 13, 305 MT_PHY_TYPE_EHT_TRIG, 306 MT_PHY_TYPE_EHT_MU, 307 __MT_PHY_TYPE_MAX, 308 }; 309 310 struct mt76_sta_stats { 311 u64 tx_mode[__MT_PHY_TYPE_MAX]; 312 u64 tx_bw[5]; /* 20, 40, 80, 160, 320 */ 313 u64 tx_nss[4]; /* 1, 2, 3, 4 */ 314 u64 tx_mcs[16]; /* mcs idx */ 315 u64 tx_bytes; 316 /* WED TX */ 317 u32 tx_packets; /* unit: MSDU */ 318 u32 tx_retries; 319 u32 tx_failed; 320 /* WED RX */ 321 u64 rx_bytes; 322 u32 rx_packets; 323 u32 rx_errors; 324 u32 rx_drops; 325 }; 326 327 enum mt76_wcid_flags { 328 MT_WCID_FLAG_CHECK_PS, 329 MT_WCID_FLAG_PS, 330 MT_WCID_FLAG_4ADDR, 331 MT_WCID_FLAG_HDR_TRANS, 332 }; 333 334 #define MT76_N_WCIDS 1088 335 336 /* stored in ieee80211_tx_info::hw_queue */ 337 #define MT_TX_HW_QUEUE_PHY GENMASK(3, 2) 338 339 DECLARE_EWMA(signal, 10, 8); 340 341 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 342 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 343 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 344 #define MT_WCID_TX_INFO_SET BIT(31) 345 346 struct mt76_wcid { 347 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 348 349 atomic_t non_aql_packets; 350 unsigned long flags; 351 352 struct ewma_signal rssi; 353 int inactive_count; 354 355 struct rate_info rate; 356 unsigned long ampdu_state; 357 358 u16 idx; 359 u8 hw_key_idx; 360 u8 hw_key_idx2; 361 362 u8 sta:1; 363 u8 sta_disabled:1; 364 u8 amsdu:1; 365 u8 phy_idx:2; 366 u8 link_id:4; 367 bool link_valid; 368 369 u8 rx_check_pn; 370 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6]; 371 u16 cipher; 372 373 u32 tx_info; 374 bool sw_iv; 375 376 struct list_head tx_list; 377 struct sk_buff_head tx_pending; 378 struct sk_buff_head tx_offchannel; 379 380 struct list_head list; 381 struct idr pktid; 382 383 struct mt76_sta_stats stats; 384 385 struct list_head poll_list; 386 387 struct mt76_wcid *def_wcid; 388 }; 389 390 struct mt76_txq { 391 u16 wcid; 392 393 u16 agg_ssn; 394 bool send_bar; 395 bool aggr; 396 }; 397 398 struct mt76_wed_rro_ind { 399 u32 se_id : 12; 400 u32 rsv : 4; 401 u32 start_sn : 12; 402 u32 ind_reason : 4; 403 u32 ind_cnt : 13; 404 u32 win_sz : 3; 405 u32 rsv2 : 13; 406 u32 magic_cnt : 3; 407 }; 408 409 struct mt76_txwi_cache { 410 struct list_head list; 411 dma_addr_t dma_addr; 412 413 union { 414 struct sk_buff *skb; 415 void *ptr; 416 }; 417 }; 418 419 struct mt76_rx_tid { 420 struct rcu_head rcu_head; 421 422 struct mt76_dev *dev; 423 424 spinlock_t lock; 425 struct delayed_work reorder_work; 426 427 u16 id; 428 u16 head; 429 u16 size; 430 u16 nframes; 431 432 u8 num; 433 434 u8 started:1, stopped:1, timer_pending:1; 435 436 struct sk_buff *reorder_buf[] __counted_by(size); 437 }; 438 439 #define MT_TX_CB_DMA_DONE BIT(0) 440 #define MT_TX_CB_TXS_DONE BIT(1) 441 #define MT_TX_CB_TXS_FAILED BIT(2) 442 443 #define MT_PACKET_ID_MASK GENMASK(6, 0) 444 #define MT_PACKET_ID_NO_ACK 0 445 #define MT_PACKET_ID_NO_SKB 1 446 #define MT_PACKET_ID_WED 2 447 #define MT_PACKET_ID_FIRST 3 448 #define MT_PACKET_ID_HAS_RATE BIT(7) 449 /* This is timer for when to give up when waiting for TXS callback, 450 * with starting time being the time at which the DMA_DONE callback 451 * was seen (so, we know packet was processed then, it should not take 452 * long after that for firmware to send the TXS callback if it is going 453 * to do so.) 454 */ 455 #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4) 456 457 struct mt76_tx_cb { 458 unsigned long jiffies; 459 u16 wcid; 460 u8 pktid; 461 u8 flags; 462 }; 463 464 enum { 465 MT76_STATE_INITIALIZED, 466 MT76_STATE_REGISTERED, 467 MT76_STATE_RUNNING, 468 MT76_STATE_MCU_RUNNING, 469 MT76_SCANNING, 470 MT76_HW_SCANNING, 471 MT76_HW_SCHED_SCANNING, 472 MT76_RESTART, 473 MT76_RESET, 474 MT76_MCU_RESET, 475 MT76_REMOVED, 476 MT76_READING_STATS, 477 MT76_STATE_POWER_OFF, 478 MT76_STATE_SUSPEND, 479 MT76_STATE_ROC, 480 MT76_STATE_PM, 481 MT76_STATE_WED_RESET, 482 }; 483 484 enum mt76_sta_event { 485 MT76_STA_EVENT_ASSOC, 486 MT76_STA_EVENT_AUTHORIZE, 487 MT76_STA_EVENT_DISASSOC, 488 }; 489 490 struct mt76_hw_cap { 491 bool has_2ghz; 492 bool has_5ghz; 493 bool has_6ghz; 494 }; 495 496 #define MT_DRV_TXWI_NO_FREE BIT(0) 497 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 498 #define MT_DRV_SW_RX_AIRTIME BIT(2) 499 #define MT_DRV_RX_DMA_HDR BIT(3) 500 #define MT_DRV_HW_MGMT_TXQ BIT(4) 501 #define MT_DRV_AMSDU_OFFLOAD BIT(5) 502 503 struct mt76_driver_ops { 504 u32 drv_flags; 505 u32 survey_flags; 506 u16 txwi_size; 507 u16 token_size; 508 u8 mcs_rates; 509 510 unsigned int link_data_size; 511 512 void (*update_survey)(struct mt76_phy *phy); 513 int (*set_channel)(struct mt76_phy *phy); 514 515 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 516 enum mt76_txq_id qid, struct mt76_wcid *wcid, 517 struct ieee80211_sta *sta, 518 struct mt76_tx_info *tx_info); 519 520 void (*tx_complete_skb)(struct mt76_dev *dev, 521 struct mt76_queue_entry *e); 522 523 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 524 525 bool (*rx_check)(struct mt76_dev *dev, void *data, int len); 526 527 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 528 struct sk_buff *skb, u32 *info); 529 530 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 531 532 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 533 bool ps); 534 535 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 536 struct ieee80211_sta *sta); 537 538 int (*sta_event)(struct mt76_dev *dev, struct ieee80211_vif *vif, 539 struct ieee80211_sta *sta, enum mt76_sta_event ev); 540 541 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 542 struct ieee80211_sta *sta); 543 544 int (*vif_link_add)(struct mt76_phy *phy, struct ieee80211_vif *vif, 545 struct ieee80211_bss_conf *link_conf, 546 struct mt76_vif_link *mlink); 547 548 void (*vif_link_remove)(struct mt76_phy *phy, 549 struct ieee80211_vif *vif, 550 struct ieee80211_bss_conf *link_conf, 551 struct mt76_vif_link *mlink); 552 }; 553 554 struct mt76_channel_state { 555 u64 cc_active; 556 u64 cc_busy; 557 u64 cc_rx; 558 u64 cc_bss_rx; 559 u64 cc_tx; 560 561 s8 noise; 562 }; 563 564 struct mt76_sband { 565 struct ieee80211_supported_band sband; 566 struct mt76_channel_state *chan; 567 }; 568 569 /* addr req mask */ 570 #define MT_VEND_TYPE_EEPROM BIT(31) 571 #define MT_VEND_TYPE_CFG BIT(30) 572 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 573 574 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 575 enum mt_vendor_req { 576 MT_VEND_DEV_MODE = 0x1, 577 MT_VEND_WRITE = 0x2, 578 MT_VEND_POWER_ON = 0x4, 579 MT_VEND_MULTI_WRITE = 0x6, 580 MT_VEND_MULTI_READ = 0x7, 581 MT_VEND_READ_EEPROM = 0x9, 582 MT_VEND_WRITE_FCE = 0x42, 583 MT_VEND_WRITE_CFG = 0x46, 584 MT_VEND_READ_CFG = 0x47, 585 MT_VEND_READ_EXT = 0x63, 586 MT_VEND_WRITE_EXT = 0x66, 587 MT_VEND_FEATURE_SET = 0x91, 588 }; 589 590 enum mt76u_in_ep { 591 MT_EP_IN_PKT_RX, 592 MT_EP_IN_CMD_RESP, 593 __MT_EP_IN_MAX, 594 }; 595 596 enum mt76u_out_ep { 597 MT_EP_OUT_INBAND_CMD, 598 MT_EP_OUT_AC_BE, 599 MT_EP_OUT_AC_BK, 600 MT_EP_OUT_AC_VI, 601 MT_EP_OUT_AC_VO, 602 MT_EP_OUT_HCCA, 603 __MT_EP_OUT_MAX, 604 }; 605 606 struct mt76_mcu { 607 struct mutex mutex; 608 u32 msg_seq; 609 int timeout; 610 611 struct sk_buff_head res_q; 612 wait_queue_head_t wait; 613 }; 614 615 #define MT_TX_SG_MAX_SIZE 8 616 #define MT_RX_SG_MAX_SIZE 4 617 #define MT_NUM_TX_ENTRIES 256 618 #define MT_NUM_RX_ENTRIES 128 619 #define MCU_RESP_URB_SIZE 1024 620 struct mt76_usb { 621 struct mutex usb_ctrl_mtx; 622 u8 *data; 623 u16 data_len; 624 625 struct mt76_worker status_worker; 626 struct mt76_worker rx_worker; 627 628 struct work_struct stat_work; 629 630 u8 out_ep[__MT_EP_OUT_MAX]; 631 u8 in_ep[__MT_EP_IN_MAX]; 632 bool sg_en; 633 634 struct mt76u_mcu { 635 u8 *data; 636 /* multiple reads */ 637 struct mt76_reg_pair *rp; 638 int rp_len; 639 u32 base; 640 } mcu; 641 }; 642 643 #define MT76S_XMIT_BUF_SZ 0x3fe00 644 #define MT76S_NUM_TX_ENTRIES 256 645 #define MT76S_NUM_RX_ENTRIES 512 646 struct mt76_sdio { 647 struct mt76_worker txrx_worker; 648 struct mt76_worker status_worker; 649 struct mt76_worker net_worker; 650 struct mt76_worker stat_worker; 651 652 u8 *xmit_buf; 653 u32 xmit_buf_sz; 654 655 struct sdio_func *func; 656 void *intr_data; 657 u8 hw_ver; 658 wait_queue_head_t wait; 659 660 int pse_mcu_quota_max; 661 struct { 662 int pse_data_quota; 663 int ple_data_quota; 664 int pse_mcu_quota; 665 int pse_page_size; 666 int deficit; 667 } sched; 668 669 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr); 670 }; 671 672 struct mt76_mmio { 673 void __iomem *regs; 674 spinlock_t irq_lock; 675 u32 irqmask; 676 677 struct mtk_wed_device wed; 678 struct mtk_wed_device wed_hif2; 679 struct completion wed_reset; 680 struct completion wed_reset_complete; 681 }; 682 683 struct mt76_rx_status { 684 union { 685 struct mt76_wcid *wcid; 686 u16 wcid_idx; 687 }; 688 689 u32 reorder_time; 690 691 u32 ampdu_ref; 692 u32 timestamp; 693 694 u8 iv[6]; 695 696 u8 phy_idx:2; 697 u8 aggr:1; 698 u8 qos_ctl; 699 u16 seqno; 700 701 u16 freq; 702 u32 flag; 703 u8 enc_flags; 704 u8 encoding:3, bw:4; 705 union { 706 struct { 707 u8 he_ru:3; 708 u8 he_gi:2; 709 u8 he_dcm:1; 710 }; 711 struct { 712 u8 ru:4; 713 u8 gi:2; 714 } eht; 715 }; 716 717 u8 amsdu:1, first_amsdu:1, last_amsdu:1; 718 u8 rate_idx; 719 u8 nss:5, band:3; 720 s8 signal; 721 u8 chains; 722 s8 chain_signal[IEEE80211_MAX_CHAINS]; 723 }; 724 725 struct mt76_freq_range_power { 726 const struct cfg80211_sar_freq_ranges *range; 727 s8 power; 728 }; 729 730 struct mt76_testmode_ops { 731 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); 732 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, 733 enum mt76_testmode_state new_state); 734 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); 735 }; 736 737 struct mt76_testmode_data { 738 enum mt76_testmode_state state; 739 740 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; 741 struct sk_buff *tx_skb; 742 743 u32 tx_count; 744 u16 tx_mpdu_len; 745 746 u8 tx_rate_mode; 747 u8 tx_rate_idx; 748 u8 tx_rate_nss; 749 u8 tx_rate_sgi; 750 u8 tx_rate_ldpc; 751 u8 tx_rate_stbc; 752 u8 tx_ltf; 753 754 u8 tx_antenna_mask; 755 u8 tx_spe_idx; 756 757 u8 tx_duty_cycle; 758 u32 tx_time; 759 u32 tx_ipg; 760 761 u32 freq_offset; 762 763 u8 tx_power[4]; 764 u8 tx_power_control; 765 766 u8 addr[3][ETH_ALEN]; 767 768 u32 tx_pending; 769 u32 tx_queued; 770 u16 tx_queued_limit; 771 u32 tx_done; 772 struct { 773 u64 packets[__MT_RXQ_MAX]; 774 u64 fcs_error[__MT_RXQ_MAX]; 775 } rx_stats; 776 }; 777 778 struct mt76_vif_link { 779 u8 idx; 780 u8 omac_idx; 781 u8 band_idx; 782 u8 wmm_idx; 783 u8 scan_seq_num; 784 u8 cipher; 785 u8 basic_rates_idx; 786 u8 mcast_rates_idx; 787 u8 beacon_rates_idx; 788 bool offchannel; 789 struct ieee80211_chanctx_conf *ctx; 790 struct mt76_wcid *wcid; 791 struct mt76_vif_data *mvif; 792 struct rcu_head rcu_head; 793 }; 794 795 struct mt76_vif_data { 796 struct mt76_vif_link __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS]; 797 798 struct mt76_phy *roc_phy; 799 u16 valid_links; 800 u8 deflink_id; 801 }; 802 803 struct mt76_phy { 804 struct ieee80211_hw *hw; 805 struct mt76_dev *dev; 806 void *priv; 807 808 unsigned long state; 809 unsigned int num_sta; 810 u8 band_idx; 811 812 spinlock_t tx_lock; 813 struct list_head tx_list; 814 struct mt76_queue *q_tx[__MT_TXQ_MAX]; 815 816 struct cfg80211_chan_def chandef; 817 struct cfg80211_chan_def main_chandef; 818 bool offchannel; 819 bool radar_enabled; 820 821 struct delayed_work roc_work; 822 struct ieee80211_vif *roc_vif; 823 struct mt76_vif_link *roc_link; 824 825 struct mt76_chanctx *chanctx; 826 827 struct mt76_channel_state *chan_state; 828 enum mt76_dfs_state dfs_state; 829 ktime_t survey_time; 830 831 u32 aggr_stats[32]; 832 833 struct mt76_hw_cap cap; 834 struct mt76_sband sband_2g; 835 struct mt76_sband sband_5g; 836 struct mt76_sband sband_6g; 837 838 u8 macaddr[ETH_ALEN]; 839 840 int txpower_cur; 841 u8 antenna_mask; 842 u16 chainmask; 843 844 #ifdef CONFIG_NL80211_TESTMODE 845 struct mt76_testmode_data test; 846 #endif 847 848 struct delayed_work mac_work; 849 u8 mac_work_count; 850 851 struct { 852 struct sk_buff *head; 853 struct sk_buff **tail; 854 u16 seqno; 855 } rx_amsdu[__MT_RXQ_MAX]; 856 857 struct mt76_freq_range_power *frp; 858 859 struct { 860 struct led_classdev cdev; 861 char name[32]; 862 bool al; 863 u8 pin; 864 } leds; 865 }; 866 867 struct mt76_dev { 868 struct mt76_phy phy; /* must be first */ 869 struct mt76_phy *phys[__MT_MAX_BAND]; 870 struct mt76_phy *band_phys[NUM_NL80211_BANDS]; 871 872 struct ieee80211_hw *hw; 873 874 spinlock_t wed_lock; 875 spinlock_t lock; 876 spinlock_t cc_lock; 877 878 u32 cur_cc_bss_rx; 879 880 struct mt76_rx_status rx_ampdu_status; 881 u32 rx_ampdu_len; 882 u32 rx_ampdu_ref; 883 884 struct mutex mutex; 885 886 const struct mt76_bus_ops *bus; 887 const struct mt76_driver_ops *drv; 888 const struct mt76_mcu_ops *mcu_ops; 889 struct device *dev; 890 struct device *dma_dev; 891 892 struct mt76_mcu mcu; 893 894 struct net_device *napi_dev; 895 struct net_device *tx_napi_dev; 896 spinlock_t rx_lock; 897 struct napi_struct napi[__MT_RXQ_MAX]; 898 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 899 struct tasklet_struct irq_tasklet; 900 901 struct list_head txwi_cache; 902 struct list_head rxwi_cache; 903 struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; 904 struct mt76_queue q_rx[__MT_RXQ_MAX]; 905 const struct mt76_queue_ops *queue_ops; 906 int tx_dma_idx[4]; 907 908 struct mt76_worker tx_worker; 909 struct napi_struct tx_napi; 910 911 spinlock_t token_lock; 912 struct idr token; 913 u16 wed_token_count; 914 u16 token_count; 915 u16 token_size; 916 917 spinlock_t rx_token_lock; 918 struct idr rx_token; 919 u16 rx_token_size; 920 921 wait_queue_head_t tx_wait; 922 /* spinclock used to protect wcid pktid linked list */ 923 spinlock_t status_lock; 924 925 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 926 927 u64 vif_mask; 928 929 struct mt76_wcid global_wcid; 930 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 931 struct list_head wcid_list; 932 933 struct list_head sta_poll_list; 934 spinlock_t sta_poll_lock; 935 936 u32 rev; 937 938 struct tasklet_struct pre_tbtt_tasklet; 939 int beacon_int; 940 u8 beacon_mask; 941 942 struct debugfs_blob_wrapper eeprom; 943 struct debugfs_blob_wrapper otp; 944 945 char alpha2[3]; 946 enum nl80211_dfs_regions region; 947 948 u32 debugfs_reg; 949 950 u8 csa_complete; 951 952 u32 rxfilter; 953 954 struct delayed_work scan_work; 955 struct { 956 struct cfg80211_scan_request *req; 957 struct ieee80211_channel *chan; 958 struct ieee80211_vif *vif; 959 struct mt76_vif_link *mlink; 960 struct mt76_phy *phy; 961 int chan_idx; 962 } scan; 963 964 #ifdef CONFIG_NL80211_TESTMODE 965 const struct mt76_testmode_ops *test_ops; 966 struct { 967 const char *name; 968 u32 offset; 969 } test_mtd; 970 #endif 971 struct workqueue_struct *wq; 972 973 union { 974 struct mt76_mmio mmio; 975 struct mt76_usb usb; 976 struct mt76_sdio sdio; 977 }; 978 }; 979 980 /* per-phy stats. */ 981 struct mt76_mib_stats { 982 u32 ack_fail_cnt; 983 u32 fcs_err_cnt; 984 u32 rts_cnt; 985 u32 rts_retries_cnt; 986 u32 ba_miss_cnt; 987 u32 tx_bf_cnt; 988 u32 tx_mu_bf_cnt; 989 u32 tx_mu_mpdu_cnt; 990 u32 tx_mu_acked_mpdu_cnt; 991 u32 tx_su_acked_mpdu_cnt; 992 u32 tx_bf_ibf_ppdu_cnt; 993 u32 tx_bf_ebf_ppdu_cnt; 994 995 u32 tx_bf_rx_fb_all_cnt; 996 u32 tx_bf_rx_fb_eht_cnt; 997 u32 tx_bf_rx_fb_he_cnt; 998 u32 tx_bf_rx_fb_vht_cnt; 999 u32 tx_bf_rx_fb_ht_cnt; 1000 1001 u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */ 1002 u32 tx_bf_rx_fb_nc_cnt; 1003 u32 tx_bf_rx_fb_nr_cnt; 1004 u32 tx_bf_fb_cpl_cnt; 1005 u32 tx_bf_fb_trig_cnt; 1006 1007 u32 tx_ampdu_cnt; 1008 u32 tx_stop_q_empty_cnt; 1009 u32 tx_mpdu_attempts_cnt; 1010 u32 tx_mpdu_success_cnt; 1011 u32 tx_pkt_ebf_cnt; 1012 u32 tx_pkt_ibf_cnt; 1013 1014 u32 tx_rwp_fail_cnt; 1015 u32 tx_rwp_need_cnt; 1016 1017 /* rx stats */ 1018 u32 rx_fifo_full_cnt; 1019 u32 channel_idle_cnt; 1020 u32 primary_cca_busy_time; 1021 u32 secondary_cca_busy_time; 1022 u32 primary_energy_detect_time; 1023 u32 cck_mdrdy_time; 1024 u32 ofdm_mdrdy_time; 1025 u32 green_mdrdy_time; 1026 u32 rx_vector_mismatch_cnt; 1027 u32 rx_delimiter_fail_cnt; 1028 u32 rx_mrdy_cnt; 1029 u32 rx_len_mismatch_cnt; 1030 u32 rx_mpdu_cnt; 1031 u32 rx_ampdu_cnt; 1032 u32 rx_ampdu_bytes_cnt; 1033 u32 rx_ampdu_valid_subframe_cnt; 1034 u32 rx_ampdu_valid_subframe_bytes_cnt; 1035 u32 rx_pfdrop_cnt; 1036 u32 rx_vec_queue_overflow_drop_cnt; 1037 u32 rx_ba_cnt; 1038 1039 u32 tx_amsdu[8]; 1040 u32 tx_amsdu_cnt; 1041 1042 /* mcu_muru_stats */ 1043 u32 dl_cck_cnt; 1044 u32 dl_ofdm_cnt; 1045 u32 dl_htmix_cnt; 1046 u32 dl_htgf_cnt; 1047 u32 dl_vht_su_cnt; 1048 u32 dl_vht_2mu_cnt; 1049 u32 dl_vht_3mu_cnt; 1050 u32 dl_vht_4mu_cnt; 1051 u32 dl_he_su_cnt; 1052 u32 dl_he_ext_su_cnt; 1053 u32 dl_he_2ru_cnt; 1054 u32 dl_he_2mu_cnt; 1055 u32 dl_he_3ru_cnt; 1056 u32 dl_he_3mu_cnt; 1057 u32 dl_he_4ru_cnt; 1058 u32 dl_he_4mu_cnt; 1059 u32 dl_he_5to8ru_cnt; 1060 u32 dl_he_9to16ru_cnt; 1061 u32 dl_he_gtr16ru_cnt; 1062 1063 u32 ul_hetrig_su_cnt; 1064 u32 ul_hetrig_2ru_cnt; 1065 u32 ul_hetrig_3ru_cnt; 1066 u32 ul_hetrig_4ru_cnt; 1067 u32 ul_hetrig_5to8ru_cnt; 1068 u32 ul_hetrig_9to16ru_cnt; 1069 u32 ul_hetrig_gtr16ru_cnt; 1070 u32 ul_hetrig_2mu_cnt; 1071 u32 ul_hetrig_3mu_cnt; 1072 u32 ul_hetrig_4mu_cnt; 1073 }; 1074 1075 struct mt76_power_limits { 1076 s8 cck[4]; 1077 s8 ofdm[8]; 1078 s8 mcs[4][10]; 1079 s8 ru[7][12]; 1080 s8 eht[16][16]; 1081 }; 1082 1083 struct mt76_ethtool_worker_info { 1084 u64 *data; 1085 int idx; 1086 int initial_stat_idx; 1087 int worker_stat_count; 1088 int sta_count; 1089 }; 1090 1091 struct mt76_chanctx { 1092 struct mt76_phy *phy; 1093 }; 1094 1095 #define CCK_RATE(_idx, _rate) { \ 1096 .bitrate = _rate, \ 1097 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 1098 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ 1099 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \ 1100 } 1101 1102 #define OFDM_RATE(_idx, _rate) { \ 1103 .bitrate = _rate, \ 1104 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 1105 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 1106 } 1107 1108 extern struct ieee80211_rate mt76_rates[12]; 1109 1110 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 1111 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 1112 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 1113 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 1114 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 1115 1116 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 1117 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 1118 1119 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 1120 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 1121 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 1122 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 1123 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 1124 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 1125 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 1126 1127 1128 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 1129 1130 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 1131 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 1132 1133 #define mt76_get_field(_dev, _reg, _field) \ 1134 FIELD_GET(_field, mt76_rr(dev, _reg)) 1135 1136 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 1137 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 1138 1139 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 1140 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 1141 1142 #define mt76_hw(dev) (dev)->mphy.hw 1143 1144 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 1145 int timeout); 1146 1147 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 1148 1149 bool ____mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 1150 int timeout, int kick); 1151 #define __mt76_poll_msec(...) ____mt76_poll_msec(__VA_ARGS__, 10) 1152 #define mt76_poll_msec(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__, 10) 1153 #define mt76_poll_msec_tick(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 1154 1155 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 1156 void mt76_pci_disable_aspm(struct pci_dev *pdev); 1157 bool mt76_pci_aspm_supported(struct pci_dev *pdev); 1158 1159 static inline u16 mt76_chip(struct mt76_dev *dev) 1160 { 1161 return dev->rev >> 16; 1162 } 1163 1164 static inline u16 mt76_rev(struct mt76_dev *dev) 1165 { 1166 return dev->rev & 0xffff; 1167 } 1168 1169 void mt76_wed_release_rx_buf(struct mtk_wed_device *wed); 1170 void mt76_wed_offload_disable(struct mtk_wed_device *wed); 1171 void mt76_wed_reset_complete(struct mtk_wed_device *wed); 1172 void mt76_wed_dma_reset(struct mt76_dev *dev); 1173 int mt76_wed_net_setup_tc(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1174 struct net_device *netdev, enum tc_setup_type type, 1175 void *type_data); 1176 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 1177 u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size); 1178 int mt76_wed_offload_enable(struct mtk_wed_device *wed); 1179 int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q, bool reset); 1180 #else 1181 static inline u32 mt76_wed_init_rx_buf(struct mtk_wed_device *wed, int size) 1182 { 1183 return 0; 1184 } 1185 1186 static inline int mt76_wed_offload_enable(struct mtk_wed_device *wed) 1187 { 1188 return 0; 1189 } 1190 1191 static inline int mt76_wed_dma_setup(struct mt76_dev *dev, struct mt76_queue *q, 1192 bool reset) 1193 { 1194 return 0; 1195 } 1196 #endif /* CONFIG_NET_MEDIATEK_SOC_WED */ 1197 1198 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 1199 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 1200 1201 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__) 1202 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 1203 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 1204 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mphy), __VA_ARGS__) 1205 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 1206 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 1207 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) 1208 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 1209 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) 1210 1211 #define mt76_for_each_q_rx(dev, i) \ 1212 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \ 1213 if ((dev)->q_rx[i].ndesc) 1214 1215 1216 #define mt76_dereference(p, dev) \ 1217 rcu_dereference_protected(p, lockdep_is_held(&(dev)->mutex)) 1218 1219 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 1220 const struct ieee80211_ops *ops, 1221 const struct mt76_driver_ops *drv_ops); 1222 int mt76_register_device(struct mt76_dev *dev, bool vht, 1223 struct ieee80211_rate *rates, int n_rates); 1224 void mt76_unregister_device(struct mt76_dev *dev); 1225 void mt76_free_device(struct mt76_dev *dev); 1226 void mt76_unregister_phy(struct mt76_phy *phy); 1227 1228 struct mt76_phy *mt76_alloc_radio_phy(struct mt76_dev *dev, unsigned int size, 1229 u8 band_idx); 1230 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 1231 const struct ieee80211_ops *ops, 1232 u8 band_idx); 1233 int mt76_register_phy(struct mt76_phy *phy, bool vht, 1234 struct ieee80211_rate *rates, int n_rates); 1235 1236 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy, 1237 const struct file_operations *ops); 1238 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev) 1239 { 1240 return mt76_register_debugfs_fops(&dev->phy, NULL); 1241 } 1242 1243 int mt76_queues_read(struct seq_file *s, void *data); 1244 void mt76_seq_puts_array(struct seq_file *file, const char *str, 1245 s8 *val, int len); 1246 1247 int mt76_eeprom_init(struct mt76_dev *dev, int len); 1248 void mt76_eeprom_override(struct mt76_phy *phy); 1249 int mt76_get_of_data_from_mtd(struct mt76_dev *dev, void *eep, int offset, int len); 1250 int mt76_get_of_data_from_nvmem(struct mt76_dev *dev, void *eep, 1251 const char *cell_name, int len); 1252 1253 struct mt76_queue * 1254 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, 1255 int ring_base, void *wed, u32 flags); 1256 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, 1257 int n_desc, int ring_base, void *wed, 1258 u32 flags) 1259 { 1260 struct mt76_queue *q; 1261 1262 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, wed, flags); 1263 if (IS_ERR(q)) 1264 return PTR_ERR(q); 1265 1266 phy->q_tx[qid] = q; 1267 1268 return 0; 1269 } 1270 1271 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, 1272 int n_desc, int ring_base) 1273 { 1274 struct mt76_queue *q; 1275 1276 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, NULL, 0); 1277 if (IS_ERR(q)) 1278 return PTR_ERR(q); 1279 1280 dev->q_mcu[qid] = q; 1281 1282 return 0; 1283 } 1284 1285 static inline struct mt76_phy * 1286 mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx) 1287 { 1288 if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) || 1289 (phy_idx == MT_BAND2 && dev->phys[phy_idx])) 1290 return dev->phys[phy_idx]; 1291 1292 return &dev->phy; 1293 } 1294 1295 static inline struct ieee80211_hw * 1296 mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx) 1297 { 1298 return mt76_dev_phy(dev, phy_idx)->hw; 1299 } 1300 1301 static inline u8 * 1302 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 1303 { 1304 return (u8 *)t - dev->drv->txwi_size; 1305 } 1306 1307 /* increment with wrap-around */ 1308 static inline int mt76_incr(int val, int size) 1309 { 1310 return (val + 1) & (size - 1); 1311 } 1312 1313 /* decrement with wrap-around */ 1314 static inline int mt76_decr(int val, int size) 1315 { 1316 return (val - 1) & (size - 1); 1317 } 1318 1319 u8 mt76_ac_to_hwq(u8 ac); 1320 1321 static inline struct ieee80211_txq * 1322 mtxq_to_txq(struct mt76_txq *mtxq) 1323 { 1324 void *ptr = mtxq; 1325 1326 return container_of(ptr, struct ieee80211_txq, drv_priv); 1327 } 1328 1329 static inline struct ieee80211_sta * 1330 wcid_to_sta(struct mt76_wcid *wcid) 1331 { 1332 void *ptr = wcid; 1333 1334 if (!wcid || !wcid->sta) 1335 return NULL; 1336 1337 if (wcid->def_wcid) 1338 ptr = wcid->def_wcid; 1339 1340 return container_of(ptr, struct ieee80211_sta, drv_priv); 1341 } 1342 1343 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 1344 { 1345 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 1346 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 1347 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 1348 } 1349 1350 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 1351 { 1352 struct mt76_rx_status mstat; 1353 u8 *data = skb->data; 1354 1355 /* Alignment concerns */ 1356 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 1357 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 1358 1359 mstat = *((struct mt76_rx_status *)skb->cb); 1360 1361 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 1362 data += sizeof(struct ieee80211_radiotap_he); 1363 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 1364 data += sizeof(struct ieee80211_radiotap_he_mu); 1365 1366 return data; 1367 } 1368 1369 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 1370 { 1371 int len = ieee80211_get_hdrlen_from_skb(skb); 1372 1373 if (len % 4 == 0) 1374 return; 1375 1376 skb_push(skb, 2); 1377 memmove(skb->data, skb->data + 2, len); 1378 1379 skb->data[len] = 0; 1380 skb->data[len + 1] = 0; 1381 } 1382 1383 static inline bool mt76_is_skb_pktid(u8 pktid) 1384 { 1385 if (pktid & MT_PACKET_ID_HAS_RATE) 1386 return false; 1387 1388 return pktid >= MT_PACKET_ID_FIRST; 1389 } 1390 1391 static inline u8 mt76_tx_power_nss_delta(u8 nss) 1392 { 1393 static const u8 nss_delta[4] = { 0, 6, 9, 12 }; 1394 u8 idx = nss - 1; 1395 1396 return (idx < ARRAY_SIZE(nss_delta)) ? nss_delta[idx] : 0; 1397 } 1398 1399 static inline bool mt76_testmode_enabled(struct mt76_phy *phy) 1400 { 1401 #ifdef CONFIG_NL80211_TESTMODE 1402 return phy->test.state != MT76_TM_STATE_OFF; 1403 #else 1404 return false; 1405 #endif 1406 } 1407 1408 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, 1409 struct sk_buff *skb, 1410 struct ieee80211_hw **hw) 1411 { 1412 #ifdef CONFIG_NL80211_TESTMODE 1413 int i; 1414 1415 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) { 1416 struct mt76_phy *phy = dev->phys[i]; 1417 1418 if (phy && skb == phy->test.tx_skb) { 1419 *hw = dev->phys[i]->hw; 1420 return true; 1421 } 1422 } 1423 return false; 1424 #else 1425 return false; 1426 #endif 1427 } 1428 1429 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 1430 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 1431 struct mt76_wcid *wcid, struct sk_buff *skb); 1432 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 1433 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, 1434 bool send_bar); 1435 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); 1436 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 1437 void mt76_txq_schedule_all(struct mt76_phy *phy); 1438 void mt76_tx_worker_run(struct mt76_dev *dev); 1439 void mt76_tx_worker(struct mt76_worker *w); 1440 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 1441 struct ieee80211_sta *sta, 1442 u16 tids, int nframes, 1443 enum ieee80211_frame_release_type reason, 1444 bool more_data); 1445 bool mt76_has_tx_pending(struct mt76_phy *phy); 1446 int mt76_update_channel(struct mt76_phy *phy); 1447 void mt76_update_survey(struct mt76_phy *phy); 1448 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); 1449 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 1450 struct survey_info *survey); 1451 int mt76_rx_signal(u8 chain_mask, s8 *chain_signal); 1452 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 1453 1454 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 1455 u16 ssn, u16 size); 1456 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 1457 1458 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 1459 struct ieee80211_key_conf *key); 1460 1461 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 1462 __acquires(&dev->status_lock); 1463 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 1464 __releases(&dev->status_lock); 1465 1466 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 1467 struct sk_buff *skb); 1468 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 1469 struct mt76_wcid *wcid, int pktid, 1470 struct sk_buff_head *list); 1471 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 1472 struct sk_buff_head *list); 1473 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb, 1474 struct list_head *free_list); 1475 static inline void 1476 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb) 1477 { 1478 __mt76_tx_complete_skb(dev, wcid, skb, NULL); 1479 } 1480 1481 void mt76_tx_status_check(struct mt76_dev *dev, bool flush); 1482 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1483 struct ieee80211_sta *sta, 1484 enum ieee80211_sta_state old_state, 1485 enum ieee80211_sta_state new_state); 1486 void __mt76_sta_remove(struct mt76_phy *phy, struct ieee80211_vif *vif, 1487 struct ieee80211_sta *sta); 1488 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1489 struct ieee80211_sta *sta); 1490 1491 int mt76_get_min_avg_rssi(struct mt76_dev *dev, u8 phy_idx); 1492 1493 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1494 unsigned int link_id, int *dbm); 1495 int mt76_init_sar_power(struct ieee80211_hw *hw, 1496 const struct cfg80211_sar_specs *sar); 1497 int mt76_get_sar_power(struct mt76_phy *phy, 1498 struct ieee80211_channel *chan, 1499 int power); 1500 1501 void mt76_csa_check(struct mt76_dev *dev); 1502 void mt76_csa_finish(struct mt76_dev *dev); 1503 1504 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 1505 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 1506 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 1507 int mt76_get_rate(struct mt76_dev *dev, 1508 struct ieee80211_supported_band *sband, 1509 int idx, bool cck); 1510 int mt76_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1511 struct ieee80211_scan_request *hw_req); 1512 void mt76_cancel_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif); 1513 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1514 const u8 *mac); 1515 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 1516 struct ieee80211_vif *vif); 1517 enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy); 1518 int mt76_add_chanctx(struct ieee80211_hw *hw, 1519 struct ieee80211_chanctx_conf *conf); 1520 void mt76_remove_chanctx(struct ieee80211_hw *hw, 1521 struct ieee80211_chanctx_conf *conf); 1522 void mt76_change_chanctx(struct ieee80211_hw *hw, 1523 struct ieee80211_chanctx_conf *conf, 1524 u32 changed); 1525 int mt76_assign_vif_chanctx(struct ieee80211_hw *hw, 1526 struct ieee80211_vif *vif, 1527 struct ieee80211_bss_conf *link_conf, 1528 struct ieee80211_chanctx_conf *conf); 1529 void mt76_unassign_vif_chanctx(struct ieee80211_hw *hw, 1530 struct ieee80211_vif *vif, 1531 struct ieee80211_bss_conf *link_conf, 1532 struct ieee80211_chanctx_conf *conf); 1533 int mt76_switch_vif_chanctx(struct ieee80211_hw *hw, 1534 struct ieee80211_vif_chanctx_switch *vifs, 1535 int n_vifs, 1536 enum ieee80211_chanctx_switch_mode mode); 1537 int mt76_remain_on_channel(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1538 struct ieee80211_channel *chan, int duration, 1539 enum ieee80211_roc_type type); 1540 int mt76_cancel_remain_on_channel(struct ieee80211_hw *hw, 1541 struct ieee80211_vif *vif); 1542 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1543 void *data, int len); 1544 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, 1545 struct netlink_callback *cb, void *data, int len); 1546 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); 1547 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); 1548 1549 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) 1550 { 1551 #ifdef CONFIG_NL80211_TESTMODE 1552 enum mt76_testmode_state state = MT76_TM_STATE_IDLE; 1553 1554 if (disable || phy->test.state == MT76_TM_STATE_OFF) 1555 state = MT76_TM_STATE_OFF; 1556 1557 mt76_testmode_set_state(phy, state); 1558 #endif 1559 } 1560 1561 1562 /* internal */ 1563 static inline struct ieee80211_hw * 1564 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 1565 { 1566 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1567 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 1568 struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx); 1569 1570 info->hw_queue &= ~MT_TX_HW_QUEUE_PHY; 1571 1572 return hw; 1573 } 1574 1575 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1576 void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1577 struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev); 1578 void mt76_free_pending_rxwi(struct mt76_dev *dev); 1579 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 1580 struct napi_struct *napi); 1581 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 1582 struct napi_struct *napi); 1583 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 1584 void mt76_testmode_tx_pending(struct mt76_phy *phy); 1585 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, 1586 struct mt76_queue_entry *e); 1587 int __mt76_set_channel(struct mt76_phy *phy, struct cfg80211_chan_def *chandef, 1588 bool offchannel); 1589 int mt76_set_channel(struct mt76_phy *phy, struct cfg80211_chan_def *chandef, 1590 bool offchannel); 1591 void mt76_scan_work(struct work_struct *work); 1592 void mt76_abort_scan(struct mt76_dev *dev); 1593 void mt76_roc_complete_work(struct work_struct *work); 1594 void mt76_abort_roc(struct mt76_phy *phy); 1595 struct mt76_vif_link *mt76_get_vif_phy_link(struct mt76_phy *phy, 1596 struct ieee80211_vif *vif); 1597 void mt76_put_vif_phy_link(struct mt76_phy *phy, struct ieee80211_vif *vif, 1598 struct mt76_vif_link *mlink); 1599 1600 /* usb */ 1601 static inline bool mt76u_urb_error(struct urb *urb) 1602 { 1603 return urb->status && 1604 urb->status != -ECONNRESET && 1605 urb->status != -ESHUTDOWN && 1606 urb->status != -ENOENT; 1607 } 1608 1609 static inline int 1610 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 1611 int timeout, int ep) 1612 { 1613 #if defined(__FreeBSD__) && !defined(CONFIG_USB) 1614 return (0); 1615 #else 1616 struct usb_interface *uintf = to_usb_interface(dev->dev); 1617 struct usb_device *udev = interface_to_usbdev(uintf); 1618 struct mt76_usb *usb = &dev->usb; 1619 unsigned int pipe; 1620 1621 if (actual_len) 1622 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 1623 else 1624 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 1625 1626 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 1627 #endif 1628 } 1629 1630 void mt76_ethtool_page_pool_stats(struct mt76_dev *dev, u64 *data, int *index); 1631 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi, 1632 struct mt76_sta_stats *stats, bool eht); 1633 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); 1634 int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type, 1635 u16 val, u16 offset, void *buf, size_t len); 1636 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 1637 u8 req_type, u16 val, u16 offset, 1638 void *buf, size_t len); 1639 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 1640 const u16 offset, const u32 val); 1641 void mt76u_read_copy(struct mt76_dev *dev, u32 offset, 1642 void *data, int len); 1643 u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr); 1644 void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type, 1645 u32 addr, u32 val); 1646 int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 1647 struct mt76_bus_ops *ops); 1648 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf); 1649 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 1650 int mt76u_alloc_queues(struct mt76_dev *dev); 1651 void mt76u_stop_tx(struct mt76_dev *dev); 1652 void mt76u_stop_rx(struct mt76_dev *dev); 1653 int mt76u_resume_rx(struct mt76_dev *dev); 1654 void mt76u_queues_deinit(struct mt76_dev *dev); 1655 1656 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, 1657 const struct mt76_bus_ops *bus_ops); 1658 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid); 1659 int mt76s_alloc_tx(struct mt76_dev *dev); 1660 void mt76s_deinit(struct mt76_dev *dev); 1661 void mt76s_sdio_irq(struct sdio_func *func); 1662 void mt76s_txrx_worker(struct mt76_sdio *sdio); 1663 bool mt76s_txqs_empty(struct mt76_dev *dev); 1664 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func, 1665 int hw_ver); 1666 u32 mt76s_rr(struct mt76_dev *dev, u32 offset); 1667 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val); 1668 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 1669 u32 mt76s_read_pcr(struct mt76_dev *dev); 1670 void mt76s_write_copy(struct mt76_dev *dev, u32 offset, 1671 const void *data, int len); 1672 void mt76s_read_copy(struct mt76_dev *dev, u32 offset, 1673 void *data, int len); 1674 int mt76s_wr_rp(struct mt76_dev *dev, u32 base, 1675 const struct mt76_reg_pair *data, 1676 int len); 1677 int mt76s_rd_rp(struct mt76_dev *dev, u32 base, 1678 struct mt76_reg_pair *data, int len); 1679 1680 struct sk_buff * 1681 __mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1682 int len, int data_len, gfp_t gfp); 1683 static inline struct sk_buff * 1684 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1685 int data_len) 1686 { 1687 return __mt76_mcu_msg_alloc(dev, data, data_len, data_len, GFP_KERNEL); 1688 } 1689 1690 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 1691 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 1692 unsigned long expires); 1693 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, 1694 int len, bool wait_resp, struct sk_buff **ret); 1695 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, 1696 int cmd, bool wait_resp, struct sk_buff **ret); 1697 #if defined(__linux__) 1698 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1699 #elif defined(__FreeBSD__) 1700 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const u8 *data, 1701 #endif 1702 int len, int max_len); 1703 static inline int 1704 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1705 int len) 1706 { 1707 int max_len = 4096 - dev->mcu_ops->headroom; 1708 1709 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len); 1710 } 1711 1712 static inline int 1713 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, 1714 bool wait_resp) 1715 { 1716 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); 1717 } 1718 1719 static inline int 1720 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, 1721 bool wait_resp) 1722 { 1723 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); 1724 } 1725 1726 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 1727 1728 struct device_node * 1729 mt76_find_power_limits_node(struct mt76_dev *dev); 1730 struct device_node * 1731 mt76_find_channel_node(struct device_node *np, struct ieee80211_channel *chan); 1732 1733 s8 mt76_get_rate_power_limits(struct mt76_phy *phy, 1734 struct ieee80211_channel *chan, 1735 struct mt76_power_limits *dest, 1736 s8 target_power); 1737 1738 static inline bool mt76_queue_is_rx(struct mt76_dev *dev, struct mt76_queue *q) 1739 { 1740 int i; 1741 1742 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++) { 1743 if (q == &dev->q_rx[i]) 1744 return true; 1745 } 1746 1747 return false; 1748 } 1749 1750 static inline bool mt76_queue_is_wed_tx_free(struct mt76_queue *q) 1751 { 1752 return (q->flags & MT_QFLAG_WED) && 1753 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_TXFREE; 1754 } 1755 1756 static inline bool mt76_queue_is_wed_rro(struct mt76_queue *q) 1757 { 1758 return q->flags & MT_QFLAG_WED_RRO; 1759 } 1760 1761 static inline bool mt76_queue_is_wed_rro_ind(struct mt76_queue *q) 1762 { 1763 return mt76_queue_is_wed_rro(q) && 1764 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_IND; 1765 } 1766 1767 static inline bool mt76_queue_is_wed_rro_data(struct mt76_queue *q) 1768 { 1769 return mt76_queue_is_wed_rro(q) && 1770 (FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_DATA || 1771 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_RRO_Q_MSDU_PG); 1772 } 1773 1774 static inline bool mt76_queue_is_wed_rx(struct mt76_queue *q) 1775 { 1776 if (!(q->flags & MT_QFLAG_WED)) 1777 return false; 1778 1779 return FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX || 1780 mt76_queue_is_wed_rro_ind(q) || mt76_queue_is_wed_rro_data(q); 1781 1782 } 1783 1784 struct mt76_txwi_cache * 1785 mt76_token_release(struct mt76_dev *dev, int token, bool *wake); 1786 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi); 1787 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked); 1788 struct mt76_txwi_cache *mt76_rx_token_release(struct mt76_dev *dev, int token); 1789 int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr, 1790 struct mt76_txwi_cache *r, dma_addr_t phys); 1791 int mt76_create_page_pool(struct mt76_dev *dev, struct mt76_queue *q); 1792 static inline void mt76_put_page_pool_buf(void *buf, bool allow_direct) 1793 { 1794 struct page *page = virt_to_head_page(buf); 1795 1796 page_pool_put_full_page(page->pp, page, allow_direct); 1797 } 1798 1799 static inline void * 1800 mt76_get_page_pool_buf(struct mt76_queue *q, u32 *offset, u32 size) 1801 { 1802 struct page *page; 1803 1804 page = page_pool_dev_alloc_frag(q->page_pool, offset, size); 1805 if (!page) 1806 return NULL; 1807 1808 #if defined(__linux__) 1809 return page_address(page) + *offset; 1810 #elif defined(__FreeBSD__) 1811 return (void *)((uintptr_t)page_address(page) + *offset); 1812 #endif 1813 } 1814 1815 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked) 1816 { 1817 spin_lock_bh(&dev->token_lock); 1818 __mt76_set_tx_blocked(dev, blocked); 1819 spin_unlock_bh(&dev->token_lock); 1820 } 1821 1822 static inline int 1823 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) 1824 { 1825 int token; 1826 1827 spin_lock_bh(&dev->token_lock); 1828 token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC); 1829 spin_unlock_bh(&dev->token_lock); 1830 1831 return token; 1832 } 1833 1834 static inline struct mt76_txwi_cache * 1835 mt76_token_put(struct mt76_dev *dev, int token) 1836 { 1837 struct mt76_txwi_cache *txwi; 1838 1839 spin_lock_bh(&dev->token_lock); 1840 txwi = idr_remove(&dev->token, token); 1841 spin_unlock_bh(&dev->token_lock); 1842 1843 return txwi; 1844 } 1845 1846 void mt76_wcid_init(struct mt76_wcid *wcid, u8 band_idx); 1847 void mt76_wcid_cleanup(struct mt76_dev *dev, struct mt76_wcid *wcid); 1848 void mt76_wcid_add_poll(struct mt76_dev *dev, struct mt76_wcid *wcid); 1849 1850 static inline void 1851 mt76_vif_init(struct ieee80211_vif *vif, struct mt76_vif_data *mvif) 1852 { 1853 struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv; 1854 1855 mlink->mvif = mvif; 1856 rcu_assign_pointer(mvif->link[0], mlink); 1857 } 1858 1859 void mt76_vif_cleanup(struct mt76_dev *dev, struct ieee80211_vif *vif); 1860 1861 static inline struct mt76_vif_link * 1862 mt76_vif_link(struct mt76_dev *dev, struct ieee80211_vif *vif, int link_id) 1863 { 1864 struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv; 1865 struct mt76_vif_data *mvif = mlink->mvif; 1866 1867 return mt76_dereference(mvif->link[link_id], dev); 1868 } 1869 1870 static inline struct mt76_vif_link * 1871 mt76_vif_conf_link(struct mt76_dev *dev, struct ieee80211_vif *vif, 1872 struct ieee80211_bss_conf *link_conf) 1873 { 1874 struct mt76_vif_link *mlink = (struct mt76_vif_link *)vif->drv_priv; 1875 struct mt76_vif_data *mvif = mlink->mvif; 1876 1877 if (link_conf == &vif->bss_conf) 1878 return mlink; 1879 1880 return mt76_dereference(mvif->link[link_conf->link_id], dev); 1881 } 1882 1883 static inline struct mt76_phy * 1884 mt76_vif_link_phy(struct mt76_vif_link *mlink) 1885 { 1886 struct mt76_chanctx *ctx; 1887 1888 if (!mlink->ctx) 1889 return NULL; 1890 1891 ctx = (struct mt76_chanctx *)mlink->ctx->drv_priv; 1892 1893 return ctx->phy; 1894 } 1895 1896 #endif 1897