1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <linux/soc/mediatek/mtk_wed.h> 17 #if defined(__FreeBSD__) 18 #include <linux/wait.h> 19 #include <linux/bitfield.h> 20 #include <linux/debugfs.h> 21 #include <linux/pci.h> 22 #include <linux/interrupt.h> 23 #endif 24 #include <net/mac80211.h> 25 #include "util.h" 26 #include "testmode.h" 27 28 #define MT_MCU_RING_SIZE 32 29 #define MT_RX_BUF_SIZE 2048 30 #define MT_SKB_HEAD_LEN 256 31 32 #define MT_MAX_NON_AQL_PKT 16 33 #define MT_TXQ_FREE_THR 32 34 35 #define MT76_TOKEN_FREE_THR 64 36 37 #define MT_QFLAG_WED_RING GENMASK(1, 0) 38 #define MT_QFLAG_WED_TYPE GENMASK(3, 2) 39 #define MT_QFLAG_WED BIT(4) 40 41 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ 42 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ 43 FIELD_PREP(MT_QFLAG_WED_RING, _n)) 44 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n) 45 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0) 46 47 struct mt76_dev; 48 struct mt76_phy; 49 struct mt76_wcid; 50 struct mt76s_intr; 51 52 struct mt76_reg_pair { 53 u32 reg; 54 u32 value; 55 }; 56 57 enum mt76_bus_type { 58 MT76_BUS_MMIO, 59 MT76_BUS_USB, 60 MT76_BUS_SDIO, 61 }; 62 63 enum mt76_wed_type { 64 MT76_WED_Q_TX, 65 MT76_WED_Q_TXFREE, 66 }; 67 68 struct mt76_bus_ops { 69 u32 (*rr)(struct mt76_dev *dev, u32 offset); 70 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 71 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 72 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 73 int len); 74 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 75 int len); 76 int (*wr_rp)(struct mt76_dev *dev, u32 base, 77 const struct mt76_reg_pair *rp, int len); 78 int (*rd_rp)(struct mt76_dev *dev, u32 base, 79 struct mt76_reg_pair *rp, int len); 80 enum mt76_bus_type type; 81 }; 82 83 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 84 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 85 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) 86 87 enum mt76_txq_id { 88 MT_TXQ_VO = IEEE80211_AC_VO, 89 MT_TXQ_VI = IEEE80211_AC_VI, 90 MT_TXQ_BE = IEEE80211_AC_BE, 91 MT_TXQ_BK = IEEE80211_AC_BK, 92 MT_TXQ_PSD, 93 MT_TXQ_BEACON, 94 MT_TXQ_CAB, 95 __MT_TXQ_MAX 96 }; 97 98 enum mt76_mcuq_id { 99 MT_MCUQ_WM, 100 MT_MCUQ_WA, 101 MT_MCUQ_FWDL, 102 __MT_MCUQ_MAX 103 }; 104 105 enum mt76_rxq_id { 106 MT_RXQ_MAIN, 107 MT_RXQ_MCU, 108 MT_RXQ_MCU_WA, 109 MT_RXQ_BAND1, 110 MT_RXQ_BAND1_WA, 111 MT_RXQ_MAIN_WA, 112 MT_RXQ_BAND2, 113 MT_RXQ_BAND2_WA, 114 __MT_RXQ_MAX 115 }; 116 117 enum mt76_band_id { 118 MT_BAND0, 119 MT_BAND1, 120 MT_BAND2, 121 __MT_MAX_BAND 122 }; 123 124 enum mt76_cipher_type { 125 MT_CIPHER_NONE, 126 MT_CIPHER_WEP40, 127 MT_CIPHER_TKIP, 128 MT_CIPHER_TKIP_NO_MIC, 129 MT_CIPHER_AES_CCMP, 130 MT_CIPHER_WEP104, 131 MT_CIPHER_BIP_CMAC_128, 132 MT_CIPHER_WEP128, 133 MT_CIPHER_WAPI, 134 MT_CIPHER_CCMP_CCX, 135 MT_CIPHER_CCMP_256, 136 MT_CIPHER_GCMP, 137 MT_CIPHER_GCMP_256, 138 }; 139 140 enum mt76_dfs_state { 141 MT_DFS_STATE_UNKNOWN, 142 MT_DFS_STATE_DISABLED, 143 MT_DFS_STATE_CAC, 144 MT_DFS_STATE_ACTIVE, 145 }; 146 147 struct mt76_queue_buf { 148 dma_addr_t addr; 149 u16 len; 150 bool skip_unmap; 151 }; 152 153 struct mt76_tx_info { 154 struct mt76_queue_buf buf[32]; 155 struct sk_buff *skb; 156 int nbuf; 157 u32 info; 158 }; 159 160 struct mt76_queue_entry { 161 union { 162 void *buf; 163 struct sk_buff *skb; 164 }; 165 union { 166 struct mt76_txwi_cache *txwi; 167 struct urb *urb; 168 int buf_sz; 169 }; 170 u32 dma_addr[2]; 171 u16 dma_len[2]; 172 u16 wcid; 173 bool skip_buf0:1; 174 bool skip_buf1:1; 175 bool done:1; 176 }; 177 178 struct mt76_queue_regs { 179 u32 desc_base; 180 u32 ring_size; 181 u32 cpu_idx; 182 u32 dma_idx; 183 } __packed __aligned(4); 184 185 struct mt76_queue { 186 struct mt76_queue_regs __iomem *regs; 187 188 spinlock_t lock; 189 spinlock_t cleanup_lock; 190 struct mt76_queue_entry *entry; 191 struct mt76_desc *desc; 192 193 u16 first; 194 u16 head; 195 u16 tail; 196 int ndesc; 197 int queued; 198 int buf_size; 199 bool stopped; 200 bool blocked; 201 202 u8 buf_offset; 203 u8 hw_idx; 204 u8 flags; 205 206 u32 wed_regs; 207 208 dma_addr_t desc_dma; 209 struct sk_buff *rx_head; 210 struct page_frag_cache rx_page; 211 }; 212 213 struct mt76_mcu_ops { 214 u32 headroom; 215 u32 tailroom; 216 217 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 218 int len, bool wait_resp); 219 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 220 int cmd, int *seq); 221 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, 222 struct sk_buff *skb, int seq); 223 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); 224 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); 225 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 226 const struct mt76_reg_pair *rp, int len); 227 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 228 struct mt76_reg_pair *rp, int len); 229 int (*mcu_restart)(struct mt76_dev *dev); 230 }; 231 232 struct mt76_queue_ops { 233 int (*init)(struct mt76_dev *dev, 234 int (*poll)(struct napi_struct *napi, int budget)); 235 236 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 237 int idx, int n_desc, int bufsize, 238 u32 ring_base); 239 240 int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q, 241 enum mt76_txq_id qid, struct sk_buff *skb, 242 struct mt76_wcid *wcid, struct ieee80211_sta *sta); 243 244 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, 245 struct sk_buff *skb, u32 tx_info); 246 247 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 248 int *len, u32 *info, bool *more); 249 250 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 251 252 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 253 bool flush); 254 255 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); 256 257 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 258 259 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q); 260 }; 261 262 enum mt76_phy_type { 263 MT_PHY_TYPE_CCK, 264 MT_PHY_TYPE_OFDM, 265 MT_PHY_TYPE_HT, 266 MT_PHY_TYPE_HT_GF, 267 MT_PHY_TYPE_VHT, 268 MT_PHY_TYPE_HE_SU = 8, 269 MT_PHY_TYPE_HE_EXT_SU, 270 MT_PHY_TYPE_HE_TB, 271 MT_PHY_TYPE_HE_MU, 272 __MT_PHY_TYPE_HE_MAX, 273 }; 274 275 struct mt76_sta_stats { 276 u64 tx_mode[__MT_PHY_TYPE_HE_MAX]; 277 u64 tx_bw[4]; /* 20, 40, 80, 160 */ 278 u64 tx_nss[4]; /* 1, 2, 3, 4 */ 279 u64 tx_mcs[16]; /* mcs idx */ 280 u64 tx_bytes; 281 u32 tx_packets; 282 u32 tx_retries; 283 u32 tx_failed; 284 }; 285 286 enum mt76_wcid_flags { 287 MT_WCID_FLAG_CHECK_PS, 288 MT_WCID_FLAG_PS, 289 MT_WCID_FLAG_4ADDR, 290 MT_WCID_FLAG_HDR_TRANS, 291 }; 292 293 #define MT76_N_WCIDS 544 294 295 /* stored in ieee80211_tx_info::hw_queue */ 296 #define MT_TX_HW_QUEUE_PHY GENMASK(3, 2) 297 298 DECLARE_EWMA(signal, 10, 8); 299 300 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 301 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 302 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 303 #define MT_WCID_TX_INFO_SET BIT(31) 304 305 struct mt76_wcid { 306 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 307 308 atomic_t non_aql_packets; 309 unsigned long flags; 310 311 struct ewma_signal rssi; 312 int inactive_count; 313 314 struct rate_info rate; 315 316 u16 idx; 317 u8 hw_key_idx; 318 u8 hw_key_idx2; 319 320 u8 sta:1; 321 u8 amsdu:1; 322 u8 phy_idx:2; 323 324 u8 rx_check_pn; 325 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6]; 326 u16 cipher; 327 328 u32 tx_info; 329 bool sw_iv; 330 331 struct list_head list; 332 struct idr pktid; 333 334 struct mt76_sta_stats stats; 335 }; 336 337 struct mt76_txq { 338 u16 wcid; 339 340 u16 agg_ssn; 341 bool send_bar; 342 bool aggr; 343 }; 344 345 struct mt76_txwi_cache { 346 struct list_head list; 347 dma_addr_t dma_addr; 348 349 struct sk_buff *skb; 350 }; 351 352 struct mt76_rx_tid { 353 struct rcu_head rcu_head; 354 355 struct mt76_dev *dev; 356 357 spinlock_t lock; 358 struct delayed_work reorder_work; 359 360 u16 head; 361 u16 size; 362 u16 nframes; 363 364 u8 num; 365 366 u8 started:1, stopped:1, timer_pending:1; 367 368 struct sk_buff *reorder_buf[]; 369 }; 370 371 #define MT_TX_CB_DMA_DONE BIT(0) 372 #define MT_TX_CB_TXS_DONE BIT(1) 373 #define MT_TX_CB_TXS_FAILED BIT(2) 374 375 #define MT_PACKET_ID_MASK GENMASK(6, 0) 376 #define MT_PACKET_ID_NO_ACK 0 377 #define MT_PACKET_ID_NO_SKB 1 378 #define MT_PACKET_ID_WED 2 379 #define MT_PACKET_ID_FIRST 3 380 #define MT_PACKET_ID_HAS_RATE BIT(7) 381 /* This is timer for when to give up when waiting for TXS callback, 382 * with starting time being the time at which the DMA_DONE callback 383 * was seen (so, we know packet was processed then, it should not take 384 * long after that for firmware to send the TXS callback if it is going 385 * to do so.) 386 */ 387 #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4) 388 389 struct mt76_tx_cb { 390 unsigned long jiffies; 391 u16 wcid; 392 u8 pktid; 393 u8 flags; 394 }; 395 396 enum { 397 MT76_STATE_INITIALIZED, 398 MT76_STATE_RUNNING, 399 MT76_STATE_MCU_RUNNING, 400 MT76_SCANNING, 401 MT76_HW_SCANNING, 402 MT76_HW_SCHED_SCANNING, 403 MT76_RESTART, 404 MT76_RESET, 405 MT76_MCU_RESET, 406 MT76_REMOVED, 407 MT76_READING_STATS, 408 MT76_STATE_POWER_OFF, 409 MT76_STATE_SUSPEND, 410 MT76_STATE_ROC, 411 MT76_STATE_PM, 412 }; 413 414 struct mt76_hw_cap { 415 bool has_2ghz; 416 bool has_5ghz; 417 bool has_6ghz; 418 }; 419 420 #define MT_DRV_TXWI_NO_FREE BIT(0) 421 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 422 #define MT_DRV_SW_RX_AIRTIME BIT(2) 423 #define MT_DRV_RX_DMA_HDR BIT(3) 424 #define MT_DRV_HW_MGMT_TXQ BIT(4) 425 426 struct mt76_driver_ops { 427 u32 drv_flags; 428 u32 survey_flags; 429 u16 txwi_size; 430 u16 token_size; 431 u8 mcs_rates; 432 433 void (*update_survey)(struct mt76_phy *phy); 434 435 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 436 enum mt76_txq_id qid, struct mt76_wcid *wcid, 437 struct ieee80211_sta *sta, 438 struct mt76_tx_info *tx_info); 439 440 void (*tx_complete_skb)(struct mt76_dev *dev, 441 struct mt76_queue_entry *e); 442 443 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 444 445 bool (*rx_check)(struct mt76_dev *dev, void *data, int len); 446 447 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 448 struct sk_buff *skb); 449 450 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 451 452 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 453 bool ps); 454 455 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 456 struct ieee80211_sta *sta); 457 458 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, 459 struct ieee80211_sta *sta); 460 461 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 462 struct ieee80211_sta *sta); 463 }; 464 465 struct mt76_channel_state { 466 u64 cc_active; 467 u64 cc_busy; 468 u64 cc_rx; 469 u64 cc_bss_rx; 470 u64 cc_tx; 471 472 s8 noise; 473 }; 474 475 struct mt76_sband { 476 struct ieee80211_supported_band sband; 477 struct mt76_channel_state *chan; 478 }; 479 480 struct mt76_rate_power { 481 union { 482 struct { 483 s8 cck[4]; 484 s8 ofdm[8]; 485 s8 stbc[10]; 486 s8 ht[16]; 487 s8 vht[10]; 488 }; 489 s8 all[48]; 490 }; 491 }; 492 493 /* addr req mask */ 494 #define MT_VEND_TYPE_EEPROM BIT(31) 495 #define MT_VEND_TYPE_CFG BIT(30) 496 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 497 498 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 499 enum mt_vendor_req { 500 MT_VEND_DEV_MODE = 0x1, 501 MT_VEND_WRITE = 0x2, 502 MT_VEND_POWER_ON = 0x4, 503 MT_VEND_MULTI_WRITE = 0x6, 504 MT_VEND_MULTI_READ = 0x7, 505 MT_VEND_READ_EEPROM = 0x9, 506 MT_VEND_WRITE_FCE = 0x42, 507 MT_VEND_WRITE_CFG = 0x46, 508 MT_VEND_READ_CFG = 0x47, 509 MT_VEND_READ_EXT = 0x63, 510 MT_VEND_WRITE_EXT = 0x66, 511 MT_VEND_FEATURE_SET = 0x91, 512 }; 513 514 enum mt76u_in_ep { 515 MT_EP_IN_PKT_RX, 516 MT_EP_IN_CMD_RESP, 517 __MT_EP_IN_MAX, 518 }; 519 520 enum mt76u_out_ep { 521 MT_EP_OUT_INBAND_CMD, 522 MT_EP_OUT_AC_BE, 523 MT_EP_OUT_AC_BK, 524 MT_EP_OUT_AC_VI, 525 MT_EP_OUT_AC_VO, 526 MT_EP_OUT_HCCA, 527 __MT_EP_OUT_MAX, 528 }; 529 530 struct mt76_mcu { 531 struct mutex mutex; 532 u32 msg_seq; 533 int timeout; 534 535 struct sk_buff_head res_q; 536 wait_queue_head_t wait; 537 }; 538 539 #define MT_TX_SG_MAX_SIZE 8 540 #define MT_RX_SG_MAX_SIZE 4 541 #define MT_NUM_TX_ENTRIES 256 542 #define MT_NUM_RX_ENTRIES 128 543 #define MCU_RESP_URB_SIZE 1024 544 struct mt76_usb { 545 struct mutex usb_ctrl_mtx; 546 u8 *data; 547 u16 data_len; 548 549 struct mt76_worker status_worker; 550 struct mt76_worker rx_worker; 551 552 struct work_struct stat_work; 553 554 u8 out_ep[__MT_EP_OUT_MAX]; 555 u8 in_ep[__MT_EP_IN_MAX]; 556 bool sg_en; 557 558 struct mt76u_mcu { 559 u8 *data; 560 /* multiple reads */ 561 struct mt76_reg_pair *rp; 562 int rp_len; 563 u32 base; 564 } mcu; 565 }; 566 567 #define MT76S_XMIT_BUF_SZ 0x3fe00 568 #define MT76S_NUM_TX_ENTRIES 256 569 #define MT76S_NUM_RX_ENTRIES 512 570 struct mt76_sdio { 571 struct mt76_worker txrx_worker; 572 struct mt76_worker status_worker; 573 struct mt76_worker net_worker; 574 575 struct work_struct stat_work; 576 577 u8 *xmit_buf; 578 u32 xmit_buf_sz; 579 580 struct sdio_func *func; 581 void *intr_data; 582 u8 hw_ver; 583 wait_queue_head_t wait; 584 585 struct { 586 int pse_data_quota; 587 int ple_data_quota; 588 int pse_mcu_quota; 589 int pse_page_size; 590 int deficit; 591 } sched; 592 593 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr); 594 }; 595 596 struct mt76_mmio { 597 void __iomem *regs; 598 spinlock_t irq_lock; 599 u32 irqmask; 600 601 struct mtk_wed_device wed; 602 }; 603 604 struct mt76_rx_status { 605 union { 606 struct mt76_wcid *wcid; 607 u16 wcid_idx; 608 }; 609 610 u32 reorder_time; 611 612 u32 ampdu_ref; 613 u32 timestamp; 614 615 u8 iv[6]; 616 617 u8 phy_idx:2; 618 u8 aggr:1; 619 u8 qos_ctl; 620 u16 seqno; 621 622 u16 freq; 623 u32 flag; 624 u8 enc_flags; 625 u8 encoding:2, bw:3, he_ru:3; 626 u8 he_gi:2, he_dcm:1; 627 u8 amsdu:1, first_amsdu:1, last_amsdu:1; 628 u8 rate_idx; 629 u8 nss; 630 u8 band; 631 s8 signal; 632 u8 chains; 633 s8 chain_signal[IEEE80211_MAX_CHAINS]; 634 }; 635 636 struct mt76_freq_range_power { 637 const struct cfg80211_sar_freq_ranges *range; 638 s8 power; 639 }; 640 641 struct mt76_testmode_ops { 642 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); 643 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, 644 enum mt76_testmode_state new_state); 645 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); 646 }; 647 648 struct mt76_testmode_data { 649 enum mt76_testmode_state state; 650 651 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; 652 struct sk_buff *tx_skb; 653 654 u32 tx_count; 655 u16 tx_mpdu_len; 656 657 u8 tx_rate_mode; 658 u8 tx_rate_idx; 659 u8 tx_rate_nss; 660 u8 tx_rate_sgi; 661 u8 tx_rate_ldpc; 662 u8 tx_rate_stbc; 663 u8 tx_ltf; 664 665 u8 tx_antenna_mask; 666 u8 tx_spe_idx; 667 668 u8 tx_duty_cycle; 669 u32 tx_time; 670 u32 tx_ipg; 671 672 u32 freq_offset; 673 674 u8 tx_power[4]; 675 u8 tx_power_control; 676 677 u8 addr[3][ETH_ALEN]; 678 679 u32 tx_pending; 680 u32 tx_queued; 681 u16 tx_queued_limit; 682 u32 tx_done; 683 struct { 684 u64 packets[__MT_RXQ_MAX]; 685 u64 fcs_error[__MT_RXQ_MAX]; 686 } rx_stats; 687 }; 688 689 struct mt76_vif { 690 u8 idx; 691 u8 omac_idx; 692 u8 band_idx; 693 u8 wmm_idx; 694 u8 scan_seq_num; 695 u8 cipher; 696 }; 697 698 struct mt76_phy { 699 struct ieee80211_hw *hw; 700 struct mt76_dev *dev; 701 void *priv; 702 703 unsigned long state; 704 u8 band_idx; 705 706 struct mt76_queue *q_tx[__MT_TXQ_MAX]; 707 708 struct cfg80211_chan_def chandef; 709 struct ieee80211_channel *main_chan; 710 711 struct mt76_channel_state *chan_state; 712 enum mt76_dfs_state dfs_state; 713 ktime_t survey_time; 714 715 struct mt76_hw_cap cap; 716 struct mt76_sband sband_2g; 717 struct mt76_sband sband_5g; 718 struct mt76_sband sband_6g; 719 720 u8 macaddr[ETH_ALEN]; 721 722 int txpower_cur; 723 u8 antenna_mask; 724 u16 chainmask; 725 726 #ifdef CONFIG_NL80211_TESTMODE 727 struct mt76_testmode_data test; 728 #endif 729 730 struct delayed_work mac_work; 731 u8 mac_work_count; 732 733 struct { 734 struct sk_buff *head; 735 struct sk_buff **tail; 736 u16 seqno; 737 } rx_amsdu[__MT_RXQ_MAX]; 738 739 struct mt76_freq_range_power *frp; 740 }; 741 742 struct mt76_dev { 743 struct mt76_phy phy; /* must be first */ 744 struct mt76_phy *phys[__MT_MAX_BAND]; 745 746 struct ieee80211_hw *hw; 747 748 spinlock_t lock; 749 spinlock_t cc_lock; 750 751 u32 cur_cc_bss_rx; 752 753 struct mt76_rx_status rx_ampdu_status; 754 u32 rx_ampdu_len; 755 u32 rx_ampdu_ref; 756 757 struct mutex mutex; 758 759 const struct mt76_bus_ops *bus; 760 const struct mt76_driver_ops *drv; 761 const struct mt76_mcu_ops *mcu_ops; 762 struct device *dev; 763 struct device *dma_dev; 764 765 struct mt76_mcu mcu; 766 767 struct net_device napi_dev; 768 struct net_device tx_napi_dev; 769 spinlock_t rx_lock; 770 struct napi_struct napi[__MT_RXQ_MAX]; 771 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 772 773 struct list_head txwi_cache; 774 struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; 775 struct mt76_queue q_rx[__MT_RXQ_MAX]; 776 const struct mt76_queue_ops *queue_ops; 777 int tx_dma_idx[4]; 778 779 struct mt76_worker tx_worker; 780 struct napi_struct tx_napi; 781 782 spinlock_t token_lock; 783 struct idr token; 784 u16 wed_token_count; 785 u16 token_count; 786 u16 token_size; 787 788 wait_queue_head_t tx_wait; 789 /* spinclock used to protect wcid pktid linked list */ 790 spinlock_t status_lock; 791 792 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 793 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 794 795 u64 vif_mask; 796 797 struct mt76_wcid global_wcid; 798 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 799 struct list_head wcid_list; 800 801 u32 rev; 802 803 u32 aggr_stats[32]; 804 805 struct tasklet_struct pre_tbtt_tasklet; 806 int beacon_int; 807 u8 beacon_mask; 808 809 struct debugfs_blob_wrapper eeprom; 810 struct debugfs_blob_wrapper otp; 811 812 struct mt76_rate_power rate_power; 813 814 char alpha2[3]; 815 enum nl80211_dfs_regions region; 816 817 u32 debugfs_reg; 818 819 struct led_classdev led_cdev; 820 char led_name[32]; 821 bool led_al; 822 u8 led_pin; 823 824 u8 csa_complete; 825 826 u32 rxfilter; 827 828 #ifdef CONFIG_NL80211_TESTMODE 829 const struct mt76_testmode_ops *test_ops; 830 struct { 831 const char *name; 832 u32 offset; 833 } test_mtd; 834 #endif 835 struct workqueue_struct *wq; 836 837 union { 838 struct mt76_mmio mmio; 839 struct mt76_usb usb; 840 struct mt76_sdio sdio; 841 }; 842 }; 843 844 struct mt76_power_limits { 845 s8 cck[4]; 846 s8 ofdm[8]; 847 s8 mcs[4][10]; 848 s8 ru[7][12]; 849 }; 850 851 struct mt76_ethtool_worker_info { 852 u64 *data; 853 int idx; 854 int initial_stat_idx; 855 int worker_stat_count; 856 int sta_count; 857 }; 858 859 #define CCK_RATE(_idx, _rate) { \ 860 .bitrate = _rate, \ 861 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 862 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ 863 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \ 864 } 865 866 #define OFDM_RATE(_idx, _rate) { \ 867 .bitrate = _rate, \ 868 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 869 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 870 } 871 872 extern struct ieee80211_rate mt76_rates[12]; 873 874 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 875 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 876 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 877 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 878 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 879 880 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 881 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 882 883 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 884 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 885 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 886 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 887 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 888 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 889 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 890 891 892 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 893 #define __mt76_mcu_restart(dev, ...) (dev)->mcu_ops->mcu_restart((dev)) 894 895 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 896 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 897 898 #define mt76_get_field(_dev, _reg, _field) \ 899 FIELD_GET(_field, mt76_rr(dev, _reg)) 900 901 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 902 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 903 904 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 905 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 906 907 #define mt76_hw(dev) (dev)->mphy.hw 908 909 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 910 int timeout); 911 912 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 913 914 bool __mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 915 int timeout); 916 917 #define mt76_poll_msec(dev, ...) __mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 918 919 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 920 void mt76_pci_disable_aspm(struct pci_dev *pdev); 921 922 static inline u16 mt76_chip(struct mt76_dev *dev) 923 { 924 return dev->rev >> 16; 925 } 926 927 static inline u16 mt76_rev(struct mt76_dev *dev) 928 { 929 return dev->rev & 0xffff; 930 } 931 932 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 933 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 934 935 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__) 936 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 937 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 938 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__) 939 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 940 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 941 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) 942 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 943 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) 944 945 #define mt76_for_each_q_rx(dev, i) \ 946 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \ 947 if ((dev)->q_rx[i].ndesc) 948 949 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 950 const struct ieee80211_ops *ops, 951 const struct mt76_driver_ops *drv_ops); 952 int mt76_register_device(struct mt76_dev *dev, bool vht, 953 struct ieee80211_rate *rates, int n_rates); 954 void mt76_unregister_device(struct mt76_dev *dev); 955 void mt76_free_device(struct mt76_dev *dev); 956 void mt76_unregister_phy(struct mt76_phy *phy); 957 958 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 959 const struct ieee80211_ops *ops, 960 u8 band_idx); 961 int mt76_register_phy(struct mt76_phy *phy, bool vht, 962 struct ieee80211_rate *rates, int n_rates); 963 964 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy, 965 const struct file_operations *ops); 966 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev) 967 { 968 return mt76_register_debugfs_fops(&dev->phy, NULL); 969 } 970 971 int mt76_queues_read(struct seq_file *s, void *data); 972 void mt76_seq_puts_array(struct seq_file *file, const char *str, 973 s8 *val, int len); 974 975 int mt76_eeprom_init(struct mt76_dev *dev, int len); 976 void mt76_eeprom_override(struct mt76_phy *phy); 977 int mt76_get_of_eeprom(struct mt76_dev *dev, void *data, int offset, int len); 978 979 struct mt76_queue * 980 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, 981 int ring_base, u32 flags); 982 u16 mt76_calculate_default_rate(struct mt76_phy *phy, int rateidx); 983 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, 984 int n_desc, int ring_base, u32 flags) 985 { 986 struct mt76_queue *q; 987 988 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, flags); 989 if (IS_ERR(q)) 990 return PTR_ERR(q); 991 992 phy->q_tx[qid] = q; 993 994 return 0; 995 } 996 997 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, 998 int n_desc, int ring_base) 999 { 1000 struct mt76_queue *q; 1001 1002 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, 0); 1003 if (IS_ERR(q)) 1004 return PTR_ERR(q); 1005 1006 dev->q_mcu[qid] = q; 1007 1008 return 0; 1009 } 1010 1011 static inline struct mt76_phy * 1012 mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx) 1013 { 1014 if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) || 1015 (phy_idx == MT_BAND2 && dev->phys[phy_idx])) 1016 return dev->phys[phy_idx]; 1017 1018 return &dev->phy; 1019 } 1020 1021 static inline struct ieee80211_hw * 1022 mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx) 1023 { 1024 return mt76_dev_phy(dev, phy_idx)->hw; 1025 } 1026 1027 static inline u8 * 1028 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 1029 { 1030 return (u8 *)t - dev->drv->txwi_size; 1031 } 1032 1033 /* increment with wrap-around */ 1034 static inline int mt76_incr(int val, int size) 1035 { 1036 return (val + 1) & (size - 1); 1037 } 1038 1039 /* decrement with wrap-around */ 1040 static inline int mt76_decr(int val, int size) 1041 { 1042 return (val - 1) & (size - 1); 1043 } 1044 1045 u8 mt76_ac_to_hwq(u8 ac); 1046 1047 static inline struct ieee80211_txq * 1048 mtxq_to_txq(struct mt76_txq *mtxq) 1049 { 1050 void *ptr = mtxq; 1051 1052 return container_of(ptr, struct ieee80211_txq, drv_priv); 1053 } 1054 1055 static inline struct ieee80211_sta * 1056 wcid_to_sta(struct mt76_wcid *wcid) 1057 { 1058 void *ptr = wcid; 1059 1060 if (!wcid || !wcid->sta) 1061 return NULL; 1062 1063 return container_of(ptr, struct ieee80211_sta, drv_priv); 1064 } 1065 1066 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 1067 { 1068 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 1069 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 1070 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 1071 } 1072 1073 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 1074 { 1075 struct mt76_rx_status mstat; 1076 u8 *data = skb->data; 1077 1078 /* Alignment concerns */ 1079 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 1080 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 1081 1082 mstat = *((struct mt76_rx_status *)skb->cb); 1083 1084 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 1085 data += sizeof(struct ieee80211_radiotap_he); 1086 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 1087 data += sizeof(struct ieee80211_radiotap_he_mu); 1088 1089 return data; 1090 } 1091 1092 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 1093 { 1094 int len = ieee80211_get_hdrlen_from_skb(skb); 1095 1096 if (len % 4 == 0) 1097 return; 1098 1099 skb_push(skb, 2); 1100 memmove(skb->data, skb->data + 2, len); 1101 1102 skb->data[len] = 0; 1103 skb->data[len + 1] = 0; 1104 } 1105 1106 static inline bool mt76_is_skb_pktid(u8 pktid) 1107 { 1108 if (pktid & MT_PACKET_ID_HAS_RATE) 1109 return false; 1110 1111 return pktid >= MT_PACKET_ID_FIRST; 1112 } 1113 1114 static inline u8 mt76_tx_power_nss_delta(u8 nss) 1115 { 1116 static const u8 nss_delta[4] = { 0, 6, 9, 12 }; 1117 1118 return nss_delta[nss - 1]; 1119 } 1120 1121 static inline bool mt76_testmode_enabled(struct mt76_phy *phy) 1122 { 1123 #ifdef CONFIG_NL80211_TESTMODE 1124 return phy->test.state != MT76_TM_STATE_OFF; 1125 #else 1126 return false; 1127 #endif 1128 } 1129 1130 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, 1131 struct sk_buff *skb, 1132 struct ieee80211_hw **hw) 1133 { 1134 #ifdef CONFIG_NL80211_TESTMODE 1135 int i; 1136 1137 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) { 1138 struct mt76_phy *phy = dev->phys[i]; 1139 1140 if (phy && skb == phy->test.tx_skb) { 1141 *hw = dev->phys[i]->hw; 1142 return true; 1143 } 1144 } 1145 return false; 1146 #else 1147 return false; 1148 #endif 1149 } 1150 1151 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 1152 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 1153 struct mt76_wcid *wcid, struct sk_buff *skb); 1154 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 1155 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, 1156 bool send_bar); 1157 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); 1158 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 1159 void mt76_txq_schedule_all(struct mt76_phy *phy); 1160 void mt76_tx_worker_run(struct mt76_dev *dev); 1161 void mt76_tx_worker(struct mt76_worker *w); 1162 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 1163 struct ieee80211_sta *sta, 1164 u16 tids, int nframes, 1165 enum ieee80211_frame_release_type reason, 1166 bool more_data); 1167 bool mt76_has_tx_pending(struct mt76_phy *phy); 1168 void mt76_set_channel(struct mt76_phy *phy); 1169 void mt76_update_survey(struct mt76_phy *phy); 1170 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); 1171 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 1172 struct survey_info *survey); 1173 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 1174 1175 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 1176 u16 ssn, u16 size); 1177 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 1178 1179 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 1180 struct ieee80211_key_conf *key); 1181 1182 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 1183 __acquires(&dev->status_lock); 1184 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 1185 __releases(&dev->status_lock); 1186 1187 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 1188 struct sk_buff *skb); 1189 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 1190 struct mt76_wcid *wcid, int pktid, 1191 struct sk_buff_head *list); 1192 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 1193 struct sk_buff_head *list); 1194 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb, 1195 struct list_head *free_list); 1196 static inline void 1197 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb) 1198 { 1199 __mt76_tx_complete_skb(dev, wcid, skb, NULL); 1200 } 1201 1202 void mt76_tx_status_check(struct mt76_dev *dev, bool flush); 1203 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1204 struct ieee80211_sta *sta, 1205 enum ieee80211_sta_state old_state, 1206 enum ieee80211_sta_state new_state); 1207 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, 1208 struct ieee80211_sta *sta); 1209 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1210 struct ieee80211_sta *sta); 1211 1212 int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy); 1213 1214 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1215 int *dbm); 1216 int mt76_init_sar_power(struct ieee80211_hw *hw, 1217 const struct cfg80211_sar_specs *sar); 1218 int mt76_get_sar_power(struct mt76_phy *phy, 1219 struct ieee80211_channel *chan, 1220 int power); 1221 1222 void mt76_csa_check(struct mt76_dev *dev); 1223 void mt76_csa_finish(struct mt76_dev *dev); 1224 1225 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 1226 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 1227 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 1228 int mt76_get_rate(struct mt76_dev *dev, 1229 struct ieee80211_supported_band *sband, 1230 int idx, bool cck); 1231 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1232 const u8 *mac); 1233 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 1234 struct ieee80211_vif *vif); 1235 enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy); 1236 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1237 void *data, int len); 1238 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, 1239 struct netlink_callback *cb, void *data, int len); 1240 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); 1241 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); 1242 1243 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) 1244 { 1245 #ifdef CONFIG_NL80211_TESTMODE 1246 enum mt76_testmode_state state = MT76_TM_STATE_IDLE; 1247 1248 if (disable || phy->test.state == MT76_TM_STATE_OFF) 1249 state = MT76_TM_STATE_OFF; 1250 1251 mt76_testmode_set_state(phy, state); 1252 #endif 1253 } 1254 1255 1256 /* internal */ 1257 static inline struct ieee80211_hw * 1258 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 1259 { 1260 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1261 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 1262 struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx); 1263 1264 info->hw_queue &= ~MT_TX_HW_QUEUE_PHY; 1265 1266 return hw; 1267 } 1268 1269 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1270 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 1271 struct napi_struct *napi); 1272 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 1273 struct napi_struct *napi); 1274 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 1275 void mt76_testmode_tx_pending(struct mt76_phy *phy); 1276 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, 1277 struct mt76_queue_entry *e); 1278 1279 /* usb */ 1280 static inline bool mt76u_urb_error(struct urb *urb) 1281 { 1282 return urb->status && 1283 urb->status != -ECONNRESET && 1284 urb->status != -ESHUTDOWN && 1285 urb->status != -ENOENT; 1286 } 1287 1288 /* Map hardware queues to usb endpoints */ 1289 static inline u8 q2ep(u8 qid) 1290 { 1291 /* TODO: take management packets to queue 5 */ 1292 return qid + 1; 1293 } 1294 1295 static inline int 1296 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 1297 int timeout, int ep) 1298 { 1299 #if defined(__FreeBSD__) && !defined(CONFIG_USB) 1300 return (0); 1301 #else 1302 struct usb_interface *uintf = to_usb_interface(dev->dev); 1303 struct usb_device *udev = interface_to_usbdev(uintf); 1304 struct mt76_usb *usb = &dev->usb; 1305 unsigned int pipe; 1306 1307 if (actual_len) 1308 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 1309 else 1310 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 1311 1312 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 1313 #endif 1314 } 1315 1316 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi, 1317 struct mt76_sta_stats *stats); 1318 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); 1319 int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type, 1320 u16 val, u16 offset, void *buf, size_t len); 1321 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 1322 u8 req_type, u16 val, u16 offset, 1323 void *buf, size_t len); 1324 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 1325 const u16 offset, const u32 val); 1326 void mt76u_read_copy(struct mt76_dev *dev, u32 offset, 1327 void *data, int len); 1328 u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr); 1329 void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type, 1330 u32 addr, u32 val); 1331 int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 1332 struct mt76_bus_ops *ops); 1333 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf); 1334 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 1335 int mt76u_alloc_queues(struct mt76_dev *dev); 1336 void mt76u_stop_tx(struct mt76_dev *dev); 1337 void mt76u_stop_rx(struct mt76_dev *dev); 1338 int mt76u_resume_rx(struct mt76_dev *dev); 1339 void mt76u_queues_deinit(struct mt76_dev *dev); 1340 1341 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, 1342 const struct mt76_bus_ops *bus_ops); 1343 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid); 1344 int mt76s_alloc_tx(struct mt76_dev *dev); 1345 void mt76s_deinit(struct mt76_dev *dev); 1346 void mt76s_sdio_irq(struct sdio_func *func); 1347 void mt76s_txrx_worker(struct mt76_sdio *sdio); 1348 bool mt76s_txqs_empty(struct mt76_dev *dev); 1349 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func, 1350 int hw_ver); 1351 u32 mt76s_rr(struct mt76_dev *dev, u32 offset); 1352 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val); 1353 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 1354 u32 mt76s_read_pcr(struct mt76_dev *dev); 1355 void mt76s_write_copy(struct mt76_dev *dev, u32 offset, 1356 const void *data, int len); 1357 void mt76s_read_copy(struct mt76_dev *dev, u32 offset, 1358 void *data, int len); 1359 int mt76s_wr_rp(struct mt76_dev *dev, u32 base, 1360 const struct mt76_reg_pair *data, 1361 int len); 1362 int mt76s_rd_rp(struct mt76_dev *dev, u32 base, 1363 struct mt76_reg_pair *data, int len); 1364 1365 struct sk_buff * 1366 __mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1367 int len, int data_len, gfp_t gfp); 1368 static inline struct sk_buff * 1369 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1370 int data_len) 1371 { 1372 return __mt76_mcu_msg_alloc(dev, data, data_len, data_len, GFP_KERNEL); 1373 } 1374 1375 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 1376 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 1377 unsigned long expires); 1378 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, 1379 int len, bool wait_resp, struct sk_buff **ret); 1380 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, 1381 int cmd, bool wait_resp, struct sk_buff **ret); 1382 #if defined(__linux__) 1383 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1384 #elif defined(__FreeBSD__) 1385 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const u8 *data, 1386 #endif 1387 int len, int max_len); 1388 static inline int 1389 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1390 int len) 1391 { 1392 int max_len = 4096 - dev->mcu_ops->headroom; 1393 1394 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len); 1395 } 1396 1397 static inline int 1398 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, 1399 bool wait_resp) 1400 { 1401 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); 1402 } 1403 1404 static inline int 1405 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, 1406 bool wait_resp) 1407 { 1408 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); 1409 } 1410 1411 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 1412 1413 s8 mt76_get_rate_power_limits(struct mt76_phy *phy, 1414 struct ieee80211_channel *chan, 1415 struct mt76_power_limits *dest, 1416 s8 target_power); 1417 1418 struct mt76_txwi_cache * 1419 mt76_token_release(struct mt76_dev *dev, int token, bool *wake); 1420 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi); 1421 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked); 1422 1423 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked) 1424 { 1425 spin_lock_bh(&dev->token_lock); 1426 __mt76_set_tx_blocked(dev, blocked); 1427 spin_unlock_bh(&dev->token_lock); 1428 } 1429 1430 static inline int 1431 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) 1432 { 1433 int token; 1434 1435 spin_lock_bh(&dev->token_lock); 1436 token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC); 1437 spin_unlock_bh(&dev->token_lock); 1438 1439 return token; 1440 } 1441 1442 static inline struct mt76_txwi_cache * 1443 mt76_token_put(struct mt76_dev *dev, int token) 1444 { 1445 struct mt76_txwi_cache *txwi; 1446 1447 spin_lock_bh(&dev->token_lock); 1448 txwi = idr_remove(&dev->token, token); 1449 spin_unlock_bh(&dev->token_lock); 1450 1451 return txwi; 1452 } 1453 1454 static inline void mt76_packet_id_init(struct mt76_wcid *wcid) 1455 { 1456 INIT_LIST_HEAD(&wcid->list); 1457 idr_init(&wcid->pktid); 1458 } 1459 1460 static inline void 1461 mt76_packet_id_flush(struct mt76_dev *dev, struct mt76_wcid *wcid) 1462 { 1463 struct sk_buff_head list; 1464 1465 mt76_tx_status_lock(dev, &list); 1466 mt76_tx_status_skb_get(dev, wcid, -1, &list); 1467 mt76_tx_status_unlock(dev, &list); 1468 1469 idr_destroy(&wcid->pktid); 1470 } 1471 1472 #endif 1473