1 /* SPDX-License-Identifier: ISC */ 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #ifndef __MT76_H 7 #define __MT76_H 8 9 #include <linux/kernel.h> 10 #include <linux/io.h> 11 #include <linux/spinlock.h> 12 #include <linux/skbuff.h> 13 #include <linux/leds.h> 14 #include <linux/usb.h> 15 #include <linux/average.h> 16 #include <linux/soc/mediatek/mtk_wed.h> 17 #if defined(__FreeBSD__) 18 #include <linux/wait.h> 19 #include <linux/bitfield.h> 20 #include <linux/debugfs.h> 21 #include <linux/pci.h> 22 #include <linux/interrupt.h> 23 #include <net/page_pool.h> 24 #endif 25 #include <net/mac80211.h> 26 #include "util.h" 27 #include "testmode.h" 28 29 #define MT_MCU_RING_SIZE 32 30 #define MT_RX_BUF_SIZE 2048 31 #define MT_SKB_HEAD_LEN 256 32 33 #define MT_MAX_NON_AQL_PKT 16 34 #define MT_TXQ_FREE_THR 32 35 36 #define MT76_TOKEN_FREE_THR 64 37 38 #define MT_QFLAG_WED_RING GENMASK(1, 0) 39 #define MT_QFLAG_WED_TYPE GENMASK(3, 2) 40 #define MT_QFLAG_WED BIT(4) 41 42 #define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ 43 FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ 44 FIELD_PREP(MT_QFLAG_WED_RING, _n)) 45 #define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n) 46 #define MT_WED_Q_RX(_n) __MT_WED_Q(MT76_WED_Q_RX, _n) 47 #define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0) 48 49 struct mt76_dev; 50 struct mt76_phy; 51 struct mt76_wcid; 52 struct mt76s_intr; 53 54 struct mt76_reg_pair { 55 u32 reg; 56 u32 value; 57 }; 58 59 enum mt76_bus_type { 60 MT76_BUS_MMIO, 61 MT76_BUS_USB, 62 MT76_BUS_SDIO, 63 }; 64 65 enum mt76_wed_type { 66 MT76_WED_Q_TX, 67 MT76_WED_Q_TXFREE, 68 MT76_WED_Q_RX, 69 }; 70 71 struct mt76_bus_ops { 72 u32 (*rr)(struct mt76_dev *dev, u32 offset); 73 void (*wr)(struct mt76_dev *dev, u32 offset, u32 val); 74 u32 (*rmw)(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 75 void (*write_copy)(struct mt76_dev *dev, u32 offset, const void *data, 76 int len); 77 void (*read_copy)(struct mt76_dev *dev, u32 offset, void *data, 78 int len); 79 int (*wr_rp)(struct mt76_dev *dev, u32 base, 80 const struct mt76_reg_pair *rp, int len); 81 int (*rd_rp)(struct mt76_dev *dev, u32 base, 82 struct mt76_reg_pair *rp, int len); 83 enum mt76_bus_type type; 84 }; 85 86 #define mt76_is_usb(dev) ((dev)->bus->type == MT76_BUS_USB) 87 #define mt76_is_mmio(dev) ((dev)->bus->type == MT76_BUS_MMIO) 88 #define mt76_is_sdio(dev) ((dev)->bus->type == MT76_BUS_SDIO) 89 90 enum mt76_txq_id { 91 MT_TXQ_VO = IEEE80211_AC_VO, 92 MT_TXQ_VI = IEEE80211_AC_VI, 93 MT_TXQ_BE = IEEE80211_AC_BE, 94 MT_TXQ_BK = IEEE80211_AC_BK, 95 MT_TXQ_PSD, 96 MT_TXQ_BEACON, 97 MT_TXQ_CAB, 98 __MT_TXQ_MAX 99 }; 100 101 enum mt76_mcuq_id { 102 MT_MCUQ_WM, 103 MT_MCUQ_WA, 104 MT_MCUQ_FWDL, 105 __MT_MCUQ_MAX 106 }; 107 108 enum mt76_rxq_id { 109 MT_RXQ_MAIN, 110 MT_RXQ_MCU, 111 MT_RXQ_MCU_WA, 112 MT_RXQ_BAND1, 113 MT_RXQ_BAND1_WA, 114 MT_RXQ_MAIN_WA, 115 MT_RXQ_BAND2, 116 MT_RXQ_BAND2_WA, 117 __MT_RXQ_MAX 118 }; 119 120 enum mt76_band_id { 121 MT_BAND0, 122 MT_BAND1, 123 MT_BAND2, 124 __MT_MAX_BAND 125 }; 126 127 enum mt76_cipher_type { 128 MT_CIPHER_NONE, 129 MT_CIPHER_WEP40, 130 MT_CIPHER_TKIP, 131 MT_CIPHER_TKIP_NO_MIC, 132 MT_CIPHER_AES_CCMP, 133 MT_CIPHER_WEP104, 134 MT_CIPHER_BIP_CMAC_128, 135 MT_CIPHER_WEP128, 136 MT_CIPHER_WAPI, 137 MT_CIPHER_CCMP_CCX, 138 MT_CIPHER_CCMP_256, 139 MT_CIPHER_GCMP, 140 MT_CIPHER_GCMP_256, 141 }; 142 143 enum mt76_dfs_state { 144 MT_DFS_STATE_UNKNOWN, 145 MT_DFS_STATE_DISABLED, 146 MT_DFS_STATE_CAC, 147 MT_DFS_STATE_ACTIVE, 148 }; 149 150 struct mt76_queue_buf { 151 dma_addr_t addr; 152 u16 len; 153 bool skip_unmap; 154 }; 155 156 struct mt76_tx_info { 157 struct mt76_queue_buf buf[32]; 158 struct sk_buff *skb; 159 int nbuf; 160 u32 info; 161 }; 162 163 struct mt76_queue_entry { 164 union { 165 void *buf; 166 struct sk_buff *skb; 167 }; 168 union { 169 struct mt76_txwi_cache *txwi; 170 struct urb *urb; 171 int buf_sz; 172 }; 173 u32 dma_addr[2]; 174 u16 dma_len[2]; 175 u16 wcid; 176 bool skip_buf0:1; 177 bool skip_buf1:1; 178 bool done:1; 179 }; 180 181 struct mt76_queue_regs { 182 u32 desc_base; 183 u32 ring_size; 184 u32 cpu_idx; 185 u32 dma_idx; 186 } __packed __aligned(4); 187 188 struct mt76_queue { 189 struct mt76_queue_regs __iomem *regs; 190 191 spinlock_t lock; 192 spinlock_t cleanup_lock; 193 struct mt76_queue_entry *entry; 194 struct mt76_desc *desc; 195 196 u16 first; 197 u16 head; 198 u16 tail; 199 int ndesc; 200 int queued; 201 int buf_size; 202 bool stopped; 203 bool blocked; 204 205 u8 buf_offset; 206 u8 hw_idx; 207 u8 flags; 208 209 u32 wed_regs; 210 211 dma_addr_t desc_dma; 212 struct sk_buff *rx_head; 213 struct page_pool *page_pool; 214 }; 215 216 struct mt76_mcu_ops { 217 u32 headroom; 218 u32 tailroom; 219 220 int (*mcu_send_msg)(struct mt76_dev *dev, int cmd, const void *data, 221 int len, bool wait_resp); 222 int (*mcu_skb_send_msg)(struct mt76_dev *dev, struct sk_buff *skb, 223 int cmd, int *seq); 224 int (*mcu_parse_response)(struct mt76_dev *dev, int cmd, 225 struct sk_buff *skb, int seq); 226 u32 (*mcu_rr)(struct mt76_dev *dev, u32 offset); 227 void (*mcu_wr)(struct mt76_dev *dev, u32 offset, u32 val); 228 int (*mcu_wr_rp)(struct mt76_dev *dev, u32 base, 229 const struct mt76_reg_pair *rp, int len); 230 int (*mcu_rd_rp)(struct mt76_dev *dev, u32 base, 231 struct mt76_reg_pair *rp, int len); 232 int (*mcu_restart)(struct mt76_dev *dev); 233 }; 234 235 struct mt76_queue_ops { 236 int (*init)(struct mt76_dev *dev, 237 int (*poll)(struct napi_struct *napi, int budget)); 238 239 int (*alloc)(struct mt76_dev *dev, struct mt76_queue *q, 240 int idx, int n_desc, int bufsize, 241 u32 ring_base); 242 243 int (*tx_queue_skb)(struct mt76_dev *dev, struct mt76_queue *q, 244 enum mt76_txq_id qid, struct sk_buff *skb, 245 struct mt76_wcid *wcid, struct ieee80211_sta *sta); 246 247 int (*tx_queue_skb_raw)(struct mt76_dev *dev, struct mt76_queue *q, 248 struct sk_buff *skb, u32 tx_info); 249 250 void *(*dequeue)(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 251 int *len, u32 *info, bool *more); 252 253 void (*rx_reset)(struct mt76_dev *dev, enum mt76_rxq_id qid); 254 255 void (*tx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q, 256 bool flush); 257 258 void (*rx_cleanup)(struct mt76_dev *dev, struct mt76_queue *q); 259 260 void (*kick)(struct mt76_dev *dev, struct mt76_queue *q); 261 262 void (*reset_q)(struct mt76_dev *dev, struct mt76_queue *q); 263 }; 264 265 enum mt76_phy_type { 266 MT_PHY_TYPE_CCK, 267 MT_PHY_TYPE_OFDM, 268 MT_PHY_TYPE_HT, 269 MT_PHY_TYPE_HT_GF, 270 MT_PHY_TYPE_VHT, 271 MT_PHY_TYPE_HE_SU = 8, 272 MT_PHY_TYPE_HE_EXT_SU, 273 MT_PHY_TYPE_HE_TB, 274 MT_PHY_TYPE_HE_MU, 275 MT_PHY_TYPE_EHT_SU = 13, 276 MT_PHY_TYPE_EHT_TRIG, 277 MT_PHY_TYPE_EHT_MU, 278 __MT_PHY_TYPE_MAX, 279 }; 280 281 struct mt76_sta_stats { 282 u64 tx_mode[__MT_PHY_TYPE_MAX]; 283 u64 tx_bw[5]; /* 20, 40, 80, 160, 320 */ 284 u64 tx_nss[4]; /* 1, 2, 3, 4 */ 285 u64 tx_mcs[16]; /* mcs idx */ 286 u64 tx_bytes; 287 /* WED TX */ 288 u32 tx_packets; /* unit: MSDU */ 289 u32 tx_retries; 290 u32 tx_failed; 291 /* WED RX */ 292 u64 rx_bytes; 293 u32 rx_packets; 294 u32 rx_errors; 295 u32 rx_drops; 296 }; 297 298 enum mt76_wcid_flags { 299 MT_WCID_FLAG_CHECK_PS, 300 MT_WCID_FLAG_PS, 301 MT_WCID_FLAG_4ADDR, 302 MT_WCID_FLAG_HDR_TRANS, 303 }; 304 305 #define MT76_N_WCIDS 1088 306 307 /* stored in ieee80211_tx_info::hw_queue */ 308 #define MT_TX_HW_QUEUE_PHY GENMASK(3, 2) 309 310 DECLARE_EWMA(signal, 10, 8); 311 312 #define MT_WCID_TX_INFO_RATE GENMASK(15, 0) 313 #define MT_WCID_TX_INFO_NSS GENMASK(17, 16) 314 #define MT_WCID_TX_INFO_TXPWR_ADJ GENMASK(25, 18) 315 #define MT_WCID_TX_INFO_SET BIT(31) 316 317 struct mt76_wcid { 318 struct mt76_rx_tid __rcu *aggr[IEEE80211_NUM_TIDS]; 319 320 atomic_t non_aql_packets; 321 unsigned long flags; 322 323 struct ewma_signal rssi; 324 int inactive_count; 325 326 struct rate_info rate; 327 unsigned long ampdu_state; 328 329 u16 idx; 330 u8 hw_key_idx; 331 u8 hw_key_idx2; 332 333 u8 sta:1; 334 u8 amsdu:1; 335 u8 phy_idx:2; 336 337 u8 rx_check_pn; 338 u8 rx_key_pn[IEEE80211_NUM_TIDS + 1][6]; 339 u16 cipher; 340 341 u32 tx_info; 342 bool sw_iv; 343 344 struct list_head list; 345 struct idr pktid; 346 347 struct mt76_sta_stats stats; 348 349 struct list_head poll_list; 350 }; 351 352 struct mt76_txq { 353 u16 wcid; 354 355 u16 agg_ssn; 356 bool send_bar; 357 bool aggr; 358 }; 359 360 struct mt76_txwi_cache { 361 struct list_head list; 362 dma_addr_t dma_addr; 363 364 union { 365 struct sk_buff *skb; 366 void *ptr; 367 }; 368 }; 369 370 struct mt76_rx_tid { 371 struct rcu_head rcu_head; 372 373 struct mt76_dev *dev; 374 375 spinlock_t lock; 376 struct delayed_work reorder_work; 377 378 u16 head; 379 u16 size; 380 u16 nframes; 381 382 u8 num; 383 384 u8 started:1, stopped:1, timer_pending:1; 385 386 struct sk_buff *reorder_buf[]; 387 }; 388 389 #define MT_TX_CB_DMA_DONE BIT(0) 390 #define MT_TX_CB_TXS_DONE BIT(1) 391 #define MT_TX_CB_TXS_FAILED BIT(2) 392 393 #define MT_PACKET_ID_MASK GENMASK(6, 0) 394 #define MT_PACKET_ID_NO_ACK 0 395 #define MT_PACKET_ID_NO_SKB 1 396 #define MT_PACKET_ID_WED 2 397 #define MT_PACKET_ID_FIRST 3 398 #define MT_PACKET_ID_HAS_RATE BIT(7) 399 /* This is timer for when to give up when waiting for TXS callback, 400 * with starting time being the time at which the DMA_DONE callback 401 * was seen (so, we know packet was processed then, it should not take 402 * long after that for firmware to send the TXS callback if it is going 403 * to do so.) 404 */ 405 #define MT_TX_STATUS_SKB_TIMEOUT (HZ / 4) 406 407 struct mt76_tx_cb { 408 unsigned long jiffies; 409 u16 wcid; 410 u8 pktid; 411 u8 flags; 412 }; 413 414 enum { 415 MT76_STATE_INITIALIZED, 416 MT76_STATE_REGISTERED, 417 MT76_STATE_RUNNING, 418 MT76_STATE_MCU_RUNNING, 419 MT76_SCANNING, 420 MT76_HW_SCANNING, 421 MT76_HW_SCHED_SCANNING, 422 MT76_RESTART, 423 MT76_RESET, 424 MT76_MCU_RESET, 425 MT76_REMOVED, 426 MT76_READING_STATS, 427 MT76_STATE_POWER_OFF, 428 MT76_STATE_SUSPEND, 429 MT76_STATE_ROC, 430 MT76_STATE_PM, 431 MT76_STATE_WED_RESET, 432 }; 433 434 struct mt76_hw_cap { 435 bool has_2ghz; 436 bool has_5ghz; 437 bool has_6ghz; 438 }; 439 440 #define MT_DRV_TXWI_NO_FREE BIT(0) 441 #define MT_DRV_TX_ALIGNED4_SKBS BIT(1) 442 #define MT_DRV_SW_RX_AIRTIME BIT(2) 443 #define MT_DRV_RX_DMA_HDR BIT(3) 444 #define MT_DRV_HW_MGMT_TXQ BIT(4) 445 #define MT_DRV_AMSDU_OFFLOAD BIT(5) 446 447 struct mt76_driver_ops { 448 u32 drv_flags; 449 u32 survey_flags; 450 u16 txwi_size; 451 u16 token_size; 452 u8 mcs_rates; 453 454 void (*update_survey)(struct mt76_phy *phy); 455 456 int (*tx_prepare_skb)(struct mt76_dev *dev, void *txwi_ptr, 457 enum mt76_txq_id qid, struct mt76_wcid *wcid, 458 struct ieee80211_sta *sta, 459 struct mt76_tx_info *tx_info); 460 461 void (*tx_complete_skb)(struct mt76_dev *dev, 462 struct mt76_queue_entry *e); 463 464 bool (*tx_status_data)(struct mt76_dev *dev, u8 *update); 465 466 bool (*rx_check)(struct mt76_dev *dev, void *data, int len); 467 468 void (*rx_skb)(struct mt76_dev *dev, enum mt76_rxq_id q, 469 struct sk_buff *skb, u32 *info); 470 471 void (*rx_poll_complete)(struct mt76_dev *dev, enum mt76_rxq_id q); 472 473 void (*sta_ps)(struct mt76_dev *dev, struct ieee80211_sta *sta, 474 bool ps); 475 476 int (*sta_add)(struct mt76_dev *dev, struct ieee80211_vif *vif, 477 struct ieee80211_sta *sta); 478 479 void (*sta_assoc)(struct mt76_dev *dev, struct ieee80211_vif *vif, 480 struct ieee80211_sta *sta); 481 482 void (*sta_remove)(struct mt76_dev *dev, struct ieee80211_vif *vif, 483 struct ieee80211_sta *sta); 484 }; 485 486 struct mt76_channel_state { 487 u64 cc_active; 488 u64 cc_busy; 489 u64 cc_rx; 490 u64 cc_bss_rx; 491 u64 cc_tx; 492 493 s8 noise; 494 }; 495 496 struct mt76_sband { 497 struct ieee80211_supported_band sband; 498 struct mt76_channel_state *chan; 499 }; 500 501 /* addr req mask */ 502 #define MT_VEND_TYPE_EEPROM BIT(31) 503 #define MT_VEND_TYPE_CFG BIT(30) 504 #define MT_VEND_TYPE_MASK (MT_VEND_TYPE_EEPROM | MT_VEND_TYPE_CFG) 505 506 #define MT_VEND_ADDR(type, n) (MT_VEND_TYPE_##type | (n)) 507 enum mt_vendor_req { 508 MT_VEND_DEV_MODE = 0x1, 509 MT_VEND_WRITE = 0x2, 510 MT_VEND_POWER_ON = 0x4, 511 MT_VEND_MULTI_WRITE = 0x6, 512 MT_VEND_MULTI_READ = 0x7, 513 MT_VEND_READ_EEPROM = 0x9, 514 MT_VEND_WRITE_FCE = 0x42, 515 MT_VEND_WRITE_CFG = 0x46, 516 MT_VEND_READ_CFG = 0x47, 517 MT_VEND_READ_EXT = 0x63, 518 MT_VEND_WRITE_EXT = 0x66, 519 MT_VEND_FEATURE_SET = 0x91, 520 }; 521 522 enum mt76u_in_ep { 523 MT_EP_IN_PKT_RX, 524 MT_EP_IN_CMD_RESP, 525 __MT_EP_IN_MAX, 526 }; 527 528 enum mt76u_out_ep { 529 MT_EP_OUT_INBAND_CMD, 530 MT_EP_OUT_AC_BE, 531 MT_EP_OUT_AC_BK, 532 MT_EP_OUT_AC_VI, 533 MT_EP_OUT_AC_VO, 534 MT_EP_OUT_HCCA, 535 __MT_EP_OUT_MAX, 536 }; 537 538 struct mt76_mcu { 539 struct mutex mutex; 540 u32 msg_seq; 541 int timeout; 542 543 struct sk_buff_head res_q; 544 wait_queue_head_t wait; 545 }; 546 547 #define MT_TX_SG_MAX_SIZE 8 548 #define MT_RX_SG_MAX_SIZE 4 549 #define MT_NUM_TX_ENTRIES 256 550 #define MT_NUM_RX_ENTRIES 128 551 #define MCU_RESP_URB_SIZE 1024 552 struct mt76_usb { 553 struct mutex usb_ctrl_mtx; 554 u8 *data; 555 u16 data_len; 556 557 struct mt76_worker status_worker; 558 struct mt76_worker rx_worker; 559 560 struct work_struct stat_work; 561 562 u8 out_ep[__MT_EP_OUT_MAX]; 563 u8 in_ep[__MT_EP_IN_MAX]; 564 bool sg_en; 565 566 struct mt76u_mcu { 567 u8 *data; 568 /* multiple reads */ 569 struct mt76_reg_pair *rp; 570 int rp_len; 571 u32 base; 572 } mcu; 573 }; 574 575 #define MT76S_XMIT_BUF_SZ 0x3fe00 576 #define MT76S_NUM_TX_ENTRIES 256 577 #define MT76S_NUM_RX_ENTRIES 512 578 struct mt76_sdio { 579 struct mt76_worker txrx_worker; 580 struct mt76_worker status_worker; 581 struct mt76_worker net_worker; 582 583 struct work_struct stat_work; 584 585 u8 *xmit_buf; 586 u32 xmit_buf_sz; 587 588 struct sdio_func *func; 589 void *intr_data; 590 u8 hw_ver; 591 wait_queue_head_t wait; 592 593 struct { 594 int pse_data_quota; 595 int ple_data_quota; 596 int pse_mcu_quota; 597 int pse_page_size; 598 int deficit; 599 } sched; 600 601 int (*parse_irq)(struct mt76_dev *dev, struct mt76s_intr *intr); 602 }; 603 604 struct mt76_mmio { 605 void __iomem *regs; 606 spinlock_t irq_lock; 607 u32 irqmask; 608 609 struct mtk_wed_device wed; 610 struct completion wed_reset; 611 struct completion wed_reset_complete; 612 }; 613 614 struct mt76_rx_status { 615 union { 616 struct mt76_wcid *wcid; 617 u16 wcid_idx; 618 }; 619 620 u32 reorder_time; 621 622 u32 ampdu_ref; 623 u32 timestamp; 624 625 u8 iv[6]; 626 627 u8 phy_idx:2; 628 u8 aggr:1; 629 u8 qos_ctl; 630 u16 seqno; 631 632 u16 freq; 633 u32 flag; 634 u8 enc_flags; 635 u8 encoding:3, bw:4; 636 union { 637 struct { 638 u8 he_ru:3; 639 u8 he_gi:2; 640 u8 he_dcm:1; 641 }; 642 struct { 643 u8 ru:4; 644 u8 gi:2; 645 } eht; 646 }; 647 648 u8 amsdu:1, first_amsdu:1, last_amsdu:1; 649 u8 rate_idx; 650 u8 nss:5, band:3; 651 s8 signal; 652 u8 chains; 653 s8 chain_signal[IEEE80211_MAX_CHAINS]; 654 }; 655 656 struct mt76_freq_range_power { 657 const struct cfg80211_sar_freq_ranges *range; 658 s8 power; 659 }; 660 661 struct mt76_testmode_ops { 662 int (*set_state)(struct mt76_phy *phy, enum mt76_testmode_state state); 663 int (*set_params)(struct mt76_phy *phy, struct nlattr **tb, 664 enum mt76_testmode_state new_state); 665 int (*dump_stats)(struct mt76_phy *phy, struct sk_buff *msg); 666 }; 667 668 struct mt76_testmode_data { 669 enum mt76_testmode_state state; 670 671 u32 param_set[DIV_ROUND_UP(NUM_MT76_TM_ATTRS, 32)]; 672 struct sk_buff *tx_skb; 673 674 u32 tx_count; 675 u16 tx_mpdu_len; 676 677 u8 tx_rate_mode; 678 u8 tx_rate_idx; 679 u8 tx_rate_nss; 680 u8 tx_rate_sgi; 681 u8 tx_rate_ldpc; 682 u8 tx_rate_stbc; 683 u8 tx_ltf; 684 685 u8 tx_antenna_mask; 686 u8 tx_spe_idx; 687 688 u8 tx_duty_cycle; 689 u32 tx_time; 690 u32 tx_ipg; 691 692 u32 freq_offset; 693 694 u8 tx_power[4]; 695 u8 tx_power_control; 696 697 u8 addr[3][ETH_ALEN]; 698 699 u32 tx_pending; 700 u32 tx_queued; 701 u16 tx_queued_limit; 702 u32 tx_done; 703 struct { 704 u64 packets[__MT_RXQ_MAX]; 705 u64 fcs_error[__MT_RXQ_MAX]; 706 } rx_stats; 707 }; 708 709 struct mt76_vif { 710 u8 idx; 711 u8 omac_idx; 712 u8 band_idx; 713 u8 wmm_idx; 714 u8 scan_seq_num; 715 u8 cipher; 716 u8 basic_rates_idx; 717 u8 mcast_rates_idx; 718 u8 beacon_rates_idx; 719 }; 720 721 struct mt76_phy { 722 struct ieee80211_hw *hw; 723 struct mt76_dev *dev; 724 void *priv; 725 726 unsigned long state; 727 u8 band_idx; 728 729 struct mt76_queue *q_tx[__MT_TXQ_MAX]; 730 731 struct cfg80211_chan_def chandef; 732 struct ieee80211_channel *main_chan; 733 734 struct mt76_channel_state *chan_state; 735 enum mt76_dfs_state dfs_state; 736 ktime_t survey_time; 737 738 u32 aggr_stats[32]; 739 740 struct mt76_hw_cap cap; 741 struct mt76_sband sband_2g; 742 struct mt76_sband sband_5g; 743 struct mt76_sband sband_6g; 744 745 u8 macaddr[ETH_ALEN]; 746 747 int txpower_cur; 748 u8 antenna_mask; 749 u16 chainmask; 750 751 #ifdef CONFIG_NL80211_TESTMODE 752 struct mt76_testmode_data test; 753 #endif 754 755 struct delayed_work mac_work; 756 u8 mac_work_count; 757 758 struct { 759 struct sk_buff *head; 760 struct sk_buff **tail; 761 u16 seqno; 762 } rx_amsdu[__MT_RXQ_MAX]; 763 764 struct mt76_freq_range_power *frp; 765 766 struct { 767 struct led_classdev cdev; 768 char name[32]; 769 bool al; 770 u8 pin; 771 } leds; 772 }; 773 774 struct mt76_dev { 775 struct mt76_phy phy; /* must be first */ 776 struct mt76_phy *phys[__MT_MAX_BAND]; 777 778 struct ieee80211_hw *hw; 779 780 spinlock_t wed_lock; 781 spinlock_t lock; 782 spinlock_t cc_lock; 783 784 u32 cur_cc_bss_rx; 785 786 struct mt76_rx_status rx_ampdu_status; 787 u32 rx_ampdu_len; 788 u32 rx_ampdu_ref; 789 790 struct mutex mutex; 791 792 const struct mt76_bus_ops *bus; 793 const struct mt76_driver_ops *drv; 794 const struct mt76_mcu_ops *mcu_ops; 795 struct device *dev; 796 struct device *dma_dev; 797 798 struct mt76_mcu mcu; 799 800 struct net_device napi_dev; 801 struct net_device tx_napi_dev; 802 spinlock_t rx_lock; 803 struct napi_struct napi[__MT_RXQ_MAX]; 804 struct sk_buff_head rx_skb[__MT_RXQ_MAX]; 805 struct tasklet_struct irq_tasklet; 806 807 struct list_head txwi_cache; 808 struct list_head rxwi_cache; 809 struct mt76_queue *q_mcu[__MT_MCUQ_MAX]; 810 struct mt76_queue q_rx[__MT_RXQ_MAX]; 811 const struct mt76_queue_ops *queue_ops; 812 int tx_dma_idx[4]; 813 814 struct mt76_worker tx_worker; 815 struct napi_struct tx_napi; 816 817 spinlock_t token_lock; 818 struct idr token; 819 u16 wed_token_count; 820 u16 token_count; 821 u16 token_size; 822 823 spinlock_t rx_token_lock; 824 struct idr rx_token; 825 u16 rx_token_size; 826 827 wait_queue_head_t tx_wait; 828 /* spinclock used to protect wcid pktid linked list */ 829 spinlock_t status_lock; 830 831 u32 wcid_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 832 u32 wcid_phy_mask[DIV_ROUND_UP(MT76_N_WCIDS, 32)]; 833 834 u64 vif_mask; 835 836 struct mt76_wcid global_wcid; 837 struct mt76_wcid __rcu *wcid[MT76_N_WCIDS]; 838 struct list_head wcid_list; 839 840 struct list_head sta_poll_list; 841 spinlock_t sta_poll_lock; 842 843 u32 rev; 844 845 struct tasklet_struct pre_tbtt_tasklet; 846 int beacon_int; 847 u8 beacon_mask; 848 849 struct debugfs_blob_wrapper eeprom; 850 struct debugfs_blob_wrapper otp; 851 852 char alpha2[3]; 853 enum nl80211_dfs_regions region; 854 855 u32 debugfs_reg; 856 857 u8 csa_complete; 858 859 u32 rxfilter; 860 861 #ifdef CONFIG_NL80211_TESTMODE 862 const struct mt76_testmode_ops *test_ops; 863 struct { 864 const char *name; 865 u32 offset; 866 } test_mtd; 867 #endif 868 struct workqueue_struct *wq; 869 870 union { 871 struct mt76_mmio mmio; 872 struct mt76_usb usb; 873 struct mt76_sdio sdio; 874 }; 875 }; 876 877 /* per-phy stats. */ 878 struct mt76_mib_stats { 879 u32 ack_fail_cnt; 880 u32 fcs_err_cnt; 881 u32 rts_cnt; 882 u32 rts_retries_cnt; 883 u32 ba_miss_cnt; 884 u32 tx_bf_cnt; 885 u32 tx_mu_bf_cnt; 886 u32 tx_mu_mpdu_cnt; 887 u32 tx_mu_acked_mpdu_cnt; 888 u32 tx_su_acked_mpdu_cnt; 889 u32 tx_bf_ibf_ppdu_cnt; 890 u32 tx_bf_ebf_ppdu_cnt; 891 892 u32 tx_bf_rx_fb_all_cnt; 893 u32 tx_bf_rx_fb_eht_cnt; 894 u32 tx_bf_rx_fb_he_cnt; 895 u32 tx_bf_rx_fb_vht_cnt; 896 u32 tx_bf_rx_fb_ht_cnt; 897 898 u32 tx_bf_rx_fb_bw; /* value of last sample, not cumulative */ 899 u32 tx_bf_rx_fb_nc_cnt; 900 u32 tx_bf_rx_fb_nr_cnt; 901 u32 tx_bf_fb_cpl_cnt; 902 u32 tx_bf_fb_trig_cnt; 903 904 u32 tx_ampdu_cnt; 905 u32 tx_stop_q_empty_cnt; 906 u32 tx_mpdu_attempts_cnt; 907 u32 tx_mpdu_success_cnt; 908 u32 tx_pkt_ebf_cnt; 909 u32 tx_pkt_ibf_cnt; 910 911 u32 tx_rwp_fail_cnt; 912 u32 tx_rwp_need_cnt; 913 914 /* rx stats */ 915 u32 rx_fifo_full_cnt; 916 u32 channel_idle_cnt; 917 u32 primary_cca_busy_time; 918 u32 secondary_cca_busy_time; 919 u32 primary_energy_detect_time; 920 u32 cck_mdrdy_time; 921 u32 ofdm_mdrdy_time; 922 u32 green_mdrdy_time; 923 u32 rx_vector_mismatch_cnt; 924 u32 rx_delimiter_fail_cnt; 925 u32 rx_mrdy_cnt; 926 u32 rx_len_mismatch_cnt; 927 u32 rx_mpdu_cnt; 928 u32 rx_ampdu_cnt; 929 u32 rx_ampdu_bytes_cnt; 930 u32 rx_ampdu_valid_subframe_cnt; 931 u32 rx_ampdu_valid_subframe_bytes_cnt; 932 u32 rx_pfdrop_cnt; 933 u32 rx_vec_queue_overflow_drop_cnt; 934 u32 rx_ba_cnt; 935 936 u32 tx_amsdu[8]; 937 u32 tx_amsdu_cnt; 938 939 /* mcu_muru_stats */ 940 u32 dl_cck_cnt; 941 u32 dl_ofdm_cnt; 942 u32 dl_htmix_cnt; 943 u32 dl_htgf_cnt; 944 u32 dl_vht_su_cnt; 945 u32 dl_vht_2mu_cnt; 946 u32 dl_vht_3mu_cnt; 947 u32 dl_vht_4mu_cnt; 948 u32 dl_he_su_cnt; 949 u32 dl_he_ext_su_cnt; 950 u32 dl_he_2ru_cnt; 951 u32 dl_he_2mu_cnt; 952 u32 dl_he_3ru_cnt; 953 u32 dl_he_3mu_cnt; 954 u32 dl_he_4ru_cnt; 955 u32 dl_he_4mu_cnt; 956 u32 dl_he_5to8ru_cnt; 957 u32 dl_he_9to16ru_cnt; 958 u32 dl_he_gtr16ru_cnt; 959 960 u32 ul_hetrig_su_cnt; 961 u32 ul_hetrig_2ru_cnt; 962 u32 ul_hetrig_3ru_cnt; 963 u32 ul_hetrig_4ru_cnt; 964 u32 ul_hetrig_5to8ru_cnt; 965 u32 ul_hetrig_9to16ru_cnt; 966 u32 ul_hetrig_gtr16ru_cnt; 967 u32 ul_hetrig_2mu_cnt; 968 u32 ul_hetrig_3mu_cnt; 969 u32 ul_hetrig_4mu_cnt; 970 }; 971 972 struct mt76_power_limits { 973 s8 cck[4]; 974 s8 ofdm[8]; 975 s8 mcs[4][10]; 976 s8 ru[7][12]; 977 }; 978 979 struct mt76_ethtool_worker_info { 980 u64 *data; 981 int idx; 982 int initial_stat_idx; 983 int worker_stat_count; 984 int sta_count; 985 }; 986 987 #define CCK_RATE(_idx, _rate) { \ 988 .bitrate = _rate, \ 989 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \ 990 .hw_value = (MT_PHY_TYPE_CCK << 8) | (_idx), \ 991 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (4 + _idx), \ 992 } 993 994 #define OFDM_RATE(_idx, _rate) { \ 995 .bitrate = _rate, \ 996 .hw_value = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 997 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | (_idx), \ 998 } 999 1000 extern struct ieee80211_rate mt76_rates[12]; 1001 1002 #define __mt76_rr(dev, ...) (dev)->bus->rr((dev), __VA_ARGS__) 1003 #define __mt76_wr(dev, ...) (dev)->bus->wr((dev), __VA_ARGS__) 1004 #define __mt76_rmw(dev, ...) (dev)->bus->rmw((dev), __VA_ARGS__) 1005 #define __mt76_wr_copy(dev, ...) (dev)->bus->write_copy((dev), __VA_ARGS__) 1006 #define __mt76_rr_copy(dev, ...) (dev)->bus->read_copy((dev), __VA_ARGS__) 1007 1008 #define __mt76_set(dev, offset, val) __mt76_rmw(dev, offset, 0, val) 1009 #define __mt76_clear(dev, offset, val) __mt76_rmw(dev, offset, val, 0) 1010 1011 #define mt76_rr(dev, ...) (dev)->mt76.bus->rr(&((dev)->mt76), __VA_ARGS__) 1012 #define mt76_wr(dev, ...) (dev)->mt76.bus->wr(&((dev)->mt76), __VA_ARGS__) 1013 #define mt76_rmw(dev, ...) (dev)->mt76.bus->rmw(&((dev)->mt76), __VA_ARGS__) 1014 #define mt76_wr_copy(dev, ...) (dev)->mt76.bus->write_copy(&((dev)->mt76), __VA_ARGS__) 1015 #define mt76_rr_copy(dev, ...) (dev)->mt76.bus->read_copy(&((dev)->mt76), __VA_ARGS__) 1016 #define mt76_wr_rp(dev, ...) (dev)->mt76.bus->wr_rp(&((dev)->mt76), __VA_ARGS__) 1017 #define mt76_rd_rp(dev, ...) (dev)->mt76.bus->rd_rp(&((dev)->mt76), __VA_ARGS__) 1018 1019 1020 #define mt76_mcu_restart(dev, ...) (dev)->mt76.mcu_ops->mcu_restart(&((dev)->mt76)) 1021 1022 #define mt76_set(dev, offset, val) mt76_rmw(dev, offset, 0, val) 1023 #define mt76_clear(dev, offset, val) mt76_rmw(dev, offset, val, 0) 1024 1025 #define mt76_get_field(_dev, _reg, _field) \ 1026 FIELD_GET(_field, mt76_rr(dev, _reg)) 1027 1028 #define mt76_rmw_field(_dev, _reg, _field, _val) \ 1029 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 1030 1031 #define __mt76_rmw_field(_dev, _reg, _field, _val) \ 1032 __mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val)) 1033 1034 #define mt76_hw(dev) (dev)->mphy.hw 1035 1036 bool __mt76_poll(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 1037 int timeout); 1038 1039 #define mt76_poll(dev, ...) __mt76_poll(&((dev)->mt76), __VA_ARGS__) 1040 1041 bool ____mt76_poll_msec(struct mt76_dev *dev, u32 offset, u32 mask, u32 val, 1042 int timeout, int kick); 1043 #define __mt76_poll_msec(...) ____mt76_poll_msec(__VA_ARGS__, 10) 1044 #define mt76_poll_msec(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__, 10) 1045 #define mt76_poll_msec_tick(dev, ...) ____mt76_poll_msec(&((dev)->mt76), __VA_ARGS__) 1046 1047 void mt76_mmio_init(struct mt76_dev *dev, void __iomem *regs); 1048 void mt76_pci_disable_aspm(struct pci_dev *pdev); 1049 1050 static inline u16 mt76_chip(struct mt76_dev *dev) 1051 { 1052 return dev->rev >> 16; 1053 } 1054 1055 static inline u16 mt76_rev(struct mt76_dev *dev) 1056 { 1057 return dev->rev & 0xffff; 1058 } 1059 1060 #define mt76xx_chip(dev) mt76_chip(&((dev)->mt76)) 1061 #define mt76xx_rev(dev) mt76_rev(&((dev)->mt76)) 1062 1063 #define mt76_init_queues(dev, ...) (dev)->mt76.queue_ops->init(&((dev)->mt76), __VA_ARGS__) 1064 #define mt76_queue_alloc(dev, ...) (dev)->mt76.queue_ops->alloc(&((dev)->mt76), __VA_ARGS__) 1065 #define mt76_tx_queue_skb_raw(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb_raw(&((dev)->mt76), __VA_ARGS__) 1066 #define mt76_tx_queue_skb(dev, ...) (dev)->mt76.queue_ops->tx_queue_skb(&((dev)->mt76), __VA_ARGS__) 1067 #define mt76_queue_rx_reset(dev, ...) (dev)->mt76.queue_ops->rx_reset(&((dev)->mt76), __VA_ARGS__) 1068 #define mt76_queue_tx_cleanup(dev, ...) (dev)->mt76.queue_ops->tx_cleanup(&((dev)->mt76), __VA_ARGS__) 1069 #define mt76_queue_rx_cleanup(dev, ...) (dev)->mt76.queue_ops->rx_cleanup(&((dev)->mt76), __VA_ARGS__) 1070 #define mt76_queue_kick(dev, ...) (dev)->mt76.queue_ops->kick(&((dev)->mt76), __VA_ARGS__) 1071 #define mt76_queue_reset(dev, ...) (dev)->mt76.queue_ops->reset_q(&((dev)->mt76), __VA_ARGS__) 1072 1073 #define mt76_for_each_q_rx(dev, i) \ 1074 for (i = 0; i < ARRAY_SIZE((dev)->q_rx); i++) \ 1075 if ((dev)->q_rx[i].ndesc) 1076 1077 struct mt76_dev *mt76_alloc_device(struct device *pdev, unsigned int size, 1078 const struct ieee80211_ops *ops, 1079 const struct mt76_driver_ops *drv_ops); 1080 int mt76_register_device(struct mt76_dev *dev, bool vht, 1081 struct ieee80211_rate *rates, int n_rates); 1082 void mt76_unregister_device(struct mt76_dev *dev); 1083 void mt76_free_device(struct mt76_dev *dev); 1084 void mt76_unregister_phy(struct mt76_phy *phy); 1085 1086 struct mt76_phy *mt76_alloc_phy(struct mt76_dev *dev, unsigned int size, 1087 const struct ieee80211_ops *ops, 1088 u8 band_idx); 1089 int mt76_register_phy(struct mt76_phy *phy, bool vht, 1090 struct ieee80211_rate *rates, int n_rates); 1091 1092 struct dentry *mt76_register_debugfs_fops(struct mt76_phy *phy, 1093 const struct file_operations *ops); 1094 static inline struct dentry *mt76_register_debugfs(struct mt76_dev *dev) 1095 { 1096 return mt76_register_debugfs_fops(&dev->phy, NULL); 1097 } 1098 1099 int mt76_queues_read(struct seq_file *s, void *data); 1100 void mt76_seq_puts_array(struct seq_file *file, const char *str, 1101 s8 *val, int len); 1102 1103 int mt76_eeprom_init(struct mt76_dev *dev, int len); 1104 void mt76_eeprom_override(struct mt76_phy *phy); 1105 int mt76_get_of_eeprom(struct mt76_dev *dev, void *data, int offset, int len); 1106 1107 struct mt76_queue * 1108 mt76_init_queue(struct mt76_dev *dev, int qid, int idx, int n_desc, 1109 int ring_base, u32 flags); 1110 u16 mt76_calculate_default_rate(struct mt76_phy *phy, int rateidx); 1111 static inline int mt76_init_tx_queue(struct mt76_phy *phy, int qid, int idx, 1112 int n_desc, int ring_base, u32 flags) 1113 { 1114 struct mt76_queue *q; 1115 1116 q = mt76_init_queue(phy->dev, qid, idx, n_desc, ring_base, flags); 1117 if (IS_ERR(q)) 1118 return PTR_ERR(q); 1119 1120 phy->q_tx[qid] = q; 1121 1122 return 0; 1123 } 1124 1125 static inline int mt76_init_mcu_queue(struct mt76_dev *dev, int qid, int idx, 1126 int n_desc, int ring_base) 1127 { 1128 struct mt76_queue *q; 1129 1130 q = mt76_init_queue(dev, qid, idx, n_desc, ring_base, 0); 1131 if (IS_ERR(q)) 1132 return PTR_ERR(q); 1133 1134 dev->q_mcu[qid] = q; 1135 1136 return 0; 1137 } 1138 1139 static inline struct mt76_phy * 1140 mt76_dev_phy(struct mt76_dev *dev, u8 phy_idx) 1141 { 1142 if ((phy_idx == MT_BAND1 && dev->phys[phy_idx]) || 1143 (phy_idx == MT_BAND2 && dev->phys[phy_idx])) 1144 return dev->phys[phy_idx]; 1145 1146 return &dev->phy; 1147 } 1148 1149 static inline struct ieee80211_hw * 1150 mt76_phy_hw(struct mt76_dev *dev, u8 phy_idx) 1151 { 1152 return mt76_dev_phy(dev, phy_idx)->hw; 1153 } 1154 1155 static inline u8 * 1156 mt76_get_txwi_ptr(struct mt76_dev *dev, struct mt76_txwi_cache *t) 1157 { 1158 return (u8 *)t - dev->drv->txwi_size; 1159 } 1160 1161 /* increment with wrap-around */ 1162 static inline int mt76_incr(int val, int size) 1163 { 1164 return (val + 1) & (size - 1); 1165 } 1166 1167 /* decrement with wrap-around */ 1168 static inline int mt76_decr(int val, int size) 1169 { 1170 return (val - 1) & (size - 1); 1171 } 1172 1173 u8 mt76_ac_to_hwq(u8 ac); 1174 1175 static inline struct ieee80211_txq * 1176 mtxq_to_txq(struct mt76_txq *mtxq) 1177 { 1178 void *ptr = mtxq; 1179 1180 return container_of(ptr, struct ieee80211_txq, drv_priv); 1181 } 1182 1183 static inline struct ieee80211_sta * 1184 wcid_to_sta(struct mt76_wcid *wcid) 1185 { 1186 void *ptr = wcid; 1187 1188 if (!wcid || !wcid->sta) 1189 return NULL; 1190 1191 return container_of(ptr, struct ieee80211_sta, drv_priv); 1192 } 1193 1194 static inline struct mt76_tx_cb *mt76_tx_skb_cb(struct sk_buff *skb) 1195 { 1196 BUILD_BUG_ON(sizeof(struct mt76_tx_cb) > 1197 sizeof(IEEE80211_SKB_CB(skb)->status.status_driver_data)); 1198 return ((void *)IEEE80211_SKB_CB(skb)->status.status_driver_data); 1199 } 1200 1201 static inline void *mt76_skb_get_hdr(struct sk_buff *skb) 1202 { 1203 struct mt76_rx_status mstat; 1204 u8 *data = skb->data; 1205 1206 /* Alignment concerns */ 1207 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he) % 4); 1208 BUILD_BUG_ON(sizeof(struct ieee80211_radiotap_he_mu) % 4); 1209 1210 mstat = *((struct mt76_rx_status *)skb->cb); 1211 1212 if (mstat.flag & RX_FLAG_RADIOTAP_HE) 1213 data += sizeof(struct ieee80211_radiotap_he); 1214 if (mstat.flag & RX_FLAG_RADIOTAP_HE_MU) 1215 data += sizeof(struct ieee80211_radiotap_he_mu); 1216 1217 return data; 1218 } 1219 1220 static inline void mt76_insert_hdr_pad(struct sk_buff *skb) 1221 { 1222 int len = ieee80211_get_hdrlen_from_skb(skb); 1223 1224 if (len % 4 == 0) 1225 return; 1226 1227 skb_push(skb, 2); 1228 memmove(skb->data, skb->data + 2, len); 1229 1230 skb->data[len] = 0; 1231 skb->data[len + 1] = 0; 1232 } 1233 1234 static inline bool mt76_is_skb_pktid(u8 pktid) 1235 { 1236 if (pktid & MT_PACKET_ID_HAS_RATE) 1237 return false; 1238 1239 return pktid >= MT_PACKET_ID_FIRST; 1240 } 1241 1242 static inline u8 mt76_tx_power_nss_delta(u8 nss) 1243 { 1244 static const u8 nss_delta[4] = { 0, 6, 9, 12 }; 1245 u8 idx = nss - 1; 1246 1247 return (idx < ARRAY_SIZE(nss_delta)) ? nss_delta[idx] : 0; 1248 } 1249 1250 static inline bool mt76_testmode_enabled(struct mt76_phy *phy) 1251 { 1252 #ifdef CONFIG_NL80211_TESTMODE 1253 return phy->test.state != MT76_TM_STATE_OFF; 1254 #else 1255 return false; 1256 #endif 1257 } 1258 1259 static inline bool mt76_is_testmode_skb(struct mt76_dev *dev, 1260 struct sk_buff *skb, 1261 struct ieee80211_hw **hw) 1262 { 1263 #ifdef CONFIG_NL80211_TESTMODE 1264 int i; 1265 1266 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) { 1267 struct mt76_phy *phy = dev->phys[i]; 1268 1269 if (phy && skb == phy->test.tx_skb) { 1270 *hw = dev->phys[i]->hw; 1271 return true; 1272 } 1273 } 1274 return false; 1275 #else 1276 return false; 1277 #endif 1278 } 1279 1280 void mt76_rx(struct mt76_dev *dev, enum mt76_rxq_id q, struct sk_buff *skb); 1281 void mt76_tx(struct mt76_phy *dev, struct ieee80211_sta *sta, 1282 struct mt76_wcid *wcid, struct sk_buff *skb); 1283 void mt76_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *txq); 1284 void mt76_stop_tx_queues(struct mt76_phy *phy, struct ieee80211_sta *sta, 1285 bool send_bar); 1286 void mt76_tx_check_agg_ssn(struct ieee80211_sta *sta, struct sk_buff *skb); 1287 void mt76_txq_schedule(struct mt76_phy *phy, enum mt76_txq_id qid); 1288 void mt76_txq_schedule_all(struct mt76_phy *phy); 1289 void mt76_tx_worker_run(struct mt76_dev *dev); 1290 void mt76_tx_worker(struct mt76_worker *w); 1291 void mt76_release_buffered_frames(struct ieee80211_hw *hw, 1292 struct ieee80211_sta *sta, 1293 u16 tids, int nframes, 1294 enum ieee80211_frame_release_type reason, 1295 bool more_data); 1296 bool mt76_has_tx_pending(struct mt76_phy *phy); 1297 void mt76_set_channel(struct mt76_phy *phy); 1298 void mt76_update_survey(struct mt76_phy *phy); 1299 void mt76_update_survey_active_time(struct mt76_phy *phy, ktime_t time); 1300 int mt76_get_survey(struct ieee80211_hw *hw, int idx, 1301 struct survey_info *survey); 1302 int mt76_rx_signal(u8 chain_mask, s8 *chain_signal); 1303 void mt76_set_stream_caps(struct mt76_phy *phy, bool vht); 1304 1305 int mt76_rx_aggr_start(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid, 1306 u16 ssn, u16 size); 1307 void mt76_rx_aggr_stop(struct mt76_dev *dev, struct mt76_wcid *wcid, u8 tid); 1308 1309 void mt76_wcid_key_setup(struct mt76_dev *dev, struct mt76_wcid *wcid, 1310 struct ieee80211_key_conf *key); 1311 1312 void mt76_tx_status_lock(struct mt76_dev *dev, struct sk_buff_head *list) 1313 __acquires(&dev->status_lock); 1314 void mt76_tx_status_unlock(struct mt76_dev *dev, struct sk_buff_head *list) 1315 __releases(&dev->status_lock); 1316 1317 int mt76_tx_status_skb_add(struct mt76_dev *dev, struct mt76_wcid *wcid, 1318 struct sk_buff *skb); 1319 struct sk_buff *mt76_tx_status_skb_get(struct mt76_dev *dev, 1320 struct mt76_wcid *wcid, int pktid, 1321 struct sk_buff_head *list); 1322 void mt76_tx_status_skb_done(struct mt76_dev *dev, struct sk_buff *skb, 1323 struct sk_buff_head *list); 1324 void __mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb, 1325 struct list_head *free_list); 1326 static inline void 1327 mt76_tx_complete_skb(struct mt76_dev *dev, u16 wcid, struct sk_buff *skb) 1328 { 1329 __mt76_tx_complete_skb(dev, wcid, skb, NULL); 1330 } 1331 1332 void mt76_tx_status_check(struct mt76_dev *dev, bool flush); 1333 int mt76_sta_state(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1334 struct ieee80211_sta *sta, 1335 enum ieee80211_sta_state old_state, 1336 enum ieee80211_sta_state new_state); 1337 void __mt76_sta_remove(struct mt76_dev *dev, struct ieee80211_vif *vif, 1338 struct ieee80211_sta *sta); 1339 void mt76_sta_pre_rcu_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1340 struct ieee80211_sta *sta); 1341 1342 int mt76_get_min_avg_rssi(struct mt76_dev *dev, bool ext_phy); 1343 1344 int mt76_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1345 int *dbm); 1346 int mt76_init_sar_power(struct ieee80211_hw *hw, 1347 const struct cfg80211_sar_specs *sar); 1348 int mt76_get_sar_power(struct mt76_phy *phy, 1349 struct ieee80211_channel *chan, 1350 int power); 1351 1352 void mt76_csa_check(struct mt76_dev *dev); 1353 void mt76_csa_finish(struct mt76_dev *dev); 1354 1355 int mt76_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant); 1356 int mt76_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set); 1357 void mt76_insert_ccmp_hdr(struct sk_buff *skb, u8 key_id); 1358 int mt76_get_rate(struct mt76_dev *dev, 1359 struct ieee80211_supported_band *sband, 1360 int idx, bool cck); 1361 void mt76_sw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1362 const u8 *mac); 1363 void mt76_sw_scan_complete(struct ieee80211_hw *hw, 1364 struct ieee80211_vif *vif); 1365 enum mt76_dfs_state mt76_phy_dfs_state(struct mt76_phy *phy); 1366 int mt76_testmode_cmd(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 1367 void *data, int len); 1368 int mt76_testmode_dump(struct ieee80211_hw *hw, struct sk_buff *skb, 1369 struct netlink_callback *cb, void *data, int len); 1370 int mt76_testmode_set_state(struct mt76_phy *phy, enum mt76_testmode_state state); 1371 int mt76_testmode_alloc_skb(struct mt76_phy *phy, u32 len); 1372 1373 static inline void mt76_testmode_reset(struct mt76_phy *phy, bool disable) 1374 { 1375 #ifdef CONFIG_NL80211_TESTMODE 1376 enum mt76_testmode_state state = MT76_TM_STATE_IDLE; 1377 1378 if (disable || phy->test.state == MT76_TM_STATE_OFF) 1379 state = MT76_TM_STATE_OFF; 1380 1381 mt76_testmode_set_state(phy, state); 1382 #endif 1383 } 1384 1385 1386 /* internal */ 1387 static inline struct ieee80211_hw * 1388 mt76_tx_status_get_hw(struct mt76_dev *dev, struct sk_buff *skb) 1389 { 1390 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1391 u8 phy_idx = (info->hw_queue & MT_TX_HW_QUEUE_PHY) >> 2; 1392 struct ieee80211_hw *hw = mt76_phy_hw(dev, phy_idx); 1393 1394 info->hw_queue &= ~MT_TX_HW_QUEUE_PHY; 1395 1396 return hw; 1397 } 1398 1399 void mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1400 void mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t); 1401 struct mt76_txwi_cache *mt76_get_rxwi(struct mt76_dev *dev); 1402 void mt76_free_pending_rxwi(struct mt76_dev *dev); 1403 void mt76_rx_complete(struct mt76_dev *dev, struct sk_buff_head *frames, 1404 struct napi_struct *napi); 1405 void mt76_rx_poll_complete(struct mt76_dev *dev, enum mt76_rxq_id q, 1406 struct napi_struct *napi); 1407 void mt76_rx_aggr_reorder(struct sk_buff *skb, struct sk_buff_head *frames); 1408 void mt76_testmode_tx_pending(struct mt76_phy *phy); 1409 void mt76_queue_tx_complete(struct mt76_dev *dev, struct mt76_queue *q, 1410 struct mt76_queue_entry *e); 1411 1412 /* usb */ 1413 static inline bool mt76u_urb_error(struct urb *urb) 1414 { 1415 return urb->status && 1416 urb->status != -ECONNRESET && 1417 urb->status != -ESHUTDOWN && 1418 urb->status != -ENOENT; 1419 } 1420 1421 /* Map hardware queues to usb endpoints */ 1422 static inline u8 q2ep(u8 qid) 1423 { 1424 /* TODO: take management packets to queue 5 */ 1425 return qid + 1; 1426 } 1427 1428 static inline int 1429 mt76u_bulk_msg(struct mt76_dev *dev, void *data, int len, int *actual_len, 1430 int timeout, int ep) 1431 { 1432 #if defined(__FreeBSD__) && !defined(CONFIG_USB) 1433 return (0); 1434 #else 1435 struct usb_interface *uintf = to_usb_interface(dev->dev); 1436 struct usb_device *udev = interface_to_usbdev(uintf); 1437 struct mt76_usb *usb = &dev->usb; 1438 unsigned int pipe; 1439 1440 if (actual_len) 1441 pipe = usb_rcvbulkpipe(udev, usb->in_ep[ep]); 1442 else 1443 pipe = usb_sndbulkpipe(udev, usb->out_ep[ep]); 1444 1445 return usb_bulk_msg(udev, pipe, data, len, actual_len, timeout); 1446 #endif 1447 } 1448 1449 void mt76_ethtool_page_pool_stats(struct mt76_dev *dev, u64 *data, int *index); 1450 void mt76_ethtool_worker(struct mt76_ethtool_worker_info *wi, 1451 struct mt76_sta_stats *stats, bool eht); 1452 int mt76_skb_adjust_pad(struct sk_buff *skb, int pad); 1453 int __mt76u_vendor_request(struct mt76_dev *dev, u8 req, u8 req_type, 1454 u16 val, u16 offset, void *buf, size_t len); 1455 int mt76u_vendor_request(struct mt76_dev *dev, u8 req, 1456 u8 req_type, u16 val, u16 offset, 1457 void *buf, size_t len); 1458 void mt76u_single_wr(struct mt76_dev *dev, const u8 req, 1459 const u16 offset, const u32 val); 1460 void mt76u_read_copy(struct mt76_dev *dev, u32 offset, 1461 void *data, int len); 1462 u32 ___mt76u_rr(struct mt76_dev *dev, u8 req, u8 req_type, u32 addr); 1463 void ___mt76u_wr(struct mt76_dev *dev, u8 req, u8 req_type, 1464 u32 addr, u32 val); 1465 int __mt76u_init(struct mt76_dev *dev, struct usb_interface *intf, 1466 struct mt76_bus_ops *ops); 1467 int mt76u_init(struct mt76_dev *dev, struct usb_interface *intf); 1468 int mt76u_alloc_mcu_queue(struct mt76_dev *dev); 1469 int mt76u_alloc_queues(struct mt76_dev *dev); 1470 void mt76u_stop_tx(struct mt76_dev *dev); 1471 void mt76u_stop_rx(struct mt76_dev *dev); 1472 int mt76u_resume_rx(struct mt76_dev *dev); 1473 void mt76u_queues_deinit(struct mt76_dev *dev); 1474 1475 int mt76s_init(struct mt76_dev *dev, struct sdio_func *func, 1476 const struct mt76_bus_ops *bus_ops); 1477 int mt76s_alloc_rx_queue(struct mt76_dev *dev, enum mt76_rxq_id qid); 1478 int mt76s_alloc_tx(struct mt76_dev *dev); 1479 void mt76s_deinit(struct mt76_dev *dev); 1480 void mt76s_sdio_irq(struct sdio_func *func); 1481 void mt76s_txrx_worker(struct mt76_sdio *sdio); 1482 bool mt76s_txqs_empty(struct mt76_dev *dev); 1483 int mt76s_hw_init(struct mt76_dev *dev, struct sdio_func *func, 1484 int hw_ver); 1485 u32 mt76s_rr(struct mt76_dev *dev, u32 offset); 1486 void mt76s_wr(struct mt76_dev *dev, u32 offset, u32 val); 1487 u32 mt76s_rmw(struct mt76_dev *dev, u32 offset, u32 mask, u32 val); 1488 u32 mt76s_read_pcr(struct mt76_dev *dev); 1489 void mt76s_write_copy(struct mt76_dev *dev, u32 offset, 1490 const void *data, int len); 1491 void mt76s_read_copy(struct mt76_dev *dev, u32 offset, 1492 void *data, int len); 1493 int mt76s_wr_rp(struct mt76_dev *dev, u32 base, 1494 const struct mt76_reg_pair *data, 1495 int len); 1496 int mt76s_rd_rp(struct mt76_dev *dev, u32 base, 1497 struct mt76_reg_pair *data, int len); 1498 1499 struct sk_buff * 1500 __mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1501 int len, int data_len, gfp_t gfp); 1502 static inline struct sk_buff * 1503 mt76_mcu_msg_alloc(struct mt76_dev *dev, const void *data, 1504 int data_len) 1505 { 1506 return __mt76_mcu_msg_alloc(dev, data, data_len, data_len, GFP_KERNEL); 1507 } 1508 1509 void mt76_mcu_rx_event(struct mt76_dev *dev, struct sk_buff *skb); 1510 struct sk_buff *mt76_mcu_get_response(struct mt76_dev *dev, 1511 unsigned long expires); 1512 int mt76_mcu_send_and_get_msg(struct mt76_dev *dev, int cmd, const void *data, 1513 int len, bool wait_resp, struct sk_buff **ret); 1514 int mt76_mcu_skb_send_and_get_msg(struct mt76_dev *dev, struct sk_buff *skb, 1515 int cmd, bool wait_resp, struct sk_buff **ret); 1516 #if defined(__linux__) 1517 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1518 #elif defined(__FreeBSD__) 1519 int __mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const u8 *data, 1520 #endif 1521 int len, int max_len); 1522 static inline int 1523 mt76_mcu_send_firmware(struct mt76_dev *dev, int cmd, const void *data, 1524 int len) 1525 { 1526 int max_len = 4096 - dev->mcu_ops->headroom; 1527 1528 return __mt76_mcu_send_firmware(dev, cmd, data, len, max_len); 1529 } 1530 1531 static inline int 1532 mt76_mcu_send_msg(struct mt76_dev *dev, int cmd, const void *data, int len, 1533 bool wait_resp) 1534 { 1535 return mt76_mcu_send_and_get_msg(dev, cmd, data, len, wait_resp, NULL); 1536 } 1537 1538 static inline int 1539 mt76_mcu_skb_send_msg(struct mt76_dev *dev, struct sk_buff *skb, int cmd, 1540 bool wait_resp) 1541 { 1542 return mt76_mcu_skb_send_and_get_msg(dev, skb, cmd, wait_resp, NULL); 1543 } 1544 1545 void mt76_set_irq_mask(struct mt76_dev *dev, u32 addr, u32 clear, u32 set); 1546 1547 s8 mt76_get_rate_power_limits(struct mt76_phy *phy, 1548 struct ieee80211_channel *chan, 1549 struct mt76_power_limits *dest, 1550 s8 target_power); 1551 1552 static inline bool mt76_queue_is_wed_rx(struct mt76_queue *q) 1553 { 1554 return (q->flags & MT_QFLAG_WED) && 1555 FIELD_GET(MT_QFLAG_WED_TYPE, q->flags) == MT76_WED_Q_RX; 1556 } 1557 1558 struct mt76_txwi_cache * 1559 mt76_token_release(struct mt76_dev *dev, int token, bool *wake); 1560 int mt76_token_consume(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi); 1561 void __mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked); 1562 struct mt76_txwi_cache *mt76_rx_token_release(struct mt76_dev *dev, int token); 1563 int mt76_rx_token_consume(struct mt76_dev *dev, void *ptr, 1564 struct mt76_txwi_cache *r, dma_addr_t phys); 1565 int mt76_create_page_pool(struct mt76_dev *dev, struct mt76_queue *q); 1566 static inline void mt76_put_page_pool_buf(void *buf, bool allow_direct) 1567 { 1568 struct page *page = virt_to_head_page(buf); 1569 1570 page_pool_put_full_page(page->pp, page, allow_direct); 1571 } 1572 1573 static inline void * 1574 mt76_get_page_pool_buf(struct mt76_queue *q, u32 *offset, u32 size) 1575 { 1576 struct page *page; 1577 1578 page = page_pool_dev_alloc_frag(q->page_pool, offset, size); 1579 if (!page) 1580 return NULL; 1581 1582 #if defined(__linux__) 1583 return page_address(page) + *offset; 1584 #elif defined(__FreeBSD__) 1585 return (void *)((uintptr_t)page_address(page) + *offset); 1586 #endif 1587 } 1588 1589 static inline void mt76_set_tx_blocked(struct mt76_dev *dev, bool blocked) 1590 { 1591 spin_lock_bh(&dev->token_lock); 1592 __mt76_set_tx_blocked(dev, blocked); 1593 spin_unlock_bh(&dev->token_lock); 1594 } 1595 1596 static inline int 1597 mt76_token_get(struct mt76_dev *dev, struct mt76_txwi_cache **ptxwi) 1598 { 1599 int token; 1600 1601 spin_lock_bh(&dev->token_lock); 1602 token = idr_alloc(&dev->token, *ptxwi, 0, dev->token_size, GFP_ATOMIC); 1603 spin_unlock_bh(&dev->token_lock); 1604 1605 return token; 1606 } 1607 1608 static inline struct mt76_txwi_cache * 1609 mt76_token_put(struct mt76_dev *dev, int token) 1610 { 1611 struct mt76_txwi_cache *txwi; 1612 1613 spin_lock_bh(&dev->token_lock); 1614 txwi = idr_remove(&dev->token, token); 1615 spin_unlock_bh(&dev->token_lock); 1616 1617 return txwi; 1618 } 1619 1620 static inline void mt76_packet_id_init(struct mt76_wcid *wcid) 1621 { 1622 INIT_LIST_HEAD(&wcid->list); 1623 idr_init(&wcid->pktid); 1624 } 1625 1626 static inline void 1627 mt76_packet_id_flush(struct mt76_dev *dev, struct mt76_wcid *wcid) 1628 { 1629 struct sk_buff_head list; 1630 1631 mt76_tx_status_lock(dev, &list); 1632 mt76_tx_status_skb_get(dev, wcid, -1, &list); 1633 mt76_tx_status_unlock(dev, &list); 1634 1635 idr_destroy(&wcid->pktid); 1636 } 1637 1638 #endif 1639