1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #include <linux/dma-mapping.h> 7 #if defined(__FreeBSD__) 8 #include <linux/cache.h> 9 #include <net/page_pool.h> 10 #endif 11 #include "mt76.h" 12 #include "dma.h" 13 14 #if IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED) 15 16 #define Q_READ(_dev, _q, _field) ({ \ 17 u32 _offset = offsetof(struct mt76_queue_regs, _field); \ 18 u32 _val; \ 19 if ((_q)->flags & MT_QFLAG_WED) \ 20 _val = mtk_wed_device_reg_read(&(_dev)->mmio.wed, \ 21 ((_q)->wed_regs + \ 22 _offset)); \ 23 else \ 24 _val = readl(&(_q)->regs->_field); \ 25 _val; \ 26 }) 27 28 #define Q_WRITE(_dev, _q, _field, _val) do { \ 29 u32 _offset = offsetof(struct mt76_queue_regs, _field); \ 30 if ((_q)->flags & MT_QFLAG_WED) \ 31 mtk_wed_device_reg_write(&(_dev)->mmio.wed, \ 32 ((_q)->wed_regs + _offset), \ 33 _val); \ 34 else \ 35 writel(_val, &(_q)->regs->_field); \ 36 } while (0) 37 38 #else 39 40 #define Q_READ(_dev, _q, _field) readl(&(_q)->regs->_field) 41 #define Q_WRITE(_dev, _q, _field, _val) writel(_val, &(_q)->regs->_field) 42 43 #endif 44 45 static struct mt76_txwi_cache * 46 mt76_alloc_txwi(struct mt76_dev *dev) 47 { 48 struct mt76_txwi_cache *t; 49 dma_addr_t addr; 50 u8 *txwi; 51 int size; 52 53 size = L1_CACHE_ALIGN(dev->drv->txwi_size + sizeof(*t)); 54 txwi = kzalloc(size, GFP_ATOMIC); 55 if (!txwi) 56 return NULL; 57 58 addr = dma_map_single(dev->dma_dev, txwi, dev->drv->txwi_size, 59 DMA_TO_DEVICE); 60 t = (struct mt76_txwi_cache *)(txwi + dev->drv->txwi_size); 61 t->dma_addr = addr; 62 63 return t; 64 } 65 66 static struct mt76_txwi_cache * 67 mt76_alloc_rxwi(struct mt76_dev *dev) 68 { 69 struct mt76_txwi_cache *t; 70 71 t = kzalloc(L1_CACHE_ALIGN(sizeof(*t)), GFP_ATOMIC); 72 if (!t) 73 return NULL; 74 75 t->ptr = NULL; 76 return t; 77 } 78 79 static struct mt76_txwi_cache * 80 __mt76_get_txwi(struct mt76_dev *dev) 81 { 82 struct mt76_txwi_cache *t = NULL; 83 84 spin_lock(&dev->lock); 85 if (!list_empty(&dev->txwi_cache)) { 86 t = list_first_entry(&dev->txwi_cache, struct mt76_txwi_cache, 87 list); 88 list_del(&t->list); 89 } 90 spin_unlock(&dev->lock); 91 92 return t; 93 } 94 95 static struct mt76_txwi_cache * 96 __mt76_get_rxwi(struct mt76_dev *dev) 97 { 98 struct mt76_txwi_cache *t = NULL; 99 100 spin_lock(&dev->wed_lock); 101 if (!list_empty(&dev->rxwi_cache)) { 102 t = list_first_entry(&dev->rxwi_cache, struct mt76_txwi_cache, 103 list); 104 list_del(&t->list); 105 } 106 spin_unlock(&dev->wed_lock); 107 108 return t; 109 } 110 111 static struct mt76_txwi_cache * 112 mt76_get_txwi(struct mt76_dev *dev) 113 { 114 struct mt76_txwi_cache *t = __mt76_get_txwi(dev); 115 116 if (t) 117 return t; 118 119 return mt76_alloc_txwi(dev); 120 } 121 122 struct mt76_txwi_cache * 123 mt76_get_rxwi(struct mt76_dev *dev) 124 { 125 struct mt76_txwi_cache *t = __mt76_get_rxwi(dev); 126 127 if (t) 128 return t; 129 130 return mt76_alloc_rxwi(dev); 131 } 132 EXPORT_SYMBOL_GPL(mt76_get_rxwi); 133 134 void 135 mt76_put_txwi(struct mt76_dev *dev, struct mt76_txwi_cache *t) 136 { 137 if (!t) 138 return; 139 140 spin_lock(&dev->lock); 141 list_add(&t->list, &dev->txwi_cache); 142 spin_unlock(&dev->lock); 143 } 144 EXPORT_SYMBOL_GPL(mt76_put_txwi); 145 146 void 147 mt76_put_rxwi(struct mt76_dev *dev, struct mt76_txwi_cache *t) 148 { 149 if (!t) 150 return; 151 152 spin_lock(&dev->wed_lock); 153 list_add(&t->list, &dev->rxwi_cache); 154 spin_unlock(&dev->wed_lock); 155 } 156 EXPORT_SYMBOL_GPL(mt76_put_rxwi); 157 158 static void 159 mt76_free_pending_txwi(struct mt76_dev *dev) 160 { 161 struct mt76_txwi_cache *t; 162 163 local_bh_disable(); 164 while ((t = __mt76_get_txwi(dev)) != NULL) { 165 dma_unmap_single(dev->dma_dev, t->dma_addr, dev->drv->txwi_size, 166 DMA_TO_DEVICE); 167 kfree(mt76_get_txwi_ptr(dev, t)); 168 } 169 local_bh_enable(); 170 } 171 172 void 173 mt76_free_pending_rxwi(struct mt76_dev *dev) 174 { 175 struct mt76_txwi_cache *t; 176 177 local_bh_disable(); 178 while ((t = __mt76_get_rxwi(dev)) != NULL) { 179 if (t->ptr) 180 mt76_put_page_pool_buf(t->ptr, false); 181 kfree(t); 182 } 183 local_bh_enable(); 184 } 185 EXPORT_SYMBOL_GPL(mt76_free_pending_rxwi); 186 187 static void 188 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q) 189 { 190 Q_WRITE(dev, q, desc_base, q->desc_dma); 191 Q_WRITE(dev, q, ring_size, q->ndesc); 192 q->head = Q_READ(dev, q, dma_idx); 193 q->tail = q->head; 194 } 195 196 static void 197 mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q) 198 { 199 int i; 200 201 if (!q || !q->ndesc) 202 return; 203 204 /* clear descriptors */ 205 for (i = 0; i < q->ndesc; i++) 206 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE); 207 208 Q_WRITE(dev, q, cpu_idx, 0); 209 Q_WRITE(dev, q, dma_idx, 0); 210 mt76_dma_sync_idx(dev, q); 211 } 212 213 static int 214 mt76_dma_add_rx_buf(struct mt76_dev *dev, struct mt76_queue *q, 215 struct mt76_queue_buf *buf, void *data) 216 { 217 struct mt76_desc *desc = &q->desc[q->head]; 218 struct mt76_queue_entry *entry = &q->entry[q->head]; 219 struct mt76_txwi_cache *txwi = NULL; 220 u32 buf1 = 0, ctrl; 221 int idx = q->head; 222 int rx_token; 223 224 ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len); 225 226 if (mt76_queue_is_wed_rx(q)) { 227 txwi = mt76_get_rxwi(dev); 228 if (!txwi) 229 return -ENOMEM; 230 231 rx_token = mt76_rx_token_consume(dev, data, txwi, buf->addr); 232 if (rx_token < 0) { 233 mt76_put_rxwi(dev, txwi); 234 return -ENOMEM; 235 } 236 237 buf1 |= FIELD_PREP(MT_DMA_CTL_TOKEN, rx_token); 238 ctrl |= MT_DMA_CTL_TO_HOST; 239 } 240 241 WRITE_ONCE(desc->buf0, cpu_to_le32(buf->addr)); 242 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1)); 243 WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl)); 244 WRITE_ONCE(desc->info, 0); 245 246 entry->dma_addr[0] = buf->addr; 247 entry->dma_len[0] = buf->len; 248 entry->txwi = txwi; 249 entry->buf = data; 250 entry->wcid = 0xffff; 251 entry->skip_buf1 = true; 252 q->head = (q->head + 1) % q->ndesc; 253 q->queued++; 254 255 return idx; 256 } 257 258 static int 259 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q, 260 struct mt76_queue_buf *buf, int nbufs, u32 info, 261 struct sk_buff *skb, void *txwi) 262 { 263 struct mt76_queue_entry *entry; 264 struct mt76_desc *desc; 265 int i, idx = -1; 266 u32 ctrl, next; 267 268 if (txwi) { 269 q->entry[q->head].txwi = DMA_DUMMY_DATA; 270 q->entry[q->head].skip_buf0 = true; 271 } 272 273 for (i = 0; i < nbufs; i += 2, buf += 2) { 274 u32 buf0 = buf[0].addr, buf1 = 0; 275 276 idx = q->head; 277 next = (q->head + 1) % q->ndesc; 278 279 desc = &q->desc[idx]; 280 entry = &q->entry[idx]; 281 282 if (buf[0].skip_unmap) 283 entry->skip_buf0 = true; 284 entry->skip_buf1 = i == nbufs - 1; 285 286 entry->dma_addr[0] = buf[0].addr; 287 entry->dma_len[0] = buf[0].len; 288 289 ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len); 290 if (i < nbufs - 1) { 291 entry->dma_addr[1] = buf[1].addr; 292 entry->dma_len[1] = buf[1].len; 293 buf1 = buf[1].addr; 294 ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len); 295 if (buf[1].skip_unmap) 296 entry->skip_buf1 = true; 297 } 298 299 if (i == nbufs - 1) 300 ctrl |= MT_DMA_CTL_LAST_SEC0; 301 else if (i == nbufs - 2) 302 ctrl |= MT_DMA_CTL_LAST_SEC1; 303 304 WRITE_ONCE(desc->buf0, cpu_to_le32(buf0)); 305 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1)); 306 WRITE_ONCE(desc->info, cpu_to_le32(info)); 307 WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl)); 308 309 q->head = next; 310 q->queued++; 311 } 312 313 q->entry[idx].txwi = txwi; 314 q->entry[idx].skb = skb; 315 q->entry[idx].wcid = 0xffff; 316 317 return idx; 318 } 319 320 static void 321 mt76_dma_tx_cleanup_idx(struct mt76_dev *dev, struct mt76_queue *q, int idx, 322 struct mt76_queue_entry *prev_e) 323 { 324 struct mt76_queue_entry *e = &q->entry[idx]; 325 326 if (!e->skip_buf0) 327 dma_unmap_single(dev->dma_dev, e->dma_addr[0], e->dma_len[0], 328 DMA_TO_DEVICE); 329 330 if (!e->skip_buf1) 331 dma_unmap_single(dev->dma_dev, e->dma_addr[1], e->dma_len[1], 332 DMA_TO_DEVICE); 333 334 if (e->txwi == DMA_DUMMY_DATA) 335 e->txwi = NULL; 336 337 if (e->skb == DMA_DUMMY_DATA) 338 e->skb = NULL; 339 340 *prev_e = *e; 341 memset(e, 0, sizeof(*e)); 342 } 343 344 static void 345 mt76_dma_kick_queue(struct mt76_dev *dev, struct mt76_queue *q) 346 { 347 wmb(); 348 Q_WRITE(dev, q, cpu_idx, q->head); 349 } 350 351 static void 352 mt76_dma_tx_cleanup(struct mt76_dev *dev, struct mt76_queue *q, bool flush) 353 { 354 struct mt76_queue_entry entry; 355 int last; 356 357 if (!q || !q->ndesc) 358 return; 359 360 spin_lock_bh(&q->cleanup_lock); 361 if (flush) 362 last = -1; 363 else 364 last = Q_READ(dev, q, dma_idx); 365 366 while (q->queued > 0 && q->tail != last) { 367 mt76_dma_tx_cleanup_idx(dev, q, q->tail, &entry); 368 mt76_queue_tx_complete(dev, q, &entry); 369 370 if (entry.txwi) { 371 if (!(dev->drv->drv_flags & MT_DRV_TXWI_NO_FREE)) 372 mt76_put_txwi(dev, entry.txwi); 373 } 374 375 if (!flush && q->tail == last) 376 last = Q_READ(dev, q, dma_idx); 377 } 378 spin_unlock_bh(&q->cleanup_lock); 379 380 if (flush) { 381 spin_lock_bh(&q->lock); 382 mt76_dma_sync_idx(dev, q); 383 mt76_dma_kick_queue(dev, q); 384 spin_unlock_bh(&q->lock); 385 } 386 387 if (!q->queued) 388 wake_up(&dev->tx_wait); 389 } 390 391 static void * 392 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx, 393 int *len, u32 *info, bool *more, bool *drop) 394 { 395 struct mt76_queue_entry *e = &q->entry[idx]; 396 struct mt76_desc *desc = &q->desc[idx]; 397 void *buf; 398 399 if (len) { 400 u32 ctrl = le32_to_cpu(READ_ONCE(desc->ctrl)); 401 *len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctrl); 402 *more = !(ctrl & MT_DMA_CTL_LAST_SEC0); 403 } 404 405 if (info) 406 *info = le32_to_cpu(desc->info); 407 408 if (mt76_queue_is_wed_rx(q)) { 409 u32 buf1 = le32_to_cpu(desc->buf1); 410 u32 token = FIELD_GET(MT_DMA_CTL_TOKEN, buf1); 411 struct mt76_txwi_cache *t = mt76_rx_token_release(dev, token); 412 413 if (!t) 414 return NULL; 415 416 dma_sync_single_for_cpu(dev->dma_dev, t->dma_addr, 417 SKB_WITH_OVERHEAD(q->buf_size), 418 page_pool_get_dma_dir(q->page_pool)); 419 420 buf = t->ptr; 421 t->dma_addr = 0; 422 t->ptr = NULL; 423 424 mt76_put_rxwi(dev, t); 425 426 if (drop) { 427 u32 ctrl = le32_to_cpu(READ_ONCE(desc->ctrl)); 428 429 *drop = !!(ctrl & (MT_DMA_CTL_TO_HOST_A | 430 MT_DMA_CTL_DROP)); 431 432 *drop |= !!(buf1 & MT_DMA_CTL_WO_DROP); 433 } 434 } else { 435 buf = e->buf; 436 e->buf = NULL; 437 dma_sync_single_for_cpu(dev->dma_dev, e->dma_addr[0], 438 SKB_WITH_OVERHEAD(q->buf_size), 439 page_pool_get_dma_dir(q->page_pool)); 440 } 441 442 return buf; 443 } 444 445 static void * 446 mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 447 int *len, u32 *info, bool *more, bool *drop) 448 { 449 int idx = q->tail; 450 451 *more = false; 452 if (!q->queued) 453 return NULL; 454 455 if (flush) 456 q->desc[idx].ctrl |= cpu_to_le32(MT_DMA_CTL_DMA_DONE); 457 else if (!(q->desc[idx].ctrl & cpu_to_le32(MT_DMA_CTL_DMA_DONE))) 458 return NULL; 459 460 q->tail = (q->tail + 1) % q->ndesc; 461 q->queued--; 462 463 return mt76_dma_get_buf(dev, q, idx, len, info, more, drop); 464 } 465 466 static int 467 mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, struct mt76_queue *q, 468 struct sk_buff *skb, u32 tx_info) 469 { 470 struct mt76_queue_buf buf = {}; 471 dma_addr_t addr; 472 473 if (test_bit(MT76_MCU_RESET, &dev->phy.state)) 474 goto error; 475 476 if (q->queued + 1 >= q->ndesc - 1) 477 goto error; 478 479 addr = dma_map_single(dev->dma_dev, skb->data, skb->len, 480 DMA_TO_DEVICE); 481 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) 482 goto error; 483 484 buf.addr = addr; 485 buf.len = skb->len; 486 487 spin_lock_bh(&q->lock); 488 mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL); 489 mt76_dma_kick_queue(dev, q); 490 spin_unlock_bh(&q->lock); 491 492 return 0; 493 494 error: 495 dev_kfree_skb(skb); 496 return -ENOMEM; 497 } 498 499 static int 500 mt76_dma_tx_queue_skb(struct mt76_dev *dev, struct mt76_queue *q, 501 enum mt76_txq_id qid, struct sk_buff *skb, 502 struct mt76_wcid *wcid, struct ieee80211_sta *sta) 503 { 504 struct ieee80211_tx_status status = { 505 .sta = sta, 506 }; 507 struct mt76_tx_info tx_info = { 508 .skb = skb, 509 }; 510 struct ieee80211_hw *hw; 511 int len, n = 0, ret = -ENOMEM; 512 struct mt76_txwi_cache *t; 513 struct sk_buff *iter; 514 dma_addr_t addr; 515 u8 *txwi; 516 517 if (test_bit(MT76_RESET, &dev->phy.state)) 518 goto free_skb; 519 520 t = mt76_get_txwi(dev); 521 if (!t) 522 goto free_skb; 523 524 txwi = mt76_get_txwi_ptr(dev, t); 525 526 skb->prev = skb->next = NULL; 527 if (dev->drv->drv_flags & MT_DRV_TX_ALIGNED4_SKBS) 528 mt76_insert_hdr_pad(skb); 529 530 len = skb_headlen(skb); 531 addr = dma_map_single(dev->dma_dev, skb->data, len, DMA_TO_DEVICE); 532 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) 533 goto free; 534 535 tx_info.buf[n].addr = t->dma_addr; 536 tx_info.buf[n++].len = dev->drv->txwi_size; 537 tx_info.buf[n].addr = addr; 538 tx_info.buf[n++].len = len; 539 540 skb_walk_frags(skb, iter) { 541 if (n == ARRAY_SIZE(tx_info.buf)) 542 goto unmap; 543 544 addr = dma_map_single(dev->dma_dev, iter->data, iter->len, 545 DMA_TO_DEVICE); 546 if (unlikely(dma_mapping_error(dev->dma_dev, addr))) 547 goto unmap; 548 549 tx_info.buf[n].addr = addr; 550 tx_info.buf[n++].len = iter->len; 551 } 552 tx_info.nbuf = n; 553 554 if (q->queued + (tx_info.nbuf + 1) / 2 >= q->ndesc - 1) { 555 ret = -ENOMEM; 556 goto unmap; 557 } 558 559 dma_sync_single_for_cpu(dev->dma_dev, t->dma_addr, dev->drv->txwi_size, 560 DMA_TO_DEVICE); 561 ret = dev->drv->tx_prepare_skb(dev, txwi, qid, wcid, sta, &tx_info); 562 dma_sync_single_for_device(dev->dma_dev, t->dma_addr, dev->drv->txwi_size, 563 DMA_TO_DEVICE); 564 if (ret < 0) 565 goto unmap; 566 567 return mt76_dma_add_buf(dev, q, tx_info.buf, tx_info.nbuf, 568 tx_info.info, tx_info.skb, t); 569 570 unmap: 571 for (n--; n > 0; n--) 572 dma_unmap_single(dev->dma_dev, tx_info.buf[n].addr, 573 tx_info.buf[n].len, DMA_TO_DEVICE); 574 575 free: 576 #ifdef CONFIG_NL80211_TESTMODE 577 /* fix tx_done accounting on queue overflow */ 578 if (mt76_is_testmode_skb(dev, skb, &hw)) { 579 struct mt76_phy *phy = hw->priv; 580 581 if (tx_info.skb == phy->test.tx_skb) 582 phy->test.tx_done--; 583 } 584 #endif 585 586 mt76_put_txwi(dev, t); 587 588 free_skb: 589 status.skb = tx_info.skb; 590 hw = mt76_tx_status_get_hw(dev, tx_info.skb); 591 spin_lock_bh(&dev->rx_lock); 592 ieee80211_tx_status_ext(hw, &status); 593 spin_unlock_bh(&dev->rx_lock); 594 595 return ret; 596 } 597 598 static int 599 mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q, 600 bool allow_direct) 601 { 602 int len = SKB_WITH_OVERHEAD(q->buf_size); 603 int frames = 0; 604 605 if (!q->ndesc) 606 return 0; 607 608 spin_lock_bh(&q->lock); 609 610 while (q->queued < q->ndesc - 1) { 611 enum dma_data_direction dir; 612 struct mt76_queue_buf qbuf; 613 dma_addr_t addr; 614 int offset; 615 void *buf; 616 617 buf = mt76_get_page_pool_buf(q, &offset, q->buf_size); 618 if (!buf) 619 break; 620 621 addr = page_pool_get_dma_addr(virt_to_head_page(buf)) + offset; 622 dir = page_pool_get_dma_dir(q->page_pool); 623 dma_sync_single_for_device(dev->dma_dev, addr, len, dir); 624 625 qbuf.addr = addr + q->buf_offset; 626 qbuf.len = len - q->buf_offset; 627 qbuf.skip_unmap = false; 628 if (mt76_dma_add_rx_buf(dev, q, &qbuf, buf) < 0) { 629 mt76_put_page_pool_buf(buf, allow_direct); 630 break; 631 } 632 frames++; 633 } 634 635 if (frames) 636 mt76_dma_kick_queue(dev, q); 637 638 spin_unlock_bh(&q->lock); 639 640 return frames; 641 } 642 643 int mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q, bool reset) 644 { 645 #ifdef CONFIG_NET_MEDIATEK_SOC_WED 646 struct mtk_wed_device *wed = &dev->mmio.wed; 647 int ret, type, ring; 648 u8 flags; 649 650 if (!q || !q->ndesc) 651 return -EINVAL; 652 653 flags = q->flags; 654 if (!mtk_wed_device_active(wed)) 655 q->flags &= ~MT_QFLAG_WED; 656 657 if (!(q->flags & MT_QFLAG_WED)) 658 return 0; 659 660 type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags); 661 ring = FIELD_GET(MT_QFLAG_WED_RING, q->flags); 662 663 switch (type) { 664 case MT76_WED_Q_TX: 665 ret = mtk_wed_device_tx_ring_setup(wed, ring, q->regs, reset); 666 if (!ret) 667 q->wed_regs = wed->tx_ring[ring].reg_base; 668 break; 669 case MT76_WED_Q_TXFREE: 670 /* WED txfree queue needs ring to be initialized before setup */ 671 q->flags = 0; 672 mt76_dma_queue_reset(dev, q); 673 mt76_dma_rx_fill(dev, q, false); 674 q->flags = flags; 675 676 ret = mtk_wed_device_txfree_ring_setup(wed, q->regs); 677 if (!ret) 678 q->wed_regs = wed->txfree_ring.reg_base; 679 break; 680 case MT76_WED_Q_RX: 681 ret = mtk_wed_device_rx_ring_setup(wed, ring, q->regs, reset); 682 if (!ret) 683 q->wed_regs = wed->rx_ring[ring].reg_base; 684 break; 685 default: 686 ret = -EINVAL; 687 } 688 689 return ret; 690 #else 691 return 0; 692 #endif 693 } 694 EXPORT_SYMBOL_GPL(mt76_dma_wed_setup); 695 696 static int 697 mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q, 698 int idx, int n_desc, int bufsize, 699 u32 ring_base) 700 { 701 int ret, size; 702 703 spin_lock_init(&q->lock); 704 spin_lock_init(&q->cleanup_lock); 705 706 #if defined(__linux__) 707 q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE; 708 #elif defined(__FreeBSD__) 709 q->regs = (void *)((u8 *)dev->mmio.regs + ring_base + idx * MT_RING_SIZE); 710 #endif 711 q->ndesc = n_desc; 712 q->buf_size = bufsize; 713 q->hw_idx = idx; 714 715 size = q->ndesc * sizeof(struct mt76_desc); 716 q->desc = dmam_alloc_coherent(dev->dma_dev, size, &q->desc_dma, GFP_KERNEL); 717 if (!q->desc) 718 return -ENOMEM; 719 720 size = q->ndesc * sizeof(*q->entry); 721 q->entry = devm_kzalloc(dev->dev, size, GFP_KERNEL); 722 if (!q->entry) 723 return -ENOMEM; 724 725 ret = mt76_create_page_pool(dev, q); 726 if (ret) 727 return ret; 728 729 ret = mt76_dma_wed_setup(dev, q, false); 730 if (ret) 731 return ret; 732 733 if (q->flags != MT_WED_Q_TXFREE) 734 mt76_dma_queue_reset(dev, q); 735 736 return 0; 737 } 738 739 static void 740 mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q) 741 { 742 void *buf; 743 bool more; 744 745 if (!q->ndesc) 746 return; 747 748 spin_lock_bh(&q->lock); 749 750 do { 751 buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more, NULL); 752 if (!buf) 753 break; 754 755 mt76_put_page_pool_buf(buf, false); 756 } while (1); 757 758 if (q->rx_head) { 759 dev_kfree_skb(q->rx_head); 760 q->rx_head = NULL; 761 } 762 763 spin_unlock_bh(&q->lock); 764 } 765 766 static void 767 mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid) 768 { 769 struct mt76_queue *q = &dev->q_rx[qid]; 770 int i; 771 772 if (!q->ndesc) 773 return; 774 775 for (i = 0; i < q->ndesc; i++) 776 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE); 777 778 mt76_dma_rx_cleanup(dev, q); 779 780 /* reset WED rx queues */ 781 mt76_dma_wed_setup(dev, q, true); 782 if (q->flags != MT_WED_Q_TXFREE) { 783 mt76_dma_sync_idx(dev, q); 784 mt76_dma_rx_fill(dev, q, false); 785 } 786 } 787 788 static void 789 mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data, 790 int len, bool more, u32 info) 791 { 792 struct sk_buff *skb = q->rx_head; 793 struct skb_shared_info *shinfo = skb_shinfo(skb); 794 int nr_frags = shinfo->nr_frags; 795 796 if (nr_frags < ARRAY_SIZE(shinfo->frags)) { 797 struct page *page = virt_to_head_page(data); 798 #if defined(__linux__) 799 int offset = data - page_address(page) + q->buf_offset; 800 #elif defined(__FreeBSD__) 801 int offset = (u8 *)data - (u8 *)page_address(page) + q->buf_offset; 802 #endif 803 804 skb_add_rx_frag(skb, nr_frags, page, offset, len, q->buf_size); 805 } else { 806 mt76_put_page_pool_buf(data, true); 807 } 808 809 if (more) 810 return; 811 812 q->rx_head = NULL; 813 if (nr_frags < ARRAY_SIZE(shinfo->frags)) 814 dev->drv->rx_skb(dev, q - dev->q_rx, skb, &info); 815 else 816 dev_kfree_skb(skb); 817 } 818 819 static int 820 mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget) 821 { 822 int len, data_len, done = 0, dma_idx; 823 struct sk_buff *skb; 824 unsigned char *data; 825 bool check_ddone = false; 826 bool more; 827 828 if (IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED) && 829 q->flags == MT_WED_Q_TXFREE) { 830 dma_idx = Q_READ(dev, q, dma_idx); 831 check_ddone = true; 832 } 833 834 while (done < budget) { 835 bool drop = false; 836 u32 info; 837 838 if (check_ddone) { 839 if (q->tail == dma_idx) 840 dma_idx = Q_READ(dev, q, dma_idx); 841 842 if (q->tail == dma_idx) 843 break; 844 } 845 846 data = mt76_dma_dequeue(dev, q, false, &len, &info, &more, 847 &drop); 848 if (!data) 849 break; 850 851 if (drop) 852 goto free_frag; 853 854 if (q->rx_head) 855 data_len = q->buf_size; 856 else 857 data_len = SKB_WITH_OVERHEAD(q->buf_size); 858 859 if (data_len < len + q->buf_offset) { 860 dev_kfree_skb(q->rx_head); 861 q->rx_head = NULL; 862 goto free_frag; 863 } 864 865 if (q->rx_head) { 866 mt76_add_fragment(dev, q, data, len, more, info); 867 continue; 868 } 869 870 if (!more && dev->drv->rx_check && 871 !(dev->drv->rx_check(dev, data, len))) 872 goto free_frag; 873 874 skb = napi_build_skb(data, q->buf_size); 875 if (!skb) 876 goto free_frag; 877 878 skb_reserve(skb, q->buf_offset); 879 skb_mark_for_recycle(skb); 880 881 *(u32 *)skb->cb = info; 882 883 __skb_put(skb, len); 884 done++; 885 886 if (more) { 887 q->rx_head = skb; 888 continue; 889 } 890 891 dev->drv->rx_skb(dev, q - dev->q_rx, skb, &info); 892 continue; 893 894 free_frag: 895 mt76_put_page_pool_buf(data, true); 896 } 897 898 mt76_dma_rx_fill(dev, q, true); 899 return done; 900 } 901 902 int mt76_dma_rx_poll(struct napi_struct *napi, int budget) 903 { 904 struct mt76_dev *dev; 905 int qid, done = 0, cur; 906 907 dev = container_of(napi->dev, struct mt76_dev, napi_dev); 908 qid = napi - dev->napi; 909 910 rcu_read_lock(); 911 912 do { 913 cur = mt76_dma_rx_process(dev, &dev->q_rx[qid], budget - done); 914 mt76_rx_poll_complete(dev, qid, napi); 915 done += cur; 916 } while (cur && done < budget); 917 918 rcu_read_unlock(); 919 920 if (done < budget && napi_complete(napi)) 921 dev->drv->rx_poll_complete(dev, qid); 922 923 return done; 924 } 925 EXPORT_SYMBOL_GPL(mt76_dma_rx_poll); 926 927 static int 928 mt76_dma_init(struct mt76_dev *dev, 929 int (*poll)(struct napi_struct *napi, int budget)) 930 { 931 int i; 932 933 init_dummy_netdev(&dev->napi_dev); 934 init_dummy_netdev(&dev->tx_napi_dev); 935 snprintf(dev->napi_dev.name, sizeof(dev->napi_dev.name), "%s", 936 wiphy_name(dev->hw->wiphy)); 937 dev->napi_dev.threaded = 1; 938 init_completion(&dev->mmio.wed_reset); 939 init_completion(&dev->mmio.wed_reset_complete); 940 941 mt76_for_each_q_rx(dev, i) { 942 netif_napi_add(&dev->napi_dev, &dev->napi[i], poll); 943 mt76_dma_rx_fill(dev, &dev->q_rx[i], false); 944 napi_enable(&dev->napi[i]); 945 } 946 947 return 0; 948 } 949 950 static const struct mt76_queue_ops mt76_dma_ops = { 951 .init = mt76_dma_init, 952 .alloc = mt76_dma_alloc_queue, 953 .reset_q = mt76_dma_queue_reset, 954 .tx_queue_skb_raw = mt76_dma_tx_queue_skb_raw, 955 .tx_queue_skb = mt76_dma_tx_queue_skb, 956 .tx_cleanup = mt76_dma_tx_cleanup, 957 .rx_cleanup = mt76_dma_rx_cleanup, 958 .rx_reset = mt76_dma_rx_reset, 959 .kick = mt76_dma_kick_queue, 960 }; 961 962 void mt76_dma_attach(struct mt76_dev *dev) 963 { 964 dev->queue_ops = &mt76_dma_ops; 965 } 966 EXPORT_SYMBOL_GPL(mt76_dma_attach); 967 968 void mt76_dma_cleanup(struct mt76_dev *dev) 969 { 970 int i; 971 972 mt76_worker_disable(&dev->tx_worker); 973 netif_napi_del(&dev->tx_napi); 974 975 for (i = 0; i < ARRAY_SIZE(dev->phys); i++) { 976 struct mt76_phy *phy = dev->phys[i]; 977 int j; 978 979 if (!phy) 980 continue; 981 982 for (j = 0; j < ARRAY_SIZE(phy->q_tx); j++) 983 mt76_dma_tx_cleanup(dev, phy->q_tx[j], true); 984 } 985 986 for (i = 0; i < ARRAY_SIZE(dev->q_mcu); i++) 987 mt76_dma_tx_cleanup(dev, dev->q_mcu[i], true); 988 989 mt76_for_each_q_rx(dev, i) { 990 struct mt76_queue *q = &dev->q_rx[i]; 991 992 netif_napi_del(&dev->napi[i]); 993 mt76_dma_rx_cleanup(dev, q); 994 995 page_pool_destroy(q->page_pool); 996 } 997 998 mt76_free_pending_txwi(dev); 999 mt76_free_pending_rxwi(dev); 1000 1001 if (mtk_wed_device_active(&dev->mmio.wed)) 1002 mtk_wed_device_detach(&dev->mmio.wed); 1003 } 1004 EXPORT_SYMBOL_GPL(mt76_dma_cleanup); 1005