1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* 3 * Copyright (C) 2007-2015, 2018-2023 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #include <linux/pci.h> 8 #include <linux/interrupt.h> 9 #include <linux/debugfs.h> 10 #include <linux/sched.h> 11 #include <linux/bitops.h> 12 #include <linux/gfp.h> 13 #include <linux/vmalloc.h> 14 #include <linux/module.h> 15 #include <linux/wait.h> 16 #include <linux/seq_file.h> 17 #if defined(__FreeBSD__) 18 #include <linux/delay.h> 19 #endif 20 21 #include "iwl-drv.h" 22 #include "iwl-trans.h" 23 #include "iwl-csr.h" 24 #include "iwl-prph.h" 25 #include "iwl-scd.h" 26 #include "iwl-agn-hw.h" 27 #include "fw/error-dump.h" 28 #include "fw/dbg.h" 29 #include "fw/api/tx.h" 30 #include "mei/iwl-mei.h" 31 #include "internal.h" 32 #include "iwl-fh.h" 33 #include "iwl-context-info-gen3.h" 34 35 /* extended range in FW SRAM */ 36 #define IWL_FW_MEM_EXTENDED_START 0x40000 37 #define IWL_FW_MEM_EXTENDED_END 0x57FFF 38 39 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans) 40 { 41 #define PCI_DUMP_SIZE 352 42 #define PCI_MEM_DUMP_SIZE 64 43 #define PCI_PARENT_DUMP_SIZE 524 44 #define PREFIX_LEN 32 45 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 46 struct pci_dev *pdev = trans_pcie->pci_dev; 47 u32 i, pos, alloc_size, *ptr, *buf; 48 char *prefix; 49 50 if (trans_pcie->pcie_dbg_dumped_once) 51 return; 52 53 /* Should be a multiple of 4 */ 54 BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3); 55 BUILD_BUG_ON(PCI_MEM_DUMP_SIZE > 4096 || PCI_MEM_DUMP_SIZE & 0x3); 56 BUILD_BUG_ON(PCI_PARENT_DUMP_SIZE > 4096 || PCI_PARENT_DUMP_SIZE & 0x3); 57 58 /* Alloc a max size buffer */ 59 alloc_size = PCI_ERR_ROOT_ERR_SRC + 4 + PREFIX_LEN; 60 alloc_size = max_t(u32, alloc_size, PCI_DUMP_SIZE + PREFIX_LEN); 61 alloc_size = max_t(u32, alloc_size, PCI_MEM_DUMP_SIZE + PREFIX_LEN); 62 alloc_size = max_t(u32, alloc_size, PCI_PARENT_DUMP_SIZE + PREFIX_LEN); 63 64 buf = kmalloc(alloc_size, GFP_ATOMIC); 65 if (!buf) 66 return; 67 prefix = (char *)buf + alloc_size - PREFIX_LEN; 68 69 IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n"); 70 71 /* Print wifi device registers */ 72 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 73 IWL_ERR(trans, "iwlwifi device config registers:\n"); 74 for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++) 75 if (pci_read_config_dword(pdev, i, ptr)) 76 goto err_read; 77 #if defined(__linux__) 78 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 79 #elif defined(__FreeBSD__) 80 iwl_print_hex_dump(NULL, IWL_DL_ANY, prefix, (u8 *)buf, i); 81 #endif 82 83 IWL_ERR(trans, "iwlwifi device memory mapped registers:\n"); 84 for (i = 0, ptr = buf; i < PCI_MEM_DUMP_SIZE; i += 4, ptr++) 85 *ptr = iwl_read32(trans, i); 86 #if defined(__linux__) 87 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 88 #elif defined(__FreeBSD__) 89 iwl_print_hex_dump(NULL, IWL_DL_ANY, prefix, (u8 *)buf, i); 90 #endif 91 92 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 93 if (pos) { 94 IWL_ERR(trans, "iwlwifi device AER capability structure:\n"); 95 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++) 96 if (pci_read_config_dword(pdev, pos + i, ptr)) 97 goto err_read; 98 #if defined(__linux__) 99 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 100 32, 4, buf, i, 0); 101 #elif defined(__FreeBSD__) 102 iwl_print_hex_dump(NULL, IWL_DL_ANY, prefix, (u8 *)buf, i); 103 #endif 104 } 105 106 /* Print parent device registers next */ 107 if (!pdev->bus->self) 108 goto out; 109 110 pdev = pdev->bus->self; 111 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 112 113 IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n", 114 pci_name(pdev)); 115 for (i = 0, ptr = buf; i < PCI_PARENT_DUMP_SIZE; i += 4, ptr++) 116 if (pci_read_config_dword(pdev, i, ptr)) 117 goto err_read; 118 #if defined(__linux__) 119 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 120 #elif defined(__FreeBSD__) 121 iwl_print_hex_dump(NULL, IWL_DL_ANY, prefix, (u8 *)buf, i); 122 #endif 123 124 /* Print root port AER registers */ 125 pos = 0; 126 pdev = pcie_find_root_port(pdev); 127 if (pdev) 128 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 129 if (pos) { 130 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n", 131 pci_name(pdev)); 132 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev)); 133 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++) 134 if (pci_read_config_dword(pdev, pos + i, ptr)) 135 goto err_read; 136 #if defined(__linux__) 137 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 138 4, buf, i, 0); 139 #elif defined(__FreeBSD__) 140 iwl_print_hex_dump(NULL, IWL_DL_ANY, prefix, (u8 *)buf, i); 141 #endif 142 } 143 goto out; 144 145 err_read: 146 #if defined(__linux__) 147 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0); 148 #elif defined(__FreeBSD__) 149 iwl_print_hex_dump(NULL, IWL_DL_ANY, prefix, (u8 *)buf, i); 150 #endif 151 IWL_ERR(trans, "Read failed at 0x%X\n", i); 152 out: 153 trans_pcie->pcie_dbg_dumped_once = 1; 154 kfree(buf); 155 } 156 157 static int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, 158 bool retake_ownership) 159 { 160 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 161 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 162 iwl_set_bit(trans, CSR_GP_CNTRL, 163 CSR_GP_CNTRL_REG_FLAG_SW_RESET); 164 usleep_range(10000, 20000); 165 } else { 166 iwl_set_bit(trans, CSR_RESET, 167 CSR_RESET_REG_FLAG_SW_RESET); 168 usleep_range(5000, 6000); 169 } 170 171 if (retake_ownership) 172 return iwl_pcie_prepare_card_hw(trans); 173 174 return 0; 175 } 176 177 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 178 { 179 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 180 181 if (!fw_mon->size) 182 return; 183 184 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, 185 fw_mon->physical); 186 187 fw_mon->block = NULL; 188 fw_mon->physical = 0; 189 fw_mon->size = 0; 190 } 191 192 static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 193 u8 max_power) 194 { 195 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 196 void *block = NULL; 197 dma_addr_t physical = 0; 198 u32 size = 0; 199 u8 power; 200 201 if (fw_mon->size) { 202 memset(fw_mon->block, 0, fw_mon->size); 203 return; 204 } 205 206 /* need at least 2 KiB, so stop at 11 */ 207 for (power = max_power; power >= 11; power--) { 208 size = BIT(power); 209 block = dma_alloc_coherent(trans->dev, size, &physical, 210 GFP_KERNEL | __GFP_NOWARN); 211 if (!block) 212 continue; 213 214 IWL_INFO(trans, 215 "Allocated 0x%08x bytes for firmware monitor.\n", 216 size); 217 break; 218 } 219 220 if (WARN_ON_ONCE(!block)) 221 return; 222 223 if (power != max_power) 224 IWL_ERR(trans, 225 "Sorry - debug buffer is only %luK while you requested %luK\n", 226 (unsigned long)BIT(power - 10), 227 (unsigned long)BIT(max_power - 10)); 228 229 fw_mon->block = block; 230 fw_mon->physical = physical; 231 fw_mon->size = size; 232 } 233 234 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 235 { 236 if (!max_power) { 237 /* default max_power is maximum */ 238 max_power = 26; 239 } else { 240 max_power += 11; 241 } 242 243 if (WARN(max_power > 26, 244 "External buffer size for monitor is too big %d, check the FW TLV\n", 245 max_power)) 246 return; 247 248 iwl_pcie_alloc_fw_monitor_block(trans, max_power); 249 } 250 251 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 252 { 253 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 254 ((reg & 0x0000ffff) | (2 << 28))); 255 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 256 } 257 258 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 259 { 260 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 261 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 262 ((reg & 0x0000ffff) | (3 << 28))); 263 } 264 265 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 266 { 267 if (trans->cfg->apmg_not_supported) 268 return; 269 270 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 271 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 272 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 273 ~APMG_PS_CTRL_MSK_PWR_SRC); 274 else 275 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 276 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 277 ~APMG_PS_CTRL_MSK_PWR_SRC); 278 } 279 280 /* PCI registers */ 281 #define PCI_CFG_RETRY_TIMEOUT 0x041 282 283 void iwl_pcie_apm_config(struct iwl_trans *trans) 284 { 285 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 286 u16 lctl; 287 u16 cap; 288 289 /* 290 * L0S states have been found to be unstable with our devices 291 * and in newer hardware they are not officially supported at 292 * all, so we must always set the L0S_DISABLED bit. 293 */ 294 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); 295 296 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 297 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 298 299 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 300 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 301 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 302 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 303 trans->ltr_enabled ? "En" : "Dis"); 304 } 305 306 /* 307 * Start up NIC's basic functionality after it has been reset 308 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 309 * NOTE: This does not load uCode nor start the embedded processor 310 */ 311 static int iwl_pcie_apm_init(struct iwl_trans *trans) 312 { 313 int ret; 314 315 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 316 317 /* 318 * Use "set_bit" below rather than "write", to preserve any hardware 319 * bits already set by default after reset. 320 */ 321 322 /* Disable L0S exit timer (platform NMI Work/Around) */ 323 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) 324 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 325 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 326 327 /* 328 * Disable L0s without affecting L1; 329 * don't wait for ICH L0s (ICH bug W/A) 330 */ 331 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 332 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 333 334 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 335 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 336 337 /* 338 * Enable HAP INTA (interrupt from management bus) to 339 * wake device's PCI Express link L1a -> L0s 340 */ 341 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 342 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A); 343 344 iwl_pcie_apm_config(trans); 345 346 /* Configure analog phase-lock-loop before activating to D0A */ 347 if (trans->trans_cfg->base_params->pll_cfg) 348 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 349 350 ret = iwl_finish_nic_init(trans); 351 if (ret) 352 return ret; 353 354 if (trans->cfg->host_interrupt_operation_mode) { 355 /* 356 * This is a bit of an abuse - This is needed for 7260 / 3160 357 * only check host_interrupt_operation_mode even if this is 358 * not related to host_interrupt_operation_mode. 359 * 360 * Enable the oscillator to count wake up time for L1 exit. This 361 * consumes slightly more power (100uA) - but allows to be sure 362 * that we wake up from L1 on time. 363 * 364 * This looks weird: read twice the same register, discard the 365 * value, set a bit, and yet again, read that same register 366 * just to discard the value. But that's the way the hardware 367 * seems to like it. 368 */ 369 iwl_read_prph(trans, OSC_CLK); 370 iwl_read_prph(trans, OSC_CLK); 371 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 372 iwl_read_prph(trans, OSC_CLK); 373 iwl_read_prph(trans, OSC_CLK); 374 } 375 376 /* 377 * Enable DMA clock and wait for it to stabilize. 378 * 379 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 380 * bits do not disable clocks. This preserves any hardware 381 * bits already set by default in "CLK_CTRL_REG" after reset. 382 */ 383 if (!trans->cfg->apmg_not_supported) { 384 iwl_write_prph(trans, APMG_CLK_EN_REG, 385 APMG_CLK_VAL_DMA_CLK_RQT); 386 udelay(20); 387 388 /* Disable L1-Active */ 389 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 390 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 391 392 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 393 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 394 APMG_RTC_INT_STT_RFKILL); 395 } 396 397 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 398 399 return 0; 400 } 401 402 /* 403 * Enable LP XTAL to avoid HW bug where device may consume much power if 404 * FW is not loaded after device reset. LP XTAL is disabled by default 405 * after device HW reset. Do it only if XTAL is fed by internal source. 406 * Configure device's "persistence" mode to avoid resetting XTAL again when 407 * SHRD_HW_RST occurs in S3. 408 */ 409 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 410 { 411 int ret; 412 u32 apmg_gp1_reg; 413 u32 apmg_xtal_cfg_reg; 414 u32 dl_cfg_reg; 415 416 /* Force XTAL ON */ 417 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, 418 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 419 420 ret = iwl_trans_pcie_sw_reset(trans, true); 421 422 if (!ret) 423 ret = iwl_finish_nic_init(trans); 424 425 if (WARN_ON(ret)) { 426 /* Release XTAL ON request */ 427 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 428 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 429 return; 430 } 431 432 /* 433 * Clear "disable persistence" to avoid LP XTAL resetting when 434 * SHRD_HW_RST is applied in S3. 435 */ 436 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 437 APMG_PCIDEV_STT_VAL_PERSIST_DIS); 438 439 /* 440 * Force APMG XTAL to be active to prevent its disabling by HW 441 * caused by APMG idle state. 442 */ 443 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 444 SHR_APMG_XTAL_CFG_REG); 445 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 446 apmg_xtal_cfg_reg | 447 SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 448 449 ret = iwl_trans_pcie_sw_reset(trans, true); 450 if (ret) 451 IWL_ERR(trans, 452 "iwl_pcie_apm_lp_xtal_enable: failed to retake NIC ownership\n"); 453 454 /* Enable LP XTAL by indirect access through CSR */ 455 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 456 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 457 SHR_APMG_GP1_WF_XTAL_LP_EN | 458 SHR_APMG_GP1_CHICKEN_BIT_SELECT); 459 460 /* Clear delay line clock power up */ 461 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 462 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 463 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 464 465 /* 466 * Enable persistence mode to avoid LP XTAL resetting when 467 * SHRD_HW_RST is applied in S3. 468 */ 469 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 470 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 471 472 /* 473 * Clear "initialization complete" bit to move adapter from 474 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 475 */ 476 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 477 478 /* Activates XTAL resources monitor */ 479 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG, 480 CSR_MONITOR_XTAL_RESOURCES); 481 482 /* Release XTAL ON request */ 483 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 484 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 485 udelay(10); 486 487 /* Release APMG XTAL */ 488 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 489 apmg_xtal_cfg_reg & 490 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 491 } 492 493 void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 494 { 495 int ret; 496 497 /* stop device's busmaster DMA activity */ 498 499 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 500 iwl_set_bit(trans, CSR_GP_CNTRL, 501 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ); 502 503 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, 504 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 505 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 506 100); 507 usleep_range(10000, 20000); 508 } else { 509 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 510 511 ret = iwl_poll_bit(trans, CSR_RESET, 512 CSR_RESET_REG_FLAG_MASTER_DISABLED, 513 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 514 } 515 516 if (ret < 0) 517 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 518 519 IWL_DEBUG_INFO(trans, "stop master\n"); 520 } 521 522 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 523 { 524 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 525 526 if (op_mode_leave) { 527 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 528 iwl_pcie_apm_init(trans); 529 530 /* inform ME that we are leaving */ 531 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) 532 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 533 APMG_PCIDEV_STT_VAL_WAKE_ME); 534 else if (trans->trans_cfg->device_family >= 535 IWL_DEVICE_FAMILY_8000) { 536 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 537 CSR_RESET_LINK_PWR_MGMT_DISABLED); 538 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 539 CSR_HW_IF_CONFIG_REG_PREPARE | 540 CSR_HW_IF_CONFIG_REG_ENABLE_PME); 541 mdelay(1); 542 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 543 CSR_RESET_LINK_PWR_MGMT_DISABLED); 544 } 545 mdelay(5); 546 } 547 548 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 549 550 /* Stop device's DMA activity */ 551 iwl_pcie_apm_stop_master(trans); 552 553 if (trans->cfg->lp_xtal_workaround) { 554 iwl_pcie_apm_lp_xtal_enable(trans); 555 return; 556 } 557 558 iwl_trans_pcie_sw_reset(trans, false); 559 560 /* 561 * Clear "initialization complete" bit to move adapter from 562 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 563 */ 564 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 565 } 566 567 static int iwl_pcie_nic_init(struct iwl_trans *trans) 568 { 569 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 570 int ret; 571 572 /* nic_init */ 573 spin_lock_bh(&trans_pcie->irq_lock); 574 ret = iwl_pcie_apm_init(trans); 575 spin_unlock_bh(&trans_pcie->irq_lock); 576 577 if (ret) 578 return ret; 579 580 iwl_pcie_set_pwr(trans, false); 581 582 iwl_op_mode_nic_config(trans->op_mode); 583 584 /* Allocate the RX queue, or reset if it is already allocated */ 585 ret = iwl_pcie_rx_init(trans); 586 if (ret) 587 return ret; 588 589 /* Allocate or reset and init all Tx and Command queues */ 590 if (iwl_pcie_tx_init(trans)) { 591 iwl_pcie_rx_free(trans); 592 return -ENOMEM; 593 } 594 595 if (trans->trans_cfg->base_params->shadow_reg_enable) { 596 /* enable shadow regs in HW */ 597 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 598 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 599 } 600 601 return 0; 602 } 603 604 #define HW_READY_TIMEOUT (50) 605 606 /* Note: returns poll_bit return value, which is >= 0 if success */ 607 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 608 { 609 int ret; 610 611 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 612 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 613 614 /* See if we got it */ 615 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG, 616 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 617 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 618 HW_READY_TIMEOUT); 619 620 if (ret >= 0) 621 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 622 623 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : ""); 624 return ret; 625 } 626 627 /* Note: returns standard 0/-ERROR code */ 628 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 629 { 630 int ret; 631 int iter; 632 633 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 634 635 ret = iwl_pcie_set_hw_ready(trans); 636 /* If the card is ready, exit 0 */ 637 if (ret >= 0) { 638 trans->csme_own = false; 639 return 0; 640 } 641 642 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 643 CSR_RESET_LINK_PWR_MGMT_DISABLED); 644 usleep_range(1000, 2000); 645 646 for (iter = 0; iter < 10; iter++) { 647 int t = 0; 648 649 /* If HW is not ready, prepare the conditions to check again */ 650 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 651 CSR_HW_IF_CONFIG_REG_PREPARE); 652 653 do { 654 ret = iwl_pcie_set_hw_ready(trans); 655 if (ret >= 0) { 656 trans->csme_own = false; 657 return 0; 658 } 659 660 if (iwl_mei_is_connected()) { 661 IWL_DEBUG_INFO(trans, 662 "Couldn't prepare the card but SAP is connected\n"); 663 trans->csme_own = true; 664 if (trans->trans_cfg->device_family != 665 IWL_DEVICE_FAMILY_9000) 666 IWL_ERR(trans, 667 "SAP not supported for this NIC family\n"); 668 669 return -EBUSY; 670 } 671 672 usleep_range(200, 1000); 673 t += 200; 674 } while (t < 150000); 675 msleep(25); 676 } 677 678 IWL_ERR(trans, "Couldn't prepare the card\n"); 679 680 return ret; 681 } 682 683 /* 684 * ucode 685 */ 686 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 687 u32 dst_addr, dma_addr_t phy_addr, 688 u32 byte_cnt) 689 { 690 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 691 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 692 693 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 694 dst_addr); 695 696 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 697 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 698 699 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 700 (iwl_get_dma_hi_addr(phy_addr) 701 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 702 703 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 704 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 705 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 706 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 707 708 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 709 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 710 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 711 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 712 } 713 714 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 715 u32 dst_addr, dma_addr_t phy_addr, 716 u32 byte_cnt) 717 { 718 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 719 int ret; 720 721 trans_pcie->ucode_write_complete = false; 722 723 if (!iwl_trans_grab_nic_access(trans)) 724 return -EIO; 725 726 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 727 byte_cnt); 728 iwl_trans_release_nic_access(trans); 729 730 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 731 trans_pcie->ucode_write_complete, 5 * HZ); 732 if (!ret) { 733 IWL_ERR(trans, "Failed to load firmware chunk!\n"); 734 iwl_trans_pcie_dump_regs(trans); 735 return -ETIMEDOUT; 736 } 737 738 return 0; 739 } 740 741 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 742 const struct fw_desc *section) 743 { 744 u8 *v_addr; 745 dma_addr_t p_addr; 746 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 747 int ret = 0; 748 749 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 750 section_num); 751 752 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 753 GFP_KERNEL | __GFP_NOWARN); 754 if (!v_addr) { 755 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 756 chunk_sz = PAGE_SIZE; 757 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 758 &p_addr, GFP_KERNEL); 759 if (!v_addr) 760 return -ENOMEM; 761 } 762 763 for (offset = 0; offset < section->len; offset += chunk_sz) { 764 u32 copy_size, dst_addr; 765 bool extended_addr = false; 766 767 copy_size = min_t(u32, chunk_sz, section->len - offset); 768 dst_addr = section->offset + offset; 769 770 if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 771 dst_addr <= IWL_FW_MEM_EXTENDED_END) 772 extended_addr = true; 773 774 if (extended_addr) 775 iwl_set_bits_prph(trans, LMPM_CHICK, 776 LMPM_CHICK_EXTENDED_ADDR_SPACE); 777 778 memcpy(v_addr, (const u8 *)section->data + offset, copy_size); 779 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 780 copy_size); 781 782 if (extended_addr) 783 iwl_clear_bits_prph(trans, LMPM_CHICK, 784 LMPM_CHICK_EXTENDED_ADDR_SPACE); 785 786 if (ret) { 787 IWL_ERR(trans, 788 "Could not load the [%d] uCode section\n", 789 section_num); 790 break; 791 } 792 } 793 794 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 795 return ret; 796 } 797 798 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 799 const struct fw_img *image, 800 int cpu, 801 int *first_ucode_section) 802 { 803 int shift_param; 804 int i, ret = 0, sec_num = 0x1; 805 u32 val, last_read_idx = 0; 806 807 if (cpu == 1) { 808 shift_param = 0; 809 *first_ucode_section = 0; 810 } else { 811 shift_param = 16; 812 (*first_ucode_section)++; 813 } 814 815 for (i = *first_ucode_section; i < image->num_sec; i++) { 816 last_read_idx = i; 817 818 /* 819 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 820 * CPU1 to CPU2. 821 * PAGING_SEPARATOR_SECTION delimiter - separate between 822 * CPU2 non paged to CPU2 paging sec. 823 */ 824 if (!image->sec[i].data || 825 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 826 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 827 IWL_DEBUG_FW(trans, 828 "Break since Data not valid or Empty section, sec = %d\n", 829 i); 830 break; 831 } 832 833 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 834 if (ret) 835 return ret; 836 837 /* Notify ucode of loaded section number and status */ 838 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 839 val = val | (sec_num << shift_param); 840 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 841 842 sec_num = (sec_num << 1) | 0x1; 843 } 844 845 *first_ucode_section = last_read_idx; 846 847 iwl_enable_interrupts(trans); 848 849 if (trans->trans_cfg->gen2) { 850 if (cpu == 1) 851 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 852 0xFFFF); 853 else 854 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 855 0xFFFFFFFF); 856 } else { 857 if (cpu == 1) 858 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 859 0xFFFF); 860 else 861 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 862 0xFFFFFFFF); 863 } 864 865 return 0; 866 } 867 868 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 869 const struct fw_img *image, 870 int cpu, 871 int *first_ucode_section) 872 { 873 int i, ret = 0; 874 u32 last_read_idx = 0; 875 876 if (cpu == 1) 877 *first_ucode_section = 0; 878 else 879 (*first_ucode_section)++; 880 881 for (i = *first_ucode_section; i < image->num_sec; i++) { 882 last_read_idx = i; 883 884 /* 885 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 886 * CPU1 to CPU2. 887 * PAGING_SEPARATOR_SECTION delimiter - separate between 888 * CPU2 non paged to CPU2 paging sec. 889 */ 890 if (!image->sec[i].data || 891 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 892 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 893 IWL_DEBUG_FW(trans, 894 "Break since Data not valid or Empty section, sec = %d\n", 895 i); 896 break; 897 } 898 899 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 900 if (ret) 901 return ret; 902 } 903 904 *first_ucode_section = last_read_idx; 905 906 return 0; 907 } 908 909 static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) 910 { 911 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 912 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 913 &trans->dbg.fw_mon_cfg[alloc_id]; 914 struct iwl_dram_data *frag; 915 916 if (!iwl_trans_dbg_ini_valid(trans)) 917 return; 918 919 if (le32_to_cpu(fw_mon_cfg->buf_location) == 920 IWL_FW_INI_LOCATION_SRAM_PATH) { 921 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); 922 /* set sram monitor by enabling bit 7 */ 923 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 924 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 925 926 return; 927 } 928 929 if (le32_to_cpu(fw_mon_cfg->buf_location) != 930 IWL_FW_INI_LOCATION_DRAM_PATH || 931 !trans->dbg.fw_mon_ini[alloc_id].num_frags) 932 return; 933 934 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 935 936 IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", 937 alloc_id); 938 939 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 940 frag->physical >> MON_BUFF_SHIFT_VER2); 941 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 942 (frag->physical + frag->size - 256) >> 943 MON_BUFF_SHIFT_VER2); 944 } 945 946 void iwl_pcie_apply_destination(struct iwl_trans *trans) 947 { 948 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 949 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 950 int i; 951 952 if (iwl_trans_dbg_ini_valid(trans)) { 953 iwl_pcie_apply_destination_ini(trans); 954 return; 955 } 956 957 IWL_INFO(trans, "Applying debug destination %s\n", 958 get_fw_dbg_mode_string(dest->monitor_mode)); 959 960 if (dest->monitor_mode == EXTERNAL_MODE) 961 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 962 else 963 IWL_WARN(trans, "PCI should have external buffer debug\n"); 964 965 for (i = 0; i < trans->dbg.n_dest_reg; i++) { 966 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 967 u32 val = le32_to_cpu(dest->reg_ops[i].val); 968 969 switch (dest->reg_ops[i].op) { 970 case CSR_ASSIGN: 971 iwl_write32(trans, addr, val); 972 break; 973 case CSR_SETBIT: 974 iwl_set_bit(trans, addr, BIT(val)); 975 break; 976 case CSR_CLEARBIT: 977 iwl_clear_bit(trans, addr, BIT(val)); 978 break; 979 case PRPH_ASSIGN: 980 iwl_write_prph(trans, addr, val); 981 break; 982 case PRPH_SETBIT: 983 iwl_set_bits_prph(trans, addr, BIT(val)); 984 break; 985 case PRPH_CLEARBIT: 986 iwl_clear_bits_prph(trans, addr, BIT(val)); 987 break; 988 case PRPH_BLOCKBIT: 989 if (iwl_read_prph(trans, addr) & BIT(val)) { 990 IWL_ERR(trans, 991 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 992 val, addr); 993 goto monitor; 994 } 995 break; 996 default: 997 IWL_ERR(trans, "FW debug - unknown OP %d\n", 998 dest->reg_ops[i].op); 999 break; 1000 } 1001 } 1002 1003 monitor: 1004 if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { 1005 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 1006 fw_mon->physical >> dest->base_shift); 1007 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1008 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 1009 (fw_mon->physical + fw_mon->size - 1010 256) >> dest->end_shift); 1011 else 1012 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 1013 (fw_mon->physical + fw_mon->size) >> 1014 dest->end_shift); 1015 } 1016 } 1017 1018 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 1019 const struct fw_img *image) 1020 { 1021 int ret = 0; 1022 int first_ucode_section; 1023 1024 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1025 image->is_dual_cpus ? "Dual" : "Single"); 1026 1027 /* load to FW the binary non secured sections of CPU1 */ 1028 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 1029 if (ret) 1030 return ret; 1031 1032 if (image->is_dual_cpus) { 1033 /* set CPU2 header address */ 1034 iwl_write_prph(trans, 1035 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 1036 LMPM_SECURE_CPU2_HDR_MEM_SPACE); 1037 1038 /* load to FW the binary sections of CPU2 */ 1039 ret = iwl_pcie_load_cpu_sections(trans, image, 2, 1040 &first_ucode_section); 1041 if (ret) 1042 return ret; 1043 } 1044 1045 if (iwl_pcie_dbg_on(trans)) 1046 iwl_pcie_apply_destination(trans); 1047 1048 iwl_enable_interrupts(trans); 1049 1050 /* release CPU reset */ 1051 iwl_write32(trans, CSR_RESET, 0); 1052 1053 return 0; 1054 } 1055 1056 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 1057 const struct fw_img *image) 1058 { 1059 int ret = 0; 1060 int first_ucode_section; 1061 1062 IWL_DEBUG_FW(trans, "working with %s CPU\n", 1063 image->is_dual_cpus ? "Dual" : "Single"); 1064 1065 if (iwl_pcie_dbg_on(trans)) 1066 iwl_pcie_apply_destination(trans); 1067 1068 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 1069 iwl_read_prph(trans, WFPM_GP2)); 1070 1071 /* 1072 * Set default value. On resume reading the values that were 1073 * zeored can provide debug data on the resume flow. 1074 * This is for debugging only and has no functional impact. 1075 */ 1076 iwl_write_prph(trans, WFPM_GP2, 0x01010101); 1077 1078 /* configure the ucode to be ready to get the secured image */ 1079 /* release CPU reset */ 1080 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 1081 1082 /* load to FW the binary Secured sections of CPU1 */ 1083 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1084 &first_ucode_section); 1085 if (ret) 1086 return ret; 1087 1088 /* load to FW the binary sections of CPU2 */ 1089 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1090 &first_ucode_section); 1091 } 1092 1093 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1094 { 1095 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1096 bool hw_rfkill = iwl_is_rfkill_set(trans); 1097 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1098 bool report; 1099 1100 if (hw_rfkill) { 1101 set_bit(STATUS_RFKILL_HW, &trans->status); 1102 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1103 } else { 1104 clear_bit(STATUS_RFKILL_HW, &trans->status); 1105 if (trans_pcie->opmode_down) 1106 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1107 } 1108 1109 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1110 1111 if (prev != report) 1112 iwl_trans_pcie_rf_kill(trans, report); 1113 1114 return hw_rfkill; 1115 } 1116 1117 struct iwl_causes_list { 1118 u16 mask_reg; 1119 u8 bit; 1120 u8 addr; 1121 }; 1122 1123 #define IWL_CAUSE(reg, mask) \ 1124 { \ 1125 .mask_reg = reg, \ 1126 .bit = ilog2(mask), \ 1127 .addr = ilog2(mask) + \ 1128 ((reg) == CSR_MSIX_FH_INT_MASK_AD ? -16 : \ 1129 (reg) == CSR_MSIX_HW_INT_MASK_AD ? 16 : \ 1130 0xffff), /* causes overflow warning */ \ 1131 } 1132 1133 static const struct iwl_causes_list causes_list_common[] = { 1134 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH0_NUM), 1135 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH1_NUM), 1136 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_S2D), 1137 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_FH_ERR), 1138 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_ALIVE), 1139 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_WAKEUP), 1140 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RESET_DONE), 1141 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_CT_KILL), 1142 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RF_KILL), 1143 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_PERIODIC), 1144 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SCD), 1145 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_FH_TX), 1146 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HW_ERR), 1147 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HAP), 1148 }; 1149 1150 static const struct iwl_causes_list causes_list_pre_bz[] = { 1151 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR), 1152 }; 1153 1154 static const struct iwl_causes_list causes_list_bz[] = { 1155 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ), 1156 }; 1157 1158 static void iwl_pcie_map_list(struct iwl_trans *trans, 1159 const struct iwl_causes_list *causes, 1160 int arr_size, int val) 1161 { 1162 int i; 1163 1164 for (i = 0; i < arr_size; i++) { 1165 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 1166 iwl_clear_bit(trans, causes[i].mask_reg, 1167 BIT(causes[i].bit)); 1168 } 1169 } 1170 1171 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1172 { 1173 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1174 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1175 /* 1176 * Access all non RX causes and map them to the default irq. 1177 * In case we are missing at least one interrupt vector, 1178 * the first interrupt vector will serve non-RX and FBQ causes. 1179 */ 1180 iwl_pcie_map_list(trans, causes_list_common, 1181 ARRAY_SIZE(causes_list_common), val); 1182 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1183 iwl_pcie_map_list(trans, causes_list_bz, 1184 ARRAY_SIZE(causes_list_bz), val); 1185 else 1186 iwl_pcie_map_list(trans, causes_list_pre_bz, 1187 ARRAY_SIZE(causes_list_pre_bz), val); 1188 } 1189 1190 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 1191 { 1192 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1193 u32 offset = 1194 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1195 u32 val, idx; 1196 1197 /* 1198 * The first RX queue - fallback queue, which is designated for 1199 * management frame, command responses etc, is always mapped to the 1200 * first interrupt vector. The other RX queues are mapped to 1201 * the other (N - 2) interrupt vectors. 1202 */ 1203 val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 1204 for (idx = 1; idx < trans->num_rx_queues; idx++) { 1205 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 1206 MSIX_FH_INT_CAUSES_Q(idx - offset)); 1207 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 1208 } 1209 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 1210 1211 val = MSIX_FH_INT_CAUSES_Q(0); 1212 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 1213 val |= MSIX_NON_AUTO_CLEAR_CAUSE; 1214 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 1215 1216 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 1217 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 1218 } 1219 1220 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 1221 { 1222 struct iwl_trans *trans = trans_pcie->trans; 1223 1224 if (!trans_pcie->msix_enabled) { 1225 if (trans->trans_cfg->mq_rx_supported && 1226 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1227 iwl_write_umac_prph(trans, UREG_CHICK, 1228 UREG_CHICK_MSI_ENABLE); 1229 return; 1230 } 1231 /* 1232 * The IVAR table needs to be configured again after reset, 1233 * but if the device is disabled, we can't write to 1234 * prph. 1235 */ 1236 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1237 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 1238 1239 /* 1240 * Each cause from the causes list above and the RX causes is 1241 * represented as a byte in the IVAR table. The first nibble 1242 * represents the bound interrupt vector of the cause, the second 1243 * represents no auto clear for this cause. This will be set if its 1244 * interrupt vector is bound to serve other causes. 1245 */ 1246 iwl_pcie_map_rx_causes(trans); 1247 1248 iwl_pcie_map_non_rx_causes(trans); 1249 } 1250 1251 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 1252 { 1253 struct iwl_trans *trans = trans_pcie->trans; 1254 1255 iwl_pcie_conf_msix_hw(trans_pcie); 1256 1257 if (!trans_pcie->msix_enabled) 1258 return; 1259 1260 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 1261 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 1262 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 1263 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 1264 } 1265 1266 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1267 { 1268 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1269 1270 lockdep_assert_held(&trans_pcie->mutex); 1271 1272 if (trans_pcie->is_down) 1273 return; 1274 1275 trans_pcie->is_down = true; 1276 1277 /* tell the device to stop sending interrupts */ 1278 iwl_disable_interrupts(trans); 1279 1280 /* device going down, Stop using ICT table */ 1281 iwl_pcie_disable_ict(trans); 1282 1283 /* 1284 * If a HW restart happens during firmware loading, 1285 * then the firmware loading might call this function 1286 * and later it might be called again due to the 1287 * restart. So don't process again if the device is 1288 * already dead. 1289 */ 1290 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1291 IWL_DEBUG_INFO(trans, 1292 "DEVICE_ENABLED bit was set and is now cleared\n"); 1293 iwl_pcie_rx_napi_sync(trans); 1294 iwl_pcie_tx_stop(trans); 1295 iwl_pcie_rx_stop(trans); 1296 1297 /* Power-down device's busmaster DMA clocks */ 1298 if (!trans->cfg->apmg_not_supported) { 1299 iwl_write_prph(trans, APMG_CLK_DIS_REG, 1300 APMG_CLK_VAL_DMA_CLK_RQT); 1301 udelay(5); 1302 } 1303 } 1304 1305 /* Make sure (redundant) we've released our request to stay awake */ 1306 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1307 iwl_clear_bit(trans, CSR_GP_CNTRL, 1308 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 1309 else 1310 iwl_clear_bit(trans, CSR_GP_CNTRL, 1311 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1312 1313 /* Stop the device, and put it in low power state */ 1314 iwl_pcie_apm_stop(trans, false); 1315 1316 /* re-take ownership to prevent other users from stealing the device */ 1317 iwl_trans_pcie_sw_reset(trans, true); 1318 1319 /* 1320 * Upon stop, the IVAR table gets erased, so msi-x won't 1321 * work. This causes a bug in RF-KILL flows, since the interrupt 1322 * that enables radio won't fire on the correct irq, and the 1323 * driver won't be able to handle the interrupt. 1324 * Configure the IVAR table again after reset. 1325 */ 1326 iwl_pcie_conf_msix_hw(trans_pcie); 1327 1328 /* 1329 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1330 * This is a bug in certain verions of the hardware. 1331 * Certain devices also keep sending HW RF kill interrupt all 1332 * the time, unless the interrupt is ACKed even if the interrupt 1333 * should be masked. Re-ACK all the interrupts here. 1334 */ 1335 iwl_disable_interrupts(trans); 1336 1337 /* clear all status bits */ 1338 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1339 clear_bit(STATUS_INT_ENABLED, &trans->status); 1340 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1341 1342 /* 1343 * Even if we stop the HW, we still want the RF kill 1344 * interrupt 1345 */ 1346 iwl_enable_rfkill_int(trans); 1347 } 1348 1349 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 1350 { 1351 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1352 1353 if (trans_pcie->msix_enabled) { 1354 int i; 1355 1356 for (i = 0; i < trans_pcie->alloc_vecs; i++) 1357 synchronize_irq(trans_pcie->msix_entries[i].vector); 1358 } else { 1359 synchronize_irq(trans_pcie->pci_dev->irq); 1360 } 1361 } 1362 1363 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1364 const struct fw_img *fw, bool run_in_rfkill) 1365 { 1366 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1367 bool hw_rfkill; 1368 int ret; 1369 1370 /* This may fail if AMT took ownership of the device */ 1371 if (iwl_pcie_prepare_card_hw(trans)) { 1372 IWL_WARN(trans, "Exit HW not ready\n"); 1373 return -EIO; 1374 } 1375 1376 iwl_enable_rfkill_int(trans); 1377 1378 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1379 1380 /* 1381 * We enabled the RF-Kill interrupt and the handler may very 1382 * well be running. Disable the interrupts to make sure no other 1383 * interrupt can be fired. 1384 */ 1385 iwl_disable_interrupts(trans); 1386 1387 /* Make sure it finished running */ 1388 iwl_pcie_synchronize_irqs(trans); 1389 1390 mutex_lock(&trans_pcie->mutex); 1391 1392 /* If platform's RF_KILL switch is NOT set to KILL */ 1393 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1394 if (hw_rfkill && !run_in_rfkill) { 1395 ret = -ERFKILL; 1396 goto out; 1397 } 1398 1399 /* Someone called stop_device, don't try to start_fw */ 1400 if (trans_pcie->is_down) { 1401 IWL_WARN(trans, 1402 "Can't start_fw since the HW hasn't been started\n"); 1403 ret = -EIO; 1404 goto out; 1405 } 1406 1407 /* make sure rfkill handshake bits are cleared */ 1408 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1409 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1410 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1411 1412 /* clear (again), then enable host interrupts */ 1413 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1414 1415 ret = iwl_pcie_nic_init(trans); 1416 if (ret) { 1417 IWL_ERR(trans, "Unable to init nic\n"); 1418 goto out; 1419 } 1420 1421 /* 1422 * Now, we load the firmware and don't want to be interrupted, even 1423 * by the RF-Kill interrupt (hence mask all the interrupt besides the 1424 * FH_TX interrupt which is needed to load the firmware). If the 1425 * RF-Kill switch is toggled, we will find out after having loaded 1426 * the firmware and return the proper value to the caller. 1427 */ 1428 iwl_enable_fw_load_int(trans); 1429 1430 /* really make sure rfkill handshake bits are cleared */ 1431 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1432 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1433 1434 /* Load the given image to the HW */ 1435 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1436 ret = iwl_pcie_load_given_ucode_8000(trans, fw); 1437 else 1438 ret = iwl_pcie_load_given_ucode(trans, fw); 1439 1440 /* re-check RF-Kill state since we may have missed the interrupt */ 1441 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1442 if (hw_rfkill && !run_in_rfkill) 1443 ret = -ERFKILL; 1444 1445 out: 1446 mutex_unlock(&trans_pcie->mutex); 1447 return ret; 1448 } 1449 1450 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr) 1451 { 1452 iwl_pcie_reset_ict(trans); 1453 iwl_pcie_tx_start(trans, scd_addr); 1454 } 1455 1456 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1457 bool was_in_rfkill) 1458 { 1459 bool hw_rfkill; 1460 1461 /* 1462 * Check again since the RF kill state may have changed while 1463 * all the interrupts were disabled, in this case we couldn't 1464 * receive the RF kill interrupt and update the state in the 1465 * op_mode. 1466 * Don't call the op_mode if the rkfill state hasn't changed. 1467 * This allows the op_mode to call stop_device from the rfkill 1468 * notification without endless recursion. Under very rare 1469 * circumstances, we might have a small recursion if the rfkill 1470 * state changed exactly now while we were called from stop_device. 1471 * This is very unlikely but can happen and is supported. 1472 */ 1473 hw_rfkill = iwl_is_rfkill_set(trans); 1474 if (hw_rfkill) { 1475 set_bit(STATUS_RFKILL_HW, &trans->status); 1476 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1477 } else { 1478 clear_bit(STATUS_RFKILL_HW, &trans->status); 1479 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1480 } 1481 if (hw_rfkill != was_in_rfkill) 1482 iwl_trans_pcie_rf_kill(trans, hw_rfkill); 1483 } 1484 1485 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1486 { 1487 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1488 bool was_in_rfkill; 1489 1490 iwl_op_mode_time_point(trans->op_mode, 1491 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, 1492 NULL); 1493 1494 mutex_lock(&trans_pcie->mutex); 1495 trans_pcie->opmode_down = true; 1496 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1497 _iwl_trans_pcie_stop_device(trans); 1498 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1499 mutex_unlock(&trans_pcie->mutex); 1500 } 1501 1502 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state) 1503 { 1504 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1505 IWL_TRANS_GET_PCIE_TRANS(trans); 1506 1507 lockdep_assert_held(&trans_pcie->mutex); 1508 1509 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1510 state ? "disabled" : "enabled"); 1511 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) { 1512 if (trans->trans_cfg->gen2) 1513 _iwl_trans_pcie_gen2_stop_device(trans); 1514 else 1515 _iwl_trans_pcie_stop_device(trans); 1516 } 1517 } 1518 1519 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1520 bool test, bool reset) 1521 { 1522 iwl_disable_interrupts(trans); 1523 1524 /* 1525 * in testing mode, the host stays awake and the 1526 * hardware won't be reset (not even partially) 1527 */ 1528 if (test) 1529 return; 1530 1531 iwl_pcie_disable_ict(trans); 1532 1533 iwl_pcie_synchronize_irqs(trans); 1534 1535 iwl_clear_bit(trans, CSR_GP_CNTRL, 1536 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1537 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1538 1539 if (reset) { 1540 /* 1541 * reset TX queues -- some of their registers reset during S3 1542 * so if we don't reset everything here the D3 image would try 1543 * to execute some invalid memory upon resume 1544 */ 1545 iwl_trans_pcie_tx_reset(trans); 1546 } 1547 1548 iwl_pcie_set_pwr(trans, true); 1549 } 1550 1551 static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend) 1552 { 1553 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1554 int ret; 1555 1556 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) 1557 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1558 suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND : 1559 UREG_DOORBELL_TO_ISR6_RESUME); 1560 else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1561 iwl_write32(trans, CSR_IPC_SLEEP_CONTROL, 1562 suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND : 1563 CSR_IPC_SLEEP_CONTROL_RESUME); 1564 else 1565 return 0; 1566 1567 ret = wait_event_timeout(trans_pcie->sx_waitq, 1568 trans_pcie->sx_complete, 2 * HZ); 1569 1570 /* Invalidate it toward next suspend or resume */ 1571 trans_pcie->sx_complete = false; 1572 1573 if (!ret) { 1574 IWL_ERR(trans, "Timeout %s D3\n", 1575 suspend ? "entering" : "exiting"); 1576 return -ETIMEDOUT; 1577 } 1578 1579 return 0; 1580 } 1581 1582 static int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, 1583 bool reset) 1584 { 1585 int ret; 1586 1587 if (!reset) 1588 /* Enable persistence mode to avoid reset */ 1589 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1590 CSR_HW_IF_CONFIG_REG_PERSIST_MODE); 1591 1592 ret = iwl_pcie_d3_handshake(trans, true); 1593 if (ret) 1594 return ret; 1595 1596 iwl_pcie_d3_complete_suspend(trans, test, reset); 1597 1598 return 0; 1599 } 1600 1601 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1602 enum iwl_d3_status *status, 1603 bool test, bool reset) 1604 { 1605 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1606 u32 val; 1607 int ret; 1608 1609 if (test) { 1610 iwl_enable_interrupts(trans); 1611 *status = IWL_D3_STATUS_ALIVE; 1612 ret = 0; 1613 goto out; 1614 } 1615 1616 iwl_set_bit(trans, CSR_GP_CNTRL, 1617 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1618 1619 ret = iwl_finish_nic_init(trans); 1620 if (ret) 1621 return ret; 1622 1623 /* 1624 * Reconfigure IVAR table in case of MSIX or reset ict table in 1625 * MSI mode since HW reset erased it. 1626 * Also enables interrupts - none will happen as 1627 * the device doesn't know we're waking it up, only when 1628 * the opmode actually tells it after this call. 1629 */ 1630 iwl_pcie_conf_msix_hw(trans_pcie); 1631 if (!trans_pcie->msix_enabled) 1632 iwl_pcie_reset_ict(trans); 1633 iwl_enable_interrupts(trans); 1634 1635 iwl_pcie_set_pwr(trans, false); 1636 1637 if (!reset) { 1638 iwl_clear_bit(trans, CSR_GP_CNTRL, 1639 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1640 } else { 1641 iwl_trans_pcie_tx_reset(trans); 1642 1643 ret = iwl_pcie_rx_init(trans); 1644 if (ret) { 1645 IWL_ERR(trans, 1646 "Failed to resume the device (RX reset)\n"); 1647 return ret; 1648 } 1649 } 1650 1651 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1652 iwl_read_umac_prph(trans, WFPM_GP2)); 1653 1654 val = iwl_read32(trans, CSR_RESET); 1655 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) 1656 *status = IWL_D3_STATUS_RESET; 1657 else 1658 *status = IWL_D3_STATUS_ALIVE; 1659 1660 out: 1661 if (*status == IWL_D3_STATUS_ALIVE) 1662 ret = iwl_pcie_d3_handshake(trans, false); 1663 1664 return ret; 1665 } 1666 1667 static void 1668 iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 1669 struct iwl_trans *trans, 1670 const struct iwl_cfg_trans_params *cfg_trans) 1671 { 1672 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1673 int max_irqs, num_irqs, i, ret; 1674 u16 pci_cmd; 1675 u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES; 1676 1677 if (!cfg_trans->mq_rx_supported) 1678 goto enable_msi; 1679 1680 if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000) 1681 max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES; 1682 1683 max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues); 1684 for (i = 0; i < max_irqs; i++) 1685 trans_pcie->msix_entries[i].entry = i; 1686 1687 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 1688 MSIX_MIN_INTERRUPT_VECTORS, 1689 max_irqs); 1690 if (num_irqs < 0) { 1691 IWL_DEBUG_INFO(trans, 1692 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 1693 num_irqs); 1694 goto enable_msi; 1695 } 1696 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1697 1698 IWL_DEBUG_INFO(trans, 1699 "MSI-X enabled. %d interrupt vectors were allocated\n", 1700 num_irqs); 1701 1702 /* 1703 * In case the OS provides fewer interrupts than requested, different 1704 * causes will share the same interrupt vector as follows: 1705 * One interrupt less: non rx causes shared with FBQ. 1706 * Two interrupts less: non rx causes shared with FBQ and RSS. 1707 * More than two interrupts: we will use fewer RSS queues. 1708 */ 1709 if (num_irqs <= max_irqs - 2) { 1710 trans_pcie->trans->num_rx_queues = num_irqs + 1; 1711 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1712 IWL_SHARED_IRQ_FIRST_RSS; 1713 } else if (num_irqs == max_irqs - 1) { 1714 trans_pcie->trans->num_rx_queues = num_irqs; 1715 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1716 } else { 1717 trans_pcie->trans->num_rx_queues = num_irqs - 1; 1718 } 1719 1720 IWL_DEBUG_INFO(trans, 1721 "MSI-X enabled with rx queues %d, vec mask 0x%x\n", 1722 trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask); 1723 1724 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); 1725 1726 trans_pcie->alloc_vecs = num_irqs; 1727 trans_pcie->msix_enabled = true; 1728 return; 1729 1730 enable_msi: 1731 ret = pci_enable_msi(pdev); 1732 if (ret) { 1733 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 1734 /* enable rfkill interrupt: hw bug w/a */ 1735 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 1736 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 1737 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 1738 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 1739 } 1740 } 1741 } 1742 1743 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans) 1744 { 1745 int iter_rx_q, i, ret, cpu, offset; 1746 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1747 1748 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 1749 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; 1750 offset = 1 + i; 1751 for (; i < iter_rx_q ; i++) { 1752 /* 1753 * Get the cpu prior to the place to search 1754 * (i.e. return will be > i - 1). 1755 */ 1756 cpu = cpumask_next(i - offset, cpu_online_mask); 1757 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 1758 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 1759 &trans_pcie->affinity_mask[i]); 1760 if (ret) 1761 IWL_ERR(trans_pcie->trans, 1762 "Failed to set affinity mask for IRQ %d\n", 1763 trans_pcie->msix_entries[i].vector); 1764 } 1765 } 1766 1767 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 1768 struct iwl_trans_pcie *trans_pcie) 1769 { 1770 int i; 1771 1772 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1773 int ret; 1774 struct msix_entry *msix_entry; 1775 const char *qname = queue_name(&pdev->dev, trans_pcie, i); 1776 1777 if (!qname) 1778 return -ENOMEM; 1779 1780 msix_entry = &trans_pcie->msix_entries[i]; 1781 ret = devm_request_threaded_irq(&pdev->dev, 1782 msix_entry->vector, 1783 iwl_pcie_msix_isr, 1784 (i == trans_pcie->def_irq) ? 1785 iwl_pcie_irq_msix_handler : 1786 iwl_pcie_irq_rx_msix_handler, 1787 IRQF_SHARED, 1788 qname, 1789 msix_entry); 1790 if (ret) { 1791 IWL_ERR(trans_pcie->trans, 1792 "Error allocating IRQ %d\n", i); 1793 1794 return ret; 1795 } 1796 } 1797 iwl_pcie_irq_set_affinity(trans_pcie->trans); 1798 1799 return 0; 1800 } 1801 1802 static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 1803 { 1804 u32 hpm, wprot; 1805 1806 switch (trans->trans_cfg->device_family) { 1807 case IWL_DEVICE_FAMILY_9000: 1808 wprot = PREG_PRPH_WPROT_9000; 1809 break; 1810 case IWL_DEVICE_FAMILY_22000: 1811 wprot = PREG_PRPH_WPROT_22000; 1812 break; 1813 default: 1814 return 0; 1815 } 1816 1817 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 1818 if (!iwl_trans_is_hw_error_value(hpm) && (hpm & PERSISTENCE_BIT)) { 1819 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 1820 1821 if (wprot_val & PREG_WFPM_ACCESS) { 1822 IWL_ERR(trans, 1823 "Error, can not clear persistence bit\n"); 1824 return -EPERM; 1825 } 1826 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 1827 hpm & ~PERSISTENCE_BIT); 1828 } 1829 1830 return 0; 1831 } 1832 1833 static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) 1834 { 1835 int ret; 1836 1837 ret = iwl_finish_nic_init(trans); 1838 if (ret < 0) 1839 return ret; 1840 1841 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 1842 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 1843 udelay(20); 1844 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 1845 HPM_HIPM_GEN_CFG_CR_PG_EN | 1846 HPM_HIPM_GEN_CFG_CR_SLP_EN); 1847 udelay(20); 1848 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, 1849 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 1850 1851 return iwl_trans_pcie_sw_reset(trans, true); 1852 } 1853 1854 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1855 { 1856 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1857 int err; 1858 1859 lockdep_assert_held(&trans_pcie->mutex); 1860 1861 err = iwl_pcie_prepare_card_hw(trans); 1862 if (err) { 1863 IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1864 return err; 1865 } 1866 1867 err = iwl_trans_pcie_clear_persistence_bit(trans); 1868 if (err) 1869 return err; 1870 1871 err = iwl_trans_pcie_sw_reset(trans, true); 1872 if (err) 1873 return err; 1874 1875 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 1876 trans->trans_cfg->integrated) { 1877 err = iwl_pcie_gen2_force_power_gating(trans); 1878 if (err) 1879 return err; 1880 } 1881 1882 err = iwl_pcie_apm_init(trans); 1883 if (err) 1884 return err; 1885 1886 iwl_pcie_init_msix(trans_pcie); 1887 1888 /* From now on, the op_mode will be kept updated about RF kill state */ 1889 iwl_enable_rfkill_int(trans); 1890 1891 trans_pcie->opmode_down = false; 1892 1893 /* Set is_down to false here so that...*/ 1894 trans_pcie->is_down = false; 1895 1896 /* ...rfkill can call stop_device and set it false if needed */ 1897 iwl_pcie_check_hw_rf_kill(trans); 1898 1899 return 0; 1900 } 1901 1902 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1903 { 1904 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1905 int ret; 1906 1907 mutex_lock(&trans_pcie->mutex); 1908 ret = _iwl_trans_pcie_start_hw(trans); 1909 mutex_unlock(&trans_pcie->mutex); 1910 1911 return ret; 1912 } 1913 1914 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1915 { 1916 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1917 1918 mutex_lock(&trans_pcie->mutex); 1919 1920 /* disable interrupts - don't enable HW RF kill interrupt */ 1921 iwl_disable_interrupts(trans); 1922 1923 iwl_pcie_apm_stop(trans, true); 1924 1925 iwl_disable_interrupts(trans); 1926 1927 iwl_pcie_disable_ict(trans); 1928 1929 mutex_unlock(&trans_pcie->mutex); 1930 1931 iwl_pcie_synchronize_irqs(trans); 1932 } 1933 1934 #if defined(__linux__) 1935 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1936 { 1937 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1938 } 1939 1940 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1941 { 1942 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1943 } 1944 1945 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1946 { 1947 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1948 } 1949 #elif defined(__FreeBSD__) 1950 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1951 { 1952 1953 IWL_DEBUG_PCI_RW(trans, "W1 %#010x %#04x\n", ofs, val); 1954 bus_write_1((struct resource *)IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base, ofs, val); 1955 } 1956 1957 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1958 { 1959 1960 IWL_DEBUG_PCI_RW(trans, "W4 %#010x %#010x\n", ofs, val); 1961 bus_write_4((struct resource *)IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base, ofs, val); 1962 } 1963 1964 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1965 { 1966 u32 v; 1967 1968 v = bus_read_4((struct resource *)IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base, ofs); 1969 IWL_DEBUG_PCI_RW(trans, "R4 %#010x %#010x\n", ofs, v); 1970 return (v); 1971 } 1972 #endif 1973 1974 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 1975 { 1976 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1977 return 0x00FFFFFF; 1978 else 1979 return 0x000FFFFF; 1980 } 1981 1982 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1983 { 1984 u32 mask = iwl_trans_pcie_prph_msk(trans); 1985 1986 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1987 ((reg & mask) | (3 << 24))); 1988 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1989 } 1990 1991 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, 1992 u32 val) 1993 { 1994 u32 mask = iwl_trans_pcie_prph_msk(trans); 1995 1996 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1997 ((addr & mask) | (3 << 24))); 1998 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1999 } 2000 2001 static void iwl_trans_pcie_configure(struct iwl_trans *trans, 2002 const struct iwl_trans_config *trans_cfg) 2003 { 2004 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2005 2006 /* free all first - we might be reconfigured for a different size */ 2007 iwl_pcie_free_rbs_pool(trans); 2008 2009 trans->txqs.cmd.q_id = trans_cfg->cmd_queue; 2010 trans->txqs.cmd.fifo = trans_cfg->cmd_fifo; 2011 trans->txqs.cmd.wdg_timeout = trans_cfg->cmd_q_wdg_timeout; 2012 trans->txqs.page_offs = trans_cfg->cb_data_offs; 2013 trans->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); 2014 trans->txqs.queue_alloc_cmd_ver = trans_cfg->queue_alloc_cmd_ver; 2015 2016 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) 2017 trans_pcie->n_no_reclaim_cmds = 0; 2018 else 2019 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; 2020 if (trans_pcie->n_no_reclaim_cmds) 2021 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, 2022 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); 2023 2024 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; 2025 trans_pcie->rx_page_order = 2026 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); 2027 trans_pcie->rx_buf_bytes = 2028 iwl_trans_get_rb_size(trans_pcie->rx_buf_size); 2029 trans_pcie->supported_dma_mask = DMA_BIT_MASK(12); 2030 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 2031 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11); 2032 2033 trans->txqs.bc_table_dword = trans_cfg->bc_table_dword; 2034 trans_pcie->scd_set_active = trans_cfg->scd_set_active; 2035 2036 trans->command_groups = trans_cfg->command_groups; 2037 trans->command_groups_size = trans_cfg->command_groups_size; 2038 2039 /* Initialize NAPI here - it should be before registering to mac80211 2040 * in the opmode but after the HW struct is allocated. 2041 * As this function may be called again in some corner cases don't 2042 * do anything if NAPI was already initialized. 2043 */ 2044 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY) 2045 init_dummy_netdev(&trans_pcie->napi_dev); 2046 2047 trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake; 2048 } 2049 2050 void iwl_trans_pcie_free_pnvm_dram_regions(struct iwl_dram_regions *dram_regions, 2051 struct device *dev) 2052 { 2053 u8 i; 2054 struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc; 2055 2056 /* free DRAM payloads */ 2057 for (i = 0; i < dram_regions->n_regions; i++) { 2058 dma_free_coherent(dev, dram_regions->drams[i].size, 2059 dram_regions->drams[i].block, 2060 dram_regions->drams[i].physical); 2061 } 2062 dram_regions->n_regions = 0; 2063 2064 /* free DRAM addresses array */ 2065 if (desc_dram->block) { 2066 dma_free_coherent(dev, desc_dram->size, 2067 desc_dram->block, 2068 desc_dram->physical); 2069 } 2070 memset(desc_dram, 0, sizeof(*desc_dram)); 2071 } 2072 2073 void iwl_trans_pcie_free(struct iwl_trans *trans) 2074 { 2075 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2076 int i; 2077 2078 iwl_pcie_synchronize_irqs(trans); 2079 2080 if (trans->trans_cfg->gen2) 2081 iwl_txq_gen2_tx_free(trans); 2082 else 2083 iwl_pcie_tx_free(trans); 2084 iwl_pcie_rx_free(trans); 2085 2086 if (trans_pcie->rba.alloc_wq) { 2087 destroy_workqueue(trans_pcie->rba.alloc_wq); 2088 trans_pcie->rba.alloc_wq = NULL; 2089 } 2090 2091 if (trans_pcie->msix_enabled) { 2092 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 2093 irq_set_affinity_hint( 2094 trans_pcie->msix_entries[i].vector, 2095 NULL); 2096 } 2097 2098 trans_pcie->msix_enabled = false; 2099 } else { 2100 iwl_pcie_free_ict(trans); 2101 } 2102 2103 iwl_pcie_free_fw_monitor(trans); 2104 2105 iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->pnvm_data, 2106 trans->dev); 2107 iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->reduced_tables_data, 2108 trans->dev); 2109 2110 mutex_destroy(&trans_pcie->mutex); 2111 iwl_trans_free(trans); 2112 } 2113 2114 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state) 2115 { 2116 if (state) 2117 set_bit(STATUS_TPOWER_PMI, &trans->status); 2118 else 2119 clear_bit(STATUS_TPOWER_PMI, &trans->status); 2120 } 2121 2122 struct iwl_trans_pcie_removal { 2123 struct pci_dev *pdev; 2124 struct work_struct work; 2125 bool rescan; 2126 }; 2127 2128 static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 2129 { 2130 struct iwl_trans_pcie_removal *removal = 2131 container_of(wk, struct iwl_trans_pcie_removal, work); 2132 struct pci_dev *pdev = removal->pdev; 2133 static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 2134 struct pci_bus *bus = pdev->bus; 2135 2136 dev_err(&pdev->dev, "Device gone - attempting removal\n"); 2137 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 2138 pci_lock_rescan_remove(); 2139 pci_dev_put(pdev); 2140 pci_stop_and_remove_bus_device(pdev); 2141 if (removal->rescan) 2142 #if defined(__linux__) 2143 pci_rescan_bus(bus->parent); 2144 #elif defined(__FreeBSD__) 2145 pci_rescan_bus(bus); 2146 #endif 2147 pci_unlock_rescan_remove(); 2148 2149 kfree(removal); 2150 module_put(THIS_MODULE); 2151 } 2152 2153 void iwl_trans_pcie_remove(struct iwl_trans *trans, bool rescan) 2154 { 2155 struct iwl_trans_pcie_removal *removal; 2156 2157 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2158 return; 2159 2160 IWL_ERR(trans, "Device gone - scheduling removal!\n"); 2161 2162 /* 2163 * get a module reference to avoid doing this 2164 * while unloading anyway and to avoid 2165 * scheduling a work with code that's being 2166 * removed. 2167 */ 2168 if (!try_module_get(THIS_MODULE)) { 2169 IWL_ERR(trans, 2170 "Module is being unloaded - abort\n"); 2171 return; 2172 } 2173 2174 removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 2175 if (!removal) { 2176 module_put(THIS_MODULE); 2177 return; 2178 } 2179 /* 2180 * we don't need to clear this flag, because 2181 * the trans will be freed and reallocated. 2182 */ 2183 set_bit(STATUS_TRANS_DEAD, &trans->status); 2184 2185 removal->pdev = to_pci_dev(trans->dev); 2186 removal->rescan = rescan; 2187 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 2188 pci_dev_get(removal->pdev); 2189 schedule_work(&removal->work); 2190 } 2191 EXPORT_SYMBOL(iwl_trans_pcie_remove); 2192 2193 /* 2194 * This version doesn't disable BHs but rather assumes they're 2195 * already disabled. 2196 */ 2197 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2198 { 2199 int ret; 2200 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2201 u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ; 2202 u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 2203 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP; 2204 u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN; 2205 2206 spin_lock(&trans_pcie->reg_lock); 2207 2208 if (trans_pcie->cmd_hold_nic_awake) 2209 goto out; 2210 2211 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 2212 write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ; 2213 mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 2214 poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 2215 } 2216 2217 /* this bit wakes up the NIC */ 2218 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL, write); 2219 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 2220 udelay(2); 2221 2222 /* 2223 * These bits say the device is running, and should keep running for 2224 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 2225 * but they do not indicate that embedded SRAM is restored yet; 2226 * HW with volatile SRAM must save/restore contents to/from 2227 * host DRAM when sleeping/waking for power-saving. 2228 * Each direction takes approximately 1/4 millisecond; with this 2229 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 2230 * series of register accesses are expected (e.g. reading Event Log), 2231 * to keep device from sleeping. 2232 * 2233 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 2234 * SRAM is okay/restored. We don't check that here because this call 2235 * is just for hardware register access; but GP1 MAC_SLEEP 2236 * check is a good idea before accessing the SRAM of HW with 2237 * volatile SRAM (e.g. reading Event Log). 2238 * 2239 * 5000 series and later (including 1000 series) have non-volatile SRAM, 2240 * and do not save/restore SRAM when power cycling. 2241 */ 2242 ret = iwl_poll_bit(trans, CSR_GP_CNTRL, poll, mask, 15000); 2243 if (unlikely(ret < 0)) { 2244 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 2245 2246 WARN_ONCE(1, 2247 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 2248 cntrl); 2249 2250 iwl_trans_pcie_dump_regs(trans); 2251 2252 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) 2253 iwl_trans_pcie_remove(trans, false); 2254 else 2255 iwl_write32(trans, CSR_RESET, 2256 CSR_RESET_REG_FLAG_FORCE_NMI); 2257 2258 spin_unlock(&trans_pcie->reg_lock); 2259 return false; 2260 } 2261 2262 out: 2263 /* 2264 * Fool sparse by faking we release the lock - sparse will 2265 * track nic_access anyway. 2266 */ 2267 __release(&trans_pcie->reg_lock); 2268 return true; 2269 } 2270 2271 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2272 { 2273 bool ret; 2274 2275 local_bh_disable(); 2276 ret = __iwl_trans_pcie_grab_nic_access(trans); 2277 if (ret) { 2278 /* keep BHs disabled until iwl_trans_pcie_release_nic_access */ 2279 return ret; 2280 } 2281 local_bh_enable(); 2282 return false; 2283 } 2284 2285 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans) 2286 { 2287 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2288 2289 lockdep_assert_held(&trans_pcie->reg_lock); 2290 2291 /* 2292 * Fool sparse by faking we acquiring the lock - sparse will 2293 * track nic_access anyway. 2294 */ 2295 __acquire(&trans_pcie->reg_lock); 2296 2297 if (trans_pcie->cmd_hold_nic_awake) 2298 goto out; 2299 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 2300 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2301 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 2302 else 2303 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL, 2304 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2305 /* 2306 * Above we read the CSR_GP_CNTRL register, which will flush 2307 * any previous writes, but we need the write that clears the 2308 * MAC_ACCESS_REQ bit to be performed before any other writes 2309 * scheduled on different CPUs (after we drop reg_lock). 2310 */ 2311 out: 2312 spin_unlock_bh(&trans_pcie->reg_lock); 2313 } 2314 2315 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2316 void *buf, int dwords) 2317 { 2318 int offs = 0; 2319 u32 *vals = buf; 2320 2321 while (offs < dwords) { 2322 /* limit the time we spin here under lock to 1/2s */ 2323 unsigned long end = jiffies + HZ / 2; 2324 bool resched = false; 2325 2326 if (iwl_trans_grab_nic_access(trans)) { 2327 iwl_write32(trans, HBUS_TARG_MEM_RADDR, 2328 addr + 4 * offs); 2329 2330 while (offs < dwords) { 2331 vals[offs] = iwl_read32(trans, 2332 HBUS_TARG_MEM_RDAT); 2333 offs++; 2334 2335 if (time_after(jiffies, end)) { 2336 resched = true; 2337 break; 2338 } 2339 } 2340 iwl_trans_release_nic_access(trans); 2341 2342 if (resched) 2343 cond_resched(); 2344 } else { 2345 return -EBUSY; 2346 } 2347 } 2348 2349 return 0; 2350 } 2351 2352 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 2353 const void *buf, int dwords) 2354 { 2355 int offs, ret = 0; 2356 const u32 *vals = buf; 2357 2358 if (iwl_trans_grab_nic_access(trans)) { 2359 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); 2360 for (offs = 0; offs < dwords; offs++) 2361 iwl_write32(trans, HBUS_TARG_MEM_WDAT, 2362 vals ? vals[offs] : 0); 2363 iwl_trans_release_nic_access(trans); 2364 } else { 2365 ret = -EBUSY; 2366 } 2367 return ret; 2368 } 2369 2370 static int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, 2371 u32 *val) 2372 { 2373 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, 2374 ofs, val); 2375 } 2376 2377 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) 2378 { 2379 int i; 2380 2381 for (i = 0; i < trans->trans_cfg->base_params->num_of_queues; i++) { 2382 struct iwl_txq *txq = trans->txqs.txq[i]; 2383 2384 if (i == trans->txqs.cmd.q_id) 2385 continue; 2386 2387 spin_lock_bh(&txq->lock); 2388 2389 if (!block && !(WARN_ON_ONCE(!txq->block))) { 2390 txq->block--; 2391 if (!txq->block) { 2392 iwl_write32(trans, HBUS_TARG_WRPTR, 2393 txq->write_ptr | (i << 8)); 2394 } 2395 } else if (block) { 2396 txq->block++; 2397 } 2398 2399 spin_unlock_bh(&txq->lock); 2400 } 2401 } 2402 2403 #define IWL_FLUSH_WAIT_MS 2000 2404 2405 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 2406 struct iwl_trans_rxq_dma_data *data) 2407 { 2408 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2409 2410 if (queue >= trans->num_rx_queues || !trans_pcie->rxq) 2411 return -EINVAL; 2412 2413 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 2414 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 2415 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 2416 data->fr_bd_wid = 0; 2417 2418 return 0; 2419 } 2420 2421 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2422 { 2423 struct iwl_txq *txq; 2424 unsigned long now = jiffies; 2425 bool overflow_tx; 2426 u8 wr_ptr; 2427 2428 /* Make sure the NIC is still alive in the bus */ 2429 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2430 return -ENODEV; 2431 2432 if (!test_bit(txq_idx, trans->txqs.queue_used)) 2433 return -EINVAL; 2434 2435 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2436 txq = trans->txqs.txq[txq_idx]; 2437 2438 spin_lock_bh(&txq->lock); 2439 overflow_tx = txq->overflow_tx || 2440 !skb_queue_empty(&txq->overflow_q); 2441 spin_unlock_bh(&txq->lock); 2442 2443 wr_ptr = READ_ONCE(txq->write_ptr); 2444 2445 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 2446 overflow_tx) && 2447 !time_after(jiffies, 2448 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 2449 u8 write_ptr = READ_ONCE(txq->write_ptr); 2450 2451 /* 2452 * If write pointer moved during the wait, warn only 2453 * if the TX came from op mode. In case TX came from 2454 * trans layer (overflow TX) don't warn. 2455 */ 2456 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2457 "WR pointer moved while flushing %d -> %d\n", 2458 wr_ptr, write_ptr)) 2459 return -ETIMEDOUT; 2460 wr_ptr = write_ptr; 2461 2462 usleep_range(1000, 2000); 2463 2464 spin_lock_bh(&txq->lock); 2465 overflow_tx = txq->overflow_tx || 2466 !skb_queue_empty(&txq->overflow_q); 2467 spin_unlock_bh(&txq->lock); 2468 } 2469 2470 if (txq->read_ptr != txq->write_ptr) { 2471 IWL_ERR(trans, 2472 "fail to flush all tx fifo queues Q %d\n", txq_idx); 2473 iwl_txq_log_scd_error(trans, txq); 2474 return -ETIMEDOUT; 2475 } 2476 2477 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2478 2479 return 0; 2480 } 2481 2482 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2483 { 2484 int cnt; 2485 int ret = 0; 2486 2487 /* waiting for all the tx frames complete might take a while */ 2488 for (cnt = 0; 2489 cnt < trans->trans_cfg->base_params->num_of_queues; 2490 cnt++) { 2491 2492 if (cnt == trans->txqs.cmd.q_id) 2493 continue; 2494 if (!test_bit(cnt, trans->txqs.queue_used)) 2495 continue; 2496 if (!(BIT(cnt) & txq_bm)) 2497 continue; 2498 2499 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 2500 if (ret) 2501 break; 2502 } 2503 2504 return ret; 2505 } 2506 2507 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2508 u32 mask, u32 value) 2509 { 2510 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2511 2512 spin_lock_bh(&trans_pcie->reg_lock); 2513 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value); 2514 spin_unlock_bh(&trans_pcie->reg_lock); 2515 } 2516 2517 static const char *get_csr_string(int cmd) 2518 { 2519 #define IWL_CMD(x) case x: return #x 2520 switch (cmd) { 2521 IWL_CMD(CSR_HW_IF_CONFIG_REG); 2522 IWL_CMD(CSR_INT_COALESCING); 2523 IWL_CMD(CSR_INT); 2524 IWL_CMD(CSR_INT_MASK); 2525 IWL_CMD(CSR_FH_INT_STATUS); 2526 IWL_CMD(CSR_GPIO_IN); 2527 IWL_CMD(CSR_RESET); 2528 IWL_CMD(CSR_GP_CNTRL); 2529 IWL_CMD(CSR_HW_REV); 2530 IWL_CMD(CSR_EEPROM_REG); 2531 IWL_CMD(CSR_EEPROM_GP); 2532 IWL_CMD(CSR_OTP_GP_REG); 2533 IWL_CMD(CSR_GIO_REG); 2534 IWL_CMD(CSR_GP_UCODE_REG); 2535 IWL_CMD(CSR_GP_DRIVER_REG); 2536 IWL_CMD(CSR_UCODE_DRV_GP1); 2537 IWL_CMD(CSR_UCODE_DRV_GP2); 2538 IWL_CMD(CSR_LED_REG); 2539 IWL_CMD(CSR_DRAM_INT_TBL_REG); 2540 IWL_CMD(CSR_GIO_CHICKEN_BITS); 2541 IWL_CMD(CSR_ANA_PLL_CFG); 2542 IWL_CMD(CSR_HW_REV_WA_REG); 2543 IWL_CMD(CSR_MONITOR_STATUS_REG); 2544 IWL_CMD(CSR_DBG_HPET_MEM_REG); 2545 default: 2546 return "UNKNOWN"; 2547 } 2548 #undef IWL_CMD 2549 } 2550 2551 void iwl_pcie_dump_csr(struct iwl_trans *trans) 2552 { 2553 int i; 2554 static const u32 csr_tbl[] = { 2555 CSR_HW_IF_CONFIG_REG, 2556 CSR_INT_COALESCING, 2557 CSR_INT, 2558 CSR_INT_MASK, 2559 CSR_FH_INT_STATUS, 2560 CSR_GPIO_IN, 2561 CSR_RESET, 2562 CSR_GP_CNTRL, 2563 CSR_HW_REV, 2564 CSR_EEPROM_REG, 2565 CSR_EEPROM_GP, 2566 CSR_OTP_GP_REG, 2567 CSR_GIO_REG, 2568 CSR_GP_UCODE_REG, 2569 CSR_GP_DRIVER_REG, 2570 CSR_UCODE_DRV_GP1, 2571 CSR_UCODE_DRV_GP2, 2572 CSR_LED_REG, 2573 CSR_DRAM_INT_TBL_REG, 2574 CSR_GIO_CHICKEN_BITS, 2575 CSR_ANA_PLL_CFG, 2576 CSR_MONITOR_STATUS_REG, 2577 CSR_HW_REV_WA_REG, 2578 CSR_DBG_HPET_MEM_REG 2579 }; 2580 IWL_ERR(trans, "CSR values:\n"); 2581 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2582 "CSR_INT_PERIODIC_REG)\n"); 2583 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2584 IWL_ERR(trans, " %25s: 0X%08x\n", 2585 get_csr_string(csr_tbl[i]), 2586 iwl_read32(trans, csr_tbl[i])); 2587 } 2588 } 2589 2590 #ifdef CONFIG_IWLWIFI_DEBUGFS 2591 /* create and remove of files */ 2592 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2593 debugfs_create_file(#name, mode, parent, trans, \ 2594 &iwl_dbgfs_##name##_ops); \ 2595 } while (0) 2596 2597 /* file operation */ 2598 #define DEBUGFS_READ_FILE_OPS(name) \ 2599 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2600 .read = iwl_dbgfs_##name##_read, \ 2601 .open = simple_open, \ 2602 .llseek = generic_file_llseek, \ 2603 }; 2604 2605 #define DEBUGFS_WRITE_FILE_OPS(name) \ 2606 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2607 .write = iwl_dbgfs_##name##_write, \ 2608 .open = simple_open, \ 2609 .llseek = generic_file_llseek, \ 2610 }; 2611 2612 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2613 static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2614 .write = iwl_dbgfs_##name##_write, \ 2615 .read = iwl_dbgfs_##name##_read, \ 2616 .open = simple_open, \ 2617 .llseek = generic_file_llseek, \ 2618 }; 2619 2620 struct iwl_dbgfs_tx_queue_priv { 2621 struct iwl_trans *trans; 2622 }; 2623 2624 struct iwl_dbgfs_tx_queue_state { 2625 loff_t pos; 2626 }; 2627 2628 static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos) 2629 { 2630 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2631 struct iwl_dbgfs_tx_queue_state *state; 2632 2633 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2634 return NULL; 2635 2636 state = kmalloc(sizeof(*state), GFP_KERNEL); 2637 if (!state) 2638 return NULL; 2639 state->pos = *pos; 2640 return state; 2641 } 2642 2643 static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq, 2644 void *v, loff_t *pos) 2645 { 2646 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2647 struct iwl_dbgfs_tx_queue_state *state = v; 2648 2649 *pos = ++state->pos; 2650 2651 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) 2652 return NULL; 2653 2654 return state; 2655 } 2656 2657 static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v) 2658 { 2659 kfree(v); 2660 } 2661 2662 static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v) 2663 { 2664 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2665 struct iwl_dbgfs_tx_queue_state *state = v; 2666 struct iwl_trans *trans = priv->trans; 2667 struct iwl_txq *txq = trans->txqs.txq[state->pos]; 2668 2669 seq_printf(seq, "hwq %.3u: used=%d stopped=%d ", 2670 (unsigned int)state->pos, 2671 !!test_bit(state->pos, trans->txqs.queue_used), 2672 !!test_bit(state->pos, trans->txqs.queue_stopped)); 2673 if (txq) 2674 seq_printf(seq, 2675 "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d", 2676 txq->read_ptr, txq->write_ptr, 2677 txq->need_update, txq->frozen, 2678 txq->n_window, txq->ampdu); 2679 else 2680 seq_puts(seq, "(unallocated)"); 2681 2682 if (state->pos == trans->txqs.cmd.q_id) 2683 seq_puts(seq, " (HCMD)"); 2684 seq_puts(seq, "\n"); 2685 2686 return 0; 2687 } 2688 2689 static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = { 2690 .start = iwl_dbgfs_tx_queue_seq_start, 2691 .next = iwl_dbgfs_tx_queue_seq_next, 2692 .stop = iwl_dbgfs_tx_queue_seq_stop, 2693 .show = iwl_dbgfs_tx_queue_seq_show, 2694 }; 2695 2696 static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp) 2697 { 2698 struct iwl_dbgfs_tx_queue_priv *priv; 2699 2700 priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops, 2701 sizeof(*priv)); 2702 2703 if (!priv) 2704 return -ENOMEM; 2705 2706 priv->trans = inode->i_private; 2707 return 0; 2708 } 2709 2710 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2711 char __user *user_buf, 2712 size_t count, loff_t *ppos) 2713 { 2714 struct iwl_trans *trans = file->private_data; 2715 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2716 char *buf; 2717 int pos = 0, i, ret; 2718 size_t bufsz; 2719 2720 bufsz = sizeof(char) * 121 * trans->num_rx_queues; 2721 2722 if (!trans_pcie->rxq) 2723 return -EAGAIN; 2724 2725 buf = kzalloc(bufsz, GFP_KERNEL); 2726 if (!buf) 2727 return -ENOMEM; 2728 2729 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { 2730 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 2731 2732 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 2733 i); 2734 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2735 rxq->read); 2736 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2737 rxq->write); 2738 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2739 rxq->write_actual); 2740 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2741 rxq->need_update); 2742 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2743 rxq->free_count); 2744 if (rxq->rb_stts) { 2745 u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans, 2746 rxq)); 2747 pos += scnprintf(buf + pos, bufsz - pos, 2748 "\tclosed_rb_num: %u\n", 2749 r & 0x0FFF); 2750 } else { 2751 pos += scnprintf(buf + pos, bufsz - pos, 2752 "\tclosed_rb_num: Not Allocated\n"); 2753 } 2754 } 2755 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2756 kfree(buf); 2757 2758 return ret; 2759 } 2760 2761 static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2762 char __user *user_buf, 2763 size_t count, loff_t *ppos) 2764 { 2765 struct iwl_trans *trans = file->private_data; 2766 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2767 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2768 2769 int pos = 0; 2770 char *buf; 2771 int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2772 ssize_t ret; 2773 2774 buf = kzalloc(bufsz, GFP_KERNEL); 2775 if (!buf) 2776 return -ENOMEM; 2777 2778 pos += scnprintf(buf + pos, bufsz - pos, 2779 "Interrupt Statistics Report:\n"); 2780 2781 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2782 isr_stats->hw); 2783 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2784 isr_stats->sw); 2785 if (isr_stats->sw || isr_stats->hw) { 2786 pos += scnprintf(buf + pos, bufsz - pos, 2787 "\tLast Restarting Code: 0x%X\n", 2788 isr_stats->err_code); 2789 } 2790 #ifdef CONFIG_IWLWIFI_DEBUG 2791 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2792 isr_stats->sch); 2793 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2794 isr_stats->alive); 2795 #endif 2796 pos += scnprintf(buf + pos, bufsz - pos, 2797 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2798 2799 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2800 isr_stats->ctkill); 2801 2802 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2803 isr_stats->wakeup); 2804 2805 pos += scnprintf(buf + pos, bufsz - pos, 2806 "Rx command responses:\t\t %u\n", isr_stats->rx); 2807 2808 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2809 isr_stats->tx); 2810 2811 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2812 isr_stats->unhandled); 2813 2814 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2815 kfree(buf); 2816 return ret; 2817 } 2818 2819 static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2820 const char __user *user_buf, 2821 size_t count, loff_t *ppos) 2822 { 2823 struct iwl_trans *trans = file->private_data; 2824 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2825 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2826 u32 reset_flag; 2827 int ret; 2828 2829 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2830 if (ret) 2831 return ret; 2832 if (reset_flag == 0) 2833 memset(isr_stats, 0, sizeof(*isr_stats)); 2834 2835 return count; 2836 } 2837 2838 static ssize_t iwl_dbgfs_csr_write(struct file *file, 2839 const char __user *user_buf, 2840 size_t count, loff_t *ppos) 2841 { 2842 struct iwl_trans *trans = file->private_data; 2843 2844 iwl_pcie_dump_csr(trans); 2845 2846 return count; 2847 } 2848 2849 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2850 char __user *user_buf, 2851 size_t count, loff_t *ppos) 2852 { 2853 struct iwl_trans *trans = file->private_data; 2854 char *buf = NULL; 2855 ssize_t ret; 2856 2857 ret = iwl_dump_fh(trans, &buf); 2858 if (ret < 0) 2859 return ret; 2860 if (!buf) 2861 return -EINVAL; 2862 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2863 kfree(buf); 2864 return ret; 2865 } 2866 2867 static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2868 char __user *user_buf, 2869 size_t count, loff_t *ppos) 2870 { 2871 struct iwl_trans *trans = file->private_data; 2872 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2873 char buf[100]; 2874 int pos; 2875 2876 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2877 trans_pcie->debug_rfkill, 2878 !(iwl_read32(trans, CSR_GP_CNTRL) & 2879 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2880 2881 return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2882 } 2883 2884 static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 2885 const char __user *user_buf, 2886 size_t count, loff_t *ppos) 2887 { 2888 struct iwl_trans *trans = file->private_data; 2889 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2890 bool new_value; 2891 int ret; 2892 2893 ret = kstrtobool_from_user(user_buf, count, &new_value); 2894 if (ret) 2895 return ret; 2896 if (new_value == trans_pcie->debug_rfkill) 2897 return count; 2898 IWL_WARN(trans, "changing debug rfkill %d->%d\n", 2899 trans_pcie->debug_rfkill, new_value); 2900 trans_pcie->debug_rfkill = new_value; 2901 iwl_pcie_handle_rfkill_irq(trans); 2902 2903 return count; 2904 } 2905 2906 static int iwl_dbgfs_monitor_data_open(struct inode *inode, 2907 struct file *file) 2908 { 2909 struct iwl_trans *trans = inode->i_private; 2910 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2911 2912 if (!trans->dbg.dest_tlv || 2913 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 2914 IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 2915 return -ENOENT; 2916 } 2917 2918 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 2919 return -EBUSY; 2920 2921 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 2922 return simple_open(inode, file); 2923 } 2924 2925 static int iwl_dbgfs_monitor_data_release(struct inode *inode, 2926 struct file *file) 2927 { 2928 struct iwl_trans_pcie *trans_pcie = 2929 IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 2930 2931 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 2932 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 2933 return 0; 2934 } 2935 2936 static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 2937 void *buf, ssize_t *size, 2938 ssize_t *bytes_copied) 2939 { 2940 ssize_t buf_size_left = count - *bytes_copied; 2941 2942 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 2943 if (*size > buf_size_left) 2944 *size = buf_size_left; 2945 2946 *size -= copy_to_user(user_buf, buf, *size); 2947 *bytes_copied += *size; 2948 2949 if (buf_size_left == *size) 2950 return true; 2951 return false; 2952 } 2953 2954 static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 2955 char __user *user_buf, 2956 size_t count, loff_t *ppos) 2957 { 2958 struct iwl_trans *trans = file->private_data; 2959 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2960 u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; 2961 struct cont_rec *data = &trans_pcie->fw_mon_data; 2962 u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 2963 ssize_t size, bytes_copied = 0; 2964 bool b_full; 2965 2966 if (trans->dbg.dest_tlv) { 2967 write_ptr_addr = 2968 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 2969 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 2970 } else { 2971 write_ptr_addr = MON_BUFF_WRPTR; 2972 wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 2973 } 2974 2975 if (unlikely(!trans->dbg.rec_on)) 2976 return 0; 2977 2978 mutex_lock(&data->mutex); 2979 if (data->state == 2980 IWL_FW_MON_DBGFS_STATE_DISABLED) { 2981 mutex_unlock(&data->mutex); 2982 return 0; 2983 } 2984 2985 /* write_ptr position in bytes rather then DW */ 2986 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 2987 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 2988 2989 if (data->prev_wrap_cnt == wrap_cnt) { 2990 size = write_ptr - data->prev_wr_ptr; 2991 curr_buf = cpu_addr + data->prev_wr_ptr; 2992 b_full = iwl_write_to_user_buf(user_buf, count, 2993 curr_buf, &size, 2994 &bytes_copied); 2995 data->prev_wr_ptr += size; 2996 2997 } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 2998 write_ptr < data->prev_wr_ptr) { 2999 size = trans->dbg.fw_mon.size - data->prev_wr_ptr; 3000 curr_buf = cpu_addr + data->prev_wr_ptr; 3001 b_full = iwl_write_to_user_buf(user_buf, count, 3002 curr_buf, &size, 3003 &bytes_copied); 3004 data->prev_wr_ptr += size; 3005 3006 if (!b_full) { 3007 size = write_ptr; 3008 b_full = iwl_write_to_user_buf(user_buf, count, 3009 cpu_addr, &size, 3010 &bytes_copied); 3011 data->prev_wr_ptr = size; 3012 data->prev_wrap_cnt++; 3013 } 3014 } else { 3015 if (data->prev_wrap_cnt == wrap_cnt - 1 && 3016 write_ptr > data->prev_wr_ptr) 3017 IWL_WARN(trans, 3018 "write pointer passed previous write pointer, start copying from the beginning\n"); 3019 else if (!unlikely(data->prev_wrap_cnt == 0 && 3020 data->prev_wr_ptr == 0)) 3021 IWL_WARN(trans, 3022 "monitor data is out of sync, start copying from the beginning\n"); 3023 3024 size = write_ptr; 3025 b_full = iwl_write_to_user_buf(user_buf, count, 3026 cpu_addr, &size, 3027 &bytes_copied); 3028 data->prev_wr_ptr = size; 3029 data->prev_wrap_cnt = wrap_cnt; 3030 } 3031 3032 mutex_unlock(&data->mutex); 3033 3034 return bytes_copied; 3035 } 3036 3037 static ssize_t iwl_dbgfs_rf_read(struct file *file, 3038 char __user *user_buf, 3039 size_t count, loff_t *ppos) 3040 { 3041 struct iwl_trans *trans = file->private_data; 3042 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3043 3044 if (!trans_pcie->rf_name[0]) 3045 return -ENODEV; 3046 3047 return simple_read_from_buffer(user_buf, count, ppos, 3048 trans_pcie->rf_name, 3049 strlen(trans_pcie->rf_name)); 3050 } 3051 3052 DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 3053 DEBUGFS_READ_FILE_OPS(fh_reg); 3054 DEBUGFS_READ_FILE_OPS(rx_queue); 3055 DEBUGFS_WRITE_FILE_OPS(csr); 3056 DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 3057 DEBUGFS_READ_FILE_OPS(rf); 3058 3059 static const struct file_operations iwl_dbgfs_tx_queue_ops = { 3060 .owner = THIS_MODULE, 3061 .open = iwl_dbgfs_tx_queue_open, 3062 .read = seq_read, 3063 .llseek = seq_lseek, 3064 .release = seq_release_private, 3065 }; 3066 3067 static const struct file_operations iwl_dbgfs_monitor_data_ops = { 3068 .read = iwl_dbgfs_monitor_data_read, 3069 .open = iwl_dbgfs_monitor_data_open, 3070 .release = iwl_dbgfs_monitor_data_release, 3071 }; 3072 3073 /* Create the debugfs files and directories */ 3074 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 3075 { 3076 struct dentry *dir = trans->dbgfs_dir; 3077 3078 DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 3079 DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 3080 DEBUGFS_ADD_FILE(interrupt, dir, 0600); 3081 DEBUGFS_ADD_FILE(csr, dir, 0200); 3082 DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 3083 DEBUGFS_ADD_FILE(rfkill, dir, 0600); 3084 DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 3085 DEBUGFS_ADD_FILE(rf, dir, 0400); 3086 } 3087 3088 static void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 3089 { 3090 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3091 struct cont_rec *data = &trans_pcie->fw_mon_data; 3092 3093 mutex_lock(&data->mutex); 3094 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 3095 mutex_unlock(&data->mutex); 3096 } 3097 #endif /*CONFIG_IWLWIFI_DEBUGFS */ 3098 3099 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 3100 { 3101 u32 cmdlen = 0; 3102 int i; 3103 3104 for (i = 0; i < trans->txqs.tfd.max_tbs; i++) 3105 cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i); 3106 3107 return cmdlen; 3108 } 3109 3110 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 3111 struct iwl_fw_error_dump_data **data, 3112 int allocated_rb_nums) 3113 { 3114 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3115 int max_len = trans_pcie->rx_buf_bytes; 3116 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3117 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3118 u32 i, r, j, rb_len = 0; 3119 3120 spin_lock(&rxq->lock); 3121 3122 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF; 3123 3124 for (i = rxq->read, j = 0; 3125 i != r && j < allocated_rb_nums; 3126 i = (i + 1) & RX_QUEUE_MASK, j++) { 3127 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 3128 struct iwl_fw_error_dump_rb *rb; 3129 3130 dma_sync_single_for_cpu(trans->dev, rxb->page_dma, 3131 max_len, DMA_FROM_DEVICE); 3132 3133 rb_len += sizeof(**data) + sizeof(*rb) + max_len; 3134 3135 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 3136 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 3137 rb = (void *)(*data)->data; 3138 rb->index = cpu_to_le32(i); 3139 memcpy(rb->data, page_address(rxb->page), max_len); 3140 3141 *data = iwl_fw_error_next_data(*data); 3142 } 3143 3144 spin_unlock(&rxq->lock); 3145 3146 return rb_len; 3147 } 3148 #define IWL_CSR_TO_DUMP (0x250) 3149 3150 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 3151 struct iwl_fw_error_dump_data **data) 3152 { 3153 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 3154 __le32 *val; 3155 int i; 3156 3157 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 3158 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 3159 val = (void *)(*data)->data; 3160 3161 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 3162 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3163 3164 *data = iwl_fw_error_next_data(*data); 3165 3166 return csr_len; 3167 } 3168 3169 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 3170 struct iwl_fw_error_dump_data **data) 3171 { 3172 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 3173 __le32 *val; 3174 int i; 3175 3176 if (!iwl_trans_grab_nic_access(trans)) 3177 return 0; 3178 3179 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 3180 (*data)->len = cpu_to_le32(fh_regs_len); 3181 val = (void *)(*data)->data; 3182 3183 if (!trans->trans_cfg->gen2) 3184 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 3185 i += sizeof(u32)) 3186 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3187 else 3188 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 3189 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 3190 i += sizeof(u32)) 3191 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 3192 i)); 3193 3194 iwl_trans_release_nic_access(trans); 3195 3196 *data = iwl_fw_error_next_data(*data); 3197 3198 return sizeof(**data) + fh_regs_len; 3199 } 3200 3201 static u32 3202 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3203 struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3204 u32 monitor_len) 3205 { 3206 u32 buf_size_in_dwords = (monitor_len >> 2); 3207 u32 *buffer = (u32 *)fw_mon_data->data; 3208 u32 i; 3209 3210 if (!iwl_trans_grab_nic_access(trans)) 3211 return 0; 3212 3213 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3214 for (i = 0; i < buf_size_in_dwords; i++) 3215 buffer[i] = iwl_read_umac_prph_no_grab(trans, 3216 MON_DMARB_RD_DATA_ADDR); 3217 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3218 3219 iwl_trans_release_nic_access(trans); 3220 3221 return monitor_len; 3222 } 3223 3224 static void 3225 iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 3226 struct iwl_fw_error_dump_fw_mon *fw_mon_data) 3227 { 3228 u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 3229 3230 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3231 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3232 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3233 write_ptr = DBGC_CUR_DBGBUF_STATUS; 3234 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 3235 } else if (trans->dbg.dest_tlv) { 3236 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 3237 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 3238 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3239 } else { 3240 base = MON_BUFF_BASE_ADDR; 3241 write_ptr = MON_BUFF_WRPTR; 3242 wrap_cnt = MON_BUFF_CYCLE_CNT; 3243 } 3244 3245 write_ptr_val = iwl_read_prph(trans, write_ptr); 3246 fw_mon_data->fw_mon_cycle_cnt = 3247 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 3248 fw_mon_data->fw_mon_base_ptr = 3249 cpu_to_le32(iwl_read_prph(trans, base)); 3250 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3251 fw_mon_data->fw_mon_base_high_ptr = 3252 cpu_to_le32(iwl_read_prph(trans, base_high)); 3253 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3254 /* convert wrtPtr to DWs, to align with all HWs */ 3255 write_ptr_val >>= 2; 3256 } 3257 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 3258 } 3259 3260 static u32 3261 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3262 struct iwl_fw_error_dump_data **data, 3263 u32 monitor_len) 3264 { 3265 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 3266 u32 len = 0; 3267 3268 if (trans->dbg.dest_tlv || 3269 (fw_mon->size && 3270 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3271 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3272 struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3273 3274 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3275 fw_mon_data = (void *)(*data)->data; 3276 3277 iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3278 3279 len += sizeof(**data) + sizeof(*fw_mon_data); 3280 if (fw_mon->size) { 3281 memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); 3282 monitor_len = fw_mon->size; 3283 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 3284 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3285 /* 3286 * Update pointers to reflect actual values after 3287 * shifting 3288 */ 3289 if (trans->dbg.dest_tlv->version) { 3290 base = (iwl_read_prph(trans, base) & 3291 IWL_LDBG_M2S_BUF_BA_MSK) << 3292 trans->dbg.dest_tlv->base_shift; 3293 base *= IWL_M2S_UNIT_SIZE; 3294 base += trans->cfg->smem_offset; 3295 } else { 3296 base = iwl_read_prph(trans, base) << 3297 trans->dbg.dest_tlv->base_shift; 3298 } 3299 3300 iwl_trans_read_mem(trans, base, fw_mon_data->data, 3301 monitor_len / sizeof(u32)); 3302 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3303 monitor_len = 3304 iwl_trans_pci_dump_marbh_monitor(trans, 3305 fw_mon_data, 3306 monitor_len); 3307 } else { 3308 /* Didn't match anything - output no monitor data */ 3309 monitor_len = 0; 3310 } 3311 3312 len += monitor_len; 3313 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3314 } 3315 3316 return len; 3317 } 3318 3319 static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3320 { 3321 if (trans->dbg.fw_mon.size) { 3322 *len += sizeof(struct iwl_fw_error_dump_data) + 3323 sizeof(struct iwl_fw_error_dump_fw_mon) + 3324 trans->dbg.fw_mon.size; 3325 return trans->dbg.fw_mon.size; 3326 } else if (trans->dbg.dest_tlv) { 3327 u32 base, end, cfg_reg, monitor_len; 3328 3329 if (trans->dbg.dest_tlv->version == 1) { 3330 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3331 cfg_reg = iwl_read_prph(trans, cfg_reg); 3332 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 3333 trans->dbg.dest_tlv->base_shift; 3334 base *= IWL_M2S_UNIT_SIZE; 3335 base += trans->cfg->smem_offset; 3336 3337 monitor_len = 3338 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 3339 trans->dbg.dest_tlv->end_shift; 3340 monitor_len *= IWL_M2S_UNIT_SIZE; 3341 } else { 3342 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3343 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3344 3345 base = iwl_read_prph(trans, base) << 3346 trans->dbg.dest_tlv->base_shift; 3347 end = iwl_read_prph(trans, end) << 3348 trans->dbg.dest_tlv->end_shift; 3349 3350 /* Make "end" point to the actual end */ 3351 if (trans->trans_cfg->device_family >= 3352 IWL_DEVICE_FAMILY_8000 || 3353 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 3354 end += (1 << trans->dbg.dest_tlv->end_shift); 3355 monitor_len = end - base; 3356 } 3357 *len += sizeof(struct iwl_fw_error_dump_data) + 3358 sizeof(struct iwl_fw_error_dump_fw_mon) + 3359 monitor_len; 3360 return monitor_len; 3361 } 3362 return 0; 3363 } 3364 3365 static struct iwl_trans_dump_data * 3366 iwl_trans_pcie_dump_data(struct iwl_trans *trans, 3367 u32 dump_mask, 3368 const struct iwl_dump_sanitize_ops *sanitize_ops, 3369 void *sanitize_ctx) 3370 { 3371 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3372 struct iwl_fw_error_dump_data *data; 3373 struct iwl_txq *cmdq = trans->txqs.txq[trans->txqs.cmd.q_id]; 3374 struct iwl_fw_error_dump_txcmd *txcmd; 3375 struct iwl_trans_dump_data *dump_data; 3376 u32 len, num_rbs = 0, monitor_len = 0; 3377 int i, ptr; 3378 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && 3379 !trans->trans_cfg->mq_rx_supported && 3380 dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 3381 3382 if (!dump_mask) 3383 return NULL; 3384 3385 /* transport dump header */ 3386 len = sizeof(*dump_data); 3387 3388 /* host commands */ 3389 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3390 len += sizeof(*data) + 3391 cmdq->n_window * (sizeof(*txcmd) + 3392 TFD_MAX_PAYLOAD_SIZE); 3393 3394 /* FW monitor */ 3395 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3396 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3397 3398 /* CSR registers */ 3399 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3400 len += sizeof(*data) + IWL_CSR_TO_DUMP; 3401 3402 /* FH registers */ 3403 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3404 if (trans->trans_cfg->gen2) 3405 len += sizeof(*data) + 3406 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3407 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3408 else 3409 len += sizeof(*data) + 3410 (FH_MEM_UPPER_BOUND - 3411 FH_MEM_LOWER_BOUND); 3412 } 3413 3414 if (dump_rbs) { 3415 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3416 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3417 /* RBs */ 3418 num_rbs = 3419 le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) 3420 & 0x0FFF; 3421 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3422 len += num_rbs * (sizeof(*data) + 3423 sizeof(struct iwl_fw_error_dump_rb) + 3424 (PAGE_SIZE << trans_pcie->rx_page_order)); 3425 } 3426 3427 /* Paged memory for gen2 HW */ 3428 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3429 for (i = 0; i < trans->init_dram.paging_cnt; i++) 3430 len += sizeof(*data) + 3431 sizeof(struct iwl_fw_error_dump_paging) + 3432 trans->init_dram.paging[i].size; 3433 3434 dump_data = vzalloc(len); 3435 if (!dump_data) 3436 return NULL; 3437 3438 len = 0; 3439 data = (void *)dump_data->data; 3440 3441 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3442 u16 tfd_size = trans->txqs.tfd.size; 3443 3444 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3445 txcmd = (void *)data->data; 3446 spin_lock_bh(&cmdq->lock); 3447 ptr = cmdq->write_ptr; 3448 for (i = 0; i < cmdq->n_window; i++) { 3449 u8 idx = iwl_txq_get_cmd_index(cmdq, ptr); 3450 u8 tfdidx; 3451 u32 caplen, cmdlen; 3452 3453 if (trans->trans_cfg->gen2) 3454 tfdidx = idx; 3455 else 3456 tfdidx = ptr; 3457 3458 cmdlen = iwl_trans_pcie_get_cmdlen(trans, 3459 (u8 *)cmdq->tfds + 3460 tfd_size * tfdidx); 3461 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3462 3463 if (cmdlen) { 3464 len += sizeof(*txcmd) + caplen; 3465 txcmd->cmdlen = cpu_to_le32(cmdlen); 3466 txcmd->caplen = cpu_to_le32(caplen); 3467 memcpy(txcmd->data, cmdq->entries[idx].cmd, 3468 caplen); 3469 if (sanitize_ops && sanitize_ops->frob_hcmd) 3470 sanitize_ops->frob_hcmd(sanitize_ctx, 3471 txcmd->data, 3472 caplen); 3473 txcmd = (void *)((u8 *)txcmd->data + caplen); 3474 } 3475 3476 ptr = iwl_txq_dec_wrap(trans, ptr); 3477 } 3478 spin_unlock_bh(&cmdq->lock); 3479 3480 data->len = cpu_to_le32(len); 3481 len += sizeof(*data); 3482 data = iwl_fw_error_next_data(data); 3483 } 3484 3485 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3486 len += iwl_trans_pcie_dump_csr(trans, &data); 3487 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3488 len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3489 if (dump_rbs) 3490 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3491 3492 /* Paged memory for gen2 HW */ 3493 if (trans->trans_cfg->gen2 && 3494 dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3495 for (i = 0; i < trans->init_dram.paging_cnt; i++) { 3496 struct iwl_fw_error_dump_paging *paging; 3497 u32 page_len = trans->init_dram.paging[i].size; 3498 3499 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 3500 data->len = cpu_to_le32(sizeof(*paging) + page_len); 3501 paging = (void *)data->data; 3502 paging->index = cpu_to_le32(i); 3503 memcpy(paging->data, 3504 trans->init_dram.paging[i].block, page_len); 3505 data = iwl_fw_error_next_data(data); 3506 3507 len += sizeof(*data) + sizeof(*paging) + page_len; 3508 } 3509 } 3510 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3511 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3512 3513 dump_data->len = len; 3514 3515 return dump_data; 3516 } 3517 3518 static void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable) 3519 { 3520 if (enable) 3521 iwl_enable_interrupts(trans); 3522 else 3523 iwl_disable_interrupts(trans); 3524 } 3525 3526 static void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 3527 { 3528 u32 inta_addr, sw_err_bit; 3529 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3530 3531 if (trans_pcie->msix_enabled) { 3532 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 3533 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 3534 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ; 3535 else 3536 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 3537 } else { 3538 inta_addr = CSR_INT; 3539 sw_err_bit = CSR_INT_BIT_SW_ERR; 3540 } 3541 3542 iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit); 3543 } 3544 3545 #define IWL_TRANS_COMMON_OPS \ 3546 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \ 3547 .write8 = iwl_trans_pcie_write8, \ 3548 .write32 = iwl_trans_pcie_write32, \ 3549 .read32 = iwl_trans_pcie_read32, \ 3550 .read_prph = iwl_trans_pcie_read_prph, \ 3551 .write_prph = iwl_trans_pcie_write_prph, \ 3552 .read_mem = iwl_trans_pcie_read_mem, \ 3553 .write_mem = iwl_trans_pcie_write_mem, \ 3554 .read_config32 = iwl_trans_pcie_read_config32, \ 3555 .configure = iwl_trans_pcie_configure, \ 3556 .set_pmi = iwl_trans_pcie_set_pmi, \ 3557 .sw_reset = iwl_trans_pcie_sw_reset, \ 3558 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \ 3559 .release_nic_access = iwl_trans_pcie_release_nic_access, \ 3560 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \ 3561 .dump_data = iwl_trans_pcie_dump_data, \ 3562 .d3_suspend = iwl_trans_pcie_d3_suspend, \ 3563 .d3_resume = iwl_trans_pcie_d3_resume, \ 3564 .interrupts = iwl_trans_pci_interrupts, \ 3565 .sync_nmi = iwl_trans_pcie_sync_nmi, \ 3566 .imr_dma_data = iwl_trans_pcie_copy_imr \ 3567 3568 static const struct iwl_trans_ops trans_ops_pcie = { 3569 IWL_TRANS_COMMON_OPS, 3570 .start_hw = iwl_trans_pcie_start_hw, 3571 .fw_alive = iwl_trans_pcie_fw_alive, 3572 .start_fw = iwl_trans_pcie_start_fw, 3573 .stop_device = iwl_trans_pcie_stop_device, 3574 3575 .send_cmd = iwl_pcie_enqueue_hcmd, 3576 3577 .tx = iwl_trans_pcie_tx, 3578 .reclaim = iwl_txq_reclaim, 3579 3580 .txq_disable = iwl_trans_pcie_txq_disable, 3581 .txq_enable = iwl_trans_pcie_txq_enable, 3582 3583 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode, 3584 3585 .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty, 3586 3587 .freeze_txq_timer = iwl_trans_txq_freeze_timer, 3588 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs, 3589 #ifdef CONFIG_IWLWIFI_DEBUGFS 3590 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3591 #endif 3592 }; 3593 3594 static const struct iwl_trans_ops trans_ops_pcie_gen2 = { 3595 IWL_TRANS_COMMON_OPS, 3596 .start_hw = iwl_trans_pcie_start_hw, 3597 .fw_alive = iwl_trans_pcie_gen2_fw_alive, 3598 .start_fw = iwl_trans_pcie_gen2_start_fw, 3599 .stop_device = iwl_trans_pcie_gen2_stop_device, 3600 3601 .send_cmd = iwl_pcie_gen2_enqueue_hcmd, 3602 3603 .tx = iwl_txq_gen2_tx, 3604 .reclaim = iwl_txq_reclaim, 3605 3606 .set_q_ptrs = iwl_txq_set_q_ptrs, 3607 3608 .txq_alloc = iwl_txq_dyn_alloc, 3609 .txq_free = iwl_txq_dyn_free, 3610 .wait_txq_empty = iwl_trans_pcie_wait_txq_empty, 3611 .rxq_dma_data = iwl_trans_pcie_rxq_dma_data, 3612 .load_pnvm = iwl_trans_pcie_ctx_info_gen3_load_pnvm, 3613 .set_pnvm = iwl_trans_pcie_ctx_info_gen3_set_pnvm, 3614 .load_reduce_power = iwl_trans_pcie_ctx_info_gen3_load_reduce_power, 3615 .set_reduce_power = iwl_trans_pcie_ctx_info_gen3_set_reduce_power, 3616 #ifdef CONFIG_IWLWIFI_DEBUGFS 3617 .debugfs_cleanup = iwl_trans_pcie_debugfs_cleanup, 3618 #endif 3619 }; 3620 3621 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev, 3622 const struct pci_device_id *ent, 3623 const struct iwl_cfg_trans_params *cfg_trans) 3624 { 3625 struct iwl_trans_pcie *trans_pcie; 3626 struct iwl_trans *trans; 3627 int ret, addr_size; 3628 const struct iwl_trans_ops *ops = &trans_ops_pcie_gen2; 3629 void __iomem * const *table; 3630 3631 if (!cfg_trans->gen2) 3632 ops = &trans_ops_pcie; 3633 3634 ret = pcim_enable_device(pdev); 3635 if (ret) 3636 return ERR_PTR(ret); 3637 3638 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, ops, 3639 cfg_trans); 3640 if (!trans) 3641 return ERR_PTR(-ENOMEM); 3642 3643 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3644 3645 trans_pcie->trans = trans; 3646 trans_pcie->opmode_down = true; 3647 spin_lock_init(&trans_pcie->irq_lock); 3648 spin_lock_init(&trans_pcie->reg_lock); 3649 spin_lock_init(&trans_pcie->alloc_page_lock); 3650 mutex_init(&trans_pcie->mutex); 3651 init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3652 init_waitqueue_head(&trans_pcie->fw_reset_waitq); 3653 init_waitqueue_head(&trans_pcie->imr_waitq); 3654 3655 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 3656 WQ_HIGHPRI | WQ_UNBOUND, 0); 3657 if (!trans_pcie->rba.alloc_wq) { 3658 ret = -ENOMEM; 3659 goto out_free_trans; 3660 } 3661 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 3662 3663 trans_pcie->debug_rfkill = -1; 3664 3665 if (!cfg_trans->base_params->pcie_l1_allowed) { 3666 /* 3667 * W/A - seems to solve weird behavior. We need to remove this 3668 * if we don't want to stay in L1 all the time. This wastes a 3669 * lot of power. 3670 */ 3671 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3672 PCIE_LINK_STATE_L1 | 3673 PCIE_LINK_STATE_CLKPM); 3674 } 3675 3676 trans_pcie->def_rx_queue = 0; 3677 3678 pci_set_master(pdev); 3679 3680 addr_size = trans->txqs.tfd.addr_size; 3681 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size)); 3682 if (ret) { 3683 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3684 /* both attempts failed: */ 3685 if (ret) { 3686 dev_err(&pdev->dev, "No suitable DMA available\n"); 3687 goto out_no_pci; 3688 } 3689 } 3690 3691 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME); 3692 if (ret) { 3693 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); 3694 goto out_no_pci; 3695 } 3696 3697 #if defined(__FreeBSD__) 3698 linuxkpi_pcim_want_to_use_bus_functions(pdev); 3699 #endif 3700 table = pcim_iomap_table(pdev); 3701 if (!table) { 3702 dev_err(&pdev->dev, "pcim_iomap_table failed\n"); 3703 ret = -ENOMEM; 3704 goto out_no_pci; 3705 } 3706 3707 trans_pcie->hw_base = table[0]; 3708 if (!trans_pcie->hw_base) { 3709 dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n"); 3710 ret = -ENODEV; 3711 goto out_no_pci; 3712 } 3713 3714 /* We disable the RETRY_TIMEOUT register (0x41) to keep 3715 * PCI Tx retries from interfering with C3 CPU state */ 3716 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3717 3718 trans_pcie->pci_dev = pdev; 3719 iwl_disable_interrupts(trans); 3720 3721 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); 3722 if (trans->hw_rev == 0xffffffff) { 3723 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); 3724 ret = -EIO; 3725 goto out_no_pci; 3726 } 3727 3728 /* 3729 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3730 * changed, and now the revision step also includes bit 0-1 (no more 3731 * "dash" value). To keep hw_rev backwards compatible - we'll store it 3732 * in the old format. 3733 */ 3734 if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) 3735 trans->hw_rev_step = trans->hw_rev & 0xF; 3736 else 3737 trans->hw_rev_step = (trans->hw_rev & 0xC) >> 2; 3738 3739 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); 3740 3741 iwl_pcie_set_interrupt_capa(pdev, trans, cfg_trans); 3742 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; 3743 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), 3744 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); 3745 3746 init_waitqueue_head(&trans_pcie->sx_waitq); 3747 3748 3749 if (trans_pcie->msix_enabled) { 3750 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie); 3751 if (ret) 3752 goto out_no_pci; 3753 } else { 3754 ret = iwl_pcie_alloc_ict(trans); 3755 if (ret) 3756 goto out_no_pci; 3757 3758 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 3759 iwl_pcie_isr, 3760 iwl_pcie_irq_handler, 3761 IRQF_SHARED, DRV_NAME, trans); 3762 if (ret) { 3763 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3764 goto out_free_ict; 3765 } 3766 } 3767 3768 #ifdef CONFIG_IWLWIFI_DEBUGFS 3769 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3770 mutex_init(&trans_pcie->fw_mon_data.mutex); 3771 #endif 3772 3773 iwl_dbg_tlv_init(trans); 3774 3775 return trans; 3776 3777 out_free_ict: 3778 iwl_pcie_free_ict(trans); 3779 out_no_pci: 3780 destroy_workqueue(trans_pcie->rba.alloc_wq); 3781 out_free_trans: 3782 iwl_trans_free(trans); 3783 return ERR_PTR(ret); 3784 } 3785 3786 void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans, 3787 u32 dst_addr, u64 src_addr, u32 byte_cnt) 3788 { 3789 iwl_write_prph(trans, IMR_UREG_CHICK, 3790 iwl_read_prph(trans, IMR_UREG_CHICK) | 3791 IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK); 3792 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr); 3793 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB, 3794 (u32)(src_addr & 0xFFFFFFFF)); 3795 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB, 3796 iwl_get_dma_hi_addr(src_addr)); 3797 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt); 3798 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL, 3799 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS | 3800 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS | 3801 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK); 3802 } 3803 3804 int iwl_trans_pcie_copy_imr(struct iwl_trans *trans, 3805 u32 dst_addr, u64 src_addr, u32 byte_cnt) 3806 { 3807 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3808 int ret = -1; 3809 3810 trans_pcie->imr_status = IMR_D2S_REQUESTED; 3811 iwl_trans_pcie_copy_imr_fh(trans, dst_addr, src_addr, byte_cnt); 3812 ret = wait_event_timeout(trans_pcie->imr_waitq, 3813 trans_pcie->imr_status != 3814 IMR_D2S_REQUESTED, 5 * HZ); 3815 if (!ret || trans_pcie->imr_status == IMR_D2S_ERROR) { 3816 IWL_ERR(trans, "Failed to copy IMR Memory chunk!\n"); 3817 iwl_trans_pcie_dump_regs(trans); 3818 return -ETIMEDOUT; 3819 } 3820 trans_pcie->imr_status = IMR_D2S_IDLE; 3821 return 0; 3822 } 3823